audio: api for mixeng code free backends
[qemu/ar7.git] / tcg / tcg.h
bloba37181c8998bb2a15217be9908e387b1c0c09f59
1 /*
2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #ifndef TCG_H
26 #define TCG_H
28 #include "cpu.h"
29 #include "exec/memop.h"
30 #include "exec/tb-context.h"
31 #include "qemu/bitops.h"
32 #include "qemu/queue.h"
33 #include "tcg-mo.h"
34 #include "tcg-target.h"
35 #include "qemu/int128.h"
37 /* XXX: make safe guess about sizes */
38 #define MAX_OP_PER_INSTR 266
40 #if HOST_LONG_BITS == 32
41 #define MAX_OPC_PARAM_PER_ARG 2
42 #else
43 #define MAX_OPC_PARAM_PER_ARG 1
44 #endif
45 #define MAX_OPC_PARAM_IARGS 6
46 #define MAX_OPC_PARAM_OARGS 1
47 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
49 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
50 * and up to 4 + N parameters on 64-bit archs
51 * (N = number of input arguments + output arguments). */
52 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
54 #define CPU_TEMP_BUF_NLONGS 128
56 /* Default target word size to pointer size. */
57 #ifndef TCG_TARGET_REG_BITS
58 # if UINTPTR_MAX == UINT32_MAX
59 # define TCG_TARGET_REG_BITS 32
60 # elif UINTPTR_MAX == UINT64_MAX
61 # define TCG_TARGET_REG_BITS 64
62 # else
63 # error Unknown pointer size for tcg target
64 # endif
65 #endif
67 #if TCG_TARGET_REG_BITS == 32
68 typedef int32_t tcg_target_long;
69 typedef uint32_t tcg_target_ulong;
70 #define TCG_PRIlx PRIx32
71 #define TCG_PRIld PRId32
72 #elif TCG_TARGET_REG_BITS == 64
73 typedef int64_t tcg_target_long;
74 typedef uint64_t tcg_target_ulong;
75 #define TCG_PRIlx PRIx64
76 #define TCG_PRIld PRId64
77 #else
78 #error unsupported
79 #endif
81 /* Oversized TCG guests make things like MTTCG hard
82 * as we can't use atomics for cputlb updates.
84 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
85 #define TCG_OVERSIZED_GUEST 1
86 #else
87 #define TCG_OVERSIZED_GUEST 0
88 #endif
90 #if TCG_TARGET_NB_REGS <= 32
91 typedef uint32_t TCGRegSet;
92 #elif TCG_TARGET_NB_REGS <= 64
93 typedef uint64_t TCGRegSet;
94 #else
95 #error unsupported
96 #endif
98 #if TCG_TARGET_REG_BITS == 32
99 /* Turn some undef macros into false macros. */
100 #define TCG_TARGET_HAS_extrl_i64_i32 0
101 #define TCG_TARGET_HAS_extrh_i64_i32 0
102 #define TCG_TARGET_HAS_div_i64 0
103 #define TCG_TARGET_HAS_rem_i64 0
104 #define TCG_TARGET_HAS_div2_i64 0
105 #define TCG_TARGET_HAS_rot_i64 0
106 #define TCG_TARGET_HAS_ext8s_i64 0
107 #define TCG_TARGET_HAS_ext16s_i64 0
108 #define TCG_TARGET_HAS_ext32s_i64 0
109 #define TCG_TARGET_HAS_ext8u_i64 0
110 #define TCG_TARGET_HAS_ext16u_i64 0
111 #define TCG_TARGET_HAS_ext32u_i64 0
112 #define TCG_TARGET_HAS_bswap16_i64 0
113 #define TCG_TARGET_HAS_bswap32_i64 0
114 #define TCG_TARGET_HAS_bswap64_i64 0
115 #define TCG_TARGET_HAS_neg_i64 0
116 #define TCG_TARGET_HAS_not_i64 0
117 #define TCG_TARGET_HAS_andc_i64 0
118 #define TCG_TARGET_HAS_orc_i64 0
119 #define TCG_TARGET_HAS_eqv_i64 0
120 #define TCG_TARGET_HAS_nand_i64 0
121 #define TCG_TARGET_HAS_nor_i64 0
122 #define TCG_TARGET_HAS_clz_i64 0
123 #define TCG_TARGET_HAS_ctz_i64 0
124 #define TCG_TARGET_HAS_ctpop_i64 0
125 #define TCG_TARGET_HAS_deposit_i64 0
126 #define TCG_TARGET_HAS_extract_i64 0
127 #define TCG_TARGET_HAS_sextract_i64 0
128 #define TCG_TARGET_HAS_extract2_i64 0
129 #define TCG_TARGET_HAS_movcond_i64 0
130 #define TCG_TARGET_HAS_add2_i64 0
131 #define TCG_TARGET_HAS_sub2_i64 0
132 #define TCG_TARGET_HAS_mulu2_i64 0
133 #define TCG_TARGET_HAS_muls2_i64 0
134 #define TCG_TARGET_HAS_muluh_i64 0
135 #define TCG_TARGET_HAS_mulsh_i64 0
136 /* Turn some undef macros into true macros. */
137 #define TCG_TARGET_HAS_add2_i32 1
138 #define TCG_TARGET_HAS_sub2_i32 1
139 #endif
141 #ifndef TCG_TARGET_deposit_i32_valid
142 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
143 #endif
144 #ifndef TCG_TARGET_deposit_i64_valid
145 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
146 #endif
147 #ifndef TCG_TARGET_extract_i32_valid
148 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
149 #endif
150 #ifndef TCG_TARGET_extract_i64_valid
151 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
152 #endif
154 /* Only one of DIV or DIV2 should be defined. */
155 #if defined(TCG_TARGET_HAS_div_i32)
156 #define TCG_TARGET_HAS_div2_i32 0
157 #elif defined(TCG_TARGET_HAS_div2_i32)
158 #define TCG_TARGET_HAS_div_i32 0
159 #define TCG_TARGET_HAS_rem_i32 0
160 #endif
161 #if defined(TCG_TARGET_HAS_div_i64)
162 #define TCG_TARGET_HAS_div2_i64 0
163 #elif defined(TCG_TARGET_HAS_div2_i64)
164 #define TCG_TARGET_HAS_div_i64 0
165 #define TCG_TARGET_HAS_rem_i64 0
166 #endif
168 /* For 32-bit targets, some sort of unsigned widening multiply is required. */
169 #if TCG_TARGET_REG_BITS == 32 \
170 && !(defined(TCG_TARGET_HAS_mulu2_i32) \
171 || defined(TCG_TARGET_HAS_muluh_i32))
172 # error "Missing unsigned widening multiply"
173 #endif
175 #if !defined(TCG_TARGET_HAS_v64) \
176 && !defined(TCG_TARGET_HAS_v128) \
177 && !defined(TCG_TARGET_HAS_v256)
178 #define TCG_TARGET_MAYBE_vec 0
179 #define TCG_TARGET_HAS_abs_vec 0
180 #define TCG_TARGET_HAS_neg_vec 0
181 #define TCG_TARGET_HAS_not_vec 0
182 #define TCG_TARGET_HAS_andc_vec 0
183 #define TCG_TARGET_HAS_orc_vec 0
184 #define TCG_TARGET_HAS_shi_vec 0
185 #define TCG_TARGET_HAS_shs_vec 0
186 #define TCG_TARGET_HAS_shv_vec 0
187 #define TCG_TARGET_HAS_mul_vec 0
188 #define TCG_TARGET_HAS_sat_vec 0
189 #define TCG_TARGET_HAS_minmax_vec 0
190 #define TCG_TARGET_HAS_bitsel_vec 0
191 #define TCG_TARGET_HAS_cmpsel_vec 0
192 #else
193 #define TCG_TARGET_MAYBE_vec 1
194 #endif
195 #ifndef TCG_TARGET_HAS_v64
196 #define TCG_TARGET_HAS_v64 0
197 #endif
198 #ifndef TCG_TARGET_HAS_v128
199 #define TCG_TARGET_HAS_v128 0
200 #endif
201 #ifndef TCG_TARGET_HAS_v256
202 #define TCG_TARGET_HAS_v256 0
203 #endif
205 #ifndef TARGET_INSN_START_EXTRA_WORDS
206 # define TARGET_INSN_START_WORDS 1
207 #else
208 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
209 #endif
211 typedef enum TCGOpcode {
212 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
213 #include "tcg-opc.h"
214 #undef DEF
215 NB_OPS,
216 } TCGOpcode;
218 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r))
219 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
220 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
222 #ifndef TCG_TARGET_INSN_UNIT_SIZE
223 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
224 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
225 typedef uint8_t tcg_insn_unit;
226 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
227 typedef uint16_t tcg_insn_unit;
228 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
229 typedef uint32_t tcg_insn_unit;
230 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
231 typedef uint64_t tcg_insn_unit;
232 #else
233 /* The port better have done this. */
234 #endif
237 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
238 # define tcg_debug_assert(X) do { assert(X); } while (0)
239 #else
240 # define tcg_debug_assert(X) \
241 do { if (!(X)) { __builtin_unreachable(); } } while (0)
242 #endif
244 typedef struct TCGRelocation TCGRelocation;
245 struct TCGRelocation {
246 QSIMPLEQ_ENTRY(TCGRelocation) next;
247 tcg_insn_unit *ptr;
248 intptr_t addend;
249 int type;
252 typedef struct TCGLabel TCGLabel;
253 struct TCGLabel {
254 unsigned present : 1;
255 unsigned has_value : 1;
256 unsigned id : 14;
257 unsigned refs : 16;
258 union {
259 uintptr_t value;
260 tcg_insn_unit *value_ptr;
261 } u;
262 QSIMPLEQ_HEAD(, TCGRelocation) relocs;
263 QSIMPLEQ_ENTRY(TCGLabel) next;
266 typedef struct TCGPool {
267 struct TCGPool *next;
268 int size;
269 uint8_t data[0] __attribute__ ((aligned));
270 } TCGPool;
272 #define TCG_POOL_CHUNK_SIZE 32768
274 #define TCG_MAX_TEMPS 512
275 #define TCG_MAX_INSNS 512
277 /* when the size of the arguments of a called function is smaller than
278 this value, they are statically allocated in the TB stack frame */
279 #define TCG_STATIC_CALL_ARGS_SIZE 128
281 typedef enum TCGType {
282 TCG_TYPE_I32,
283 TCG_TYPE_I64,
285 TCG_TYPE_V64,
286 TCG_TYPE_V128,
287 TCG_TYPE_V256,
289 TCG_TYPE_COUNT, /* number of different types */
291 /* An alias for the size of the host register. */
292 #if TCG_TARGET_REG_BITS == 32
293 TCG_TYPE_REG = TCG_TYPE_I32,
294 #else
295 TCG_TYPE_REG = TCG_TYPE_I64,
296 #endif
298 /* An alias for the size of the native pointer. */
299 #if UINTPTR_MAX == UINT32_MAX
300 TCG_TYPE_PTR = TCG_TYPE_I32,
301 #else
302 TCG_TYPE_PTR = TCG_TYPE_I64,
303 #endif
305 /* An alias for the size of the target "long", aka register. */
306 #if TARGET_LONG_BITS == 64
307 TCG_TYPE_TL = TCG_TYPE_I64,
308 #else
309 TCG_TYPE_TL = TCG_TYPE_I32,
310 #endif
311 } TCGType;
314 * get_alignment_bits
315 * @memop: MemOp value
317 * Extract the alignment size from the memop.
319 static inline unsigned get_alignment_bits(MemOp memop)
321 unsigned a = memop & MO_AMASK;
323 if (a == MO_UNALN) {
324 /* No alignment required. */
325 a = 0;
326 } else if (a == MO_ALIGN) {
327 /* A natural alignment requirement. */
328 a = memop & MO_SIZE;
329 } else {
330 /* A specific alignment requirement. */
331 a = a >> MO_ASHIFT;
333 #if defined(CONFIG_SOFTMMU)
334 /* The requested alignment cannot overlap the TLB flags. */
335 tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
336 #endif
337 return a;
340 typedef tcg_target_ulong TCGArg;
342 /* Define type and accessor macros for TCG variables.
344 TCG variables are the inputs and outputs of TCG ops, as described
345 in tcg/README. Target CPU front-end code uses these types to deal
346 with TCG variables as it emits TCG code via the tcg_gen_* functions.
347 They come in several flavours:
348 * TCGv_i32 : 32 bit integer type
349 * TCGv_i64 : 64 bit integer type
350 * TCGv_ptr : a host pointer type
351 * TCGv_vec : a host vector type; the exact size is not exposed
352 to the CPU front-end code.
353 * TCGv : an integer type the same size as target_ulong
354 (an alias for either TCGv_i32 or TCGv_i64)
355 The compiler's type checking will complain if you mix them
356 up and pass the wrong sized TCGv to a function.
358 Users of tcg_gen_* don't need to know about any of the internal
359 details of these, and should treat them as opaque types.
360 You won't be able to look inside them in a debugger either.
362 Internal implementation details follow:
364 Note that there is no definition of the structs TCGv_i32_d etc anywhere.
365 This is deliberate, because the values we store in variables of type
366 TCGv_i32 are not really pointers-to-structures. They're just small
367 integers, but keeping them in pointer types like this means that the
368 compiler will complain if you accidentally pass a TCGv_i32 to a
369 function which takes a TCGv_i64, and so on. Only the internals of
370 TCG need to care about the actual contents of the types. */
372 typedef struct TCGv_i32_d *TCGv_i32;
373 typedef struct TCGv_i64_d *TCGv_i64;
374 typedef struct TCGv_ptr_d *TCGv_ptr;
375 typedef struct TCGv_vec_d *TCGv_vec;
376 typedef TCGv_ptr TCGv_env;
377 #if TARGET_LONG_BITS == 32
378 #define TCGv TCGv_i32
379 #elif TARGET_LONG_BITS == 64
380 #define TCGv TCGv_i64
381 #else
382 #error Unhandled TARGET_LONG_BITS value
383 #endif
385 /* call flags */
386 /* Helper does not read globals (either directly or through an exception). It
387 implies TCG_CALL_NO_WRITE_GLOBALS. */
388 #define TCG_CALL_NO_READ_GLOBALS 0x0001
389 /* Helper does not write globals */
390 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002
391 /* Helper can be safely suppressed if the return value is not used. */
392 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004
393 /* Helper is QEMU_NORETURN. */
394 #define TCG_CALL_NO_RETURN 0x0008
396 /* convenience version of most used call flags */
397 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS
398 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS
399 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS
400 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
401 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
403 /* Used to align parameters. See the comment before tcgv_i32_temp. */
404 #define TCG_CALL_DUMMY_ARG ((TCGArg)0)
406 /* Conditions. Note that these are laid out for easy manipulation by
407 the functions below:
408 bit 0 is used for inverting;
409 bit 1 is signed,
410 bit 2 is unsigned,
411 bit 3 is used with bit 0 for swapping signed/unsigned. */
412 typedef enum {
413 /* non-signed */
414 TCG_COND_NEVER = 0 | 0 | 0 | 0,
415 TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
416 TCG_COND_EQ = 8 | 0 | 0 | 0,
417 TCG_COND_NE = 8 | 0 | 0 | 1,
418 /* signed */
419 TCG_COND_LT = 0 | 0 | 2 | 0,
420 TCG_COND_GE = 0 | 0 | 2 | 1,
421 TCG_COND_LE = 8 | 0 | 2 | 0,
422 TCG_COND_GT = 8 | 0 | 2 | 1,
423 /* unsigned */
424 TCG_COND_LTU = 0 | 4 | 0 | 0,
425 TCG_COND_GEU = 0 | 4 | 0 | 1,
426 TCG_COND_LEU = 8 | 4 | 0 | 0,
427 TCG_COND_GTU = 8 | 4 | 0 | 1,
428 } TCGCond;
430 /* Invert the sense of the comparison. */
431 static inline TCGCond tcg_invert_cond(TCGCond c)
433 return (TCGCond)(c ^ 1);
436 /* Swap the operands in a comparison. */
437 static inline TCGCond tcg_swap_cond(TCGCond c)
439 return c & 6 ? (TCGCond)(c ^ 9) : c;
442 /* Create an "unsigned" version of a "signed" comparison. */
443 static inline TCGCond tcg_unsigned_cond(TCGCond c)
445 return c & 2 ? (TCGCond)(c ^ 6) : c;
448 /* Create a "signed" version of an "unsigned" comparison. */
449 static inline TCGCond tcg_signed_cond(TCGCond c)
451 return c & 4 ? (TCGCond)(c ^ 6) : c;
454 /* Must a comparison be considered unsigned? */
455 static inline bool is_unsigned_cond(TCGCond c)
457 return (c & 4) != 0;
460 /* Create a "high" version of a double-word comparison.
461 This removes equality from a LTE or GTE comparison. */
462 static inline TCGCond tcg_high_cond(TCGCond c)
464 switch (c) {
465 case TCG_COND_GE:
466 case TCG_COND_LE:
467 case TCG_COND_GEU:
468 case TCG_COND_LEU:
469 return (TCGCond)(c ^ 8);
470 default:
471 return c;
475 typedef enum TCGTempVal {
476 TEMP_VAL_DEAD,
477 TEMP_VAL_REG,
478 TEMP_VAL_MEM,
479 TEMP_VAL_CONST,
480 } TCGTempVal;
482 typedef struct TCGTemp {
483 TCGReg reg:8;
484 TCGTempVal val_type:8;
485 TCGType base_type:8;
486 TCGType type:8;
487 unsigned int fixed_reg:1;
488 unsigned int indirect_reg:1;
489 unsigned int indirect_base:1;
490 unsigned int mem_coherent:1;
491 unsigned int mem_allocated:1;
492 /* If true, the temp is saved across both basic blocks and
493 translation blocks. */
494 unsigned int temp_global:1;
495 /* If true, the temp is saved across basic blocks but dead
496 at the end of translation blocks. If false, the temp is
497 dead at the end of basic blocks. */
498 unsigned int temp_local:1;
499 unsigned int temp_allocated:1;
501 tcg_target_long val;
502 struct TCGTemp *mem_base;
503 intptr_t mem_offset;
504 const char *name;
506 /* Pass-specific information that can be stored for a temporary.
507 One word worth of integer data, and one pointer to data
508 allocated separately. */
509 uintptr_t state;
510 void *state_ptr;
511 } TCGTemp;
513 typedef struct TCGContext TCGContext;
515 typedef struct TCGTempSet {
516 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
517 } TCGTempSet;
519 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
520 this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
521 There are never more than 2 outputs, which means that we can store all
522 dead + sync data within 16 bits. */
523 #define DEAD_ARG 4
524 #define SYNC_ARG 1
525 typedef uint16_t TCGLifeData;
527 /* The layout here is designed to avoid a bitfield crossing of
528 a 32-bit boundary, which would cause GCC to add extra padding. */
529 typedef struct TCGOp {
530 TCGOpcode opc : 8; /* 8 */
532 /* Parameters for this opcode. See below. */
533 unsigned param1 : 4; /* 12 */
534 unsigned param2 : 4; /* 16 */
536 /* Lifetime data of the operands. */
537 unsigned life : 16; /* 32 */
539 /* Next and previous opcodes. */
540 QTAILQ_ENTRY(TCGOp) link;
542 /* Arguments for the opcode. */
543 TCGArg args[MAX_OPC_PARAM];
545 /* Register preferences for the output(s). */
546 TCGRegSet output_pref[2];
547 } TCGOp;
549 #define TCGOP_CALLI(X) (X)->param1
550 #define TCGOP_CALLO(X) (X)->param2
552 #define TCGOP_VECL(X) (X)->param1
553 #define TCGOP_VECE(X) (X)->param2
555 /* Make sure operands fit in the bitfields above. */
556 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
558 typedef struct TCGProfile {
559 int64_t cpu_exec_time;
560 int64_t tb_count1;
561 int64_t tb_count;
562 int64_t op_count; /* total insn count */
563 int op_count_max; /* max insn per TB */
564 int temp_count_max;
565 int64_t temp_count;
566 int64_t del_op_count;
567 int64_t code_in_len;
568 int64_t code_out_len;
569 int64_t search_out_len;
570 int64_t interm_time;
571 int64_t code_time;
572 int64_t la_time;
573 int64_t opt_time;
574 int64_t restore_count;
575 int64_t restore_time;
576 int64_t table_op_count[NB_OPS];
577 } TCGProfile;
579 struct TCGContext {
580 uint8_t *pool_cur, *pool_end;
581 TCGPool *pool_first, *pool_current, *pool_first_large;
582 int nb_labels;
583 int nb_globals;
584 int nb_temps;
585 int nb_indirects;
586 int nb_ops;
588 /* goto_tb support */
589 tcg_insn_unit *code_buf;
590 uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
591 uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */
592 uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
594 TCGRegSet reserved_regs;
595 uint32_t tb_cflags; /* cflags of the current TB */
596 intptr_t current_frame_offset;
597 intptr_t frame_start;
598 intptr_t frame_end;
599 TCGTemp *frame_temp;
601 tcg_insn_unit *code_ptr;
603 #ifdef CONFIG_PROFILER
604 TCGProfile prof;
605 #endif
607 #ifdef CONFIG_DEBUG_TCG
608 int temps_in_use;
609 int goto_tb_issue_mask;
610 const TCGOpcode *vecop_list;
611 #endif
613 /* Code generation. Note that we specifically do not use tcg_insn_unit
614 here, because there's too much arithmetic throughout that relies
615 on addition and subtraction working on bytes. Rely on the GCC
616 extension that allows arithmetic on void*. */
617 void *code_gen_prologue;
618 void *code_gen_epilogue;
619 void *code_gen_buffer;
620 size_t code_gen_buffer_size;
621 void *code_gen_ptr;
622 void *data_gen_ptr;
624 /* Threshold to flush the translated code buffer. */
625 void *code_gen_highwater;
627 size_t tb_phys_invalidate_count;
629 /* Track which vCPU triggers events */
630 CPUState *cpu; /* *_trans */
632 /* These structures are private to tcg-target.inc.c. */
633 #ifdef TCG_TARGET_NEED_LDST_LABELS
634 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels;
635 #endif
636 #ifdef TCG_TARGET_NEED_POOL_LABELS
637 struct TCGLabelPoolData *pool_labels;
638 #endif
640 TCGLabel *exitreq_label;
642 TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
643 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
645 QTAILQ_HEAD(, TCGOp) ops, free_ops;
646 QSIMPLEQ_HEAD(, TCGLabel) labels;
648 /* Tells which temporary holds a given register.
649 It does not take into account fixed registers */
650 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
652 uint16_t gen_insn_end_off[TCG_MAX_INSNS];
653 target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
656 extern TCGContext tcg_init_ctx;
657 extern __thread TCGContext *tcg_ctx;
658 extern TCGv_env cpu_env;
660 static inline size_t temp_idx(TCGTemp *ts)
662 ptrdiff_t n = ts - tcg_ctx->temps;
663 tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps);
664 return n;
667 static inline TCGArg temp_arg(TCGTemp *ts)
669 return (uintptr_t)ts;
672 static inline TCGTemp *arg_temp(TCGArg a)
674 return (TCGTemp *)(uintptr_t)a;
677 /* Using the offset of a temporary, relative to TCGContext, rather than
678 its index means that we don't use 0. That leaves offset 0 free for
679 a NULL representation without having to leave index 0 unused. */
680 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v)
682 uintptr_t o = (uintptr_t)v;
683 TCGTemp *t = (void *)tcg_ctx + o;
684 tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o);
685 return t;
688 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v)
690 return tcgv_i32_temp((TCGv_i32)v);
693 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v)
695 return tcgv_i32_temp((TCGv_i32)v);
698 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v)
700 return tcgv_i32_temp((TCGv_i32)v);
703 static inline TCGArg tcgv_i32_arg(TCGv_i32 v)
705 return temp_arg(tcgv_i32_temp(v));
708 static inline TCGArg tcgv_i64_arg(TCGv_i64 v)
710 return temp_arg(tcgv_i64_temp(v));
713 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
715 return temp_arg(tcgv_ptr_temp(v));
718 static inline TCGArg tcgv_vec_arg(TCGv_vec v)
720 return temp_arg(tcgv_vec_temp(v));
723 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
725 (void)temp_idx(t); /* trigger embedded assert */
726 return (TCGv_i32)((void *)t - (void *)tcg_ctx);
729 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
731 return (TCGv_i64)temp_tcgv_i32(t);
734 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
736 return (TCGv_ptr)temp_tcgv_i32(t);
739 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
741 return (TCGv_vec)temp_tcgv_i32(t);
744 #if TCG_TARGET_REG_BITS == 32
745 static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
747 return temp_tcgv_i32(tcgv_i64_temp(t));
750 static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
752 return temp_tcgv_i32(tcgv_i64_temp(t) + 1);
754 #endif
756 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
758 op->args[arg] = v;
761 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
763 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
764 tcg_set_insn_param(op, arg, v);
765 #else
766 tcg_set_insn_param(op, arg * 2, v);
767 tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
768 #endif
771 /* The last op that was emitted. */
772 static inline TCGOp *tcg_last_op(void)
774 return QTAILQ_LAST(&tcg_ctx->ops);
777 /* Test for whether to terminate the TB for using too many opcodes. */
778 static inline bool tcg_op_buf_full(void)
780 /* This is not a hard limit, it merely stops translation when
781 * we have produced "enough" opcodes. We want to limit TB size
782 * such that a RISC host can reasonably use a 16-bit signed
783 * branch within the TB. We also need to be mindful of the
784 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[]
785 * and TCGContext.gen_insn_end_off[].
787 return tcg_ctx->nb_ops >= 4000;
790 /* pool based memory allocation */
792 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */
793 void *tcg_malloc_internal(TCGContext *s, int size);
794 void tcg_pool_reset(TCGContext *s);
795 TranslationBlock *tcg_tb_alloc(TCGContext *s);
797 void tcg_region_init(void);
798 void tcg_region_reset_all(void);
800 size_t tcg_code_size(void);
801 size_t tcg_code_capacity(void);
803 void tcg_tb_insert(TranslationBlock *tb);
804 void tcg_tb_remove(TranslationBlock *tb);
805 size_t tcg_tb_phys_invalidate_count(void);
806 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr);
807 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data);
808 size_t tcg_nb_tbs(void);
810 /* user-mode: Called with mmap_lock held. */
811 static inline void *tcg_malloc(int size)
813 TCGContext *s = tcg_ctx;
814 uint8_t *ptr, *ptr_end;
816 /* ??? This is a weak placeholder for minimum malloc alignment. */
817 size = QEMU_ALIGN_UP(size, 8);
819 ptr = s->pool_cur;
820 ptr_end = ptr + size;
821 if (unlikely(ptr_end > s->pool_end)) {
822 return tcg_malloc_internal(tcg_ctx, size);
823 } else {
824 s->pool_cur = ptr_end;
825 return ptr;
829 void tcg_context_init(TCGContext *s);
830 void tcg_register_thread(void);
831 void tcg_prologue_init(TCGContext *s);
832 void tcg_func_start(TCGContext *s);
834 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
836 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
838 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
839 intptr_t, const char *);
840 TCGTemp *tcg_temp_new_internal(TCGType, bool);
841 void tcg_temp_free_internal(TCGTemp *);
842 TCGv_vec tcg_temp_new_vec(TCGType type);
843 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
845 static inline void tcg_temp_free_i32(TCGv_i32 arg)
847 tcg_temp_free_internal(tcgv_i32_temp(arg));
850 static inline void tcg_temp_free_i64(TCGv_i64 arg)
852 tcg_temp_free_internal(tcgv_i64_temp(arg));
855 static inline void tcg_temp_free_ptr(TCGv_ptr arg)
857 tcg_temp_free_internal(tcgv_ptr_temp(arg));
860 static inline void tcg_temp_free_vec(TCGv_vec arg)
862 tcg_temp_free_internal(tcgv_vec_temp(arg));
865 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
866 const char *name)
868 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
869 return temp_tcgv_i32(t);
872 static inline TCGv_i32 tcg_temp_new_i32(void)
874 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false);
875 return temp_tcgv_i32(t);
878 static inline TCGv_i32 tcg_temp_local_new_i32(void)
880 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true);
881 return temp_tcgv_i32(t);
884 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
885 const char *name)
887 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
888 return temp_tcgv_i64(t);
891 static inline TCGv_i64 tcg_temp_new_i64(void)
893 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false);
894 return temp_tcgv_i64(t);
897 static inline TCGv_i64 tcg_temp_local_new_i64(void)
899 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true);
900 return temp_tcgv_i64(t);
903 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
904 const char *name)
906 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name);
907 return temp_tcgv_ptr(t);
910 static inline TCGv_ptr tcg_temp_new_ptr(void)
912 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false);
913 return temp_tcgv_ptr(t);
916 static inline TCGv_ptr tcg_temp_local_new_ptr(void)
918 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true);
919 return temp_tcgv_ptr(t);
922 #if defined(CONFIG_DEBUG_TCG)
923 /* If you call tcg_clear_temp_count() at the start of a section of
924 * code which is not supposed to leak any TCG temporaries, then
925 * calling tcg_check_temp_count() at the end of the section will
926 * return 1 if the section did in fact leak a temporary.
928 void tcg_clear_temp_count(void);
929 int tcg_check_temp_count(void);
930 #else
931 #define tcg_clear_temp_count() do { } while (0)
932 #define tcg_check_temp_count() 0
933 #endif
935 int64_t tcg_cpu_exec_time(void);
936 void tcg_dump_info(void);
937 void tcg_dump_op_count(void);
939 #define TCG_CT_ALIAS 0x80
940 #define TCG_CT_IALIAS 0x40
941 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
942 #define TCG_CT_REG 0x01
943 #define TCG_CT_CONST 0x02 /* any constant of register size */
945 typedef struct TCGArgConstraint {
946 uint16_t ct;
947 uint8_t alias_index;
948 union {
949 TCGRegSet regs;
950 } u;
951 } TCGArgConstraint;
953 #define TCG_MAX_OP_ARGS 16
955 /* Bits for TCGOpDef->flags, 8 bits available. */
956 enum {
957 /* Instruction exits the translation block. */
958 TCG_OPF_BB_EXIT = 0x01,
959 /* Instruction defines the end of a basic block. */
960 TCG_OPF_BB_END = 0x02,
961 /* Instruction clobbers call registers and potentially update globals. */
962 TCG_OPF_CALL_CLOBBER = 0x04,
963 /* Instruction has side effects: it cannot be removed if its outputs
964 are not used, and might trigger exceptions. */
965 TCG_OPF_SIDE_EFFECTS = 0x08,
966 /* Instruction operands are 64-bits (otherwise 32-bits). */
967 TCG_OPF_64BIT = 0x10,
968 /* Instruction is optional and not implemented by the host, or insn
969 is generic and should not be implemened by the host. */
970 TCG_OPF_NOT_PRESENT = 0x20,
971 /* Instruction operands are vectors. */
972 TCG_OPF_VECTOR = 0x40,
975 typedef struct TCGOpDef {
976 const char *name;
977 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
978 uint8_t flags;
979 TCGArgConstraint *args_ct;
980 int *sorted_args;
981 #if defined(CONFIG_DEBUG_TCG)
982 int used;
983 #endif
984 } TCGOpDef;
986 extern TCGOpDef tcg_op_defs[];
987 extern const size_t tcg_op_defs_max;
989 typedef struct TCGTargetOpDef {
990 TCGOpcode op;
991 const char *args_ct_str[TCG_MAX_OP_ARGS];
992 } TCGTargetOpDef;
994 #define tcg_abort() \
995 do {\
996 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
997 abort();\
998 } while (0)
1000 bool tcg_op_supported(TCGOpcode op);
1002 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args);
1004 TCGOp *tcg_emit_op(TCGOpcode opc);
1005 void tcg_op_remove(TCGContext *s, TCGOp *op);
1006 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc);
1007 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc);
1009 void tcg_optimize(TCGContext *s);
1011 TCGv_i32 tcg_const_i32(int32_t val);
1012 TCGv_i64 tcg_const_i64(int64_t val);
1013 TCGv_i32 tcg_const_local_i32(int32_t val);
1014 TCGv_i64 tcg_const_local_i64(int64_t val);
1015 TCGv_vec tcg_const_zeros_vec(TCGType);
1016 TCGv_vec tcg_const_ones_vec(TCGType);
1017 TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
1018 TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
1020 #if UINTPTR_MAX == UINT32_MAX
1021 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
1022 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
1023 #else
1024 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
1025 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x)))
1026 #endif
1028 TCGLabel *gen_new_label(void);
1031 * label_arg
1032 * @l: label
1034 * Encode a label for storage in the TCG opcode stream.
1037 static inline TCGArg label_arg(TCGLabel *l)
1039 return (uintptr_t)l;
1043 * arg_label
1044 * @i: value
1046 * The opposite of label_arg. Retrieve a label from the
1047 * encoding of the TCG opcode stream.
1050 static inline TCGLabel *arg_label(TCGArg i)
1052 return (TCGLabel *)(uintptr_t)i;
1056 * tcg_ptr_byte_diff
1057 * @a, @b: addresses to be differenced
1059 * There are many places within the TCG backends where we need a byte
1060 * difference between two pointers. While this can be accomplished
1061 * with local casting, it's easy to get wrong -- especially if one is
1062 * concerned with the signedness of the result.
1064 * This version relies on GCC's void pointer arithmetic to get the
1065 * correct result.
1068 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
1070 return a - b;
1074 * tcg_pcrel_diff
1075 * @s: the tcg context
1076 * @target: address of the target
1078 * Produce a pc-relative difference, from the current code_ptr
1079 * to the destination address.
1082 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
1084 return tcg_ptr_byte_diff(target, s->code_ptr);
1088 * tcg_current_code_size
1089 * @s: the tcg context
1091 * Compute the current code size within the translation block.
1092 * This is used to fill in qemu's data structures for goto_tb.
1095 static inline size_t tcg_current_code_size(TCGContext *s)
1097 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
1100 /* Combine the MemOp and mmu_idx parameters into a single value. */
1101 typedef uint32_t TCGMemOpIdx;
1104 * make_memop_idx
1105 * @op: memory operation
1106 * @idx: mmu index
1108 * Encode these values into a single parameter.
1110 static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx)
1112 tcg_debug_assert(idx <= 15);
1113 return (op << 4) | idx;
1117 * get_memop
1118 * @oi: combined op/idx parameter
1120 * Extract the memory operation from the combined value.
1122 static inline MemOp get_memop(TCGMemOpIdx oi)
1124 return oi >> 4;
1128 * get_mmuidx
1129 * @oi: combined op/idx parameter
1131 * Extract the mmu index from the combined value.
1133 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
1135 return oi & 15;
1139 * tcg_qemu_tb_exec:
1140 * @env: pointer to CPUArchState for the CPU
1141 * @tb_ptr: address of generated code for the TB to execute
1143 * Start executing code from a given translation block.
1144 * Where translation blocks have been linked, execution
1145 * may proceed from the given TB into successive ones.
1146 * Control eventually returns only when some action is needed
1147 * from the top-level loop: either control must pass to a TB
1148 * which has not yet been directly linked, or an asynchronous
1149 * event such as an interrupt needs handling.
1151 * Return: The return value is the value passed to the corresponding
1152 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1153 * The value is either zero or a 4-byte aligned pointer to that TB combined
1154 * with additional information in its two least significant bits. The
1155 * additional information is encoded as follows:
1156 * 0, 1: the link between this TB and the next is via the specified
1157 * TB index (0 or 1). That is, we left the TB via (the equivalent
1158 * of) "goto_tb <index>". The main loop uses this to determine
1159 * how to link the TB just executed to the next.
1160 * 2: we are using instruction counting code generation, and we
1161 * did not start executing this TB because the instruction counter
1162 * would hit zero midway through it. In this case the pointer
1163 * returned is the TB we were about to execute, and the caller must
1164 * arrange to execute the remaining count of instructions.
1165 * 3: we stopped because the CPU's exit_request flag was set
1166 * (usually meaning that there is an interrupt that needs to be
1167 * handled). The pointer returned is the TB we were about to execute
1168 * when we noticed the pending exit request.
1170 * If the bottom two bits indicate an exit-via-index then the CPU
1171 * state is correctly synchronised and ready for execution of the next
1172 * TB (and in particular the guest PC is the address to execute next).
1173 * Otherwise, we gave up on execution of this TB before it started, and
1174 * the caller must fix up the CPU state by calling the CPU's
1175 * synchronize_from_tb() method with the TB pointer we return (falling
1176 * back to calling the CPU's set_pc method with tb->pb if no
1177 * synchronize_from_tb() method exists).
1179 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1180 * to this default (which just calls the prologue.code emitted by
1181 * tcg_target_qemu_prologue()).
1183 #define TB_EXIT_MASK 3
1184 #define TB_EXIT_IDX0 0
1185 #define TB_EXIT_IDX1 1
1186 #define TB_EXIT_IDXMAX 1
1187 #define TB_EXIT_REQUESTED 3
1189 #ifdef HAVE_TCG_QEMU_TB_EXEC
1190 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1191 #else
1192 # define tcg_qemu_tb_exec(env, tb_ptr) \
1193 ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
1194 #endif
1196 void tcg_register_jit(void *buf, size_t buf_size);
1198 #if TCG_TARGET_MAYBE_vec
1199 /* Return zero if the tuple (opc, type, vece) is unsupportable;
1200 return > 0 if it is directly supportable;
1201 return < 0 if we must call tcg_expand_vec_op. */
1202 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
1203 #else
1204 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
1206 return 0;
1208 #endif
1210 /* Expand the tuple (opc, type, vece) on the given arguments. */
1211 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
1213 /* Replicate a constant C accoring to the log2 of the element size. */
1214 uint64_t dup_const(unsigned vece, uint64_t c);
1216 #define dup_const(VECE, C) \
1217 (__builtin_constant_p(VECE) \
1218 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \
1219 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \
1220 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \
1221 : dup_const(VECE, C)) \
1222 : dup_const(VECE, C))
1226 * Memory helpers that will be used by TCG generated code.
1228 #ifdef CONFIG_SOFTMMU
1229 /* Value zero-extended to tcg register size. */
1230 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1231 TCGMemOpIdx oi, uintptr_t retaddr);
1232 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1233 TCGMemOpIdx oi, uintptr_t retaddr);
1234 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1235 TCGMemOpIdx oi, uintptr_t retaddr);
1236 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1237 TCGMemOpIdx oi, uintptr_t retaddr);
1238 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1239 TCGMemOpIdx oi, uintptr_t retaddr);
1240 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1241 TCGMemOpIdx oi, uintptr_t retaddr);
1242 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1243 TCGMemOpIdx oi, uintptr_t retaddr);
1245 /* Value sign-extended to tcg register size. */
1246 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1247 TCGMemOpIdx oi, uintptr_t retaddr);
1248 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1249 TCGMemOpIdx oi, uintptr_t retaddr);
1250 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1251 TCGMemOpIdx oi, uintptr_t retaddr);
1252 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1253 TCGMemOpIdx oi, uintptr_t retaddr);
1254 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1255 TCGMemOpIdx oi, uintptr_t retaddr);
1257 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1258 TCGMemOpIdx oi, uintptr_t retaddr);
1259 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1260 TCGMemOpIdx oi, uintptr_t retaddr);
1261 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1262 TCGMemOpIdx oi, uintptr_t retaddr);
1263 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1264 TCGMemOpIdx oi, uintptr_t retaddr);
1265 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1266 TCGMemOpIdx oi, uintptr_t retaddr);
1267 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1268 TCGMemOpIdx oi, uintptr_t retaddr);
1269 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1270 TCGMemOpIdx oi, uintptr_t retaddr);
1272 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1273 TCGMemOpIdx oi, uintptr_t retaddr);
1274 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1275 TCGMemOpIdx oi, uintptr_t retaddr);
1276 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1277 TCGMemOpIdx oi, uintptr_t retaddr);
1278 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1279 TCGMemOpIdx oi, uintptr_t retaddr);
1280 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1281 TCGMemOpIdx oi, uintptr_t retaddr);
1282 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1283 TCGMemOpIdx oi, uintptr_t retaddr);
1284 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1285 TCGMemOpIdx oi, uintptr_t retaddr);
1287 /* Temporary aliases until backends are converted. */
1288 #ifdef TARGET_WORDS_BIGENDIAN
1289 # define helper_ret_ldsw_mmu helper_be_ldsw_mmu
1290 # define helper_ret_lduw_mmu helper_be_lduw_mmu
1291 # define helper_ret_ldsl_mmu helper_be_ldsl_mmu
1292 # define helper_ret_ldul_mmu helper_be_ldul_mmu
1293 # define helper_ret_ldl_mmu helper_be_ldul_mmu
1294 # define helper_ret_ldq_mmu helper_be_ldq_mmu
1295 # define helper_ret_stw_mmu helper_be_stw_mmu
1296 # define helper_ret_stl_mmu helper_be_stl_mmu
1297 # define helper_ret_stq_mmu helper_be_stq_mmu
1298 # define helper_ret_ldw_cmmu helper_be_ldw_cmmu
1299 # define helper_ret_ldl_cmmu helper_be_ldl_cmmu
1300 # define helper_ret_ldq_cmmu helper_be_ldq_cmmu
1301 #else
1302 # define helper_ret_ldsw_mmu helper_le_ldsw_mmu
1303 # define helper_ret_lduw_mmu helper_le_lduw_mmu
1304 # define helper_ret_ldsl_mmu helper_le_ldsl_mmu
1305 # define helper_ret_ldul_mmu helper_le_ldul_mmu
1306 # define helper_ret_ldl_mmu helper_le_ldul_mmu
1307 # define helper_ret_ldq_mmu helper_le_ldq_mmu
1308 # define helper_ret_stw_mmu helper_le_stw_mmu
1309 # define helper_ret_stl_mmu helper_le_stl_mmu
1310 # define helper_ret_stq_mmu helper_le_stq_mmu
1311 # define helper_ret_ldw_cmmu helper_le_ldw_cmmu
1312 # define helper_ret_ldl_cmmu helper_le_ldl_cmmu
1313 # define helper_ret_ldq_cmmu helper_le_ldq_cmmu
1314 #endif
1316 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
1317 uint32_t cmpv, uint32_t newv,
1318 TCGMemOpIdx oi, uintptr_t retaddr);
1319 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
1320 uint32_t cmpv, uint32_t newv,
1321 TCGMemOpIdx oi, uintptr_t retaddr);
1322 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
1323 uint32_t cmpv, uint32_t newv,
1324 TCGMemOpIdx oi, uintptr_t retaddr);
1325 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
1326 uint64_t cmpv, uint64_t newv,
1327 TCGMemOpIdx oi, uintptr_t retaddr);
1328 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
1329 uint32_t cmpv, uint32_t newv,
1330 TCGMemOpIdx oi, uintptr_t retaddr);
1331 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
1332 uint32_t cmpv, uint32_t newv,
1333 TCGMemOpIdx oi, uintptr_t retaddr);
1334 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
1335 uint64_t cmpv, uint64_t newv,
1336 TCGMemOpIdx oi, uintptr_t retaddr);
1338 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
1339 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \
1340 (CPUArchState *env, target_ulong addr, TYPE val, \
1341 TCGMemOpIdx oi, uintptr_t retaddr);
1343 #ifdef CONFIG_ATOMIC64
1344 #define GEN_ATOMIC_HELPER_ALL(NAME) \
1345 GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
1346 GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
1347 GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
1348 GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
1349 GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \
1350 GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \
1351 GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1352 #else
1353 #define GEN_ATOMIC_HELPER_ALL(NAME) \
1354 GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
1355 GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
1356 GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
1357 GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
1358 GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1359 #endif
1361 GEN_ATOMIC_HELPER_ALL(fetch_add)
1362 GEN_ATOMIC_HELPER_ALL(fetch_sub)
1363 GEN_ATOMIC_HELPER_ALL(fetch_and)
1364 GEN_ATOMIC_HELPER_ALL(fetch_or)
1365 GEN_ATOMIC_HELPER_ALL(fetch_xor)
1366 GEN_ATOMIC_HELPER_ALL(fetch_smin)
1367 GEN_ATOMIC_HELPER_ALL(fetch_umin)
1368 GEN_ATOMIC_HELPER_ALL(fetch_smax)
1369 GEN_ATOMIC_HELPER_ALL(fetch_umax)
1371 GEN_ATOMIC_HELPER_ALL(add_fetch)
1372 GEN_ATOMIC_HELPER_ALL(sub_fetch)
1373 GEN_ATOMIC_HELPER_ALL(and_fetch)
1374 GEN_ATOMIC_HELPER_ALL(or_fetch)
1375 GEN_ATOMIC_HELPER_ALL(xor_fetch)
1376 GEN_ATOMIC_HELPER_ALL(smin_fetch)
1377 GEN_ATOMIC_HELPER_ALL(umin_fetch)
1378 GEN_ATOMIC_HELPER_ALL(smax_fetch)
1379 GEN_ATOMIC_HELPER_ALL(umax_fetch)
1381 GEN_ATOMIC_HELPER_ALL(xchg)
1383 #undef GEN_ATOMIC_HELPER_ALL
1384 #undef GEN_ATOMIC_HELPER
1385 #endif /* CONFIG_SOFTMMU */
1388 * These aren't really a "proper" helpers because TCG cannot manage Int128.
1389 * However, use the same format as the others, for use by the backends.
1391 * The cmpxchg functions are only defined if HAVE_CMPXCHG128;
1392 * the ld/st functions are only defined if HAVE_ATOMIC128,
1393 * as defined by <qemu/atomic128.h>.
1395 Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
1396 Int128 cmpv, Int128 newv,
1397 TCGMemOpIdx oi, uintptr_t retaddr);
1398 Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
1399 Int128 cmpv, Int128 newv,
1400 TCGMemOpIdx oi, uintptr_t retaddr);
1402 Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
1403 TCGMemOpIdx oi, uintptr_t retaddr);
1404 Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
1405 TCGMemOpIdx oi, uintptr_t retaddr);
1406 void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1407 TCGMemOpIdx oi, uintptr_t retaddr);
1408 void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1409 TCGMemOpIdx oi, uintptr_t retaddr);
1411 #ifdef CONFIG_DEBUG_TCG
1412 void tcg_assert_listed_vecop(TCGOpcode);
1413 #else
1414 static inline void tcg_assert_listed_vecop(TCGOpcode op) { }
1415 #endif
1417 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n)
1419 #ifdef CONFIG_DEBUG_TCG
1420 const TCGOpcode *o = tcg_ctx->vecop_list;
1421 tcg_ctx->vecop_list = n;
1422 return o;
1423 #else
1424 return NULL;
1425 #endif
1428 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned);
1430 #endif /* TCG_H */