hw/arm/armv7m.c

   1 /*
   2  * ARMV7M System emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/arm/armv7m.h"
  12 #include "qapi/error.h"
  13 #include "qemu-common.h"
  14 #include "cpu.h"
  15 #include "hw/sysbus.h"
  16 #include "hw/arm/arm.h"
  17 #include "hw/loader.h"
  18 #include "elf.h"
  19 #include "sysemu/qtest.h"
  20 #include "qemu/error-report.h"
  21 #include "exec/address-spaces.h"
  22
  23 /* Bitbanded IO.  Each word corresponds to a single bit.  */
  24
  25 /* Get the byte address of the real memory for a bitband access.  */
  26 static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
  27 {
  28     return s->base | (offset & 0x1ffffff) >> 5;
  29 }
  30
  31 static MemTxResult bitband_read(void *opaque, hwaddr offset,
  32                                 uint64_t *data, unsigned size, MemTxAttrs attrs)
  33 {
  34     BitBandState *s = opaque;
  35     uint8_t buf[4];
  36     MemTxResult res;
  37     int bitpos, bit;
  38     hwaddr addr;
  39
  40     assert(size <= 4);
  41
  42     /* Find address in underlying memory and round down to multiple of size */
  43     addr = bitband_addr(s, offset) & (-size);
  44     res = address_space_read(&s->source_as, addr, attrs, buf, size);
  45     if (res) {
  46         return res;
  47     }
  48     /* Bit position in the N bytes read... */
  49     bitpos = (offset >> 2) & ((size * 8) - 1);
  50     /* ...converted to byte in buffer and bit in byte */
  51     bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
  52     *data = bit;
  53     return MEMTX_OK;
  54 }
  55
  56 static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
  57                                  unsigned size, MemTxAttrs attrs)
  58 {
  59     BitBandState *s = opaque;
  60     uint8_t buf[4];
  61     MemTxResult res;
  62     int bitpos, bit;
  63     hwaddr addr;
  64
  65     assert(size <= 4);
  66
  67     /* Find address in underlying memory and round down to multiple of size */
  68     addr = bitband_addr(s, offset) & (-size);
  69     res = address_space_read(&s->source_as, addr, attrs, buf, size);
  70     if (res) {
  71         return res;
  72     }
  73     /* Bit position in the N bytes read... */
  74     bitpos = (offset >> 2) & ((size * 8) - 1);
  75     /* ...converted to byte in buffer and bit in byte */
  76     bit = 1 << (bitpos & 7);
  77     if (value & 1) {
  78         buf[bitpos >> 3] |= bit;
  79     } else {
  80         buf[bitpos >> 3] &= ~bit;
  81     }
  82     return address_space_write(&s->source_as, addr, attrs, buf, size);
  83 }
  84
  85 static const MemoryRegionOps bitband_ops = {
  86     .read_with_attrs = bitband_read,
  87     .write_with_attrs = bitband_write,
  88     .endianness = DEVICE_NATIVE_ENDIAN,
  89     .impl.min_access_size = 1,
  90     .impl.max_access_size = 4,
  91     .valid.min_access_size = 1,
  92     .valid.max_access_size = 4,
  93 };
  94
  95 static void bitband_init(Object *obj)
  96 {
  97     BitBandState *s = BITBAND(obj);
  98     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
  99
 100     memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
 101                           "bitband", 0x02000000);
 102     sysbus_init_mmio(dev, &s->iomem);
 103 }
 104
 105 static void bitband_realize(DeviceState *dev, Error **errp)
 106 {
 107     BitBandState *s = BITBAND(dev);
 108
 109     if (!s->source_memory) {
 110         error_setg(errp, "source-memory property not set");
 111         return;
 112     }
 113
 114     address_space_init(&s->source_as, s->source_memory, "bitband-source");
 115 }
 116
 117 /* Board init.  */
 118
 119 static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
 120     0x20000000, 0x40000000
 121 };
 122
 123 static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
 124     0x22000000, 0x42000000
 125 };
 126
 127 static void armv7m_instance_init(Object *obj)
 128 {
 129     ARMv7MState *s = ARMV7M(obj);
 130     int i;
 131
 132     /* Can't init the cpu here, we don't yet know which model to use */
 133
 134     memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
 135
 136     object_initialize(&s->nvic, sizeof(s->nvic), TYPE_NVIC);
 137     qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
 138     object_property_add_alias(obj, "num-irq",
 139                               OBJECT(&s->nvic), "num-irq", &error_abort);
 140
 141     for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
 142         object_initialize(&s->bitband[i], sizeof(s->bitband[i]), TYPE_BITBAND);
 143         qdev_set_parent_bus(DEVICE(&s->bitband[i]), sysbus_get_default());
 144     }
 145 }
 146
 147 static void armv7m_realize(DeviceState *dev, Error **errp)
 148 {
 149     ARMv7MState *s = ARMV7M(dev);
 150     SysBusDevice *sbd;
 151     Error *err = NULL;
 152     int i;
 153
 154     if (!s->board_memory) {
 155         error_setg(errp, "memory property was not set");
 156         return;
 157     }
 158
 159     memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
 160
 161     s->cpu = ARM_CPU(object_new(s->cpu_type));
 162
 163     object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
 164                              &error_abort);
 165     object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
 166     if (err != NULL) {
 167         error_propagate(errp, err);
 168         return;
 169     }
 170
 171     /* Note that we must realize the NVIC after the CPU */
 172     object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
 173     if (err != NULL) {
 174         error_propagate(errp, err);
 175         return;
 176     }
 177
 178     /* Alias the NVIC's input and output GPIOs as our own so the board
 179      * code can wire them up. (We do this in realize because the
 180      * NVIC doesn't create the input GPIO array until realize.)
 181      */
 182     qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
 183     qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
 184
 185     /* Wire the NVIC up to the CPU */
 186     sbd = SYS_BUS_DEVICE(&s->nvic);
 187     sysbus_connect_irq(sbd, 0,
 188                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
 189     s->cpu->env.nvic = &s->nvic;
 190
 191     memory_region_add_subregion(&s->container, 0xe000e000,
 192                                 sysbus_mmio_get_region(sbd, 0));
 193
 194     for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
 195         Object *obj = OBJECT(&s->bitband[i]);
 196         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
 197
 198         object_property_set_int(obj, bitband_input_addr[i], "base", &err);
 199         if (err != NULL) {
 200             error_propagate(errp, err);
 201             return;
 202         }
 203         object_property_set_link(obj, OBJECT(s->board_memory),
 204                                  "source-memory", &error_abort);
 205         object_property_set_bool(obj, true, "realized", &err);
 206         if (err != NULL) {
 207             error_propagate(errp, err);
 208             return;
 209         }
 210
 211         memory_region_add_subregion(&s->container, bitband_output_addr[i],
 212                                     sysbus_mmio_get_region(sbd, 0));
 213     }
 214 }
 215
 216 static Property armv7m_properties[] = {
 217     DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type),
 218     DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
 219                      MemoryRegion *),
 220     DEFINE_PROP_END_OF_LIST(),
 221 };
 222
 223 static void armv7m_class_init(ObjectClass *klass, void *data)
 224 {
 225     DeviceClass *dc = DEVICE_CLASS(klass);
 226
 227     dc->realize = armv7m_realize;
 228     dc->props = armv7m_properties;
 229 }
 230
 231 static const TypeInfo armv7m_info = {
 232     .name = TYPE_ARMV7M,
 233     .parent = TYPE_SYS_BUS_DEVICE,
 234     .instance_size = sizeof(ARMv7MState),
 235     .instance_init = armv7m_instance_init,
 236     .class_init = armv7m_class_init,
 237 };
 238
 239 static void armv7m_reset(void *opaque)
 240 {
 241     ARMCPU *cpu = opaque;
 242
 243     cpu_reset(CPU(cpu));
 244 }
 245
 246 /* Init CPU and memory for a v7-M based board.
 247    mem_size is in bytes.
 248    Returns the ARMv7M device.  */
 249
 250 DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
 251                          const char *kernel_filename, const char *cpu_type)
 252 {
 253     DeviceState *armv7m;
 254
 255     armv7m = qdev_create(NULL, TYPE_ARMV7M);
 256     qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
 257     qdev_prop_set_string(armv7m, "cpu-type", cpu_type);
 258     object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),
 259                                      "memory", &error_abort);
 260     /* This will exit with an error if the user passed us a bad cpu_type */
 261     qdev_init_nofail(armv7m);
 262
 263     armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);
 264     return armv7m;
 265 }
 266
 267 void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
 268 {
 269     int image_size;
 270     uint64_t entry;
 271     uint64_t lowaddr;
 272     int big_endian;
 273
 274 #ifdef TARGET_WORDS_BIGENDIAN
 275     big_endian = 1;
 276 #else
 277     big_endian = 0;
 278 #endif
 279
 280     if (!kernel_filename && !qtest_enabled()) {
 281         fprintf(stderr, "Guest image must be specified (using -kernel)\n");
 282         exit(1);
 283     }
 284
 285     if (kernel_filename) {
 286         image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr,
 287                               NULL, big_endian, EM_ARM, 1, 0);
 288         if (image_size < 0) {
 289             image_size = load_image_targphys(kernel_filename, 0, mem_size);
 290             lowaddr = 0;
 291         }
 292         if (image_size < 0) {
 293             error_report("Could not load kernel '%s'", kernel_filename);
 294             exit(1);
 295         }
 296     }
 297
 298     /* CPU objects (unlike devices) are not automatically reset on system
 299      * reset, so we must always register a handler to do so. Unlike
 300      * A-profile CPUs, we don't need to do anything special in the
 301      * handler to arrange that it starts correctly.
 302      * This is arguably the wrong place to do this, but it matches the
 303      * way A-profile does it. Note that this means that every M profile
 304      * board must call this function!
 305      */
 306     qemu_register_reset(armv7m_reset, cpu);
 307 }
 308
 309 static Property bitband_properties[] = {
 310     DEFINE_PROP_UINT32("base", BitBandState, base, 0),
 311     DEFINE_PROP_LINK("source-memory", BitBandState, source_memory,
 312                      TYPE_MEMORY_REGION, MemoryRegion *),
 313     DEFINE_PROP_END_OF_LIST(),
 314 };
 315
 316 static void bitband_class_init(ObjectClass *klass, void *data)
 317 {
 318     DeviceClass *dc = DEVICE_CLASS(klass);
 319
 320     dc->realize = bitband_realize;
 321     dc->props = bitband_properties;
 322 }
 323
 324 static const TypeInfo bitband_info = {
 325     .name          = TYPE_BITBAND,
 326     .parent        = TYPE_SYS_BUS_DEVICE,
 327     .instance_size = sizeof(BitBandState),
 328     .instance_init = bitband_init,
 329     .class_init    = bitband_class_init,
 330 };
 331
 332 static void armv7m_register_types(void)
 333 {
 334     type_register_static(&bitband_info);
 335     type_register_static(&armv7m_info);
 336 }
 337
 338 type_init(armv7m_register_types)