hw/ppc/pnv_core.c

   1 /*
   2  * QEMU PowerPC PowerNV CPU Core model
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public License
   8  * as published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "sysemu/reset.h"
  22 #include "qapi/error.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25 #include "target/ppc/cpu.h"
  26 #include "hw/ppc/ppc.h"
  27 #include "hw/ppc/pnv.h"
  28 #include "hw/ppc/pnv_core.h"
  29 #include "hw/ppc/pnv_xscom.h"
  30 #include "hw/ppc/xics.h"
  31 #include "hw/qdev-properties.h"
  32
  33 static const char *pnv_core_cpu_typename(PnvCore *pc)
  34 {
  35     const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
  36     int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
  37     char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type);
  38     const char *cpu_type = object_class_get_name(object_class_by_name(s));
  39     g_free(s);
  40     return cpu_type;
  41 }
  42
  43 static void pnv_core_cpu_reset(PowerPCCPU *cpu, PnvChip *chip)
  44 {
  45     CPUState *cs = CPU(cpu);
  46     CPUPPCState *env = &cpu->env;
  47     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
  48
  49     cpu_reset(cs);
  50
  51     /*
  52      * the skiboot firmware elects a primary thread to initialize the
  53      * system and it can be any.
  54      */
  55     env->gpr[3] = PNV_FDT_ADDR;
  56     env->nip = 0x10;
  57     env->msr |= MSR_HVB; /* Hypervisor mode */
  58
  59     pcc->intc_reset(chip, cpu);
  60 }
  61
  62 /*
  63  * These values are read by the PowerNV HW monitors under Linux
  64  */
  65 #define PNV_XSCOM_EX_DTS_RESULT0     0x50000
  66 #define PNV_XSCOM_EX_DTS_RESULT1     0x50001
  67
  68 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr,
  69                                            unsigned int width)
  70 {
  71     uint32_t offset = addr >> 3;
  72     uint64_t val = 0;
  73
  74     /* The result should be 38 C */
  75     switch (offset) {
  76     case PNV_XSCOM_EX_DTS_RESULT0:
  77         val = 0x26f024f023f0000ull;
  78         break;
  79     case PNV_XSCOM_EX_DTS_RESULT1:
  80         val = 0x24f000000000000ull;
  81         break;
  82     default:
  83         qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
  84                   addr);
  85     }
  86
  87     return val;
  88 }
  89
  90 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val,
  91                                         unsigned int width)
  92 {
  93     qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
  94                   addr);
  95 }
  96
  97 static const MemoryRegionOps pnv_core_power8_xscom_ops = {
  98     .read = pnv_core_power8_xscom_read,
  99     .write = pnv_core_power8_xscom_write,
 100     .valid.min_access_size = 8,
 101     .valid.max_access_size = 8,
 102     .impl.min_access_size = 8,
 103     .impl.max_access_size = 8,
 104     .endianness = DEVICE_BIG_ENDIAN,
 105 };
 106
 107
 108 /*
 109  * POWER9 core controls
 110  */
 111 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
 112 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
 113
 114 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
 115                                            unsigned int width)
 116 {
 117     uint32_t offset = addr >> 3;
 118     uint64_t val = 0;
 119
 120     /* The result should be 38 C */
 121     switch (offset) {
 122     case PNV_XSCOM_EX_DTS_RESULT0:
 123         val = 0x26f024f023f0000ull;
 124         break;
 125     case PNV_XSCOM_EX_DTS_RESULT1:
 126         val = 0x24f000000000000ull;
 127         break;
 128     case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
 129     case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
 130         val = 0x0;
 131         break;
 132     default:
 133         qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
 134                   addr);
 135     }
 136
 137     return val;
 138 }
 139
 140 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
 141                                         unsigned int width)
 142 {
 143     uint32_t offset = addr >> 3;
 144
 145     switch (offset) {
 146     case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
 147     case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
 148         break;
 149     default:
 150         qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
 151                       addr);
 152     }
 153 }
 154
 155 static const MemoryRegionOps pnv_core_power9_xscom_ops = {
 156     .read = pnv_core_power9_xscom_read,
 157     .write = pnv_core_power9_xscom_write,
 158     .valid.min_access_size = 8,
 159     .valid.max_access_size = 8,
 160     .impl.min_access_size = 8,
 161     .impl.max_access_size = 8,
 162     .endianness = DEVICE_BIG_ENDIAN,
 163 };
 164
 165 static void pnv_core_cpu_realize(PowerPCCPU *cpu, PnvChip *chip, Error **errp)
 166 {
 167     CPUPPCState *env = &cpu->env;
 168     int core_pir;
 169     int thread_index = 0; /* TODO: TCG supports only one thread */
 170     ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
 171     Error *local_err = NULL;
 172     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 173
 174     object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
 175     if (local_err) {
 176         error_propagate(errp, local_err);
 177         return;
 178     }
 179
 180     pcc->intc_create(chip, cpu, &local_err);
 181     if (local_err) {
 182         error_propagate(errp, local_err);
 183         return;
 184     }
 185
 186     core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
 187
 188     /*
 189      * The PIR of a thread is the core PIR + the thread index. We will
 190      * need to find a way to get the thread index when TCG supports
 191      * more than 1. We could use the object name ?
 192      */
 193     pir->default_value = core_pir + thread_index;
 194
 195     /* Set time-base frequency to 512 MHz */
 196     cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
 197 }
 198
 199 static void pnv_core_reset(void *dev)
 200 {
 201     CPUCore *cc = CPU_CORE(dev);
 202     PnvCore *pc = PNV_CORE(dev);
 203     int i;
 204
 205     for (i = 0; i < cc->nr_threads; i++) {
 206         pnv_core_cpu_reset(pc->threads[i], pc->chip);
 207     }
 208 }
 209
 210 static void pnv_core_realize(DeviceState *dev, Error **errp)
 211 {
 212     PnvCore *pc = PNV_CORE(OBJECT(dev));
 213     PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc);
 214     CPUCore *cc = CPU_CORE(OBJECT(dev));
 215     const char *typename = pnv_core_cpu_typename(pc);
 216     Error *local_err = NULL;
 217     void *obj;
 218     int i, j;
 219     char name[32];
 220
 221     assert(pc->chip);
 222
 223     pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
 224     for (i = 0; i < cc->nr_threads; i++) {
 225         PowerPCCPU *cpu;
 226
 227         obj = object_new(typename);
 228         cpu = POWERPC_CPU(obj);
 229
 230         pc->threads[i] = POWERPC_CPU(obj);
 231
 232         snprintf(name, sizeof(name), "thread[%d]", i);
 233         object_property_add_child(OBJECT(pc), name, obj, &error_abort);
 234         object_property_add_alias(obj, "core-pir", OBJECT(pc),
 235                                   "pir", &error_abort);
 236
 237         cpu->machine_data = g_new0(PnvCPUState, 1);
 238
 239         object_unref(obj);
 240     }
 241
 242     for (j = 0; j < cc->nr_threads; j++) {
 243         pnv_core_cpu_realize(pc->threads[j], pc->chip, &local_err);
 244         if (local_err) {
 245             goto err;
 246         }
 247     }
 248
 249     snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
 250     pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
 251                           pc, name, PNV_XSCOM_EX_SIZE);
 252
 253     qemu_register_reset(pnv_core_reset, pc);
 254     return;
 255
 256 err:
 257     while (--i >= 0) {
 258         obj = OBJECT(pc->threads[i]);
 259         object_unparent(obj);
 260     }
 261     g_free(pc->threads);
 262     error_propagate(errp, local_err);
 263 }
 264
 265 static void pnv_core_cpu_unrealize(PowerPCCPU *cpu, PnvChip *chip)
 266 {
 267     PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
 268     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 269
 270     pcc->intc_destroy(chip, cpu);
 271     cpu_remove_sync(CPU(cpu));
 272     cpu->machine_data = NULL;
 273     g_free(pnv_cpu);
 274     object_unparent(OBJECT(cpu));
 275 }
 276
 277 static void pnv_core_unrealize(DeviceState *dev, Error **errp)
 278 {
 279     PnvCore *pc = PNV_CORE(dev);
 280     CPUCore *cc = CPU_CORE(dev);
 281     int i;
 282
 283     qemu_unregister_reset(pnv_core_reset, pc);
 284
 285     for (i = 0; i < cc->nr_threads; i++) {
 286         pnv_core_cpu_unrealize(pc->threads[i], pc->chip);
 287     }
 288     g_free(pc->threads);
 289 }
 290
 291 static Property pnv_core_properties[] = {
 292     DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
 293     DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *),
 294     DEFINE_PROP_END_OF_LIST(),
 295 };
 296
 297 static void pnv_core_power8_class_init(ObjectClass *oc, void *data)
 298 {
 299     PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
 300
 301     pcc->xscom_ops = &pnv_core_power8_xscom_ops;
 302 }
 303
 304 static void pnv_core_power9_class_init(ObjectClass *oc, void *data)
 305 {
 306     PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
 307
 308     pcc->xscom_ops = &pnv_core_power9_xscom_ops;
 309 }
 310
 311 static void pnv_core_class_init(ObjectClass *oc, void *data)
 312 {
 313     DeviceClass *dc = DEVICE_CLASS(oc);
 314
 315     dc->realize = pnv_core_realize;
 316     dc->unrealize = pnv_core_unrealize;
 317     dc->props = pnv_core_properties;
 318 }
 319
 320 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
 321     {                                           \
 322         .parent = TYPE_PNV_CORE,                \
 323         .name = PNV_CORE_TYPE_NAME(cpu_model),  \
 324         .class_init = pnv_core_##family##_class_init, \
 325     }
 326
 327 static const TypeInfo pnv_core_infos[] = {
 328     {
 329         .name           = TYPE_PNV_CORE,
 330         .parent         = TYPE_CPU_CORE,
 331         .instance_size  = sizeof(PnvCore),
 332         .class_size     = sizeof(PnvCoreClass),
 333         .class_init = pnv_core_class_init,
 334         .abstract       = true,
 335     },
 336     DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"),
 337     DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
 338     DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
 339     DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
 340 };
 341
 342 DEFINE_TYPES(pnv_core_infos)
 343
 344 /*
 345  * POWER9 Quads
 346  */
 347
 348 #define P9X_EX_NCU_SPEC_BAR                     0x11010
 349
 350 static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
 351                                     unsigned int width)
 352 {
 353     uint32_t offset = addr >> 3;
 354     uint64_t val = -1;
 355
 356     switch (offset) {
 357     case P9X_EX_NCU_SPEC_BAR:
 358     case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
 359         val = 0;
 360         break;
 361     default:
 362         qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
 363                       offset);
 364     }
 365
 366     return val;
 367 }
 368
 369 static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
 370                                  unsigned int width)
 371 {
 372     uint32_t offset = addr >> 3;
 373
 374     switch (offset) {
 375     case P9X_EX_NCU_SPEC_BAR:
 376     case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
 377         break;
 378     default:
 379         qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
 380                   offset);
 381     }
 382 }
 383
 384 static const MemoryRegionOps pnv_quad_xscom_ops = {
 385     .read = pnv_quad_xscom_read,
 386     .write = pnv_quad_xscom_write,
 387     .valid.min_access_size = 8,
 388     .valid.max_access_size = 8,
 389     .impl.min_access_size = 8,
 390     .impl.max_access_size = 8,
 391     .endianness = DEVICE_BIG_ENDIAN,
 392 };
 393
 394 static void pnv_quad_realize(DeviceState *dev, Error **errp)
 395 {
 396     PnvQuad *eq = PNV_QUAD(dev);
 397     char name[32];
 398
 399     snprintf(name, sizeof(name), "xscom-quad.%d", eq->id);
 400     pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
 401                           eq, name, PNV9_XSCOM_EQ_SIZE);
 402 }
 403
 404 static Property pnv_quad_properties[] = {
 405     DEFINE_PROP_UINT32("id", PnvQuad, id, 0),
 406     DEFINE_PROP_END_OF_LIST(),
 407 };
 408
 409 static void pnv_quad_class_init(ObjectClass *oc, void *data)
 410 {
 411     DeviceClass *dc = DEVICE_CLASS(oc);
 412
 413     dc->realize = pnv_quad_realize;
 414     dc->props = pnv_quad_properties;
 415 }
 416
 417 static const TypeInfo pnv_quad_info = {
 418     .name          = TYPE_PNV_QUAD,
 419     .parent        = TYPE_DEVICE,
 420     .instance_size = sizeof(PnvQuad),
 421     .class_init    = pnv_quad_class_init,
 422 };
 423
 424 static void pnv_core_register_types(void)
 425 {
 426     type_register_static(&pnv_quad_info);
 427 }
 428
 429 type_init(pnv_core_register_types)