ppc/pnv: Loop on the threads of the chip to find a matching NVT
[qemu/ar7.git] / hw / intc / openpic_kvm.c
blobc09bebedd16846cdc83e7bd9fe41d7034285e4cc
1 /*
2 * KVM in-kernel OpenPIC
4 * Copyright 2013 Freescale Semiconductor, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "cpu.h"
28 #include <sys/ioctl.h>
29 #include "exec/address-spaces.h"
30 #include "hw/ppc/openpic.h"
31 #include "hw/ppc/openpic_kvm.h"
32 #include "hw/pci/msi.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/sysbus.h"
35 #include "sysemu/kvm.h"
36 #include "qemu/log.h"
37 #include "qemu/module.h"
39 #define GCR_RESET 0x80000000
41 #define KVM_OPENPIC(obj) \
42 OBJECT_CHECK(KVMOpenPICState, (obj), TYPE_KVM_OPENPIC)
44 typedef struct KVMOpenPICState {
45 /*< private >*/
46 SysBusDevice parent_obj;
47 /*< public >*/
49 MemoryRegion mem;
50 MemoryListener mem_listener;
51 uint32_t fd;
52 uint32_t model;
53 hwaddr mapped;
54 } KVMOpenPICState;
56 static void kvm_openpic_set_irq(void *opaque, int n_IRQ, int level)
58 kvm_set_irq(kvm_state, n_IRQ, level);
61 static void kvm_openpic_write(void *opaque, hwaddr addr, uint64_t val,
62 unsigned size)
64 KVMOpenPICState *opp = opaque;
65 struct kvm_device_attr attr;
66 uint32_t val32 = val;
67 int ret;
69 attr.group = KVM_DEV_MPIC_GRP_REGISTER;
70 attr.attr = addr;
71 attr.addr = (uint64_t)(unsigned long)&val32;
73 ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
74 if (ret < 0) {
75 qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
76 strerror(errno), attr.attr);
80 static void kvm_openpic_reset(DeviceState *d)
82 KVMOpenPICState *opp = KVM_OPENPIC(d);
84 /* Trigger the GCR.RESET bit to reset the PIC */
85 kvm_openpic_write(opp, 0x1020, GCR_RESET, sizeof(uint32_t));
88 static uint64_t kvm_openpic_read(void *opaque, hwaddr addr, unsigned size)
90 KVMOpenPICState *opp = opaque;
91 struct kvm_device_attr attr;
92 uint32_t val = 0xdeadbeef;
93 int ret;
95 attr.group = KVM_DEV_MPIC_GRP_REGISTER;
96 attr.attr = addr;
97 attr.addr = (uint64_t)(unsigned long)&val;
99 ret = ioctl(opp->fd, KVM_GET_DEVICE_ATTR, &attr);
100 if (ret < 0) {
101 qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
102 strerror(errno), attr.attr);
103 return 0;
106 return val;
109 static const MemoryRegionOps kvm_openpic_mem_ops = {
110 .write = kvm_openpic_write,
111 .read = kvm_openpic_read,
112 .endianness = DEVICE_BIG_ENDIAN,
113 .impl = {
114 .min_access_size = 4,
115 .max_access_size = 4,
119 static void kvm_openpic_region_add(MemoryListener *listener,
120 MemoryRegionSection *section)
122 KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
123 mem_listener);
124 struct kvm_device_attr attr;
125 uint64_t reg_base;
126 int ret;
128 /* Ignore events on regions that are not us */
129 if (section->mr != &opp->mem) {
130 return;
133 if (opp->mapped) {
135 * We can only map the MPIC once. Since we are already mapped,
136 * the best we can do is ignore new maps.
138 return;
141 reg_base = section->offset_within_address_space;
142 opp->mapped = reg_base;
144 attr.group = KVM_DEV_MPIC_GRP_MISC;
145 attr.attr = KVM_DEV_MPIC_BASE_ADDR;
146 attr.addr = (uint64_t)(unsigned long)&reg_base;
148 ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
149 if (ret < 0) {
150 fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
151 strerror(errno), reg_base);
155 static void kvm_openpic_region_del(MemoryListener *listener,
156 MemoryRegionSection *section)
158 KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
159 mem_listener);
160 struct kvm_device_attr attr;
161 uint64_t reg_base = 0;
162 int ret;
164 /* Ignore events on regions that are not us */
165 if (section->mr != &opp->mem) {
166 return;
169 if (section->offset_within_address_space != opp->mapped) {
171 * We can only map the MPIC once. This mapping was a secondary
172 * one that we couldn't fulfill. Ignore it.
174 return;
176 opp->mapped = 0;
178 attr.group = KVM_DEV_MPIC_GRP_MISC;
179 attr.attr = KVM_DEV_MPIC_BASE_ADDR;
180 attr.addr = (uint64_t)(unsigned long)&reg_base;
182 ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
183 if (ret < 0) {
184 fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
185 strerror(errno), reg_base);
189 static void kvm_openpic_init(Object *obj)
191 KVMOpenPICState *opp = KVM_OPENPIC(obj);
193 memory_region_init_io(&opp->mem, OBJECT(opp), &kvm_openpic_mem_ops, opp,
194 "kvm-openpic", 0x40000);
197 static void kvm_openpic_realize(DeviceState *dev, Error **errp)
199 SysBusDevice *d = SYS_BUS_DEVICE(dev);
200 KVMOpenPICState *opp = KVM_OPENPIC(dev);
201 KVMState *s = kvm_state;
202 int kvm_openpic_model;
203 struct kvm_create_device cd = {0};
204 int ret, i;
206 if (!kvm_check_extension(s, KVM_CAP_DEVICE_CTRL)) {
207 error_setg(errp, "Kernel is lacking Device Control API");
208 return;
211 switch (opp->model) {
212 case OPENPIC_MODEL_FSL_MPIC_20:
213 kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_20;
214 break;
216 case OPENPIC_MODEL_FSL_MPIC_42:
217 kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_42;
218 break;
220 default:
221 error_setg(errp, "Unsupported OpenPIC model %" PRIu32, opp->model);
222 return;
225 cd.type = kvm_openpic_model;
226 ret = kvm_vm_ioctl(s, KVM_CREATE_DEVICE, &cd);
227 if (ret < 0) {
228 error_setg(errp, "Can't create device %d: %s",
229 cd.type, strerror(errno));
230 return;
232 opp->fd = cd.fd;
234 sysbus_init_mmio(d, &opp->mem);
235 qdev_init_gpio_in(dev, kvm_openpic_set_irq, OPENPIC_MAX_IRQ);
237 opp->mem_listener.region_add = kvm_openpic_region_add;
238 opp->mem_listener.region_del = kvm_openpic_region_del;
239 memory_listener_register(&opp->mem_listener, &address_space_memory);
241 /* indicate pic capabilities */
242 msi_nonbroken = true;
243 kvm_kernel_irqchip = true;
244 kvm_async_interrupts_allowed = true;
246 /* set up irq routing */
247 kvm_init_irq_routing(kvm_state);
248 for (i = 0; i < 256; ++i) {
249 kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
252 kvm_msi_via_irqfd_allowed = true;
253 kvm_gsi_routing_allowed = true;
255 kvm_irqchip_commit_routes(s);
258 int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs)
260 KVMOpenPICState *opp = KVM_OPENPIC(d);
262 return kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_MPIC, 0, opp->fd,
263 kvm_arch_vcpu_id(cs));
266 static Property kvm_openpic_properties[] = {
267 DEFINE_PROP_UINT32("model", KVMOpenPICState, model,
268 OPENPIC_MODEL_FSL_MPIC_20),
269 DEFINE_PROP_END_OF_LIST(),
272 static void kvm_openpic_class_init(ObjectClass *oc, void *data)
274 DeviceClass *dc = DEVICE_CLASS(oc);
276 dc->realize = kvm_openpic_realize;
277 dc->props = kvm_openpic_properties;
278 dc->reset = kvm_openpic_reset;
279 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
282 static const TypeInfo kvm_openpic_info = {
283 .name = TYPE_KVM_OPENPIC,
284 .parent = TYPE_SYS_BUS_DEVICE,
285 .instance_size = sizeof(KVMOpenPICState),
286 .instance_init = kvm_openpic_init,
287 .class_init = kvm_openpic_class_init,
290 static void kvm_openpic_register_types(void)
292 type_register_static(&kvm_openpic_info);
295 type_init(kvm_openpic_register_types)