ppc/pnv: Loop on the threads of the chip to find a matching NVT
[qemu/ar7.git] / hw / intc / arm_gic_kvm.c
blob9deb15e7e691edb0b0659407119e7d819b335fbc
1 /*
2 * ARM Generic Interrupt Controller using KVM in-kernel support
4 * Copyright (c) 2012 Linaro Limited
5 * Written by Peter Maydell
6 * Save/Restore logic added by Christoffer Dall.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "qemu/module.h"
25 #include "cpu.h"
26 #include "hw/sysbus.h"
27 #include "migration/blocker.h"
28 #include "sysemu/kvm.h"
29 #include "kvm_arm.h"
30 #include "gic_internal.h"
31 #include "vgic_common.h"
33 #define TYPE_KVM_ARM_GIC "kvm-arm-gic"
34 #define KVM_ARM_GIC(obj) \
35 OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC)
36 #define KVM_ARM_GIC_CLASS(klass) \
37 OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC)
38 #define KVM_ARM_GIC_GET_CLASS(obj) \
39 OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC)
41 typedef struct KVMARMGICClass {
42 ARMGICCommonClass parent_class;
43 DeviceRealize parent_realize;
44 void (*parent_reset)(DeviceState *dev);
45 } KVMARMGICClass;
47 void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level)
49 /* Meaning of the 'irq' parameter:
50 * [0..N-1] : external interrupts
51 * [N..N+31] : PPI (internal) interrupts for CPU 0
52 * [N+32..N+63] : PPI (internal interrupts for CPU 1
53 * ...
54 * Convert this to the kernel's desired encoding, which
55 * has separate fields in the irq number for type,
56 * CPU number and interrupt number.
58 int irqtype, cpu;
60 if (irq < (num_irq - GIC_INTERNAL)) {
61 /* External interrupt. The kernel numbers these like the GIC
62 * hardware, with external interrupt IDs starting after the
63 * internal ones.
65 irqtype = KVM_ARM_IRQ_TYPE_SPI;
66 cpu = 0;
67 irq += GIC_INTERNAL;
68 } else {
69 /* Internal interrupt: decode into (cpu, interrupt id) */
70 irqtype = KVM_ARM_IRQ_TYPE_PPI;
71 irq -= (num_irq - GIC_INTERNAL);
72 cpu = irq / GIC_INTERNAL;
73 irq %= GIC_INTERNAL;
75 kvm_arm_set_irq(cpu, irqtype, irq, !!level);
78 static void kvm_arm_gicv2_set_irq(void *opaque, int irq, int level)
80 GICState *s = (GICState *)opaque;
82 kvm_arm_gic_set_irq(s->num_irq, irq, level);
85 static bool kvm_arm_gic_can_save_restore(GICState *s)
87 return s->dev_fd >= 0;
90 #define KVM_VGIC_ATTR(offset, cpu) \
91 ((((uint64_t)(cpu) << KVM_DEV_ARM_VGIC_CPUID_SHIFT) & \
92 KVM_DEV_ARM_VGIC_CPUID_MASK) | \
93 (((uint64_t)(offset) << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) & \
94 KVM_DEV_ARM_VGIC_OFFSET_MASK))
96 static void kvm_gicd_access(GICState *s, int offset, int cpu,
97 uint32_t *val, bool write)
99 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
100 KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort);
103 static void kvm_gicc_access(GICState *s, int offset, int cpu,
104 uint32_t *val, bool write)
106 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
107 KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort);
110 #define for_each_irq_reg(_ctr, _max_irq, _field_width) \
111 for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++)
114 * Translate from the in-kernel field for an IRQ value to/from the qemu
115 * representation.
117 typedef void (*vgic_translate_fn)(GICState *s, int irq, int cpu,
118 uint32_t *field, bool to_kernel);
120 /* synthetic translate function used for clear/set registers to completely
121 * clear a setting using a clear-register before setting the remaining bits
122 * using a set-register */
123 static void translate_clear(GICState *s, int irq, int cpu,
124 uint32_t *field, bool to_kernel)
126 if (to_kernel) {
127 *field = ~0;
128 } else {
129 /* does not make sense: qemu model doesn't use set/clear regs */
130 abort();
134 static void translate_group(GICState *s, int irq, int cpu,
135 uint32_t *field, bool to_kernel)
137 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
139 if (to_kernel) {
140 *field = GIC_DIST_TEST_GROUP(irq, cm);
141 } else {
142 if (*field & 1) {
143 GIC_DIST_SET_GROUP(irq, cm);
148 static void translate_enabled(GICState *s, int irq, int cpu,
149 uint32_t *field, bool to_kernel)
151 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
153 if (to_kernel) {
154 *field = GIC_DIST_TEST_ENABLED(irq, cm);
155 } else {
156 if (*field & 1) {
157 GIC_DIST_SET_ENABLED(irq, cm);
162 static void translate_pending(GICState *s, int irq, int cpu,
163 uint32_t *field, bool to_kernel)
165 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
167 if (to_kernel) {
168 *field = gic_test_pending(s, irq, cm);
169 } else {
170 if (*field & 1) {
171 GIC_DIST_SET_PENDING(irq, cm);
172 /* TODO: Capture is level-line is held high in the kernel */
177 static void translate_active(GICState *s, int irq, int cpu,
178 uint32_t *field, bool to_kernel)
180 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
182 if (to_kernel) {
183 *field = GIC_DIST_TEST_ACTIVE(irq, cm);
184 } else {
185 if (*field & 1) {
186 GIC_DIST_SET_ACTIVE(irq, cm);
191 static void translate_trigger(GICState *s, int irq, int cpu,
192 uint32_t *field, bool to_kernel)
194 if (to_kernel) {
195 *field = (GIC_DIST_TEST_EDGE_TRIGGER(irq)) ? 0x2 : 0x0;
196 } else {
197 if (*field & 0x2) {
198 GIC_DIST_SET_EDGE_TRIGGER(irq);
203 static void translate_priority(GICState *s, int irq, int cpu,
204 uint32_t *field, bool to_kernel)
206 if (to_kernel) {
207 *field = GIC_DIST_GET_PRIORITY(irq, cpu) & 0xff;
208 } else {
209 gic_dist_set_priority(s, cpu, irq,
210 *field & 0xff, MEMTXATTRS_UNSPECIFIED);
214 static void translate_targets(GICState *s, int irq, int cpu,
215 uint32_t *field, bool to_kernel)
217 if (to_kernel) {
218 *field = s->irq_target[irq] & 0xff;
219 } else {
220 s->irq_target[irq] = *field & 0xff;
224 static void translate_sgisource(GICState *s, int irq, int cpu,
225 uint32_t *field, bool to_kernel)
227 if (to_kernel) {
228 *field = s->sgi_pending[irq][cpu] & 0xff;
229 } else {
230 s->sgi_pending[irq][cpu] = *field & 0xff;
234 /* Read a register group from the kernel VGIC */
235 static void kvm_dist_get(GICState *s, uint32_t offset, int width,
236 int maxirq, vgic_translate_fn translate_fn)
238 uint32_t reg;
239 int i;
240 int j;
241 int irq;
242 int cpu;
243 int regsz = 32 / width; /* irqs per kernel register */
244 uint32_t field;
246 for_each_irq_reg(i, maxirq, width) {
247 irq = i * regsz;
248 cpu = 0;
249 while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
250 kvm_gicd_access(s, offset, cpu, &reg, false);
251 for (j = 0; j < regsz; j++) {
252 field = extract32(reg, j * width, width);
253 translate_fn(s, irq + j, cpu, &field, false);
256 cpu++;
258 offset += 4;
262 /* Write a register group to the kernel VGIC */
263 static void kvm_dist_put(GICState *s, uint32_t offset, int width,
264 int maxirq, vgic_translate_fn translate_fn)
266 uint32_t reg;
267 int i;
268 int j;
269 int irq;
270 int cpu;
271 int regsz = 32 / width; /* irqs per kernel register */
272 uint32_t field;
274 for_each_irq_reg(i, maxirq, width) {
275 irq = i * regsz;
276 cpu = 0;
277 while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
278 reg = 0;
279 for (j = 0; j < regsz; j++) {
280 translate_fn(s, irq + j, cpu, &field, true);
281 reg = deposit32(reg, j * width, width, field);
283 kvm_gicd_access(s, offset, cpu, &reg, true);
285 cpu++;
287 offset += 4;
291 static void kvm_arm_gic_put(GICState *s)
293 uint32_t reg;
294 int i;
295 int cpu;
296 int num_cpu;
297 int num_irq;
299 /* Note: We do the restore in a slightly different order than the save
300 * (where the order doesn't matter and is simply ordered according to the
301 * register offset values */
303 /*****************************************************************
304 * Distributor State
307 /* s->ctlr -> GICD_CTLR */
308 reg = s->ctlr;
309 kvm_gicd_access(s, 0x0, 0, &reg, true);
311 /* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */
312 kvm_gicd_access(s, 0x4, 0, &reg, false);
313 num_irq = ((reg & 0x1f) + 1) * 32;
314 num_cpu = ((reg & 0xe0) >> 5) + 1;
316 if (num_irq < s->num_irq) {
317 fprintf(stderr, "Restoring %u IRQs, but kernel supports max %d\n",
318 s->num_irq, num_irq);
319 abort();
320 } else if (num_cpu != s->num_cpu) {
321 fprintf(stderr, "Restoring %u CPU interfaces, kernel only has %d\n",
322 s->num_cpu, num_cpu);
323 /* Did we not create the VCPUs in the kernel yet? */
324 abort();
327 /* TODO: Consider checking compatibility with the IIDR ? */
329 /* irq_state[n].enabled -> GICD_ISENABLERn */
330 kvm_dist_put(s, 0x180, 1, s->num_irq, translate_clear);
331 kvm_dist_put(s, 0x100, 1, s->num_irq, translate_enabled);
333 /* irq_state[n].group -> GICD_IGROUPRn */
334 kvm_dist_put(s, 0x80, 1, s->num_irq, translate_group);
336 /* s->irq_target[irq] -> GICD_ITARGETSRn
337 * (restore targets before pending to ensure the pending state is set on
338 * the appropriate CPU interfaces in the kernel) */
339 kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
341 /* irq_state[n].trigger -> GICD_ICFGRn
342 * (restore configuration registers before pending IRQs so we treat
343 * level/edge correctly) */
344 kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
346 /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
347 kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
348 kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);
350 /* irq_state[n].active -> GICD_ISACTIVERn */
351 kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
352 kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);
355 /* s->priorityX[irq] -> ICD_IPRIORITYRn */
356 kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);
358 /* s->sgi_pending -> ICD_CPENDSGIRn */
359 kvm_dist_put(s, 0xf10, 8, GIC_NR_SGIS, translate_clear);
360 kvm_dist_put(s, 0xf20, 8, GIC_NR_SGIS, translate_sgisource);
363 /*****************************************************************
364 * CPU Interface(s) State
367 for (cpu = 0; cpu < s->num_cpu; cpu++) {
368 /* s->cpu_ctlr[cpu] -> GICC_CTLR */
369 reg = s->cpu_ctlr[cpu];
370 kvm_gicc_access(s, 0x00, cpu, &reg, true);
372 /* s->priority_mask[cpu] -> GICC_PMR */
373 reg = (s->priority_mask[cpu] & 0xff);
374 kvm_gicc_access(s, 0x04, cpu, &reg, true);
376 /* s->bpr[cpu] -> GICC_BPR */
377 reg = (s->bpr[cpu] & 0x7);
378 kvm_gicc_access(s, 0x08, cpu, &reg, true);
380 /* s->abpr[cpu] -> GICC_ABPR */
381 reg = (s->abpr[cpu] & 0x7);
382 kvm_gicc_access(s, 0x1c, cpu, &reg, true);
384 /* s->apr[n][cpu] -> GICC_APRn */
385 for (i = 0; i < 4; i++) {
386 reg = s->apr[i][cpu];
387 kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, true);
392 static void kvm_arm_gic_get(GICState *s)
394 uint32_t reg;
395 int i;
396 int cpu;
398 /*****************************************************************
399 * Distributor State
402 /* GICD_CTLR -> s->ctlr */
403 kvm_gicd_access(s, 0x0, 0, &reg, false);
404 s->ctlr = reg;
406 /* Sanity checking on GICD_TYPER -> s->num_irq, s->num_cpu */
407 kvm_gicd_access(s, 0x4, 0, &reg, false);
408 s->num_irq = ((reg & 0x1f) + 1) * 32;
409 s->num_cpu = ((reg & 0xe0) >> 5) + 1;
411 if (s->num_irq > GIC_MAXIRQ) {
412 fprintf(stderr, "Too many IRQs reported from the kernel: %d\n",
413 s->num_irq);
414 abort();
417 /* GICD_IIDR -> ? */
418 kvm_gicd_access(s, 0x8, 0, &reg, false);
420 /* Clear all the IRQ settings */
421 for (i = 0; i < s->num_irq; i++) {
422 memset(&s->irq_state[i], 0, sizeof(s->irq_state[0]));
425 /* GICD_IGROUPRn -> irq_state[n].group */
426 kvm_dist_get(s, 0x80, 1, s->num_irq, translate_group);
428 /* GICD_ISENABLERn -> irq_state[n].enabled */
429 kvm_dist_get(s, 0x100, 1, s->num_irq, translate_enabled);
431 /* GICD_ISPENDRn -> irq_state[n].pending + irq_state[n].level */
432 kvm_dist_get(s, 0x200, 1, s->num_irq, translate_pending);
434 /* GICD_ISACTIVERn -> irq_state[n].active */
435 kvm_dist_get(s, 0x300, 1, s->num_irq, translate_active);
437 /* GICD_ICFRn -> irq_state[n].trigger */
438 kvm_dist_get(s, 0xc00, 2, s->num_irq, translate_trigger);
440 /* GICD_IPRIORITYRn -> s->priorityX[irq] */
441 kvm_dist_get(s, 0x400, 8, s->num_irq, translate_priority);
443 /* GICD_ITARGETSRn -> s->irq_target[irq] */
444 kvm_dist_get(s, 0x800, 8, s->num_irq, translate_targets);
446 /* GICD_CPENDSGIRn -> s->sgi_pending */
447 kvm_dist_get(s, 0xf10, 8, GIC_NR_SGIS, translate_sgisource);
450 /*****************************************************************
451 * CPU Interface(s) State
454 for (cpu = 0; cpu < s->num_cpu; cpu++) {
455 /* GICC_CTLR -> s->cpu_ctlr[cpu] */
456 kvm_gicc_access(s, 0x00, cpu, &reg, false);
457 s->cpu_ctlr[cpu] = reg;
459 /* GICC_PMR -> s->priority_mask[cpu] */
460 kvm_gicc_access(s, 0x04, cpu, &reg, false);
461 s->priority_mask[cpu] = (reg & 0xff);
463 /* GICC_BPR -> s->bpr[cpu] */
464 kvm_gicc_access(s, 0x08, cpu, &reg, false);
465 s->bpr[cpu] = (reg & 0x7);
467 /* GICC_ABPR -> s->abpr[cpu] */
468 kvm_gicc_access(s, 0x1c, cpu, &reg, false);
469 s->abpr[cpu] = (reg & 0x7);
471 /* GICC_APRn -> s->apr[n][cpu] */
472 for (i = 0; i < 4; i++) {
473 kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, false);
474 s->apr[i][cpu] = reg;
479 static void kvm_arm_gic_reset(DeviceState *dev)
481 GICState *s = ARM_GIC_COMMON(dev);
482 KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
484 kgc->parent_reset(dev);
486 if (kvm_arm_gic_can_save_restore(s)) {
487 kvm_arm_gic_put(s);
491 static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
493 int i;
494 GICState *s = KVM_ARM_GIC(dev);
495 KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
496 Error *local_err = NULL;
497 int ret;
499 kgc->parent_realize(dev, &local_err);
500 if (local_err) {
501 error_propagate(errp, local_err);
502 return;
505 if (s->security_extn) {
506 error_setg(errp, "the in-kernel VGIC does not implement the "
507 "security extensions");
508 return;
511 if (s->virt_extn) {
512 error_setg(errp, "the in-kernel VGIC does not implement the "
513 "virtualization extensions");
514 return;
517 if (!kvm_arm_gic_can_save_restore(s)) {
518 error_setg(&s->migration_blocker, "This operating system kernel does "
519 "not support vGICv2 migration");
520 migrate_add_blocker(s->migration_blocker, &local_err);
521 if (local_err) {
522 error_propagate(errp, local_err);
523 error_free(s->migration_blocker);
524 return;
528 gic_init_irqs_and_mmio(s, kvm_arm_gicv2_set_irq, NULL, NULL);
530 for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
531 qemu_irq irq = qdev_get_gpio_in(dev, i);
532 kvm_irqchip_set_qemuirq_gsi(kvm_state, irq, i);
535 /* Try to create the device via the device control API */
536 s->dev_fd = -1;
537 ret = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V2, false);
538 if (ret >= 0) {
539 s->dev_fd = ret;
541 /* Newstyle API is used, we may have attributes */
542 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) {
543 uint32_t numirqs = s->num_irq;
544 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0,
545 &numirqs, true, &error_abort);
547 /* Tell the kernel to complete VGIC initialization now */
548 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
549 KVM_DEV_ARM_VGIC_CTRL_INIT)) {
550 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
551 KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true,
552 &error_abort);
554 } else if (ret != -ENODEV && ret != -ENOTSUP) {
555 error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
556 return;
559 /* Distributor */
560 kvm_arm_register_device(&s->iomem,
561 (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
562 | KVM_VGIC_V2_ADDR_TYPE_DIST,
563 KVM_DEV_ARM_VGIC_GRP_ADDR,
564 KVM_VGIC_V2_ADDR_TYPE_DIST,
565 s->dev_fd, 0);
566 /* CPU interface for current core. Unlike arm_gic, we don't
567 * provide the "interface for core #N" memory regions, because
568 * cores with a VGIC don't have those.
570 kvm_arm_register_device(&s->cpuiomem[0],
571 (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
572 | KVM_VGIC_V2_ADDR_TYPE_CPU,
573 KVM_DEV_ARM_VGIC_GRP_ADDR,
574 KVM_VGIC_V2_ADDR_TYPE_CPU,
575 s->dev_fd, 0);
577 if (kvm_has_gsi_routing()) {
578 /* set up irq routing */
579 for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
580 kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
583 kvm_gsi_routing_allowed = true;
585 kvm_irqchip_commit_routes(kvm_state);
589 static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
591 DeviceClass *dc = DEVICE_CLASS(klass);
592 ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
593 KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
595 agcc->pre_save = kvm_arm_gic_get;
596 agcc->post_load = kvm_arm_gic_put;
597 device_class_set_parent_realize(dc, kvm_arm_gic_realize,
598 &kgc->parent_realize);
599 device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_reset);
602 static const TypeInfo kvm_arm_gic_info = {
603 .name = TYPE_KVM_ARM_GIC,
604 .parent = TYPE_ARM_GIC_COMMON,
605 .instance_size = sizeof(GICState),
606 .class_init = kvm_arm_gic_class_init,
607 .class_size = sizeof(KVMARMGICClass),
610 static void kvm_arm_gic_register_types(void)
612 type_register_static(&kvm_arm_gic_info);
615 type_init(kvm_arm_gic_register_types)