hw/arm/mps2-tz.c

   1 /*
   2  * ARM V2M MPS2 board emulation, trustzone aware FPGA images
   3  *
   4  * Copyright (c) 2017 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
  13  * FPGA but is otherwise the same as the 2). Since the CPU itself
  14  * and most of the devices are in the FPGA, the details of the board
  15  * as seen by the guest depend significantly on the FPGA image.
  16  * This source file covers the following FPGA images, for TrustZone cores:
  17  *  "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
  18  *  "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
  19  *
  20  * Links to the TRM for the board itself and to the various Application
  21  * Notes which document the FPGA images can be found here:
  22  * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
  23  *
  24  * Board TRM:
  25  * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf
  26  * Application Note AN505:
  27  * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
  28  * Application Note AN521:
  29  * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html
  30  *
  31  * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
  32  * (ARM ECM0601256) for the details of some of the device layout:
  33  *   http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
  34  * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines
  35  * most of the device layout:
  36  *  http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
  37  *
  38  */
  39
  40 #include "qemu/osdep.h"
  41 #include "qemu/units.h"
  42 #include "qemu/cutils.h"
  43 #include "qapi/error.h"
  44 #include "qemu/error-report.h"
  45 #include "hw/arm/boot.h"
  46 #include "hw/arm/armv7m.h"
  47 #include "hw/or-irq.h"
  48 #include "hw/boards.h"
  49 #include "exec/address-spaces.h"
  50 #include "sysemu/sysemu.h"
  51 #include "hw/misc/unimp.h"
  52 #include "hw/char/cmsdk-apb-uart.h"
  53 #include "hw/timer/cmsdk-apb-timer.h"
  54 #include "hw/misc/mps2-scc.h"
  55 #include "hw/misc/mps2-fpgaio.h"
  56 #include "hw/misc/tz-mpc.h"
  57 #include "hw/misc/tz-msc.h"
  58 #include "hw/arm/armsse.h"
  59 #include "hw/dma/pl080.h"
  60 #include "hw/ssi/pl022.h"
  61 #include "hw/i2c/arm_sbcon_i2c.h"
  62 #include "hw/net/lan9118.h"
  63 #include "net/net.h"
  64 #include "hw/core/split-irq.h"
  65 #include "hw/qdev-clock.h"
  66 #include "qom/object.h"
  67
  68 #define MPS2TZ_NUMIRQ_MAX 92
  69
  70 typedef enum MPS2TZFPGAType {
  71     FPGA_AN505,
  72     FPGA_AN521,
  73 } MPS2TZFPGAType;
  74
  75 struct MPS2TZMachineClass {
  76     MachineClass parent;
  77     MPS2TZFPGAType fpga_type;
  78     uint32_t scc_id;
  79     uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */
  80     uint32_t len_oscclk;
  81     const uint32_t *oscclk;
  82     uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */
  83     bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */
  84     int numirq; /* Number of external interrupts */
  85     const char *armsse_type;
  86 };
  87
  88 struct MPS2TZMachineState {
  89     MachineState parent;
  90
  91     ARMSSE iotkit;
  92     MemoryRegion ssram[3];
  93     MemoryRegion ssram1_m;
  94     MPS2SCC scc;
  95     MPS2FPGAIO fpgaio;
  96     TZPPC ppc[5];
  97     TZMPC ssram_mpc[3];
  98     PL022State spi[5];
  99     ArmSbconI2CState i2c[4];
 100     UnimplementedDeviceState i2s_audio;
 101     UnimplementedDeviceState gpio[4];
 102     UnimplementedDeviceState gfx;
 103     PL080State dma[4];
 104     TZMSC msc[4];
 105     CMSDKAPBUART uart[5];
 106     SplitIRQ sec_resp_splitter;
 107     qemu_or_irq uart_irq_orgate;
 108     DeviceState *lan9118;
 109     SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX];
 110     Clock *sysclk;
 111     Clock *s32kclk;
 112 };
 113
 114 #define TYPE_MPS2TZ_MACHINE "mps2tz"
 115 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
 116 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521")
 117
 118 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
 119
 120 /* Slow 32Khz S32KCLK frequency in Hz */
 121 #define S32KCLK_FRQ (32 * 1000)
 122
 123 static const uint32_t an505_oscclk[] = {
 124     40000000,
 125     24580000,
 126     25000000,
 127 };
 128
 129 /* Create an alias of an entire original MemoryRegion @orig
 130  * located at @base in the memory map.
 131  */
 132 static void make_ram_alias(MemoryRegion *mr, const char *name,
 133                            MemoryRegion *orig, hwaddr base)
 134 {
 135     memory_region_init_alias(mr, NULL, name, orig, 0,
 136                              memory_region_size(orig));
 137     memory_region_add_subregion(get_system_memory(), base, mr);
 138 }
 139
 140 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno)
 141 {
 142     /*
 143      * Return a qemu_irq which will signal IRQ n to all CPUs in the
 144      * SSE.  The irqno should be as the CPU sees it, so the first
 145      * external-to-the-SSE interrupt is 32.
 146      */
 147     MachineClass *mc = MACHINE_GET_CLASS(mms);
 148     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
 149
 150     assert(irqno >= 32 && irqno < (mmc->numirq + 32));
 151
 152     /*
 153      * Convert from "CPU irq number" (as listed in the FPGA image
 154      * documentation) to the SSE external-interrupt number.
 155      */
 156     irqno -= 32;
 157
 158     if (mc->max_cpus > 1) {
 159         return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0);
 160     } else {
 161         return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno);
 162     }
 163 }
 164
 165 /* Most of the devices in the AN505 FPGA image sit behind
 166  * Peripheral Protection Controllers. These data structures
 167  * define the layout of which devices sit behind which PPCs.
 168  * The devfn for each port is a function which creates, configures
 169  * and initializes the device, returning the MemoryRegion which
 170  * needs to be plugged into the downstream end of the PPC port.
 171  */
 172 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque,
 173                                 const char *name, hwaddr size);
 174
 175 typedef struct PPCPortInfo {
 176     const char *name;
 177     MakeDevFn *devfn;
 178     void *opaque;
 179     hwaddr addr;
 180     hwaddr size;
 181 } PPCPortInfo;
 182
 183 typedef struct PPCInfo {
 184     const char *name;
 185     PPCPortInfo ports[TZ_NUM_PORTS];
 186 } PPCInfo;
 187
 188 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
 189                                        void *opaque,
 190                                        const char *name, hwaddr size)
 191 {
 192     /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
 193      * and return a pointer to its MemoryRegion.
 194      */
 195     UnimplementedDeviceState *uds = opaque;
 196
 197     object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE);
 198     qdev_prop_set_string(DEVICE(uds), "name", name);
 199     qdev_prop_set_uint64(DEVICE(uds), "size", size);
 200     sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
 201     return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
 202 }
 203
 204 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
 205                                const char *name, hwaddr size)
 206 {
 207     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
 208     CMSDKAPBUART *uart = opaque;
 209     int i = uart - &mms->uart[0];
 210     int rxirqno = i * 2 + 32;
 211     int txirqno = i * 2 + 33;
 212     int combirqno = i + 42;
 213     SysBusDevice *s;
 214     DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
 215
 216     object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART);
 217     qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
 218     qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq);
 219     sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
 220     s = SYS_BUS_DEVICE(uart);
 221     sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno));
 222     sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno));
 223     sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
 224     sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
 225     sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno));
 226     return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);
 227 }
 228
 229 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
 230                               const char *name, hwaddr size)
 231 {
 232     MPS2SCC *scc = opaque;
 233     DeviceState *sccdev;
 234     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
 235     uint32_t i;
 236
 237     object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC);
 238     sccdev = DEVICE(scc);
 239     qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
 240     qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
 241     qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
 242     qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk);
 243     for (i = 0; i < mmc->len_oscclk; i++) {
 244         g_autofree char *propname = g_strdup_printf("oscclk[%u]", i);
 245         qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]);
 246     }
 247     sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal);
 248     return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
 249 }
 250
 251 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque,
 252                                  const char *name, hwaddr size)
 253 {
 254     MPS2FPGAIO *fpgaio = opaque;
 255     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
 256
 257     object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO);
 258     qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds);
 259     qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches);
 260     sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal);
 261     return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0);
 262 }
 263
 264 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
 265                                   const char *name, hwaddr size)
 266 {
 267     SysBusDevice *s;
 268     NICInfo *nd = &nd_table[0];
 269
 270     /* In hardware this is a LAN9220; the LAN9118 is software compatible
 271      * except that it doesn't support the checksum-offload feature.
 272      */
 273     qemu_check_nic_model(nd, "lan9118");
 274     mms->lan9118 = qdev_new(TYPE_LAN9118);
 275     qdev_set_nic_properties(mms->lan9118, nd);
 276
 277     s = SYS_BUS_DEVICE(mms->lan9118);
 278     sysbus_realize_and_unref(s, &error_fatal);
 279     sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48));
 280     return sysbus_mmio_get_region(s, 0);
 281 }
 282
 283 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
 284                               const char *name, hwaddr size)
 285 {
 286     TZMPC *mpc = opaque;
 287     int i = mpc - &mms->ssram_mpc[0];
 288     MemoryRegion *ssram = &mms->ssram[i];
 289     MemoryRegion *upstream;
 290     char *mpcname = g_strdup_printf("%s-mpc", name);
 291     static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 };
 292     static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 };
 293
 294     memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);
 295
 296     object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC);
 297     object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ssram),
 298                              &error_fatal);
 299     sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal);
 300     /* Map the upstream end of the MPC into system memory */
 301     upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
 302     memory_region_add_subregion(get_system_memory(), rambase[i], upstream);
 303     /* and connect its interrupt to the IoTKit */
 304     qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0,
 305                                 qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
 306                                                        "mpcexp_status", i));
 307
 308     /* The first SSRAM is a special case as it has an alias; accesses to
 309      * the alias region at 0x00400000 must also go to the MPC upstream.
 310      */
 311     if (i == 0) {
 312         make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000);
 313     }
 314
 315     g_free(mpcname);
 316     /* Return the register interface MR for our caller to map behind the PPC */
 317     return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);
 318 }
 319
 320 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
 321                               const char *name, hwaddr size)
 322 {
 323     PL080State *dma = opaque;
 324     int i = dma - &mms->dma[0];
 325     SysBusDevice *s;
 326     char *mscname = g_strdup_printf("%s-msc", name);
 327     TZMSC *msc = &mms->msc[i];
 328     DeviceState *iotkitdev = DEVICE(&mms->iotkit);
 329     MemoryRegion *msc_upstream;
 330     MemoryRegion *msc_downstream;
 331
 332     /*
 333      * Each DMA device is a PL081 whose transaction master interface
 334      * is guarded by a Master Security Controller. The downstream end of
 335      * the MSC connects to the IoTKit AHB Slave Expansion port, so the
 336      * DMA devices can see all devices and memory that the CPU does.
 337      */
 338     object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC);
 339     msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0);
 340     object_property_set_link(OBJECT(msc), "downstream",
 341                              OBJECT(msc_downstream), &error_fatal);
 342     object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal);
 343     sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal);
 344
 345     qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0,
 346                                 qdev_get_gpio_in_named(iotkitdev,
 347                                                        "mscexp_status", i));
 348     qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i,
 349                                 qdev_get_gpio_in_named(DEVICE(msc),
 350                                                        "irq_clear", 0));
 351     qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i,
 352                                 qdev_get_gpio_in_named(DEVICE(msc),
 353                                                        "cfg_nonsec", 0));
 354     qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter),
 355                           ARRAY_SIZE(mms->ppc) + i,
 356                           qdev_get_gpio_in_named(DEVICE(msc),
 357                                                  "cfg_sec_resp", 0));
 358     msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0);
 359
 360     object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081);
 361     object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream),
 362                              &error_fatal);
 363     sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal);
 364
 365     s = SYS_BUS_DEVICE(dma);
 366     /* Wire up DMACINTR, DMACINTERR, DMACINTTC */
 367     sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3));
 368     sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3));
 369     sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3));
 370
 371     g_free(mscname);
 372     return sysbus_mmio_get_region(s, 0);
 373 }
 374
 375 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
 376                               const char *name, hwaddr size)
 377 {
 378     /*
 379      * The AN505 has five PL022 SPI controllers.
 380      * One of these should have the LCD controller behind it; the others
 381      * are connected only to the FPGA's "general purpose SPI connector"
 382      * or "shield" expansion connectors.
 383      * Note that if we do implement devices behind SPI, the chip select
 384      * lines are set via the "MISC" register in the MPS2 FPGAIO device.
 385      */
 386     PL022State *spi = opaque;
 387     int i = spi - &mms->spi[0];
 388     SysBusDevice *s;
 389
 390     object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022);
 391     sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal);
 392     s = SYS_BUS_DEVICE(spi);
 393     sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i));
 394     return sysbus_mmio_get_region(s, 0);
 395 }
 396
 397 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque,
 398                               const char *name, hwaddr size)
 399 {
 400     ArmSbconI2CState *i2c = opaque;
 401     SysBusDevice *s;
 402
 403     object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C);
 404     s = SYS_BUS_DEVICE(i2c);
 405     sysbus_realize(s, &error_fatal);
 406     return sysbus_mmio_get_region(s, 0);
 407 }
 408
 409 static void mps2tz_common_init(MachineState *machine)
 410 {
 411     MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
 412     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
 413     MachineClass *mc = MACHINE_GET_CLASS(machine);
 414     MemoryRegion *system_memory = get_system_memory();
 415     DeviceState *iotkitdev;
 416     DeviceState *dev_splitter;
 417     int i;
 418
 419     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
 420         error_report("This board can only be used with CPU %s",
 421                      mc->default_cpu_type);
 422         exit(1);
 423     }
 424
 425     if (machine->ram_size != mc->default_ram_size) {
 426         char *sz = size_to_str(mc->default_ram_size);
 427         error_report("Invalid RAM size, should be %s", sz);
 428         g_free(sz);
 429         exit(EXIT_FAILURE);
 430     }
 431
 432     /* These clocks don't need migration because they are fixed-frequency */
 433     mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
 434     clock_set_hz(mms->sysclk, mmc->sysclk_frq);
 435     mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
 436     clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
 437
 438     object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
 439                             mmc->armsse_type);
 440     iotkitdev = DEVICE(&mms->iotkit);
 441     object_property_set_link(OBJECT(&mms->iotkit), "memory",
 442                              OBJECT(system_memory), &error_abort);
 443     qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
 444     qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
 445     qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
 446     sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
 447
 448     /*
 449      * If this board has more than one CPU, then we need to create splitters
 450      * to feed the IRQ inputs for each CPU in the SSE from each device in the
 451      * board. If there is only one CPU, we can just wire the device IRQ
 452      * directly to the SSE's IRQ input.
 453      */
 454     assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX);
 455     if (mc->max_cpus > 1) {
 456         for (i = 0; i < mmc->numirq; i++) {
 457             char *name = g_strdup_printf("mps2-irq-splitter%d", i);
 458             SplitIRQ *splitter = &mms->cpu_irq_splitter[i];
 459
 460             object_initialize_child_with_props(OBJECT(machine), name,
 461                                                splitter, sizeof(*splitter),
 462                                                TYPE_SPLIT_IRQ, &error_fatal,
 463                                                NULL);
 464             g_free(name);
 465
 466             object_property_set_int(OBJECT(splitter), "num-lines", 2,
 467                                     &error_fatal);
 468             qdev_realize(DEVICE(splitter), NULL, &error_fatal);
 469             qdev_connect_gpio_out(DEVICE(splitter), 0,
 470                                   qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
 471                                                          "EXP_IRQ", i));
 472             qdev_connect_gpio_out(DEVICE(splitter), 1,
 473                                   qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
 474                                                          "EXP_CPU1_IRQ", i));
 475         }
 476     }
 477
 478     /* The sec_resp_cfg output from the IoTKit must be split into multiple
 479      * lines, one for each of the PPCs we create here, plus one per MSC.
 480      */
 481     object_initialize_child(OBJECT(machine), "sec-resp-splitter",
 482                             &mms->sec_resp_splitter, TYPE_SPLIT_IRQ);
 483     object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines",
 484                             ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc),
 485                             &error_fatal);
 486     qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal);
 487     dev_splitter = DEVICE(&mms->sec_resp_splitter);
 488     qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0,
 489                                 qdev_get_gpio_in(dev_splitter, 0));
 490
 491     /* The IoTKit sets up much of the memory layout, including
 492      * the aliases between secure and non-secure regions in the
 493      * address space. The FPGA itself contains:
 494      *
 495      * 0x00000000..0x003fffff  SSRAM1
 496      * 0x00400000..0x007fffff  alias of SSRAM1
 497      * 0x28000000..0x283fffff  4MB SSRAM2 + SSRAM3
 498      * 0x40100000..0x4fffffff  AHB Master Expansion 1 interface devices
 499      * 0x80000000..0x80ffffff  16MB PSRAM
 500      */
 501
 502     /* The FPGA images have an odd combination of different RAMs,
 503      * because in hardware they are different implementations and
 504      * connected to different buses, giving varying performance/size
 505      * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
 506      * call the 16MB our "system memory", as it's the largest lump.
 507      */
 508     memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
 509
 510     /* The overflow IRQs for all UARTs are ORed together.
 511      * Tx, Rx and "combined" IRQs are sent to the NVIC separately.
 512      * Create the OR gate for this.
 513      */
 514     object_initialize_child(OBJECT(mms), "uart-irq-orgate",
 515                             &mms->uart_irq_orgate, TYPE_OR_IRQ);
 516     object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 10,
 517                             &error_fatal);
 518     qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal);
 519     qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,
 520                           get_sse_irq_in(mms, 47));
 521
 522     /* Most of the devices in the FPGA are behind Peripheral Protection
 523      * Controllers. The required order for initializing things is:
 524      *  + initialize the PPC
 525      *  + initialize, configure and realize downstream devices
 526      *  + connect downstream device MemoryRegions to the PPC
 527      *  + realize the PPC
 528      *  + map the PPC's MemoryRegions to the places in the address map
 529      *    where the downstream devices should appear
 530      *  + wire up the PPC's control lines to the IoTKit object
 531      */
 532
 533     const PPCInfo ppcs[] = { {
 534             .name = "apb_ppcexp0",
 535             .ports = {
 536                 { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 },
 537                 { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 },
 538                 { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 },
 539             },
 540         }, {
 541             .name = "apb_ppcexp1",
 542             .ports = {
 543                 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 },
 544                 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 },
 545                 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 },
 546                 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 },
 547                 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 },
 548                 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 },
 549                 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 },
 550                 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 },
 551                 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 },
 552                 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 },
 553                 { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 },
 554                 { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 },
 555                 { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 },
 556                 { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 },
 557             },
 558         }, {
 559             .name = "apb_ppcexp2",
 560             .ports = {
 561                 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 },
 562                 { "i2s-audio", make_unimp_dev, &mms->i2s_audio,
 563                   0x40301000, 0x1000 },
 564                 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 },
 565             },
 566         }, {
 567             .name = "ahb_ppcexp0",
 568             .ports = {
 569                 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 },
 570                 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 },
 571                 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 },
 572                 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 },
 573                 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 },
 574                 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 },
 575             },
 576         }, {
 577             .name = "ahb_ppcexp1",
 578             .ports = {
 579                 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 },
 580                 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 },
 581                 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 },
 582                 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 },
 583             },
 584         },
 585     };
 586
 587     for (i = 0; i < ARRAY_SIZE(ppcs); i++) {
 588         const PPCInfo *ppcinfo = &ppcs[i];
 589         TZPPC *ppc = &mms->ppc[i];
 590         DeviceState *ppcdev;
 591         int port;
 592         char *gpioname;
 593
 594         object_initialize_child(OBJECT(machine), ppcinfo->name, ppc,
 595                                 TYPE_TZ_PPC);
 596         ppcdev = DEVICE(ppc);
 597
 598         for (port = 0; port < TZ_NUM_PORTS; port++) {
 599             const PPCPortInfo *pinfo = &ppcinfo->ports[port];
 600             MemoryRegion *mr;
 601             char *portname;
 602
 603             if (!pinfo->devfn) {
 604                 continue;
 605             }
 606
 607             mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
 608             portname = g_strdup_printf("port[%d]", port);
 609             object_property_set_link(OBJECT(ppc), portname, OBJECT(mr),
 610                                      &error_fatal);
 611             g_free(portname);
 612         }
 613
 614         sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal);
 615
 616         for (port = 0; port < TZ_NUM_PORTS; port++) {
 617             const PPCPortInfo *pinfo = &ppcinfo->ports[port];
 618
 619             if (!pinfo->devfn) {
 620                 continue;
 621             }
 622             sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr);
 623
 624             gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name);
 625             qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
 626                                         qdev_get_gpio_in_named(ppcdev,
 627                                                                "cfg_nonsec",
 628                                                                port));
 629             g_free(gpioname);
 630             gpioname = g_strdup_printf("%s_ap", ppcinfo->name);
 631             qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
 632                                         qdev_get_gpio_in_named(ppcdev,
 633                                                                "cfg_ap", port));
 634             g_free(gpioname);
 635         }
 636
 637         gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name);
 638         qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
 639                                     qdev_get_gpio_in_named(ppcdev,
 640                                                            "irq_enable", 0));
 641         g_free(gpioname);
 642         gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name);
 643         qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
 644                                     qdev_get_gpio_in_named(ppcdev,
 645                                                            "irq_clear", 0));
 646         g_free(gpioname);
 647         gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name);
 648         qdev_connect_gpio_out_named(ppcdev, "irq", 0,
 649                                     qdev_get_gpio_in_named(iotkitdev,
 650                                                            gpioname, 0));
 651         g_free(gpioname);
 652
 653         qdev_connect_gpio_out(dev_splitter, i,
 654                               qdev_get_gpio_in_named(ppcdev,
 655                                                      "cfg_sec_resp", 0));
 656     }
 657
 658     create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
 659
 660     armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000);
 661 }
 662
 663 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address,
 664                                int *iregion, bool *exempt, bool *ns, bool *nsc)
 665 {
 666     /*
 667      * The MPS2 TZ FPGA images have IDAUs in them which are connected to
 668      * the Master Security Controllers. Thes have the same logic as
 669      * is used by the IoTKit for the IDAU connected to the CPU, except
 670      * that MSCs don't care about the NSC attribute.
 671      */
 672     int region = extract32(address, 28, 4);
 673
 674     *ns = !(region & 1);
 675     *nsc = false;
 676     /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
 677     *exempt = (address & 0xeff00000) == 0xe0000000;
 678     *iregion = region;
 679 }
 680
 681 static void mps2tz_class_init(ObjectClass *oc, void *data)
 682 {
 683     MachineClass *mc = MACHINE_CLASS(oc);
 684     IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
 685
 686     mc->init = mps2tz_common_init;
 687     iic->check = mps2_tz_idau_check;
 688     mc->default_ram_size = 16 * MiB;
 689     mc->default_ram_id = "mps.ram";
 690 }
 691
 692 static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
 693 {
 694     MachineClass *mc = MACHINE_CLASS(oc);
 695     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
 696
 697     mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33";
 698     mc->default_cpus = 1;
 699     mc->min_cpus = mc->default_cpus;
 700     mc->max_cpus = mc->default_cpus;
 701     mmc->fpga_type = FPGA_AN505;
 702     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
 703     mmc->scc_id = 0x41045050;
 704     mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
 705     mmc->oscclk = an505_oscclk;
 706     mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
 707     mmc->fpgaio_num_leds = 2;
 708     mmc->fpgaio_has_switches = false;
 709     mmc->numirq = 92;
 710     mmc->armsse_type = TYPE_IOTKIT;
 711 }
 712
 713 static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
 714 {
 715     MachineClass *mc = MACHINE_CLASS(oc);
 716     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
 717
 718     mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33";
 719     mc->default_cpus = 2;
 720     mc->min_cpus = mc->default_cpus;
 721     mc->max_cpus = mc->default_cpus;
 722     mmc->fpga_type = FPGA_AN521;
 723     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
 724     mmc->scc_id = 0x41045210;
 725     mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
 726     mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */
 727     mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
 728     mmc->fpgaio_num_leds = 2;
 729     mmc->fpgaio_has_switches = false;
 730     mmc->numirq = 92;
 731     mmc->armsse_type = TYPE_SSE200;
 732 }
 733
 734 static const TypeInfo mps2tz_info = {
 735     .name = TYPE_MPS2TZ_MACHINE,
 736     .parent = TYPE_MACHINE,
 737     .abstract = true,
 738     .instance_size = sizeof(MPS2TZMachineState),
 739     .class_size = sizeof(MPS2TZMachineClass),
 740     .class_init = mps2tz_class_init,
 741     .interfaces = (InterfaceInfo[]) {
 742         { TYPE_IDAU_INTERFACE },
 743         { }
 744     },
 745 };
 746
 747 static const TypeInfo mps2tz_an505_info = {
 748     .name = TYPE_MPS2TZ_AN505_MACHINE,
 749     .parent = TYPE_MPS2TZ_MACHINE,
 750     .class_init = mps2tz_an505_class_init,
 751 };
 752
 753 static const TypeInfo mps2tz_an521_info = {
 754     .name = TYPE_MPS2TZ_AN521_MACHINE,
 755     .parent = TYPE_MPS2TZ_MACHINE,
 756     .class_init = mps2tz_an521_class_init,
 757 };
 758
 759 static void mps2tz_machine_init(void)
 760 {
 761     type_register_static(&mps2tz_info);
 762     type_register_static(&mps2tz_an505_info);
 763     type_register_static(&mps2tz_an521_info);
 764 }
 765
 766 type_init(mps2tz_machine_init);