target-arm/translate.h

   1 #ifndef TARGET_ARM_TRANSLATE_H
   2 #define TARGET_ARM_TRANSLATE_H
   3
   4 /* internal defines */
   5 typedef struct DisasContext {
   6     target_ulong pc;
   7     uint32_t insn;
   8     int is_jmp;
   9     /* Nonzero if this instruction has been conditionally skipped.  */
  10     int condjmp;
  11     /* The label that will be jumped to when the instruction is skipped.  */
  12     int condlabel;
  13     /* Thumb-2 conditional execution bits.  */
  14     int condexec_mask;
  15     int condexec_cond;
  16     struct TranslationBlock *tb;
  17     int singlestep_enabled;
  18     int thumb;
  19     int bswap_code;
  20 #if !defined(CONFIG_USER_ONLY)
  21     int user;
  22 #endif
  23     bool cpacr_fpen; /* FP enabled via CPACR.FPEN */
  24     bool vfp_enabled; /* FP enabled via FPSCR.EN */
  25     int vec_len;
  26     int vec_stride;
  27     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  28      * so that top level loop can generate correct syndrome information.
  29      */
  30     uint32_t svc_imm;
  31     int aarch64;
  32     int current_pl;
  33     GHashTable *cp_regs;
  34     uint64_t features; /* CPU features bits */
  35     /* Because unallocated encodings generate different exception syndrome
  36      * information from traps due to FP being disabled, we can't do a single
  37      * "is fp access disabled" check at a high level in the decode tree.
  38      * To help in catching bugs where the access check was forgotten in some
  39      * code path, we set this flag when the access check is done, and assert
  40      * that it is set at the point where we actually touch the FP regs.
  41      */
  42     bool fp_access_checked;
  43 #define TMP_A64_MAX 16
  44     int tmp_a64_count;
  45     TCGv_i64 tmp_a64[TMP_A64_MAX];
  46 } DisasContext;
  47
  48 extern TCGv_ptr cpu_env;
  49
  50 static inline int arm_dc_feature(DisasContext *dc, int feature)
  51 {
  52     return (dc->features & (1ULL << feature)) != 0;
  53 }
  54
  55 /* target-specific extra values for is_jmp */
  56 /* These instructions trap after executing, so the A32/T32 decoder must
  57  * defer them until after the conditional execution state has been updated.
  58  * WFI also needs special handling when single-stepping.
  59  */
  60 #define DISAS_WFI 4
  61 #define DISAS_SWI 5
  62 /* For instructions which unconditionally cause an exception we can skip
  63  * emitting unreachable code at the end of the TB in the A64 decoder
  64  */
  65 #define DISAS_EXC 6
  66 /* WFE */
  67 #define DISAS_WFE 7
  68
  69 #ifdef TARGET_AARCH64
  70 void a64_translate_init(void);
  71 void gen_intermediate_code_internal_a64(ARMCPU *cpu,
  72                                         TranslationBlock *tb,
  73                                         bool search_pc);
  74 void gen_a64_set_pc_im(uint64_t val);
  75 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
  76                             fprintf_function cpu_fprintf, int flags);
  77 #else
  78 static inline void a64_translate_init(void)
  79 {
  80 }
  81
  82 static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,
  83                                                       TranslationBlock *tb,
  84                                                       bool search_pc)
  85 {
  86 }
  87
  88 static inline void gen_a64_set_pc_im(uint64_t val)
  89 {
  90 }
  91
  92 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
  93                                           fprintf_function cpu_fprintf,
  94                                           int flags)
  95 {
  96 }
  97 #endif
  98
  99 void arm_gen_test_cc(int cc, int label);
 100
 101 #endif /* TARGET_ARM_TRANSLATE_H */