2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
15 #include "hw/ppc/spapr.h"
16 #include "hw/ppc/spapr_cpu_core.h"
17 #include "hw/ppc/spapr_xive.h"
18 #include "hw/ppc/xics.h"
19 #include "hw/ppc/xics_spapr.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
22 #include "sysemu/kvm.h"
26 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
28 spapr
->irq_map_nr
= nr_msis
;
29 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
32 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
38 * The 'align_mask' parameter of bitmap_find_next_zero_area()
39 * should be one less than a power of 2; 0 means no
40 * alignment. Adapt the 'align' value of the former allocator
41 * to fit the requirements of bitmap_find_next_zero_area()
45 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
47 if (irq
== spapr
->irq_map_nr
) {
48 error_setg(errp
, "can't find a free %d-IRQ block", num
);
52 bitmap_set(spapr
->irq_map
, irq
, num
);
54 return irq
+ SPAPR_IRQ_MSI
;
57 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
59 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
62 static void spapr_irq_init_kvm(SpaprMachineState
*spapr
,
63 SpaprIrq
*irq
, Error
**errp
)
65 MachineState
*machine
= MACHINE(spapr
);
66 Error
*local_err
= NULL
;
68 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
69 irq
->init_kvm(spapr
, &local_err
);
70 if (local_err
&& machine_kernel_irqchip_required(machine
)) {
71 error_prepend(&local_err
,
72 "kernel_irqchip requested but unavailable: ");
73 error_propagate(errp
, local_err
);
82 * We failed to initialize the KVM device, fallback to
85 error_prepend(&local_err
, "kernel_irqchip allowed but unavailable: ");
86 error_append_hint(&local_err
, "Falling back to kernel-irqchip=off\n");
87 warn_report_err(local_err
);
95 static void spapr_irq_init_xics(SpaprMachineState
*spapr
, Error
**errp
)
98 Error
*local_err
= NULL
;
100 obj
= object_new(TYPE_ICS_SPAPR
);
101 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
102 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
104 object_property_set_int(obj
, spapr
->irq
->nr_xirqs
,
105 "nr-irqs", &error_fatal
);
106 object_property_set_bool(obj
, true, "realized", &local_err
);
108 error_propagate(errp
, local_err
);
112 spapr
->ics
= ICS_SPAPR(obj
);
115 static int spapr_irq_claim_xics(SpaprMachineState
*spapr
, int irq
, bool lsi
,
118 ICSState
*ics
= spapr
->ics
;
122 if (!ics_valid_irq(ics
, irq
)) {
123 error_setg(errp
, "IRQ %d is invalid", irq
);
127 if (!ics_irq_free(ics
, irq
- ics
->offset
)) {
128 error_setg(errp
, "IRQ %d is not free", irq
);
132 ics_set_irq_type(ics
, irq
- ics
->offset
, lsi
);
136 static void spapr_irq_free_xics(SpaprMachineState
*spapr
, int irq
, int num
)
138 ICSState
*ics
= spapr
->ics
;
139 uint32_t srcno
= irq
- ics
->offset
;
142 if (ics_valid_irq(ics
, irq
)) {
143 trace_spapr_irq_free(0, irq
, num
);
144 for (i
= srcno
; i
< srcno
+ num
; ++i
) {
145 if (ics_irq_free(ics
, i
)) {
146 trace_spapr_irq_free_warn(0, i
);
148 memset(&ics
->irqs
[i
], 0, sizeof(ICSIRQState
));
153 static qemu_irq
spapr_qirq_xics(SpaprMachineState
*spapr
, int irq
)
155 ICSState
*ics
= spapr
->ics
;
156 uint32_t srcno
= irq
- ics
->offset
;
158 if (ics_valid_irq(ics
, irq
)) {
159 return spapr
->qirqs
[srcno
];
165 static void spapr_irq_print_info_xics(SpaprMachineState
*spapr
, Monitor
*mon
)
170 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
172 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
175 ics_pic_print_info(spapr
->ics
, mon
);
178 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState
*spapr
,
179 PowerPCCPU
*cpu
, Error
**errp
)
181 Error
*local_err
= NULL
;
183 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
185 obj
= icp_create(OBJECT(cpu
), TYPE_ICP
, XICS_FABRIC(spapr
),
188 error_propagate(errp
, local_err
);
192 spapr_cpu
->icp
= ICP(obj
);
195 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
197 if (!kvm_irqchip_in_kernel()) {
200 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
201 icp_resend(spapr_cpu_state(cpu
)->icp
);
207 static void spapr_irq_set_irq_xics(void *opaque
, int srcno
, int val
)
209 SpaprMachineState
*spapr
= opaque
;
211 ics_set_irq(spapr
->ics
, srcno
, val
);
214 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
216 Error
*local_err
= NULL
;
218 spapr_irq_init_kvm(spapr
, &spapr_irq_xics
, &local_err
);
220 error_propagate(errp
, local_err
);
225 static const char *spapr_irq_get_nodename_xics(SpaprMachineState
*spapr
)
227 return XICS_NODENAME
;
230 static void spapr_irq_init_kvm_xics(SpaprMachineState
*spapr
, Error
**errp
)
233 xics_kvm_connect(spapr
, errp
);
237 SpaprIrq spapr_irq_xics
= {
238 .nr_xirqs
= SPAPR_NR_XIRQS
,
239 .nr_msis
= SPAPR_NR_MSIS
,
240 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
242 .init
= spapr_irq_init_xics
,
243 .claim
= spapr_irq_claim_xics
,
244 .free
= spapr_irq_free_xics
,
245 .qirq
= spapr_qirq_xics
,
246 .print_info
= spapr_irq_print_info_xics
,
247 .dt_populate
= spapr_dt_xics
,
248 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
249 .post_load
= spapr_irq_post_load_xics
,
250 .reset
= spapr_irq_reset_xics
,
251 .set_irq
= spapr_irq_set_irq_xics
,
252 .get_nodename
= spapr_irq_get_nodename_xics
,
253 .init_kvm
= spapr_irq_init_kvm_xics
,
259 static void spapr_irq_init_xive(SpaprMachineState
*spapr
, Error
**errp
)
261 uint32_t nr_servers
= spapr_max_server_number(spapr
);
265 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
266 qdev_prop_set_uint32(dev
, "nr-irqs",
267 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
269 * 8 XIVE END structures per CPU. One for each available priority
271 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
272 qdev_init_nofail(dev
);
274 spapr
->xive
= SPAPR_XIVE(dev
);
276 /* Enable the CPU IPIs */
277 for (i
= 0; i
< nr_servers
; ++i
) {
278 spapr_xive_irq_claim(spapr
->xive
, SPAPR_IRQ_IPI
+ i
, false);
281 spapr_xive_hcall_init(spapr
);
284 static int spapr_irq_claim_xive(SpaprMachineState
*spapr
, int irq
, bool lsi
,
287 if (!spapr_xive_irq_claim(spapr
->xive
, irq
, lsi
)) {
288 error_setg(errp
, "IRQ %d is invalid", irq
);
294 static void spapr_irq_free_xive(SpaprMachineState
*spapr
, int irq
, int num
)
298 for (i
= irq
; i
< irq
+ num
; ++i
) {
299 spapr_xive_irq_free(spapr
->xive
, i
);
303 static qemu_irq
spapr_qirq_xive(SpaprMachineState
*spapr
, int irq
)
305 SpaprXive
*xive
= spapr
->xive
;
307 if ((irq
< SPAPR_XIRQ_BASE
) || (irq
>= xive
->nr_irqs
)) {
311 /* The sPAPR machine/device should have claimed the IRQ before */
312 assert(xive_eas_is_valid(&xive
->eat
[irq
]));
314 return spapr
->qirqs
[irq
];
317 static void spapr_irq_print_info_xive(SpaprMachineState
*spapr
,
323 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
325 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
328 spapr_xive_pic_print_info(spapr
->xive
, mon
);
331 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState
*spapr
,
332 PowerPCCPU
*cpu
, Error
**errp
)
334 Error
*local_err
= NULL
;
336 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
338 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(spapr
->xive
), &local_err
);
340 error_propagate(errp
, local_err
);
344 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
347 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
348 * don't beneficiate from the reset of the XIVE IRQ backend
350 spapr_xive_set_tctx_os_cam(spapr_cpu
->tctx
);
353 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
355 return spapr_xive_post_load(spapr
->xive
, version_id
);
358 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
361 Error
*local_err
= NULL
;
364 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
366 /* (TCG) Set the OS CAM line of the thread interrupt context. */
367 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
370 spapr_irq_init_kvm(spapr
, &spapr_irq_xive
, &local_err
);
372 error_propagate(errp
, local_err
);
376 /* Activate the XIVE MMIOs */
377 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
380 static void spapr_irq_set_irq_xive(void *opaque
, int srcno
, int val
)
382 SpaprMachineState
*spapr
= opaque
;
384 if (kvm_irqchip_in_kernel()) {
385 kvmppc_xive_source_set_irq(&spapr
->xive
->source
, srcno
, val
);
387 xive_source_set_irq(&spapr
->xive
->source
, srcno
, val
);
391 static const char *spapr_irq_get_nodename_xive(SpaprMachineState
*spapr
)
393 return spapr
->xive
->nodename
;
396 static void spapr_irq_init_kvm_xive(SpaprMachineState
*spapr
, Error
**errp
)
399 kvmppc_xive_connect(spapr
->xive
, errp
);
403 SpaprIrq spapr_irq_xive
= {
404 .nr_xirqs
= SPAPR_NR_XIRQS
,
405 .nr_msis
= SPAPR_NR_MSIS
,
406 .ov5
= SPAPR_OV5_XIVE_EXPLOIT
,
408 .init
= spapr_irq_init_xive
,
409 .claim
= spapr_irq_claim_xive
,
410 .free
= spapr_irq_free_xive
,
411 .qirq
= spapr_qirq_xive
,
412 .print_info
= spapr_irq_print_info_xive
,
413 .dt_populate
= spapr_dt_xive
,
414 .cpu_intc_create
= spapr_irq_cpu_intc_create_xive
,
415 .post_load
= spapr_irq_post_load_xive
,
416 .reset
= spapr_irq_reset_xive
,
417 .set_irq
= spapr_irq_set_irq_xive
,
418 .get_nodename
= spapr_irq_get_nodename_xive
,
419 .init_kvm
= spapr_irq_init_kvm_xive
,
423 * Dual XIVE and XICS IRQ backend.
425 * Both interrupt mode, XIVE and XICS, objects are created but the
426 * machine starts in legacy interrupt mode (XICS). It can be changed
427 * by the CAS negotiation process and, in that case, the new mode is
428 * activated after an extra machine reset.
432 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
435 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
437 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
438 &spapr_irq_xive
: &spapr_irq_xics
;
441 static void spapr_irq_init_dual(SpaprMachineState
*spapr
, Error
**errp
)
443 Error
*local_err
= NULL
;
445 spapr_irq_xics
.init(spapr
, &local_err
);
447 error_propagate(errp
, local_err
);
451 spapr_irq_xive
.init(spapr
, &local_err
);
453 error_propagate(errp
, local_err
);
458 static int spapr_irq_claim_dual(SpaprMachineState
*spapr
, int irq
, bool lsi
,
461 Error
*local_err
= NULL
;
464 ret
= spapr_irq_xics
.claim(spapr
, irq
, lsi
, &local_err
);
466 error_propagate(errp
, local_err
);
470 ret
= spapr_irq_xive
.claim(spapr
, irq
, lsi
, &local_err
);
472 error_propagate(errp
, local_err
);
479 static void spapr_irq_free_dual(SpaprMachineState
*spapr
, int irq
, int num
)
481 spapr_irq_xics
.free(spapr
, irq
, num
);
482 spapr_irq_xive
.free(spapr
, irq
, num
);
485 static qemu_irq
spapr_qirq_dual(SpaprMachineState
*spapr
, int irq
)
487 return spapr_irq_current(spapr
)->qirq(spapr
, irq
);
490 static void spapr_irq_print_info_dual(SpaprMachineState
*spapr
, Monitor
*mon
)
492 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
495 static void spapr_irq_dt_populate_dual(SpaprMachineState
*spapr
,
496 uint32_t nr_servers
, void *fdt
,
499 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
502 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState
*spapr
,
503 PowerPCCPU
*cpu
, Error
**errp
)
505 Error
*local_err
= NULL
;
507 spapr_irq_xive
.cpu_intc_create(spapr
, cpu
, &local_err
);
509 error_propagate(errp
, local_err
);
513 spapr_irq_xics
.cpu_intc_create(spapr
, cpu
, errp
);
516 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
519 * Force a reset of the XIVE backend after migration. The machine
520 * defaults to XICS at startup.
522 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
523 if (kvm_irqchip_in_kernel()) {
524 xics_kvm_disconnect(spapr
, &error_fatal
);
526 spapr_irq_xive
.reset(spapr
, &error_fatal
);
529 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
532 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
534 Error
*local_err
= NULL
;
537 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
540 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
542 /* Destroy all KVM devices */
543 if (kvm_irqchip_in_kernel()) {
544 xics_kvm_disconnect(spapr
, &local_err
);
546 error_propagate(errp
, local_err
);
547 error_prepend(errp
, "KVM XICS disconnect failed: ");
550 kvmppc_xive_disconnect(spapr
->xive
, &local_err
);
552 error_propagate(errp
, local_err
);
553 error_prepend(errp
, "KVM XIVE disconnect failed: ");
558 spapr_irq_current(spapr
)->reset(spapr
, errp
);
561 static void spapr_irq_set_irq_dual(void *opaque
, int srcno
, int val
)
563 SpaprMachineState
*spapr
= opaque
;
565 spapr_irq_current(spapr
)->set_irq(spapr
, srcno
, val
);
568 static const char *spapr_irq_get_nodename_dual(SpaprMachineState
*spapr
)
570 return spapr_irq_current(spapr
)->get_nodename(spapr
);
574 * Define values in sync with the XIVE and XICS backend
576 SpaprIrq spapr_irq_dual
= {
577 .nr_xirqs
= SPAPR_NR_XIRQS
,
578 .nr_msis
= SPAPR_NR_MSIS
,
579 .ov5
= SPAPR_OV5_XIVE_BOTH
,
581 .init
= spapr_irq_init_dual
,
582 .claim
= spapr_irq_claim_dual
,
583 .free
= spapr_irq_free_dual
,
584 .qirq
= spapr_qirq_dual
,
585 .print_info
= spapr_irq_print_info_dual
,
586 .dt_populate
= spapr_irq_dt_populate_dual
,
587 .cpu_intc_create
= spapr_irq_cpu_intc_create_dual
,
588 .post_load
= spapr_irq_post_load_dual
,
589 .reset
= spapr_irq_reset_dual
,
590 .set_irq
= spapr_irq_set_irq_dual
,
591 .get_nodename
= spapr_irq_get_nodename_dual
,
592 .init_kvm
= NULL
, /* should not be used */
596 static void spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
598 MachineState
*machine
= MACHINE(spapr
);
601 * Sanity checks on non-P9 machines. On these, XIVE is not
602 * advertised, see spapr_dt_ov5_platform_support()
604 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
605 0, spapr
->max_compat_pvr
)) {
607 * If the 'dual' interrupt mode is selected, force XICS as CAS
608 * negotiation is useless.
610 if (spapr
->irq
== &spapr_irq_dual
) {
611 spapr
->irq
= &spapr_irq_xics
;
616 * Non-P9 machines using only XIVE is a bogus setup. We have two
617 * scenarios to take into account because of the compat mode:
619 * 1. POWER7/8 machines should fail to init later on when creating
620 * the XIVE interrupt presenters because a POWER9 exception
623 * 2. POWER9 machines using the POWER8 compat mode won't fail and
624 * will let the OS boot with a partial XIVE setup : DT
625 * properties but no hcalls.
627 * To cover both and not confuse the OS, add an early failure in
630 if (spapr
->irq
== &spapr_irq_xive
) {
631 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
637 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
638 * re-created. Detect that early to avoid QEMU to exit later when the
642 spapr
->irq
== &spapr_irq_dual
&&
643 machine_kernel_irqchip_required(machine
) &&
644 xics_kvm_has_broken_disconnect(spapr
)) {
645 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
651 * sPAPR IRQ frontend routines for devices
653 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
655 MachineState
*machine
= MACHINE(spapr
);
656 Error
*local_err
= NULL
;
658 if (machine_kernel_irqchip_split(machine
)) {
659 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
663 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
665 "kernel_irqchip requested but only available with KVM");
669 spapr_irq_check(spapr
, &local_err
);
671 error_propagate(errp
, local_err
);
675 /* Initialize the MSI IRQ allocator. */
676 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
677 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
680 spapr
->irq
->init(spapr
, errp
);
682 spapr
->qirqs
= qemu_allocate_irqs(spapr
->irq
->set_irq
, spapr
,
683 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
686 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
688 return spapr
->irq
->claim(spapr
, irq
, lsi
, errp
);
691 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
693 spapr
->irq
->free(spapr
, irq
, num
);
696 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
698 return spapr
->irq
->qirq(spapr
, irq
);
701 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
703 return spapr
->irq
->post_load(spapr
, version_id
);
706 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
708 assert(!spapr
->irq_map
|| bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
));
710 if (spapr
->irq
->reset
) {
711 spapr
->irq
->reset(spapr
, errp
);
715 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
717 const char *nodename
= spapr
->irq
->get_nodename(spapr
);
720 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
722 error_setg(errp
, "Can't find node \"%s\": %s", nodename
,
723 fdt_strerror(offset
));
727 phandle
= fdt_get_phandle(fdt
, offset
);
729 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
737 * XICS legacy routines - to deprecate one day
740 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
744 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
745 if (num
> (ics
->nr_irqs
- first
)) {
748 for (i
= first
; i
< first
+ num
; ++i
) {
749 if (!ics_irq_free(ics
, i
)) {
753 if (i
== (first
+ num
)) {
761 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
763 ICSState
*ics
= spapr
->ics
;
769 * MSIMesage::data is used for storing VIRQ so
770 * it has to be aligned to num to support multiple
771 * MSI vectors. MSI-X is not affected by this.
772 * The hint is used for the first IRQ, the rest should
773 * be allocated continuously.
776 assert((num
== 1) || (num
== 2) || (num
== 4) ||
777 (num
== 8) || (num
== 16) || (num
== 32));
778 first
= ics_find_free_block(ics
, num
, num
);
780 first
= ics_find_free_block(ics
, num
, 1);
784 error_setg(errp
, "can't find a free %d-IRQ block", num
);
788 return first
+ ics
->offset
;
791 #define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400
793 SpaprIrq spapr_irq_xics_legacy
= {
794 .nr_xirqs
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
795 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
796 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
798 .init
= spapr_irq_init_xics
,
799 .claim
= spapr_irq_claim_xics
,
800 .free
= spapr_irq_free_xics
,
801 .qirq
= spapr_qirq_xics
,
802 .print_info
= spapr_irq_print_info_xics
,
803 .dt_populate
= spapr_dt_xics
,
804 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
805 .post_load
= spapr_irq_post_load_xics
,
806 .reset
= spapr_irq_reset_xics
,
807 .set_irq
= spapr_irq_set_irq_xics
,
808 .get_nodename
= spapr_irq_get_nodename_xics
,
809 .init_kvm
= spapr_irq_init_kvm_xics
,