hw/cpu/a15mpcore.c

   1 /*
   2  * Cortex-A15MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2012 Linaro Limited.
   5  * Written by Peter Maydell.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "hw/cpu/a15mpcore.h"
  22 #include "sysemu/kvm.h"
  23
  24 static void a15mp_priv_set_irq(void *opaque, int irq, int level)
  25 {
  26     A15MPPrivState *s = (A15MPPrivState *)opaque;
  27
  28     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  29 }
  30
  31 static void a15mp_priv_initfn(Object *obj)
  32 {
  33     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  34     A15MPPrivState *s = A15MPCORE_PRIV(obj);
  35     DeviceState *gicdev;
  36     const char *gictype = "arm_gic";
  37
  38     if (kvm_irqchip_in_kernel()) {
  39         gictype = "kvm-arm-gic";
  40     }
  41
  42     memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
  43     sysbus_init_mmio(sbd, &s->container);
  44
  45     object_initialize(&s->gic, sizeof(s->gic), gictype);
  46     gicdev = DEVICE(&s->gic);
  47     qdev_set_parent_bus(gicdev, sysbus_get_default());
  48     qdev_prop_set_uint32(gicdev, "revision", 2);
  49 }
  50
  51 static void a15mp_priv_realize(DeviceState *dev, Error **errp)
  52 {
  53     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  54     A15MPPrivState *s = A15MPCORE_PRIV(dev);
  55     DeviceState *gicdev;
  56     SysBusDevice *busdev;
  57     int i;
  58     Error *err = NULL;
  59
  60     gicdev = DEVICE(&s->gic);
  61     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  62     qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  63     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
  64     if (err != NULL) {
  65         error_propagate(errp, err);
  66         return;
  67     }
  68     busdev = SYS_BUS_DEVICE(&s->gic);
  69
  70     /* Pass through outbound IRQ lines from the GIC */
  71     sysbus_pass_irq(sbd, busdev);
  72
  73     /* Pass through inbound GPIO lines to the GIC */
  74     qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32);
  75
  76     /* Wire the outputs from each CPU's generic timer to the
  77      * appropriate GIC PPI inputs
  78      */
  79     for (i = 0; i < s->num_cpu; i++) {
  80         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
  81         int ppibase = s->num_irq - 32 + i * 32;
  82         /* physical timer; we wire it up to the non-secure timer's ID,
  83          * since a real A15 always has TrustZone but QEMU doesn't.
  84          */
  85         qdev_connect_gpio_out(cpudev, 0,
  86                               qdev_get_gpio_in(gicdev, ppibase + 30));
  87         /* virtual timer */
  88         qdev_connect_gpio_out(cpudev, 1,
  89                               qdev_get_gpio_in(gicdev, ppibase + 27));
  90     }
  91
  92     /* Memory map (addresses are offsets from PERIPHBASE):
  93      *  0x0000-0x0fff -- reserved
  94      *  0x1000-0x1fff -- GIC Distributor
  95      *  0x2000-0x2fff -- GIC CPU interface
  96      *  0x4000-0x4fff -- GIC virtual interface control (not modelled)
  97      *  0x5000-0x5fff -- GIC virtual interface control (not modelled)
  98      *  0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
  99      */
 100     memory_region_add_subregion(&s->container, 0x1000,
 101                                 sysbus_mmio_get_region(busdev, 0));
 102     memory_region_add_subregion(&s->container, 0x2000,
 103                                 sysbus_mmio_get_region(busdev, 1));
 104 }
 105
 106 static Property a15mp_priv_properties[] = {
 107     DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
 108     /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
 109      * IRQ lines (with another 32 internal). We default to 128+32, which
 110      * is the number provided by the Cortex-A15MP test chip in the
 111      * Versatile Express A15 development board.
 112      * Other boards may differ and should set this property appropriately.
 113      */
 114     DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160),
 115     DEFINE_PROP_END_OF_LIST(),
 116 };
 117
 118 static void a15mp_priv_class_init(ObjectClass *klass, void *data)
 119 {
 120     DeviceClass *dc = DEVICE_CLASS(klass);
 121
 122     dc->realize = a15mp_priv_realize;
 123     dc->props = a15mp_priv_properties;
 124     /* We currently have no savable state */
 125 }
 126
 127 static const TypeInfo a15mp_priv_info = {
 128     .name  = TYPE_A15MPCORE_PRIV,
 129     .parent = TYPE_SYS_BUS_DEVICE,
 130     .instance_size  = sizeof(A15MPPrivState),
 131     .instance_init = a15mp_priv_initfn,
 132     .class_init = a15mp_priv_class_init,
 133 };
 134
 135 static void a15mp_register_types(void)
 136 {
 137     type_register_static(&a15mp_priv_info);
 138 }
 139
 140 type_init(a15mp_register_types)