aio / timers: Add scripts/switch-timer-api
[qemu/ar7.git] / dma-helpers.c
blobc9620a5bbd52ee8211b5f0faa8ab35690a60910d
1 /*
2 * DMA helper functions
4 * Copyright (c) 2009 Red Hat
6 * This work is licensed under the terms of the GNU General Public License
7 * (GNU GPL), version 2 or later.
8 */
10 #include "sysemu/dma.h"
11 #include "trace.h"
12 #include "qemu/range.h"
13 #include "qemu/thread.h"
14 #include "qemu/main-loop.h"
16 /* #define DEBUG_IOMMU */
18 int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len)
20 dma_barrier(as, DMA_DIRECTION_FROM_DEVICE);
22 #define FILLBUF_SIZE 512
23 uint8_t fillbuf[FILLBUF_SIZE];
24 int l;
25 bool error = false;
27 memset(fillbuf, c, FILLBUF_SIZE);
28 while (len > 0) {
29 l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE;
30 error |= address_space_rw(as, addr, fillbuf, l, true);
31 len -= l;
32 addr += l;
35 return error;
38 void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint,
39 AddressSpace *as)
41 qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry));
42 qsg->nsg = 0;
43 qsg->nalloc = alloc_hint;
44 qsg->size = 0;
45 qsg->as = as;
46 qsg->dev = dev;
47 object_ref(OBJECT(dev));
50 void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len)
52 if (qsg->nsg == qsg->nalloc) {
53 qsg->nalloc = 2 * qsg->nalloc + 1;
54 qsg->sg = g_realloc(qsg->sg, qsg->nalloc * sizeof(ScatterGatherEntry));
56 qsg->sg[qsg->nsg].base = base;
57 qsg->sg[qsg->nsg].len = len;
58 qsg->size += len;
59 ++qsg->nsg;
62 void qemu_sglist_destroy(QEMUSGList *qsg)
64 object_unref(OBJECT(qsg->dev));
65 g_free(qsg->sg);
66 memset(qsg, 0, sizeof(*qsg));
69 typedef struct {
70 BlockDriverAIOCB common;
71 BlockDriverState *bs;
72 BlockDriverAIOCB *acb;
73 QEMUSGList *sg;
74 uint64_t sector_num;
75 DMADirection dir;
76 bool in_cancel;
77 int sg_cur_index;
78 dma_addr_t sg_cur_byte;
79 QEMUIOVector iov;
80 QEMUBH *bh;
81 DMAIOFunc *io_func;
82 } DMAAIOCB;
84 static void dma_bdrv_cb(void *opaque, int ret);
86 static void reschedule_dma(void *opaque)
88 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
90 qemu_bh_delete(dbs->bh);
91 dbs->bh = NULL;
92 dma_bdrv_cb(dbs, 0);
95 static void continue_after_map_failure(void *opaque)
97 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
99 dbs->bh = qemu_bh_new(reschedule_dma, dbs);
100 qemu_bh_schedule(dbs->bh);
103 static void dma_bdrv_unmap(DMAAIOCB *dbs)
105 int i;
107 for (i = 0; i < dbs->iov.niov; ++i) {
108 dma_memory_unmap(dbs->sg->as, dbs->iov.iov[i].iov_base,
109 dbs->iov.iov[i].iov_len, dbs->dir,
110 dbs->iov.iov[i].iov_len);
112 qemu_iovec_reset(&dbs->iov);
115 static void dma_complete(DMAAIOCB *dbs, int ret)
117 trace_dma_complete(dbs, ret, dbs->common.cb);
119 dma_bdrv_unmap(dbs);
120 if (dbs->common.cb) {
121 dbs->common.cb(dbs->common.opaque, ret);
123 qemu_iovec_destroy(&dbs->iov);
124 if (dbs->bh) {
125 qemu_bh_delete(dbs->bh);
126 dbs->bh = NULL;
128 if (!dbs->in_cancel) {
129 /* Requests may complete while dma_aio_cancel is in progress. In
130 * this case, the AIOCB should not be released because it is still
131 * referenced by dma_aio_cancel. */
132 qemu_aio_release(dbs);
136 static void dma_bdrv_cb(void *opaque, int ret)
138 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
139 dma_addr_t cur_addr, cur_len;
140 void *mem;
142 trace_dma_bdrv_cb(dbs, ret);
144 dbs->acb = NULL;
145 dbs->sector_num += dbs->iov.size / 512;
146 dma_bdrv_unmap(dbs);
148 if (dbs->sg_cur_index == dbs->sg->nsg || ret < 0) {
149 dma_complete(dbs, ret);
150 return;
153 while (dbs->sg_cur_index < dbs->sg->nsg) {
154 cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte;
155 cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte;
156 mem = dma_memory_map(dbs->sg->as, cur_addr, &cur_len, dbs->dir);
157 if (!mem)
158 break;
159 qemu_iovec_add(&dbs->iov, mem, cur_len);
160 dbs->sg_cur_byte += cur_len;
161 if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) {
162 dbs->sg_cur_byte = 0;
163 ++dbs->sg_cur_index;
167 if (dbs->iov.size == 0) {
168 trace_dma_map_wait(dbs);
169 cpu_register_map_client(dbs, continue_after_map_failure);
170 return;
173 dbs->acb = dbs->io_func(dbs->bs, dbs->sector_num, &dbs->iov,
174 dbs->iov.size / 512, dma_bdrv_cb, dbs);
175 assert(dbs->acb);
178 static void dma_aio_cancel(BlockDriverAIOCB *acb)
180 DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
182 trace_dma_aio_cancel(dbs);
184 if (dbs->acb) {
185 BlockDriverAIOCB *acb = dbs->acb;
186 dbs->acb = NULL;
187 dbs->in_cancel = true;
188 bdrv_aio_cancel(acb);
189 dbs->in_cancel = false;
191 dbs->common.cb = NULL;
192 dma_complete(dbs, 0);
195 static const AIOCBInfo dma_aiocb_info = {
196 .aiocb_size = sizeof(DMAAIOCB),
197 .cancel = dma_aio_cancel,
200 BlockDriverAIOCB *dma_bdrv_io(
201 BlockDriverState *bs, QEMUSGList *sg, uint64_t sector_num,
202 DMAIOFunc *io_func, BlockDriverCompletionFunc *cb,
203 void *opaque, DMADirection dir)
205 DMAAIOCB *dbs = qemu_aio_get(&dma_aiocb_info, bs, cb, opaque);
207 trace_dma_bdrv_io(dbs, bs, sector_num, (dir == DMA_DIRECTION_TO_DEVICE));
209 dbs->acb = NULL;
210 dbs->bs = bs;
211 dbs->sg = sg;
212 dbs->sector_num = sector_num;
213 dbs->sg_cur_index = 0;
214 dbs->sg_cur_byte = 0;
215 dbs->dir = dir;
216 dbs->io_func = io_func;
217 dbs->bh = NULL;
218 qemu_iovec_init(&dbs->iov, sg->nsg);
219 dma_bdrv_cb(dbs, 0);
220 return &dbs->common;
224 BlockDriverAIOCB *dma_bdrv_read(BlockDriverState *bs,
225 QEMUSGList *sg, uint64_t sector,
226 void (*cb)(void *opaque, int ret), void *opaque)
228 return dma_bdrv_io(bs, sg, sector, bdrv_aio_readv, cb, opaque,
229 DMA_DIRECTION_FROM_DEVICE);
232 BlockDriverAIOCB *dma_bdrv_write(BlockDriverState *bs,
233 QEMUSGList *sg, uint64_t sector,
234 void (*cb)(void *opaque, int ret), void *opaque)
236 return dma_bdrv_io(bs, sg, sector, bdrv_aio_writev, cb, opaque,
237 DMA_DIRECTION_TO_DEVICE);
241 static uint64_t dma_buf_rw(uint8_t *ptr, int32_t len, QEMUSGList *sg,
242 DMADirection dir)
244 uint64_t resid;
245 int sg_cur_index;
247 resid = sg->size;
248 sg_cur_index = 0;
249 len = MIN(len, resid);
250 while (len > 0) {
251 ScatterGatherEntry entry = sg->sg[sg_cur_index++];
252 int32_t xfer = MIN(len, entry.len);
253 dma_memory_rw(sg->as, entry.base, ptr, xfer, dir);
254 ptr += xfer;
255 len -= xfer;
256 resid -= xfer;
259 return resid;
262 uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg)
264 return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_FROM_DEVICE);
267 uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg)
269 return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_TO_DEVICE);
272 void dma_acct_start(BlockDriverState *bs, BlockAcctCookie *cookie,
273 QEMUSGList *sg, enum BlockAcctType type)
275 bdrv_acct_start(bs, cookie, sg->size, type);