tcg/tcg.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_H
  26 #define TCG_H
  27
  28 #include "qemu-common.h"
  29 #include "cpu.h"
  30 #include "exec/tb-context.h"
  31 #include "qemu/bitops.h"
  32 #include "qemu/queue.h"
  33 #include "tcg-mo.h"
  34 #include "tcg-target.h"
  35 #include "qemu/int128.h"
  36
  37 /* XXX: make safe guess about sizes */
  38 #define MAX_OP_PER_INSTR 266
  39
  40 #if HOST_LONG_BITS == 32
  41 #define MAX_OPC_PARAM_PER_ARG 2
  42 #else
  43 #define MAX_OPC_PARAM_PER_ARG 1
  44 #endif
  45 #define MAX_OPC_PARAM_IARGS 6
  46 #define MAX_OPC_PARAM_OARGS 1
  47 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  48
  49 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  50  * and up to 4 + N parameters on 64-bit archs
  51  * (N = number of input arguments + output arguments).  */
  52 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  53
  54 #define CPU_TEMP_BUF_NLONGS 128
  55
  56 /* Default target word size to pointer size.  */
  57 #ifndef TCG_TARGET_REG_BITS
  58 # if UINTPTR_MAX == UINT32_MAX
  59 #  define TCG_TARGET_REG_BITS 32
  60 # elif UINTPTR_MAX == UINT64_MAX
  61 #  define TCG_TARGET_REG_BITS 64
  62 # else
  63 #  error Unknown pointer size for tcg target
  64 # endif
  65 #endif
  66
  67 #if TCG_TARGET_REG_BITS == 32
  68 typedef int32_t tcg_target_long;
  69 typedef uint32_t tcg_target_ulong;
  70 #define TCG_PRIlx PRIx32
  71 #define TCG_PRIld PRId32
  72 #elif TCG_TARGET_REG_BITS == 64
  73 typedef int64_t tcg_target_long;
  74 typedef uint64_t tcg_target_ulong;
  75 #define TCG_PRIlx PRIx64
  76 #define TCG_PRIld PRId64
  77 #else
  78 #error unsupported
  79 #endif
  80
  81 /* Oversized TCG guests make things like MTTCG hard
  82  * as we can't use atomics for cputlb updates.
  83  */
  84 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  85 #define TCG_OVERSIZED_GUEST 1
  86 #else
  87 #define TCG_OVERSIZED_GUEST 0
  88 #endif
  89
  90 #if TCG_TARGET_NB_REGS <= 32
  91 typedef uint32_t TCGRegSet;
  92 #elif TCG_TARGET_NB_REGS <= 64
  93 typedef uint64_t TCGRegSet;
  94 #else
  95 #error unsupported
  96 #endif
  97
  98 #if TCG_TARGET_REG_BITS == 32
  99 /* Turn some undef macros into false macros.  */
 100 #define TCG_TARGET_HAS_extrl_i64_i32    0
 101 #define TCG_TARGET_HAS_extrh_i64_i32    0
 102 #define TCG_TARGET_HAS_div_i64          0
 103 #define TCG_TARGET_HAS_rem_i64          0
 104 #define TCG_TARGET_HAS_div2_i64         0
 105 #define TCG_TARGET_HAS_rot_i64          0
 106 #define TCG_TARGET_HAS_ext8s_i64        0
 107 #define TCG_TARGET_HAS_ext16s_i64       0
 108 #define TCG_TARGET_HAS_ext32s_i64       0
 109 #define TCG_TARGET_HAS_ext8u_i64        0
 110 #define TCG_TARGET_HAS_ext16u_i64       0
 111 #define TCG_TARGET_HAS_ext32u_i64       0
 112 #define TCG_TARGET_HAS_bswap16_i64      0
 113 #define TCG_TARGET_HAS_bswap32_i64      0
 114 #define TCG_TARGET_HAS_bswap64_i64      0
 115 #define TCG_TARGET_HAS_neg_i64          0
 116 #define TCG_TARGET_HAS_not_i64          0
 117 #define TCG_TARGET_HAS_andc_i64         0
 118 #define TCG_TARGET_HAS_orc_i64          0
 119 #define TCG_TARGET_HAS_eqv_i64          0
 120 #define TCG_TARGET_HAS_nand_i64         0
 121 #define TCG_TARGET_HAS_nor_i64          0
 122 #define TCG_TARGET_HAS_clz_i64          0
 123 #define TCG_TARGET_HAS_ctz_i64          0
 124 #define TCG_TARGET_HAS_ctpop_i64        0
 125 #define TCG_TARGET_HAS_deposit_i64      0
 126 #define TCG_TARGET_HAS_extract_i64      0
 127 #define TCG_TARGET_HAS_sextract_i64     0
 128 #define TCG_TARGET_HAS_movcond_i64      0
 129 #define TCG_TARGET_HAS_add2_i64         0
 130 #define TCG_TARGET_HAS_sub2_i64         0
 131 #define TCG_TARGET_HAS_mulu2_i64        0
 132 #define TCG_TARGET_HAS_muls2_i64        0
 133 #define TCG_TARGET_HAS_muluh_i64        0
 134 #define TCG_TARGET_HAS_mulsh_i64        0
 135 /* Turn some undef macros into true macros.  */
 136 #define TCG_TARGET_HAS_add2_i32         1
 137 #define TCG_TARGET_HAS_sub2_i32         1
 138 #endif
 139
 140 #ifndef TCG_TARGET_deposit_i32_valid
 141 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
 142 #endif
 143 #ifndef TCG_TARGET_deposit_i64_valid
 144 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
 145 #endif
 146 #ifndef TCG_TARGET_extract_i32_valid
 147 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
 148 #endif
 149 #ifndef TCG_TARGET_extract_i64_valid
 150 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
 151 #endif
 152
 153 /* Only one of DIV or DIV2 should be defined.  */
 154 #if defined(TCG_TARGET_HAS_div_i32)
 155 #define TCG_TARGET_HAS_div2_i32         0
 156 #elif defined(TCG_TARGET_HAS_div2_i32)
 157 #define TCG_TARGET_HAS_div_i32          0
 158 #define TCG_TARGET_HAS_rem_i32          0
 159 #endif
 160 #if defined(TCG_TARGET_HAS_div_i64)
 161 #define TCG_TARGET_HAS_div2_i64         0
 162 #elif defined(TCG_TARGET_HAS_div2_i64)
 163 #define TCG_TARGET_HAS_div_i64          0
 164 #define TCG_TARGET_HAS_rem_i64          0
 165 #endif
 166
 167 /* For 32-bit targets, some sort of unsigned widening multiply is required.  */
 168 #if TCG_TARGET_REG_BITS == 32 \
 169     && !(defined(TCG_TARGET_HAS_mulu2_i32) \
 170          || defined(TCG_TARGET_HAS_muluh_i32))
 171 # error "Missing unsigned widening multiply"
 172 #endif
 173
 174 #if !defined(TCG_TARGET_HAS_v64) \
 175     && !defined(TCG_TARGET_HAS_v128) \
 176     && !defined(TCG_TARGET_HAS_v256)
 177 #define TCG_TARGET_MAYBE_vec            0
 178 #define TCG_TARGET_HAS_neg_vec          0
 179 #define TCG_TARGET_HAS_not_vec          0
 180 #define TCG_TARGET_HAS_andc_vec         0
 181 #define TCG_TARGET_HAS_orc_vec          0
 182 #define TCG_TARGET_HAS_shi_vec          0
 183 #define TCG_TARGET_HAS_shs_vec          0
 184 #define TCG_TARGET_HAS_shv_vec          0
 185 #define TCG_TARGET_HAS_mul_vec          0
 186 #else
 187 #define TCG_TARGET_MAYBE_vec            1
 188 #endif
 189 #ifndef TCG_TARGET_HAS_v64
 190 #define TCG_TARGET_HAS_v64              0
 191 #endif
 192 #ifndef TCG_TARGET_HAS_v128
 193 #define TCG_TARGET_HAS_v128             0
 194 #endif
 195 #ifndef TCG_TARGET_HAS_v256
 196 #define TCG_TARGET_HAS_v256             0
 197 #endif
 198
 199 #ifndef TARGET_INSN_START_EXTRA_WORDS
 200 # define TARGET_INSN_START_WORDS 1
 201 #else
 202 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
 203 #endif
 204
 205 typedef enum TCGOpcode {
 206 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
 207 #include "tcg-opc.h"
 208 #undef DEF
 209     NB_OPS,
 210 } TCGOpcode;
 211
 212 #define tcg_regset_set_reg(d, r)   ((d) |= (TCGRegSet)1 << (r))
 213 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
 214 #define tcg_regset_test_reg(d, r)  (((d) >> (r)) & 1)
 215
 216 #ifndef TCG_TARGET_INSN_UNIT_SIZE
 217 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
 218 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
 219 typedef uint8_t tcg_insn_unit;
 220 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
 221 typedef uint16_t tcg_insn_unit;
 222 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
 223 typedef uint32_t tcg_insn_unit;
 224 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
 225 typedef uint64_t tcg_insn_unit;
 226 #else
 227 /* The port better have done this.  */
 228 #endif
 229
 230
 231 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
 232 # define tcg_debug_assert(X) do { assert(X); } while (0)
 233 #else
 234 # define tcg_debug_assert(X) \
 235     do { if (!(X)) { __builtin_unreachable(); } } while (0)
 236 #endif
 237
 238 typedef struct TCGRelocation {
 239     struct TCGRelocation *next;
 240     int type;
 241     tcg_insn_unit *ptr;
 242     intptr_t addend;
 243 } TCGRelocation;
 244
 245 typedef struct TCGLabel {
 246     unsigned has_value : 1;
 247     unsigned id : 15;
 248     unsigned refs : 16;
 249     union {
 250         uintptr_t value;
 251         tcg_insn_unit *value_ptr;
 252         TCGRelocation *first_reloc;
 253     } u;
 254 } TCGLabel;
 255
 256 typedef struct TCGPool {
 257     struct TCGPool *next;
 258     int size;
 259     uint8_t data[0] __attribute__ ((aligned));
 260 } TCGPool;
 261
 262 #define TCG_POOL_CHUNK_SIZE 32768
 263
 264 #define TCG_MAX_TEMPS 512
 265 #define TCG_MAX_INSNS 512
 266
 267 /* when the size of the arguments of a called function is smaller than
 268    this value, they are statically allocated in the TB stack frame */
 269 #define TCG_STATIC_CALL_ARGS_SIZE 128
 270
 271 typedef enum TCGType {
 272     TCG_TYPE_I32,
 273     TCG_TYPE_I64,
 274
 275     TCG_TYPE_V64,
 276     TCG_TYPE_V128,
 277     TCG_TYPE_V256,
 278
 279     TCG_TYPE_COUNT, /* number of different types */
 280
 281     /* An alias for the size of the host register.  */
 282 #if TCG_TARGET_REG_BITS == 32
 283     TCG_TYPE_REG = TCG_TYPE_I32,
 284 #else
 285     TCG_TYPE_REG = TCG_TYPE_I64,
 286 #endif
 287
 288     /* An alias for the size of the native pointer.  */
 289 #if UINTPTR_MAX == UINT32_MAX
 290     TCG_TYPE_PTR = TCG_TYPE_I32,
 291 #else
 292     TCG_TYPE_PTR = TCG_TYPE_I64,
 293 #endif
 294
 295     /* An alias for the size of the target "long", aka register.  */
 296 #if TARGET_LONG_BITS == 64
 297     TCG_TYPE_TL = TCG_TYPE_I64,
 298 #else
 299     TCG_TYPE_TL = TCG_TYPE_I32,
 300 #endif
 301 } TCGType;
 302
 303 /* Constants for qemu_ld and qemu_st for the Memory Operation field.  */
 304 typedef enum TCGMemOp {
 305     MO_8     = 0,
 306     MO_16    = 1,
 307     MO_32    = 2,
 308     MO_64    = 3,
 309     MO_SIZE  = 3,   /* Mask for the above.  */
 310
 311     MO_SIGN  = 4,   /* Sign-extended, otherwise zero-extended.  */
 312
 313     MO_BSWAP = 8,   /* Host reverse endian.  */
 314 #ifdef HOST_WORDS_BIGENDIAN
 315     MO_LE    = MO_BSWAP,
 316     MO_BE    = 0,
 317 #else
 318     MO_LE    = 0,
 319     MO_BE    = MO_BSWAP,
 320 #endif
 321 #ifdef TARGET_WORDS_BIGENDIAN
 322     MO_TE    = MO_BE,
 323 #else
 324     MO_TE    = MO_LE,
 325 #endif
 326
 327     /* MO_UNALN accesses are never checked for alignment.
 328      * MO_ALIGN accesses will result in a call to the CPU's
 329      * do_unaligned_access hook if the guest address is not aligned.
 330      * The default depends on whether the target CPU defines ALIGNED_ONLY.
 331      *
 332      * Some architectures (e.g. ARMv8) need the address which is aligned
 333      * to a size more than the size of the memory access.
 334      * Some architectures (e.g. SPARCv9) need an address which is aligned,
 335      * but less strictly than the natural alignment.
 336      *
 337      * MO_ALIGN supposes the alignment size is the size of a memory access.
 338      *
 339      * There are three options:
 340      * - unaligned access permitted (MO_UNALN).
 341      * - an alignment to the size of an access (MO_ALIGN);
 342      * - an alignment to a specified size, which may be more or less than
 343      *   the access size (MO_ALIGN_x where 'x' is a size in bytes);
 344      */
 345     MO_ASHIFT = 4,
 346     MO_AMASK = 7 << MO_ASHIFT,
 347 #ifdef ALIGNED_ONLY
 348     MO_ALIGN = 0,
 349     MO_UNALN = MO_AMASK,
 350 #else
 351     MO_ALIGN = MO_AMASK,
 352     MO_UNALN = 0,
 353 #endif
 354     MO_ALIGN_2  = 1 << MO_ASHIFT,
 355     MO_ALIGN_4  = 2 << MO_ASHIFT,
 356     MO_ALIGN_8  = 3 << MO_ASHIFT,
 357     MO_ALIGN_16 = 4 << MO_ASHIFT,
 358     MO_ALIGN_32 = 5 << MO_ASHIFT,
 359     MO_ALIGN_64 = 6 << MO_ASHIFT,
 360
 361     /* Combinations of the above, for ease of use.  */
 362     MO_UB    = MO_8,
 363     MO_UW    = MO_16,
 364     MO_UL    = MO_32,
 365     MO_SB    = MO_SIGN | MO_8,
 366     MO_SW    = MO_SIGN | MO_16,
 367     MO_SL    = MO_SIGN | MO_32,
 368     MO_Q     = MO_64,
 369
 370     MO_LEUW  = MO_LE | MO_UW,
 371     MO_LEUL  = MO_LE | MO_UL,
 372     MO_LESW  = MO_LE | MO_SW,
 373     MO_LESL  = MO_LE | MO_SL,
 374     MO_LEQ   = MO_LE | MO_Q,
 375
 376     MO_BEUW  = MO_BE | MO_UW,
 377     MO_BEUL  = MO_BE | MO_UL,
 378     MO_BESW  = MO_BE | MO_SW,
 379     MO_BESL  = MO_BE | MO_SL,
 380     MO_BEQ   = MO_BE | MO_Q,
 381
 382     MO_TEUW  = MO_TE | MO_UW,
 383     MO_TEUL  = MO_TE | MO_UL,
 384     MO_TESW  = MO_TE | MO_SW,
 385     MO_TESL  = MO_TE | MO_SL,
 386     MO_TEQ   = MO_TE | MO_Q,
 387
 388     MO_SSIZE = MO_SIZE | MO_SIGN,
 389 } TCGMemOp;
 390
 391 /**
 392  * get_alignment_bits
 393  * @memop: TCGMemOp value
 394  *
 395  * Extract the alignment size from the memop.
 396  */
 397 static inline unsigned get_alignment_bits(TCGMemOp memop)
 398 {
 399     unsigned a = memop & MO_AMASK;
 400
 401     if (a == MO_UNALN) {
 402         /* No alignment required.  */
 403         a = 0;
 404     } else if (a == MO_ALIGN) {
 405         /* A natural alignment requirement.  */
 406         a = memop & MO_SIZE;
 407     } else {
 408         /* A specific alignment requirement.  */
 409         a = a >> MO_ASHIFT;
 410     }
 411 #if defined(CONFIG_SOFTMMU)
 412     /* The requested alignment cannot overlap the TLB flags.  */
 413     tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
 414 #endif
 415     return a;
 416 }
 417
 418 typedef tcg_target_ulong TCGArg;
 419
 420 /* Define type and accessor macros for TCG variables.
 421
 422    TCG variables are the inputs and outputs of TCG ops, as described
 423    in tcg/README. Target CPU front-end code uses these types to deal
 424    with TCG variables as it emits TCG code via the tcg_gen_* functions.
 425    They come in several flavours:
 426     * TCGv_i32 : 32 bit integer type
 427     * TCGv_i64 : 64 bit integer type
 428     * TCGv_ptr : a host pointer type
 429     * TCGv_vec : a host vector type; the exact size is not exposed
 430                  to the CPU front-end code.
 431     * TCGv : an integer type the same size as target_ulong
 432              (an alias for either TCGv_i32 or TCGv_i64)
 433    The compiler's type checking will complain if you mix them
 434    up and pass the wrong sized TCGv to a function.
 435
 436    Users of tcg_gen_* don't need to know about any of the internal
 437    details of these, and should treat them as opaque types.
 438    You won't be able to look inside them in a debugger either.
 439
 440    Internal implementation details follow:
 441
 442    Note that there is no definition of the structs TCGv_i32_d etc anywhere.
 443    This is deliberate, because the values we store in variables of type
 444    TCGv_i32 are not really pointers-to-structures. They're just small
 445    integers, but keeping them in pointer types like this means that the
 446    compiler will complain if you accidentally pass a TCGv_i32 to a
 447    function which takes a TCGv_i64, and so on. Only the internals of
 448    TCG need to care about the actual contents of the types.  */
 449
 450 typedef struct TCGv_i32_d *TCGv_i32;
 451 typedef struct TCGv_i64_d *TCGv_i64;
 452 typedef struct TCGv_ptr_d *TCGv_ptr;
 453 typedef struct TCGv_vec_d *TCGv_vec;
 454 typedef TCGv_ptr TCGv_env;
 455 #if TARGET_LONG_BITS == 32
 456 #define TCGv TCGv_i32
 457 #elif TARGET_LONG_BITS == 64
 458 #define TCGv TCGv_i64
 459 #else
 460 #error Unhandled TARGET_LONG_BITS value
 461 #endif
 462
 463 /* call flags */
 464 /* Helper does not read globals (either directly or through an exception). It
 465    implies TCG_CALL_NO_WRITE_GLOBALS. */
 466 #define TCG_CALL_NO_READ_GLOBALS    0x0001
 467 /* Helper does not write globals */
 468 #define TCG_CALL_NO_WRITE_GLOBALS   0x0002
 469 /* Helper can be safely suppressed if the return value is not used. */
 470 #define TCG_CALL_NO_SIDE_EFFECTS    0x0004
 471 /* Helper is QEMU_NORETURN.  */
 472 #define TCG_CALL_NO_RETURN          0x0008
 473
 474 /* convenience version of most used call flags */
 475 #define TCG_CALL_NO_RWG         TCG_CALL_NO_READ_GLOBALS
 476 #define TCG_CALL_NO_WG          TCG_CALL_NO_WRITE_GLOBALS
 477 #define TCG_CALL_NO_SE          TCG_CALL_NO_SIDE_EFFECTS
 478 #define TCG_CALL_NO_RWG_SE      (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
 479 #define TCG_CALL_NO_WG_SE       (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
 480
 481 /* Used to align parameters.  See the comment before tcgv_i32_temp.  */
 482 #define TCG_CALL_DUMMY_ARG      ((TCGArg)0)
 483
 484 /* Conditions.  Note that these are laid out for easy manipulation by
 485    the functions below:
 486      bit 0 is used for inverting;
 487      bit 1 is signed,
 488      bit 2 is unsigned,
 489      bit 3 is used with bit 0 for swapping signed/unsigned.  */
 490 typedef enum {
 491     /* non-signed */
 492     TCG_COND_NEVER  = 0 | 0 | 0 | 0,
 493     TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
 494     TCG_COND_EQ     = 8 | 0 | 0 | 0,
 495     TCG_COND_NE     = 8 | 0 | 0 | 1,
 496     /* signed */
 497     TCG_COND_LT     = 0 | 0 | 2 | 0,
 498     TCG_COND_GE     = 0 | 0 | 2 | 1,
 499     TCG_COND_LE     = 8 | 0 | 2 | 0,
 500     TCG_COND_GT     = 8 | 0 | 2 | 1,
 501     /* unsigned */
 502     TCG_COND_LTU    = 0 | 4 | 0 | 0,
 503     TCG_COND_GEU    = 0 | 4 | 0 | 1,
 504     TCG_COND_LEU    = 8 | 4 | 0 | 0,
 505     TCG_COND_GTU    = 8 | 4 | 0 | 1,
 506 } TCGCond;
 507
 508 /* Invert the sense of the comparison.  */
 509 static inline TCGCond tcg_invert_cond(TCGCond c)
 510 {
 511     return (TCGCond)(c ^ 1);
 512 }
 513
 514 /* Swap the operands in a comparison.  */
 515 static inline TCGCond tcg_swap_cond(TCGCond c)
 516 {
 517     return c & 6 ? (TCGCond)(c ^ 9) : c;
 518 }
 519
 520 /* Create an "unsigned" version of a "signed" comparison.  */
 521 static inline TCGCond tcg_unsigned_cond(TCGCond c)
 522 {
 523     return c & 2 ? (TCGCond)(c ^ 6) : c;
 524 }
 525
 526 /* Create a "signed" version of an "unsigned" comparison.  */
 527 static inline TCGCond tcg_signed_cond(TCGCond c)
 528 {
 529     return c & 4 ? (TCGCond)(c ^ 6) : c;
 530 }
 531
 532 /* Must a comparison be considered unsigned?  */
 533 static inline bool is_unsigned_cond(TCGCond c)
 534 {
 535     return (c & 4) != 0;
 536 }
 537
 538 /* Create a "high" version of a double-word comparison.
 539    This removes equality from a LTE or GTE comparison.  */
 540 static inline TCGCond tcg_high_cond(TCGCond c)
 541 {
 542     switch (c) {
 543     case TCG_COND_GE:
 544     case TCG_COND_LE:
 545     case TCG_COND_GEU:
 546     case TCG_COND_LEU:
 547         return (TCGCond)(c ^ 8);
 548     default:
 549         return c;
 550     }
 551 }
 552
 553 typedef enum TCGTempVal {
 554     TEMP_VAL_DEAD,
 555     TEMP_VAL_REG,
 556     TEMP_VAL_MEM,
 557     TEMP_VAL_CONST,
 558 } TCGTempVal;
 559
 560 typedef struct TCGTemp {
 561     TCGReg reg:8;
 562     TCGTempVal val_type:8;
 563     TCGType base_type:8;
 564     TCGType type:8;
 565     unsigned int fixed_reg:1;
 566     unsigned int indirect_reg:1;
 567     unsigned int indirect_base:1;
 568     unsigned int mem_coherent:1;
 569     unsigned int mem_allocated:1;
 570     /* If true, the temp is saved across both basic blocks and
 571        translation blocks.  */
 572     unsigned int temp_global:1;
 573     /* If true, the temp is saved across basic blocks but dead
 574        at the end of translation blocks.  If false, the temp is
 575        dead at the end of basic blocks.  */
 576     unsigned int temp_local:1;
 577     unsigned int temp_allocated:1;
 578
 579     tcg_target_long val;
 580     struct TCGTemp *mem_base;
 581     intptr_t mem_offset;
 582     const char *name;
 583
 584     /* Pass-specific information that can be stored for a temporary.
 585        One word worth of integer data, and one pointer to data
 586        allocated separately.  */
 587     uintptr_t state;
 588     void *state_ptr;
 589 } TCGTemp;
 590
 591 typedef struct TCGContext TCGContext;
 592
 593 typedef struct TCGTempSet {
 594     unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
 595 } TCGTempSet;
 596
 597 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
 598    this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
 599    There are never more than 2 outputs, which means that we can store all
 600    dead + sync data within 16 bits.  */
 601 #define DEAD_ARG  4
 602 #define SYNC_ARG  1
 603 typedef uint16_t TCGLifeData;
 604
 605 /* The layout here is designed to avoid a bitfield crossing of
 606    a 32-bit boundary, which would cause GCC to add extra padding.  */
 607 typedef struct TCGOp {
 608     TCGOpcode opc   : 8;        /*  8 */
 609
 610     /* Parameters for this opcode.  See below.  */
 611     unsigned param1 : 4;        /* 12 */
 612     unsigned param2 : 4;        /* 16 */
 613
 614     /* Lifetime data of the operands.  */
 615     unsigned life   : 16;       /* 32 */
 616
 617     /* Next and previous opcodes.  */
 618     QTAILQ_ENTRY(TCGOp) link;
 619
 620     /* Arguments for the opcode.  */
 621     TCGArg args[MAX_OPC_PARAM];
 622
 623     /* Register preferences for the output(s).  */
 624     TCGRegSet output_pref[2];
 625 } TCGOp;
 626
 627 #define TCGOP_CALLI(X)    (X)->param1
 628 #define TCGOP_CALLO(X)    (X)->param2
 629
 630 #define TCGOP_VECL(X)     (X)->param1
 631 #define TCGOP_VECE(X)     (X)->param2
 632
 633 /* Make sure operands fit in the bitfields above.  */
 634 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
 635
 636 typedef struct TCGProfile {
 637     int64_t cpu_exec_time;
 638     int64_t tb_count1;
 639     int64_t tb_count;
 640     int64_t op_count; /* total insn count */
 641     int op_count_max; /* max insn per TB */
 642     int temp_count_max;
 643     int64_t temp_count;
 644     int64_t del_op_count;
 645     int64_t code_in_len;
 646     int64_t code_out_len;
 647     int64_t search_out_len;
 648     int64_t interm_time;
 649     int64_t code_time;
 650     int64_t la_time;
 651     int64_t opt_time;
 652     int64_t restore_count;
 653     int64_t restore_time;
 654     int64_t table_op_count[NB_OPS];
 655 } TCGProfile;
 656
 657 struct TCGContext {
 658     uint8_t *pool_cur, *pool_end;
 659     TCGPool *pool_first, *pool_current, *pool_first_large;
 660     int nb_labels;
 661     int nb_globals;
 662     int nb_temps;
 663     int nb_indirects;
 664     int nb_ops;
 665
 666     /* goto_tb support */
 667     tcg_insn_unit *code_buf;
 668     uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
 669     uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */
 670     uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
 671
 672     TCGRegSet reserved_regs;
 673     uint32_t tb_cflags; /* cflags of the current TB */
 674     intptr_t current_frame_offset;
 675     intptr_t frame_start;
 676     intptr_t frame_end;
 677     TCGTemp *frame_temp;
 678
 679     tcg_insn_unit *code_ptr;
 680
 681 #ifdef CONFIG_PROFILER
 682     TCGProfile prof;
 683 #endif
 684
 685 #ifdef CONFIG_DEBUG_TCG
 686     int temps_in_use;
 687     int goto_tb_issue_mask;
 688 #endif
 689
 690     /* Code generation.  Note that we specifically do not use tcg_insn_unit
 691        here, because there's too much arithmetic throughout that relies
 692        on addition and subtraction working on bytes.  Rely on the GCC
 693        extension that allows arithmetic on void*.  */
 694     void *code_gen_prologue;
 695     void *code_gen_epilogue;
 696     void *code_gen_buffer;
 697     size_t code_gen_buffer_size;
 698     void *code_gen_ptr;
 699     void *data_gen_ptr;
 700
 701     /* Threshold to flush the translated code buffer.  */
 702     void *code_gen_highwater;
 703
 704     size_t tb_phys_invalidate_count;
 705
 706     /* Track which vCPU triggers events */
 707     CPUState *cpu;                      /* *_trans */
 708
 709     /* These structures are private to tcg-target.inc.c.  */
 710 #ifdef TCG_TARGET_NEED_LDST_LABELS
 711     QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels;
 712 #endif
 713 #ifdef TCG_TARGET_NEED_POOL_LABELS
 714     struct TCGLabelPoolData *pool_labels;
 715 #endif
 716
 717     TCGLabel *exitreq_label;
 718
 719     TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
 720     TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
 721
 722     QTAILQ_HEAD(, TCGOp) ops, free_ops;
 723
 724     /* Tells which temporary holds a given register.
 725        It does not take into account fixed registers */
 726     TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
 727
 728     uint16_t gen_insn_end_off[TCG_MAX_INSNS];
 729     target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
 730 };
 731
 732 extern TCGContext tcg_init_ctx;
 733 extern __thread TCGContext *tcg_ctx;
 734 extern TCGv_env cpu_env;
 735
 736 static inline size_t temp_idx(TCGTemp *ts)
 737 {
 738     ptrdiff_t n = ts - tcg_ctx->temps;
 739     tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps);
 740     return n;
 741 }
 742
 743 static inline TCGArg temp_arg(TCGTemp *ts)
 744 {
 745     return (uintptr_t)ts;
 746 }
 747
 748 static inline TCGTemp *arg_temp(TCGArg a)
 749 {
 750     return (TCGTemp *)(uintptr_t)a;
 751 }
 752
 753 /* Using the offset of a temporary, relative to TCGContext, rather than
 754    its index means that we don't use 0.  That leaves offset 0 free for
 755    a NULL representation without having to leave index 0 unused.  */
 756 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v)
 757 {
 758     uintptr_t o = (uintptr_t)v;
 759     TCGTemp *t = (void *)tcg_ctx + o;
 760     tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o);
 761     return t;
 762 }
 763
 764 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v)
 765 {
 766     return tcgv_i32_temp((TCGv_i32)v);
 767 }
 768
 769 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v)
 770 {
 771     return tcgv_i32_temp((TCGv_i32)v);
 772 }
 773
 774 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v)
 775 {
 776     return tcgv_i32_temp((TCGv_i32)v);
 777 }
 778
 779 static inline TCGArg tcgv_i32_arg(TCGv_i32 v)
 780 {
 781     return temp_arg(tcgv_i32_temp(v));
 782 }
 783
 784 static inline TCGArg tcgv_i64_arg(TCGv_i64 v)
 785 {
 786     return temp_arg(tcgv_i64_temp(v));
 787 }
 788
 789 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
 790 {
 791     return temp_arg(tcgv_ptr_temp(v));
 792 }
 793
 794 static inline TCGArg tcgv_vec_arg(TCGv_vec v)
 795 {
 796     return temp_arg(tcgv_vec_temp(v));
 797 }
 798
 799 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
 800 {
 801     (void)temp_idx(t); /* trigger embedded assert */
 802     return (TCGv_i32)((void *)t - (void *)tcg_ctx);
 803 }
 804
 805 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
 806 {
 807     return (TCGv_i64)temp_tcgv_i32(t);
 808 }
 809
 810 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
 811 {
 812     return (TCGv_ptr)temp_tcgv_i32(t);
 813 }
 814
 815 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
 816 {
 817     return (TCGv_vec)temp_tcgv_i32(t);
 818 }
 819
 820 #if TCG_TARGET_REG_BITS == 32
 821 static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
 822 {
 823     return temp_tcgv_i32(tcgv_i64_temp(t));
 824 }
 825
 826 static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
 827 {
 828     return temp_tcgv_i32(tcgv_i64_temp(t) + 1);
 829 }
 830 #endif
 831
 832 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
 833 {
 834     op->args[arg] = v;
 835 }
 836
 837 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
 838 {
 839 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
 840     tcg_set_insn_param(op, arg, v);
 841 #else
 842     tcg_set_insn_param(op, arg * 2, v);
 843     tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
 844 #endif
 845 }
 846
 847 /* The last op that was emitted.  */
 848 static inline TCGOp *tcg_last_op(void)
 849 {
 850     return QTAILQ_LAST(&tcg_ctx->ops);
 851 }
 852
 853 /* Test for whether to terminate the TB for using too many opcodes.  */
 854 static inline bool tcg_op_buf_full(void)
 855 {
 856     /* This is not a hard limit, it merely stops translation when
 857      * we have produced "enough" opcodes.  We want to limit TB size
 858      * such that a RISC host can reasonably use a 16-bit signed
 859      * branch within the TB.  We also need to be mindful of the
 860      * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[]
 861      * and TCGContext.gen_insn_end_off[].
 862      */
 863     return tcg_ctx->nb_ops >= 4000;
 864 }
 865
 866 /* pool based memory allocation */
 867
 868 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */
 869 void *tcg_malloc_internal(TCGContext *s, int size);
 870 void tcg_pool_reset(TCGContext *s);
 871 TranslationBlock *tcg_tb_alloc(TCGContext *s);
 872
 873 void tcg_region_init(void);
 874 void tcg_region_reset_all(void);
 875
 876 size_t tcg_code_size(void);
 877 size_t tcg_code_capacity(void);
 878
 879 void tcg_tb_insert(TranslationBlock *tb);
 880 void tcg_tb_remove(TranslationBlock *tb);
 881 size_t tcg_tb_phys_invalidate_count(void);
 882 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr);
 883 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data);
 884 size_t tcg_nb_tbs(void);
 885
 886 /* user-mode: Called with mmap_lock held.  */
 887 static inline void *tcg_malloc(int size)
 888 {
 889     TCGContext *s = tcg_ctx;
 890     uint8_t *ptr, *ptr_end;
 891
 892     /* ??? This is a weak placeholder for minimum malloc alignment.  */
 893     size = QEMU_ALIGN_UP(size, 8);
 894
 895     ptr = s->pool_cur;
 896     ptr_end = ptr + size;
 897     if (unlikely(ptr_end > s->pool_end)) {
 898         return tcg_malloc_internal(tcg_ctx, size);
 899     } else {
 900         s->pool_cur = ptr_end;
 901         return ptr;
 902     }
 903 }
 904
 905 void tcg_context_init(TCGContext *s);
 906 void tcg_register_thread(void);
 907 void tcg_prologue_init(TCGContext *s);
 908 void tcg_func_start(TCGContext *s);
 909
 910 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
 911
 912 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 913
 914 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
 915                                      intptr_t, const char *);
 916 TCGTemp *tcg_temp_new_internal(TCGType, bool);
 917 void tcg_temp_free_internal(TCGTemp *);
 918 TCGv_vec tcg_temp_new_vec(TCGType type);
 919 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
 920
 921 static inline void tcg_temp_free_i32(TCGv_i32 arg)
 922 {
 923     tcg_temp_free_internal(tcgv_i32_temp(arg));
 924 }
 925
 926 static inline void tcg_temp_free_i64(TCGv_i64 arg)
 927 {
 928     tcg_temp_free_internal(tcgv_i64_temp(arg));
 929 }
 930
 931 static inline void tcg_temp_free_ptr(TCGv_ptr arg)
 932 {
 933     tcg_temp_free_internal(tcgv_ptr_temp(arg));
 934 }
 935
 936 static inline void tcg_temp_free_vec(TCGv_vec arg)
 937 {
 938     tcg_temp_free_internal(tcgv_vec_temp(arg));
 939 }
 940
 941 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
 942                                               const char *name)
 943 {
 944     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
 945     return temp_tcgv_i32(t);
 946 }
 947
 948 static inline TCGv_i32 tcg_temp_new_i32(void)
 949 {
 950     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false);
 951     return temp_tcgv_i32(t);
 952 }
 953
 954 static inline TCGv_i32 tcg_temp_local_new_i32(void)
 955 {
 956     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true);
 957     return temp_tcgv_i32(t);
 958 }
 959
 960 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
 961                                               const char *name)
 962 {
 963     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
 964     return temp_tcgv_i64(t);
 965 }
 966
 967 static inline TCGv_i64 tcg_temp_new_i64(void)
 968 {
 969     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false);
 970     return temp_tcgv_i64(t);
 971 }
 972
 973 static inline TCGv_i64 tcg_temp_local_new_i64(void)
 974 {
 975     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true);
 976     return temp_tcgv_i64(t);
 977 }
 978
 979 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
 980                                               const char *name)
 981 {
 982     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name);
 983     return temp_tcgv_ptr(t);
 984 }
 985
 986 static inline TCGv_ptr tcg_temp_new_ptr(void)
 987 {
 988     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false);
 989     return temp_tcgv_ptr(t);
 990 }
 991
 992 static inline TCGv_ptr tcg_temp_local_new_ptr(void)
 993 {
 994     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true);
 995     return temp_tcgv_ptr(t);
 996 }
 997
 998 #if defined(CONFIG_DEBUG_TCG)
 999 /* If you call tcg_clear_temp_count() at the start of a section of
1000  * code which is not supposed to leak any TCG temporaries, then
1001  * calling tcg_check_temp_count() at the end of the section will
1002  * return 1 if the section did in fact leak a temporary.
1003  */
1004 void tcg_clear_temp_count(void);
1005 int tcg_check_temp_count(void);
1006 #else
1007 #define tcg_clear_temp_count() do { } while (0)
1008 #define tcg_check_temp_count() 0
1009 #endif
1010
1011 int64_t tcg_cpu_exec_time(void);
1012 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf);
1013 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf);
1014
1015 #define TCG_CT_ALIAS  0x80
1016 #define TCG_CT_IALIAS 0x40
1017 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
1018 #define TCG_CT_REG    0x01
1019 #define TCG_CT_CONST  0x02 /* any constant of register size */
1020
1021 typedef struct TCGArgConstraint {
1022     uint16_t ct;
1023     uint8_t alias_index;
1024     union {
1025         TCGRegSet regs;
1026     } u;
1027 } TCGArgConstraint;
1028
1029 #define TCG_MAX_OP_ARGS 16
1030
1031 /* Bits for TCGOpDef->flags, 8 bits available.  */
1032 enum {
1033     /* Instruction exits the translation block.  */
1034     TCG_OPF_BB_EXIT      = 0x01,
1035     /* Instruction defines the end of a basic block.  */
1036     TCG_OPF_BB_END       = 0x02,
1037     /* Instruction clobbers call registers and potentially update globals.  */
1038     TCG_OPF_CALL_CLOBBER = 0x04,
1039     /* Instruction has side effects: it cannot be removed if its outputs
1040        are not used, and might trigger exceptions.  */
1041     TCG_OPF_SIDE_EFFECTS = 0x08,
1042     /* Instruction operands are 64-bits (otherwise 32-bits).  */
1043     TCG_OPF_64BIT        = 0x10,
1044     /* Instruction is optional and not implemented by the host, or insn
1045        is generic and should not be implemened by the host.  */
1046     TCG_OPF_NOT_PRESENT  = 0x20,
1047     /* Instruction operands are vectors.  */
1048     TCG_OPF_VECTOR       = 0x40,
1049 };
1050
1051 typedef struct TCGOpDef {
1052     const char *name;
1053     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
1054     uint8_t flags;
1055     TCGArgConstraint *args_ct;
1056     int *sorted_args;
1057 #if defined(CONFIG_DEBUG_TCG)
1058     int used;
1059 #endif
1060 } TCGOpDef;
1061
1062 extern TCGOpDef tcg_op_defs[];
1063 extern const size_t tcg_op_defs_max;
1064
1065 typedef struct TCGTargetOpDef {
1066     TCGOpcode op;
1067     const char *args_ct_str[TCG_MAX_OP_ARGS];
1068 } TCGTargetOpDef;
1069
1070 #define tcg_abort() \
1071 do {\
1072     fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
1073     abort();\
1074 } while (0)
1075
1076 bool tcg_op_supported(TCGOpcode op);
1077
1078 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args);
1079
1080 TCGOp *tcg_emit_op(TCGOpcode opc);
1081 void tcg_op_remove(TCGContext *s, TCGOp *op);
1082 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc);
1083 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc);
1084
1085 void tcg_optimize(TCGContext *s);
1086
1087 TCGv_i32 tcg_const_i32(int32_t val);
1088 TCGv_i64 tcg_const_i64(int64_t val);
1089 TCGv_i32 tcg_const_local_i32(int32_t val);
1090 TCGv_i64 tcg_const_local_i64(int64_t val);
1091 TCGv_vec tcg_const_zeros_vec(TCGType);
1092 TCGv_vec tcg_const_ones_vec(TCGType);
1093 TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
1094 TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
1095
1096 #if UINTPTR_MAX == UINT32_MAX
1097 # define tcg_const_ptr(x)        ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
1098 # define tcg_const_local_ptr(x)  ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
1099 #else
1100 # define tcg_const_ptr(x)        ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
1101 # define tcg_const_local_ptr(x)  ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x)))
1102 #endif
1103
1104 TCGLabel *gen_new_label(void);
1105
1106 /**
1107  * label_arg
1108  * @l: label
1109  *
1110  * Encode a label for storage in the TCG opcode stream.
1111  */
1112
1113 static inline TCGArg label_arg(TCGLabel *l)
1114 {
1115     return (uintptr_t)l;
1116 }
1117
1118 /**
1119  * arg_label
1120  * @i: value
1121  *
1122  * The opposite of label_arg.  Retrieve a label from the
1123  * encoding of the TCG opcode stream.
1124  */
1125
1126 static inline TCGLabel *arg_label(TCGArg i)
1127 {
1128     return (TCGLabel *)(uintptr_t)i;
1129 }
1130
1131 /**
1132  * tcg_ptr_byte_diff
1133  * @a, @b: addresses to be differenced
1134  *
1135  * There are many places within the TCG backends where we need a byte
1136  * difference between two pointers.  While this can be accomplished
1137  * with local casting, it's easy to get wrong -- especially if one is
1138  * concerned with the signedness of the result.
1139  *
1140  * This version relies on GCC's void pointer arithmetic to get the
1141  * correct result.
1142  */
1143
1144 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
1145 {
1146     return a - b;
1147 }
1148
1149 /**
1150  * tcg_pcrel_diff
1151  * @s: the tcg context
1152  * @target: address of the target
1153  *
1154  * Produce a pc-relative difference, from the current code_ptr
1155  * to the destination address.
1156  */
1157
1158 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
1159 {
1160     return tcg_ptr_byte_diff(target, s->code_ptr);
1161 }
1162
1163 /**
1164  * tcg_current_code_size
1165  * @s: the tcg context
1166  *
1167  * Compute the current code size within the translation block.
1168  * This is used to fill in qemu's data structures for goto_tb.
1169  */
1170
1171 static inline size_t tcg_current_code_size(TCGContext *s)
1172 {
1173     return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
1174 }
1175
1176 /* Combine the TCGMemOp and mmu_idx parameters into a single value.  */
1177 typedef uint32_t TCGMemOpIdx;
1178
1179 /**
1180  * make_memop_idx
1181  * @op: memory operation
1182  * @idx: mmu index
1183  *
1184  * Encode these values into a single parameter.
1185  */
1186 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
1187 {
1188     tcg_debug_assert(idx <= 15);
1189     return (op << 4) | idx;
1190 }
1191
1192 /**
1193  * get_memop
1194  * @oi: combined op/idx parameter
1195  *
1196  * Extract the memory operation from the combined value.
1197  */
1198 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
1199 {
1200     return oi >> 4;
1201 }
1202
1203 /**
1204  * get_mmuidx
1205  * @oi: combined op/idx parameter
1206  *
1207  * Extract the mmu index from the combined value.
1208  */
1209 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
1210 {
1211     return oi & 15;
1212 }
1213
1214 /**
1215  * tcg_qemu_tb_exec:
1216  * @env: pointer to CPUArchState for the CPU
1217  * @tb_ptr: address of generated code for the TB to execute
1218  *
1219  * Start executing code from a given translation block.
1220  * Where translation blocks have been linked, execution
1221  * may proceed from the given TB into successive ones.
1222  * Control eventually returns only when some action is needed
1223  * from the top-level loop: either control must pass to a TB
1224  * which has not yet been directly linked, or an asynchronous
1225  * event such as an interrupt needs handling.
1226  *
1227  * Return: The return value is the value passed to the corresponding
1228  * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1229  * The value is either zero or a 4-byte aligned pointer to that TB combined
1230  * with additional information in its two least significant bits. The
1231  * additional information is encoded as follows:
1232  *  0, 1: the link between this TB and the next is via the specified
1233  *        TB index (0 or 1). That is, we left the TB via (the equivalent
1234  *        of) "goto_tb <index>". The main loop uses this to determine
1235  *        how to link the TB just executed to the next.
1236  *  2:    we are using instruction counting code generation, and we
1237  *        did not start executing this TB because the instruction counter
1238  *        would hit zero midway through it. In this case the pointer
1239  *        returned is the TB we were about to execute, and the caller must
1240  *        arrange to execute the remaining count of instructions.
1241  *  3:    we stopped because the CPU's exit_request flag was set
1242  *        (usually meaning that there is an interrupt that needs to be
1243  *        handled). The pointer returned is the TB we were about to execute
1244  *        when we noticed the pending exit request.
1245  *
1246  * If the bottom two bits indicate an exit-via-index then the CPU
1247  * state is correctly synchronised and ready for execution of the next
1248  * TB (and in particular the guest PC is the address to execute next).
1249  * Otherwise, we gave up on execution of this TB before it started, and
1250  * the caller must fix up the CPU state by calling the CPU's
1251  * synchronize_from_tb() method with the TB pointer we return (falling
1252  * back to calling the CPU's set_pc method with tb->pb if no
1253  * synchronize_from_tb() method exists).
1254  *
1255  * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1256  * to this default (which just calls the prologue.code emitted by
1257  * tcg_target_qemu_prologue()).
1258  */
1259 #define TB_EXIT_MASK      3
1260 #define TB_EXIT_IDX0      0
1261 #define TB_EXIT_IDX1      1
1262 #define TB_EXIT_IDXMAX    1
1263 #define TB_EXIT_REQUESTED 3
1264
1265 #ifdef HAVE_TCG_QEMU_TB_EXEC
1266 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1267 #else
1268 # define tcg_qemu_tb_exec(env, tb_ptr) \
1269     ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
1270 #endif
1271
1272 void tcg_register_jit(void *buf, size_t buf_size);
1273
1274 #if TCG_TARGET_MAYBE_vec
1275 /* Return zero if the tuple (opc, type, vece) is unsupportable;
1276    return > 0 if it is directly supportable;
1277    return < 0 if we must call tcg_expand_vec_op.  */
1278 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
1279 #else
1280 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
1281 {
1282     return 0;
1283 }
1284 #endif
1285
1286 /* Expand the tuple (opc, type, vece) on the given arguments.  */
1287 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
1288
1289 /* Replicate a constant C accoring to the log2 of the element size.  */
1290 uint64_t dup_const(unsigned vece, uint64_t c);
1291
1292 #define dup_const(VECE, C)                                         \
1293     (__builtin_constant_p(VECE)                                    \
1294      ? (  (VECE) == MO_8  ? 0x0101010101010101ull * (uint8_t)(C)   \
1295         : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C)  \
1296         : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C)  \
1297         : dup_const(VECE, C))                                      \
1298      : dup_const(VECE, C))
1299
1300
1301 /*
1302  * Memory helpers that will be used by TCG generated code.
1303  */
1304 #ifdef CONFIG_SOFTMMU
1305 /* Value zero-extended to tcg register size.  */
1306 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1307                                      TCGMemOpIdx oi, uintptr_t retaddr);
1308 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1309                                     TCGMemOpIdx oi, uintptr_t retaddr);
1310 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1311                                     TCGMemOpIdx oi, uintptr_t retaddr);
1312 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1313                            TCGMemOpIdx oi, uintptr_t retaddr);
1314 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1315                                     TCGMemOpIdx oi, uintptr_t retaddr);
1316 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1317                                     TCGMemOpIdx oi, uintptr_t retaddr);
1318 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1319                            TCGMemOpIdx oi, uintptr_t retaddr);
1320
1321 /* Value sign-extended to tcg register size.  */
1322 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1323                                      TCGMemOpIdx oi, uintptr_t retaddr);
1324 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1325                                     TCGMemOpIdx oi, uintptr_t retaddr);
1326 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1327                                     TCGMemOpIdx oi, uintptr_t retaddr);
1328 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1329                                     TCGMemOpIdx oi, uintptr_t retaddr);
1330 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1331                                     TCGMemOpIdx oi, uintptr_t retaddr);
1332
1333 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1334                         TCGMemOpIdx oi, uintptr_t retaddr);
1335 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1336                        TCGMemOpIdx oi, uintptr_t retaddr);
1337 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1338                        TCGMemOpIdx oi, uintptr_t retaddr);
1339 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1340                        TCGMemOpIdx oi, uintptr_t retaddr);
1341 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1342                        TCGMemOpIdx oi, uintptr_t retaddr);
1343 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1344                        TCGMemOpIdx oi, uintptr_t retaddr);
1345 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1346                        TCGMemOpIdx oi, uintptr_t retaddr);
1347
1348 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1349                             TCGMemOpIdx oi, uintptr_t retaddr);
1350 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1351                             TCGMemOpIdx oi, uintptr_t retaddr);
1352 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1353                             TCGMemOpIdx oi, uintptr_t retaddr);
1354 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1355                             TCGMemOpIdx oi, uintptr_t retaddr);
1356 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1357                             TCGMemOpIdx oi, uintptr_t retaddr);
1358 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1359                             TCGMemOpIdx oi, uintptr_t retaddr);
1360 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1361                             TCGMemOpIdx oi, uintptr_t retaddr);
1362
1363 /* Temporary aliases until backends are converted.  */
1364 #ifdef TARGET_WORDS_BIGENDIAN
1365 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
1366 # define helper_ret_lduw_mmu  helper_be_lduw_mmu
1367 # define helper_ret_ldsl_mmu  helper_be_ldsl_mmu
1368 # define helper_ret_ldul_mmu  helper_be_ldul_mmu
1369 # define helper_ret_ldl_mmu   helper_be_ldul_mmu
1370 # define helper_ret_ldq_mmu   helper_be_ldq_mmu
1371 # define helper_ret_stw_mmu   helper_be_stw_mmu
1372 # define helper_ret_stl_mmu   helper_be_stl_mmu
1373 # define helper_ret_stq_mmu   helper_be_stq_mmu
1374 # define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
1375 # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
1376 # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
1377 #else
1378 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
1379 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
1380 # define helper_ret_ldsl_mmu  helper_le_ldsl_mmu
1381 # define helper_ret_ldul_mmu  helper_le_ldul_mmu
1382 # define helper_ret_ldl_mmu   helper_le_ldul_mmu
1383 # define helper_ret_ldq_mmu   helper_le_ldq_mmu
1384 # define helper_ret_stw_mmu   helper_le_stw_mmu
1385 # define helper_ret_stl_mmu   helper_le_stl_mmu
1386 # define helper_ret_stq_mmu   helper_le_stq_mmu
1387 # define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
1388 # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
1389 # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
1390 #endif
1391
1392 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
1393                                     uint32_t cmpv, uint32_t newv,
1394                                     TCGMemOpIdx oi, uintptr_t retaddr);
1395 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
1396                                        uint32_t cmpv, uint32_t newv,
1397                                        TCGMemOpIdx oi, uintptr_t retaddr);
1398 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
1399                                        uint32_t cmpv, uint32_t newv,
1400                                        TCGMemOpIdx oi, uintptr_t retaddr);
1401 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
1402                                        uint64_t cmpv, uint64_t newv,
1403                                        TCGMemOpIdx oi, uintptr_t retaddr);
1404 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
1405                                        uint32_t cmpv, uint32_t newv,
1406                                        TCGMemOpIdx oi, uintptr_t retaddr);
1407 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
1408                                        uint32_t cmpv, uint32_t newv,
1409                                        TCGMemOpIdx oi, uintptr_t retaddr);
1410 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
1411                                        uint64_t cmpv, uint64_t newv,
1412                                        TCGMemOpIdx oi, uintptr_t retaddr);
1413
1414 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX)         \
1415 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu         \
1416     (CPUArchState *env, target_ulong addr, TYPE val,  \
1417      TCGMemOpIdx oi, uintptr_t retaddr);
1418
1419 #ifdef CONFIG_ATOMIC64
1420 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1421     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1422     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1423     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1424     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1425     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)  \
1426     GEN_ATOMIC_HELPER(NAME, uint64_t, q_le)  \
1427     GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1428 #else
1429 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1430     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1431     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1432     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1433     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1434     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1435 #endif
1436
1437 GEN_ATOMIC_HELPER_ALL(fetch_add)
1438 GEN_ATOMIC_HELPER_ALL(fetch_sub)
1439 GEN_ATOMIC_HELPER_ALL(fetch_and)
1440 GEN_ATOMIC_HELPER_ALL(fetch_or)
1441 GEN_ATOMIC_HELPER_ALL(fetch_xor)
1442 GEN_ATOMIC_HELPER_ALL(fetch_smin)
1443 GEN_ATOMIC_HELPER_ALL(fetch_umin)
1444 GEN_ATOMIC_HELPER_ALL(fetch_smax)
1445 GEN_ATOMIC_HELPER_ALL(fetch_umax)
1446
1447 GEN_ATOMIC_HELPER_ALL(add_fetch)
1448 GEN_ATOMIC_HELPER_ALL(sub_fetch)
1449 GEN_ATOMIC_HELPER_ALL(and_fetch)
1450 GEN_ATOMIC_HELPER_ALL(or_fetch)
1451 GEN_ATOMIC_HELPER_ALL(xor_fetch)
1452 GEN_ATOMIC_HELPER_ALL(smin_fetch)
1453 GEN_ATOMIC_HELPER_ALL(umin_fetch)
1454 GEN_ATOMIC_HELPER_ALL(smax_fetch)
1455 GEN_ATOMIC_HELPER_ALL(umax_fetch)
1456
1457 GEN_ATOMIC_HELPER_ALL(xchg)
1458
1459 #undef GEN_ATOMIC_HELPER_ALL
1460 #undef GEN_ATOMIC_HELPER
1461 #endif /* CONFIG_SOFTMMU */
1462
1463 /*
1464  * These aren't really a "proper" helpers because TCG cannot manage Int128.
1465  * However, use the same format as the others, for use by the backends.
1466  *
1467  * The cmpxchg functions are only defined if HAVE_CMPXCHG128;
1468  * the ld/st functions are only defined if HAVE_ATOMIC128,
1469  * as defined by <qemu/atomic128.h>.
1470  */
1471 Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
1472                                      Int128 cmpv, Int128 newv,
1473                                      TCGMemOpIdx oi, uintptr_t retaddr);
1474 Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
1475                                      Int128 cmpv, Int128 newv,
1476                                      TCGMemOpIdx oi, uintptr_t retaddr);
1477
1478 Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
1479                                 TCGMemOpIdx oi, uintptr_t retaddr);
1480 Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
1481                                 TCGMemOpIdx oi, uintptr_t retaddr);
1482 void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1483                               TCGMemOpIdx oi, uintptr_t retaddr);
1484 void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1485                               TCGMemOpIdx oi, uintptr_t retaddr);
1486
1487 #endif /* TCG_H */