2 * User emulator execution
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "hw/core/tcg-cpu-ops.h"
22 #include "disas/disas.h"
23 #include "exec/exec-all.h"
25 #include "qemu/bitops.h"
26 #include "exec/cpu_ldst.h"
27 #include "exec/translate-all.h"
28 #include "exec/helper-proto.h"
29 #include "qemu/atomic128.h"
30 #include "trace/trace-root.h"
31 #include "trace/mem.h"
43 #include <sys/ucontext.h>
46 __thread
uintptr_t helper_retaddr
;
48 //#define DEBUG_SIGNAL
50 /* exit the current TB from a signal handler. The host registers are
51 restored in a state compatible with the CPU emulator
53 static void QEMU_NORETURN
cpu_exit_tb_from_sighandler(CPUState
*cpu
,
56 /* XXX: use siglongjmp ? */
57 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
58 cpu_loop_exit_noexc(cpu
);
61 /* 'pc' is the host PC at which the exception was raised. 'address' is
62 the effective address of the memory exception. 'is_write' is 1 if a
63 write caused the exception and otherwise 0'. 'old_set' is the
64 signal set which should be restored */
65 static inline int handle_cpu_signal(uintptr_t pc
, siginfo_t
*info
,
66 int is_write
, sigset_t
*old_set
)
68 CPUState
*cpu
= current_cpu
;
70 unsigned long address
= (unsigned long)info
->si_addr
;
71 MMUAccessType access_type
= is_write
? MMU_DATA_STORE
: MMU_DATA_LOAD
;
73 switch (helper_retaddr
) {
76 * Fault during host memory operation within a helper function.
77 * The helper's host return address, saved here, gives us a
78 * pointer into the generated code that will unwind to the
86 * Fault during host memory operation within generated code.
87 * (Or, a unrelated bug within qemu, but we can't tell from here).
89 * We take the host pc from the signal frame. However, we cannot
90 * use that value directly. Within cpu_restore_state_from_tb, we
91 * assume PC comes from GETPC(), as used by the helper functions,
92 * so we adjust the address by -GETPC_ADJ to form an address that
93 * is within the call insn, so that the address does not accidentally
94 * match the beginning of the next guest insn. However, when the
95 * pc comes from the signal frame it points to the actual faulting
96 * host memory insn and not the return from a call insn.
98 * Therefore, adjust to compensate for what will be done later
99 * by cpu_restore_state_from_tb.
106 * Fault during host read for translation, or loosely, "execution".
108 * The guest pc is already pointing to the start of the TB for which
109 * code is being generated. If the guest translator manages the
110 * page crossings correctly, this is exactly the correct address
111 * (and if the translator doesn't handle page boundaries correctly
112 * there's little we can do about that here). Therefore, do not
113 * trigger the unwinder.
115 * Like tb_gen_code, release the memory lock before cpu_loop_exit.
118 access_type
= MMU_INST_FETCH
;
123 /* For synchronous signals we expect to be coming from the vCPU
124 * thread (so current_cpu should be valid) and either from running
125 * code or during translation which can fault as we cross pages.
127 * If neither is true then something has gone wrong and we should
128 * abort rather than try and restart the vCPU execution.
130 if (!cpu
|| !cpu
->running
) {
131 printf("qemu:%s received signal outside vCPU context @ pc=0x%"
132 PRIxPTR
"\n", __func__
, pc
);
136 #if defined(DEBUG_SIGNAL)
137 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
138 pc
, address
, is_write
, *(unsigned long *)old_set
);
140 /* XXX: locking issue */
141 /* Note that it is important that we don't call page_unprotect() unless
142 * this is really a "write to nonwriteable page" fault, because
143 * page_unprotect() assumes that if it is called for an access to
144 * a page that's writeable this means we had two threads racing and
145 * another thread got there first and already made the page writeable;
146 * so we will retry the access. If we were to call page_unprotect()
147 * for some other kind of fault that should really be passed to the
148 * guest, we'd end up in an infinite loop of retrying the faulting
151 if (is_write
&& info
->si_signo
== SIGSEGV
&& info
->si_code
== SEGV_ACCERR
&&
152 h2g_valid(address
)) {
153 switch (page_unprotect(h2g(address
), pc
)) {
155 /* Fault not caused by a page marked unwritable to protect
156 * cached translations, must be the guest binary's problem.
160 /* Fault caused by protection of cached translation; TBs
161 * invalidated, so resume execution. Retain helper_retaddr
162 * for a possible second fault.
166 /* Fault caused by protection of cached translation, and the
167 * currently executing TB was modified and must be exited
168 * immediately. Clear helper_retaddr for next execution.
170 clear_helper_retaddr();
171 cpu_exit_tb_from_sighandler(cpu
, old_set
);
175 g_assert_not_reached();
179 /* Convert forcefully to guest address space, invalid addresses
180 are still valid segv ones */
181 address
= h2g_nocheck(address
);
184 * There is no way the target can handle this other than raising
185 * an exception. Undo signal and retaddr state prior to longjmp.
187 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
188 clear_helper_retaddr();
190 cc
= CPU_GET_CLASS(cpu
);
191 cc
->tcg_ops
->tlb_fill(cpu
, address
, 0, access_type
,
192 MMU_USER_IDX
, false, pc
);
193 g_assert_not_reached();
196 static int probe_access_internal(CPUArchState
*env
, target_ulong addr
,
197 int fault_size
, MMUAccessType access_type
,
198 bool nonfault
, uintptr_t ra
)
202 switch (access_type
) {
213 g_assert_not_reached();
216 if (!guest_addr_valid_untagged(addr
) ||
217 page_check_range(addr
, 1, flags
) < 0) {
219 return TLB_INVALID_MASK
;
221 CPUState
*cpu
= env_cpu(env
);
222 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
223 cc
->tcg_ops
->tlb_fill(cpu
, addr
, fault_size
, access_type
,
224 MMU_USER_IDX
, false, ra
);
225 g_assert_not_reached();
231 int probe_access_flags(CPUArchState
*env
, target_ulong addr
,
232 MMUAccessType access_type
, int mmu_idx
,
233 bool nonfault
, void **phost
, uintptr_t ra
)
237 flags
= probe_access_internal(env
, addr
, 0, access_type
, nonfault
, ra
);
238 *phost
= flags
? NULL
: g2h(env_cpu(env
), addr
);
242 void *probe_access(CPUArchState
*env
, target_ulong addr
, int size
,
243 MMUAccessType access_type
, int mmu_idx
, uintptr_t ra
)
247 g_assert(-(addr
| TARGET_PAGE_MASK
) >= size
);
248 flags
= probe_access_internal(env
, addr
, size
, access_type
, false, ra
);
249 g_assert(flags
== 0);
251 return size
? g2h(env_cpu(env
), addr
) : NULL
;
254 #if defined(__i386__)
256 #if defined(__NetBSD__)
257 #include <ucontext.h>
259 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
260 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
261 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
262 #define MASK_sig(context) ((context)->uc_sigmask)
263 #elif defined(__FreeBSD__) || defined(__DragonFly__)
264 #include <ucontext.h>
266 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
267 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
268 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
269 #define MASK_sig(context) ((context)->uc_sigmask)
270 #elif defined(__OpenBSD__)
271 #define EIP_sig(context) ((context)->sc_eip)
272 #define TRAP_sig(context) ((context)->sc_trapno)
273 #define ERROR_sig(context) ((context)->sc_err)
274 #define MASK_sig(context) ((context)->sc_mask)
276 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
277 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
278 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
279 #define MASK_sig(context) ((context)->uc_sigmask)
282 int cpu_signal_handler(int host_signum
, void *pinfo
,
285 siginfo_t
*info
= pinfo
;
286 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
287 ucontext_t
*uc
= puc
;
288 #elif defined(__OpenBSD__)
289 struct sigcontext
*uc
= puc
;
291 ucontext_t
*uc
= puc
;
300 #define REG_TRAPNO TRAPNO
303 trapno
= TRAP_sig(uc
);
304 return handle_cpu_signal(pc
, info
,
305 trapno
== 0xe ? (ERROR_sig(uc
) >> 1) & 1 : 0,
309 #elif defined(__x86_64__)
312 #define PC_sig(context) _UC_MACHINE_PC(context)
313 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
314 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
315 #define MASK_sig(context) ((context)->uc_sigmask)
316 #elif defined(__OpenBSD__)
317 #define PC_sig(context) ((context)->sc_rip)
318 #define TRAP_sig(context) ((context)->sc_trapno)
319 #define ERROR_sig(context) ((context)->sc_err)
320 #define MASK_sig(context) ((context)->sc_mask)
321 #elif defined(__FreeBSD__) || defined(__DragonFly__)
322 #include <ucontext.h>
324 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
325 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
326 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
327 #define MASK_sig(context) ((context)->uc_sigmask)
329 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
330 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
331 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
332 #define MASK_sig(context) ((context)->uc_sigmask)
335 int cpu_signal_handler(int host_signum
, void *pinfo
,
338 siginfo_t
*info
= pinfo
;
340 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
341 ucontext_t
*uc
= puc
;
342 #elif defined(__OpenBSD__)
343 struct sigcontext
*uc
= puc
;
345 ucontext_t
*uc
= puc
;
349 return handle_cpu_signal(pc
, info
,
350 TRAP_sig(uc
) == 0xe ? (ERROR_sig(uc
) >> 1) & 1 : 0,
354 #elif defined(_ARCH_PPC)
356 /***********************************************************************
357 * signal context platform-specific definitions
361 /* All Registers access - only for local access */
362 #define REG_sig(reg_name, context) \
363 ((context)->uc_mcontext.regs->reg_name)
364 /* Gpr Registers access */
365 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
366 /* Program counter */
367 #define IAR_sig(context) REG_sig(nip, context)
368 /* Machine State Register (Supervisor) */
369 #define MSR_sig(context) REG_sig(msr, context)
371 #define CTR_sig(context) REG_sig(ctr, context)
372 /* User's integer exception register */
373 #define XER_sig(context) REG_sig(xer, context)
375 #define LR_sig(context) REG_sig(link, context)
376 /* Condition register */
377 #define CR_sig(context) REG_sig(ccr, context)
379 /* Float Registers access */
380 #define FLOAT_sig(reg_num, context) \
381 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
382 #define FPSCR_sig(context) \
383 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
384 /* Exception Registers access */
385 #define DAR_sig(context) REG_sig(dar, context)
386 #define DSISR_sig(context) REG_sig(dsisr, context)
387 #define TRAP_sig(context) REG_sig(trap, context)
390 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
391 #include <ucontext.h>
392 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
393 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
394 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
395 #define XER_sig(context) ((context)->uc_mcontext.mc_xer)
396 #define LR_sig(context) ((context)->uc_mcontext.mc_lr)
397 #define CR_sig(context) ((context)->uc_mcontext.mc_cr)
398 /* Exception Registers access */
399 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
400 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
401 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
402 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
404 int cpu_signal_handler(int host_signum
, void *pinfo
,
407 siginfo_t
*info
= pinfo
;
408 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
409 ucontext_t
*uc
= puc
;
411 ucontext_t
*uc
= puc
;
420 if (DSISR_sig(uc
) & 0x00800000) {
424 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000)) {
428 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
431 #elif defined(__alpha__)
433 int cpu_signal_handler(int host_signum
, void *pinfo
,
436 siginfo_t
*info
= pinfo
;
437 ucontext_t
*uc
= puc
;
438 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
442 /* XXX: need kernel patch to get write flag faster */
443 switch (insn
>> 26) {
446 case 0x0f: /* stq_u */
453 case 0x2e: /* stl_c */
454 case 0x2f: /* stq_c */
458 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
460 #elif defined(__sparc__)
462 int cpu_signal_handler(int host_signum
, void *pinfo
,
465 siginfo_t
*info
= pinfo
;
468 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
469 uint32_t *regs
= (uint32_t *)(info
+ 1);
470 void *sigmask
= (regs
+ 20);
471 /* XXX: is there a standard glibc define ? */
472 unsigned long pc
= regs
[1];
475 struct sigcontext
*sc
= puc
;
476 unsigned long pc
= sc
->sigc_regs
.tpc
;
477 void *sigmask
= (void *)sc
->sigc_mask
;
478 #elif defined(__OpenBSD__)
479 struct sigcontext
*uc
= puc
;
480 unsigned long pc
= uc
->sc_pc
;
481 void *sigmask
= (void *)(long)uc
->sc_mask
;
482 #elif defined(__NetBSD__)
483 ucontext_t
*uc
= puc
;
484 unsigned long pc
= _UC_MACHINE_PC(uc
);
485 void *sigmask
= (void *)&uc
->uc_sigmask
;
489 /* XXX: need kernel patch to get write flag faster */
491 insn
= *(uint32_t *)pc
;
492 if ((insn
>> 30) == 3) {
493 switch ((insn
>> 19) & 0x3f) {
495 case 0x15: /* stba */
497 case 0x16: /* stha */
501 case 0x17: /* stda */
503 case 0x1e: /* stxa */
505 case 0x34: /* stfa */
506 case 0x27: /* stdf */
507 case 0x37: /* stdfa */
508 case 0x26: /* stqf */
509 case 0x36: /* stqfa */
510 case 0x25: /* stfsr */
511 case 0x3c: /* casa */
512 case 0x3e: /* casxa */
517 return handle_cpu_signal(pc
, info
, is_write
, sigmask
);
520 #elif defined(__arm__)
522 #if defined(__NetBSD__)
523 #include <ucontext.h>
524 #include <sys/siginfo.h>
527 int cpu_signal_handler(int host_signum
, void *pinfo
,
530 siginfo_t
*info
= pinfo
;
531 #if defined(__NetBSD__)
532 ucontext_t
*uc
= puc
;
533 siginfo_t
*si
= pinfo
;
535 ucontext_t
*uc
= puc
;
541 #if defined(__NetBSD__)
542 pc
= uc
->uc_mcontext
.__gregs
[_REG_R15
];
543 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
544 pc
= uc
->uc_mcontext
.gregs
[R15
];
546 pc
= uc
->uc_mcontext
.arm_pc
;
552 fsr
= uc
->uc_mcontext
.error_code
;
555 * In the FSR, bit 11 is WnR, assuming a v6 or
556 * later processor. On v5 we will always report
557 * this as a read, which will fail later.
559 is_write
= extract32(fsr
, 11, 1);
560 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
563 #elif defined(__aarch64__)
565 #if defined(__NetBSD__)
567 #include <ucontext.h>
568 #include <sys/siginfo.h>
570 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
572 ucontext_t
*uc
= puc
;
573 siginfo_t
*si
= pinfo
;
578 pc
= uc
->uc_mcontext
.__gregs
[_REG_PC
];
582 * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC
583 * is 0b10010x: then bit 6 is the WnR bit
585 is_write
= extract32(esr
, 27, 5) == 0x12 && extract32(esr
, 6, 1) == 1;
586 return handle_cpu_signal(pc
, si
, is_write
, &uc
->uc_sigmask
);
592 /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
593 #define ESR_MAGIC 0x45535201
595 struct _aarch64_ctx head
;
600 static inline struct _aarch64_ctx
*first_ctx(ucontext_t
*uc
)
602 return (struct _aarch64_ctx
*)&uc
->uc_mcontext
.__reserved
;
605 static inline struct _aarch64_ctx
*next_ctx(struct _aarch64_ctx
*hdr
)
607 return (struct _aarch64_ctx
*)((char *)hdr
+ hdr
->size
);
610 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
612 siginfo_t
*info
= pinfo
;
613 ucontext_t
*uc
= puc
;
614 uintptr_t pc
= uc
->uc_mcontext
.pc
;
616 struct _aarch64_ctx
*hdr
;
617 struct esr_context
const *esrctx
= NULL
;
619 /* Find the esr_context, which has the WnR bit in it */
620 for (hdr
= first_ctx(uc
); hdr
->magic
; hdr
= next_ctx(hdr
)) {
621 if (hdr
->magic
== ESR_MAGIC
) {
622 esrctx
= (struct esr_context
const *)hdr
;
628 /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */
629 uint64_t esr
= esrctx
->esr
;
630 is_write
= extract32(esr
, 27, 5) == 0x12 && extract32(esr
, 6, 1) == 1;
633 * Fall back to parsing instructions; will only be needed
634 * for really ancient (pre-3.16) kernels.
636 uint32_t insn
= *(uint32_t *)pc
;
638 is_write
= ((insn
& 0xbfff0000) == 0x0c000000 /* C3.3.1 */
639 || (insn
& 0xbfe00000) == 0x0c800000 /* C3.3.2 */
640 || (insn
& 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
641 || (insn
& 0xbfc00000) == 0x0d800000 /* C3.3.4 */
642 || (insn
& 0x3f400000) == 0x08000000 /* C3.3.6 */
643 || (insn
& 0x3bc00000) == 0x39000000 /* C3.3.13 */
644 || (insn
& 0x3fc00000) == 0x3d800000 /* ... 128bit */
645 /* Ignore bits 10, 11 & 21, controlling indexing. */
646 || (insn
& 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
647 || (insn
& 0x3fe00000) == 0x3c800000 /* ... 128bit */
648 /* Ignore bits 23 & 24, controlling indexing. */
649 || (insn
& 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
651 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
655 #elif defined(__s390__)
657 int cpu_signal_handler(int host_signum
, void *pinfo
,
660 siginfo_t
*info
= pinfo
;
661 ucontext_t
*uc
= puc
;
666 pc
= uc
->uc_mcontext
.psw
.addr
;
668 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
669 of the normal 2 arguments. The 3rd argument contains the "int_code"
670 from the hardware which does in fact contain the is_write value.
671 The rt signal handler, as far as I can tell, does not give this value
672 at all. Not that we could get to it from here even if it were. */
673 /* ??? This is not even close to complete, since it ignores all
674 of the read-modify-write instructions. */
675 pinsn
= (uint16_t *)pc
;
676 switch (pinsn
[0] >> 8) {
682 case 0xc4: /* RIL format insns */
683 switch (pinsn
[0] & 0xf) {
685 case 0xb: /* STGRL */
686 case 0x7: /* STHRL */
690 case 0xe3: /* RXY format insns */
691 switch (pinsn
[2] & 0xff) {
694 case 0x72: /* STCY */
695 case 0x70: /* STHY */
696 case 0x8e: /* STPQ */
697 case 0x3f: /* STRVH */
698 case 0x3e: /* STRV */
699 case 0x2f: /* STRVG */
704 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
707 #elif defined(__mips__)
709 #if defined(__misp16) || defined(__mips_micromips)
710 #error "Unsupported encoding"
713 int cpu_signal_handler(int host_signum
, void *pinfo
,
716 siginfo_t
*info
= pinfo
;
717 ucontext_t
*uc
= puc
;
718 uintptr_t pc
= uc
->uc_mcontext
.pc
;
719 uint32_t insn
= *(uint32_t *)pc
;
722 /* Detect all store instructions at program counter. */
723 switch((insn
>> 26) & 077) {
736 #if !defined(__mips_isa_rev) || __mips_isa_rev < 6
742 case 023: /* COP1X */
743 /* Required in all versions of MIPS64 since
744 MIPS64r1 and subsequent versions of MIPS32r2. */
745 switch (insn
& 077) {
746 case 010: /* SWXC1 */
747 case 011: /* SDXC1 */
748 case 015: /* SUXC1 */
754 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
757 #elif defined(__riscv)
759 int cpu_signal_handler(int host_signum
, void *pinfo
,
762 siginfo_t
*info
= pinfo
;
763 ucontext_t
*uc
= puc
;
764 greg_t pc
= uc
->uc_mcontext
.__gregs
[REG_PC
];
765 uint32_t insn
= *(uint32_t *)pc
;
768 /* Detect store by reading the instruction at the program
769 counter. Note: we currently only generate 32-bit
770 instructions so we thus only detect 32-bit stores */
771 switch (((insn
>> 0) & 0b11)) {
773 switch (((insn
>> 2) & 0b11111)) {
775 switch (((insn
>> 12) & 0b111)) {
788 switch (((insn
>> 12) & 0b111)) {
803 /* Check for compressed instructions */
804 switch (((insn
>> 13) & 0b111)) {
806 switch (insn
& 0b11) {
816 switch (insn
& 0b11) {
829 return handle_cpu_signal(pc
, info
, is_write
, &uc
->uc_sigmask
);
834 #error host CPU specific signal handler needed
838 /* The softmmu versions of these helpers are in cputlb.c. */
840 uint32_t cpu_ldub_data(CPUArchState
*env
, abi_ptr ptr
)
843 uint16_t meminfo
= trace_mem_get_info(MO_UB
, MMU_USER_IDX
, false);
845 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
846 ret
= ldub_p(g2h(env_cpu(env
), ptr
));
847 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
851 int cpu_ldsb_data(CPUArchState
*env
, abi_ptr ptr
)
854 uint16_t meminfo
= trace_mem_get_info(MO_SB
, MMU_USER_IDX
, false);
856 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
857 ret
= ldsb_p(g2h(env_cpu(env
), ptr
));
858 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
862 uint32_t cpu_lduw_be_data(CPUArchState
*env
, abi_ptr ptr
)
865 uint16_t meminfo
= trace_mem_get_info(MO_BEUW
, MMU_USER_IDX
, false);
867 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
868 ret
= lduw_be_p(g2h(env_cpu(env
), ptr
));
869 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
873 int cpu_ldsw_be_data(CPUArchState
*env
, abi_ptr ptr
)
876 uint16_t meminfo
= trace_mem_get_info(MO_BESW
, MMU_USER_IDX
, false);
878 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
879 ret
= ldsw_be_p(g2h(env_cpu(env
), ptr
));
880 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
884 uint32_t cpu_ldl_be_data(CPUArchState
*env
, abi_ptr ptr
)
887 uint16_t meminfo
= trace_mem_get_info(MO_BEUL
, MMU_USER_IDX
, false);
889 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
890 ret
= ldl_be_p(g2h(env_cpu(env
), ptr
));
891 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
895 uint64_t cpu_ldq_be_data(CPUArchState
*env
, abi_ptr ptr
)
898 uint16_t meminfo
= trace_mem_get_info(MO_BEQ
, MMU_USER_IDX
, false);
900 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
901 ret
= ldq_be_p(g2h(env_cpu(env
), ptr
));
902 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
906 uint32_t cpu_lduw_le_data(CPUArchState
*env
, abi_ptr ptr
)
909 uint16_t meminfo
= trace_mem_get_info(MO_LEUW
, MMU_USER_IDX
, false);
911 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
912 ret
= lduw_le_p(g2h(env_cpu(env
), ptr
));
913 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
917 int cpu_ldsw_le_data(CPUArchState
*env
, abi_ptr ptr
)
920 uint16_t meminfo
= trace_mem_get_info(MO_LESW
, MMU_USER_IDX
, false);
922 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
923 ret
= ldsw_le_p(g2h(env_cpu(env
), ptr
));
924 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
928 uint32_t cpu_ldl_le_data(CPUArchState
*env
, abi_ptr ptr
)
931 uint16_t meminfo
= trace_mem_get_info(MO_LEUL
, MMU_USER_IDX
, false);
933 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
934 ret
= ldl_le_p(g2h(env_cpu(env
), ptr
));
935 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
939 uint64_t cpu_ldq_le_data(CPUArchState
*env
, abi_ptr ptr
)
942 uint16_t meminfo
= trace_mem_get_info(MO_LEQ
, MMU_USER_IDX
, false);
944 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
945 ret
= ldq_le_p(g2h(env_cpu(env
), ptr
));
946 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
950 uint32_t cpu_ldub_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
954 set_helper_retaddr(retaddr
);
955 ret
= cpu_ldub_data(env
, ptr
);
956 clear_helper_retaddr();
960 int cpu_ldsb_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
964 set_helper_retaddr(retaddr
);
965 ret
= cpu_ldsb_data(env
, ptr
);
966 clear_helper_retaddr();
970 uint32_t cpu_lduw_be_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
974 set_helper_retaddr(retaddr
);
975 ret
= cpu_lduw_be_data(env
, ptr
);
976 clear_helper_retaddr();
980 int cpu_ldsw_be_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
984 set_helper_retaddr(retaddr
);
985 ret
= cpu_ldsw_be_data(env
, ptr
);
986 clear_helper_retaddr();
990 uint32_t cpu_ldl_be_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
994 set_helper_retaddr(retaddr
);
995 ret
= cpu_ldl_be_data(env
, ptr
);
996 clear_helper_retaddr();
1000 uint64_t cpu_ldq_be_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1004 set_helper_retaddr(retaddr
);
1005 ret
= cpu_ldq_be_data(env
, ptr
);
1006 clear_helper_retaddr();
1010 uint32_t cpu_lduw_le_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1014 set_helper_retaddr(retaddr
);
1015 ret
= cpu_lduw_le_data(env
, ptr
);
1016 clear_helper_retaddr();
1020 int cpu_ldsw_le_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1024 set_helper_retaddr(retaddr
);
1025 ret
= cpu_ldsw_le_data(env
, ptr
);
1026 clear_helper_retaddr();
1030 uint32_t cpu_ldl_le_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1034 set_helper_retaddr(retaddr
);
1035 ret
= cpu_ldl_le_data(env
, ptr
);
1036 clear_helper_retaddr();
1040 uint64_t cpu_ldq_le_data_ra(CPUArchState
*env
, abi_ptr ptr
, uintptr_t retaddr
)
1044 set_helper_retaddr(retaddr
);
1045 ret
= cpu_ldq_le_data(env
, ptr
);
1046 clear_helper_retaddr();
1050 void cpu_stb_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
1052 uint16_t meminfo
= trace_mem_get_info(MO_UB
, MMU_USER_IDX
, true);
1054 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1055 stb_p(g2h(env_cpu(env
), ptr
), val
);
1056 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1059 void cpu_stw_be_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
1061 uint16_t meminfo
= trace_mem_get_info(MO_BEUW
, MMU_USER_IDX
, true);
1063 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1064 stw_be_p(g2h(env_cpu(env
), ptr
), val
);
1065 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1068 void cpu_stl_be_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
1070 uint16_t meminfo
= trace_mem_get_info(MO_BEUL
, MMU_USER_IDX
, true);
1072 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1073 stl_be_p(g2h(env_cpu(env
), ptr
), val
);
1074 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1077 void cpu_stq_be_data(CPUArchState
*env
, abi_ptr ptr
, uint64_t val
)
1079 uint16_t meminfo
= trace_mem_get_info(MO_BEQ
, MMU_USER_IDX
, true);
1081 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1082 stq_be_p(g2h(env_cpu(env
), ptr
), val
);
1083 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1086 void cpu_stw_le_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
1088 uint16_t meminfo
= trace_mem_get_info(MO_LEUW
, MMU_USER_IDX
, true);
1090 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1091 stw_le_p(g2h(env_cpu(env
), ptr
), val
);
1092 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1095 void cpu_stl_le_data(CPUArchState
*env
, abi_ptr ptr
, uint32_t val
)
1097 uint16_t meminfo
= trace_mem_get_info(MO_LEUL
, MMU_USER_IDX
, true);
1099 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1100 stl_le_p(g2h(env_cpu(env
), ptr
), val
);
1101 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1104 void cpu_stq_le_data(CPUArchState
*env
, abi_ptr ptr
, uint64_t val
)
1106 uint16_t meminfo
= trace_mem_get_info(MO_LEQ
, MMU_USER_IDX
, true);
1108 trace_guest_mem_before_exec(env_cpu(env
), ptr
, meminfo
);
1109 stq_le_p(g2h(env_cpu(env
), ptr
), val
);
1110 qemu_plugin_vcpu_mem_cb(env_cpu(env
), ptr
, meminfo
);
1113 void cpu_stb_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1114 uint32_t val
, uintptr_t retaddr
)
1116 set_helper_retaddr(retaddr
);
1117 cpu_stb_data(env
, ptr
, val
);
1118 clear_helper_retaddr();
1121 void cpu_stw_be_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1122 uint32_t val
, uintptr_t retaddr
)
1124 set_helper_retaddr(retaddr
);
1125 cpu_stw_be_data(env
, ptr
, val
);
1126 clear_helper_retaddr();
1129 void cpu_stl_be_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1130 uint32_t val
, uintptr_t retaddr
)
1132 set_helper_retaddr(retaddr
);
1133 cpu_stl_be_data(env
, ptr
, val
);
1134 clear_helper_retaddr();
1137 void cpu_stq_be_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1138 uint64_t val
, uintptr_t retaddr
)
1140 set_helper_retaddr(retaddr
);
1141 cpu_stq_be_data(env
, ptr
, val
);
1142 clear_helper_retaddr();
1145 void cpu_stw_le_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1146 uint32_t val
, uintptr_t retaddr
)
1148 set_helper_retaddr(retaddr
);
1149 cpu_stw_le_data(env
, ptr
, val
);
1150 clear_helper_retaddr();
1153 void cpu_stl_le_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1154 uint32_t val
, uintptr_t retaddr
)
1156 set_helper_retaddr(retaddr
);
1157 cpu_stl_le_data(env
, ptr
, val
);
1158 clear_helper_retaddr();
1161 void cpu_stq_le_data_ra(CPUArchState
*env
, abi_ptr ptr
,
1162 uint64_t val
, uintptr_t retaddr
)
1164 set_helper_retaddr(retaddr
);
1165 cpu_stq_le_data(env
, ptr
, val
);
1166 clear_helper_retaddr();
1169 uint32_t cpu_ldub_code(CPUArchState
*env
, abi_ptr ptr
)
1173 set_helper_retaddr(1);
1174 ret
= ldub_p(g2h_untagged(ptr
));
1175 clear_helper_retaddr();
1179 uint32_t cpu_lduw_code(CPUArchState
*env
, abi_ptr ptr
)
1183 set_helper_retaddr(1);
1184 ret
= lduw_p(g2h_untagged(ptr
));
1185 clear_helper_retaddr();
1189 uint32_t cpu_ldl_code(CPUArchState
*env
, abi_ptr ptr
)
1193 set_helper_retaddr(1);
1194 ret
= ldl_p(g2h_untagged(ptr
));
1195 clear_helper_retaddr();
1199 uint64_t cpu_ldq_code(CPUArchState
*env
, abi_ptr ptr
)
1203 set_helper_retaddr(1);
1204 ret
= ldq_p(g2h_untagged(ptr
));
1205 clear_helper_retaddr();
1209 /* Do not allow unaligned operations to proceed. Return the host address. */
1210 static void *atomic_mmu_lookup(CPUArchState
*env
, target_ulong addr
,
1211 int size
, uintptr_t retaddr
)
1213 /* Enforce qemu required alignment. */
1214 if (unlikely(addr
& (size
- 1))) {
1215 cpu_loop_exit_atomic(env_cpu(env
), retaddr
);
1217 void *ret
= g2h(env_cpu(env
), addr
);
1218 set_helper_retaddr(retaddr
);
1222 /* Macro to call the above, with local variables from the use context. */
1223 #define ATOMIC_MMU_DECLS do {} while (0)
1224 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC())
1225 #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0)
1226 #define ATOMIC_MMU_IDX MMU_USER_IDX
1228 #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
1231 #include "atomic_common.c.inc"
1234 #include "atomic_template.h"
1237 #include "atomic_template.h"
1240 #include "atomic_template.h"
1242 #ifdef CONFIG_ATOMIC64
1244 #include "atomic_template.h"
1247 /* The following is only callable from other helpers, and matches up
1248 with the softmmu version. */
1250 #if HAVE_ATOMIC128 || HAVE_CMPXCHG128
1254 #undef ATOMIC_MMU_LOOKUP
1256 #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr
1257 #define ATOMIC_NAME(X) \
1258 HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu))
1259 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr)
1261 #define DATA_SIZE 16
1262 #include "atomic_template.h"