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net/vmxnet3: Refactor 'vmxnet_rx_pkt_attach_data'
[qemu/ar7.git] / target-cris / translate.c
blob3e59601eb4dd96690c3ad6e2b9df4978c174ae23
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * FIXME:
23 * The condition code translation is in need of attention.
24 */
25
26 #include "cpu.h"
27 #include "disas/disas.h"
28 #include "tcg-op.h"
29 #include "exec/helper-proto.h"
30 #include "mmu.h"
31 #include "exec/cpu_ldst.h"
32 #include "crisv32-decode.h"
33
34 #include "exec/helper-gen.h"
35
36 #include "trace-tcg.h"
37
38
39 #define DISAS_CRIS 0
40 #if DISAS_CRIS
41 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
42 #else
43 # define LOG_DIS(...) do { } while (0)
44 #endif
45
46 #define D(x)
47 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
48 #define BUG_ON(x) ({if (x) BUG();})
49
50 #define DISAS_SWI 5
51
52 /* Used by the decoder. */
53 #define EXTRACT_FIELD(src, start, end) \
54 (((src) >> start) & ((1 << (end - start + 1)) - 1))
55
56 #define CC_MASK_NZ 0xc
57 #define CC_MASK_NZV 0xe
58 #define CC_MASK_NZVC 0xf
59 #define CC_MASK_RNZV 0x10e
60
61 static TCGv_ptr cpu_env;
62 static TCGv cpu_R[16];
63 static TCGv cpu_PR[16];
64 static TCGv cc_x;
65 static TCGv cc_src;
66 static TCGv cc_dest;
67 static TCGv cc_result;
68 static TCGv cc_op;
69 static TCGv cc_size;
70 static TCGv cc_mask;
71
72 static TCGv env_btaken;
73 static TCGv env_btarget;
74 static TCGv env_pc;
75
76 #include "exec/gen-icount.h"
77
78 /* This is the state at translation time. */
79 typedef struct DisasContext {
80 CRISCPU *cpu;
81 target_ulong pc, ppc;
82
83 /* Decoder. */
84 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
85 uint32_t ir;
86 uint32_t opcode;
87 unsigned int op1;
88 unsigned int op2;
89 unsigned int zsize, zzsize;
90 unsigned int mode;
91 unsigned int postinc;
92
93 unsigned int size;
94 unsigned int src;
95 unsigned int dst;
96 unsigned int cond;
97
98 int update_cc;
99 int cc_op;
100 int cc_size;
101 uint32_t cc_mask;
102
103 int cc_size_uptodate; /* -1 invalid or last written value. */
104
105 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
106 int flags_uptodate; /* Wether or not $ccs is uptodate. */
107 int flagx_known; /* Wether or not flags_x has the x flag known at
108 translation time. */
109 int flags_x;
110
111 int clear_x; /* Clear x after this insn? */
112 int clear_prefix; /* Clear prefix after this insn? */
113 int clear_locked_irq; /* Clear the irq lockout. */
114 int cpustate_changed;
115 unsigned int tb_flags; /* tb dependent flags. */
116 int is_jmp;
117
118 #define JMP_NOJMP 0
119 #define JMP_DIRECT 1
120 #define JMP_DIRECT_CC 2
121 #define JMP_INDIRECT 3
122 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
123 uint32_t jmp_pc;
124
125 int delayed_branch;
126
127 struct TranslationBlock *tb;
128 int singlestep_enabled;
129 } DisasContext;
130
131 static void gen_BUG(DisasContext *dc, const char *file, int line)
132 {
133 printf("BUG: pc=%x %s %d\n", dc->pc, file, line);
134 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
135 cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line);
136 }
137
138 static const char *regnames[] =
139 {
140 "$r0", "$r1", "$r2", "$r3",
141 "$r4", "$r5", "$r6", "$r7",
142 "$r8", "$r9", "$r10", "$r11",
143 "$r12", "$r13", "$sp", "$acr",
144 };
145 static const char *pregnames[] =
146 {
147 "$bz", "$vr", "$pid", "$srs",
148 "$wz", "$exs", "$eda", "$mof",
149 "$dz", "$ebp", "$erp", "$srp",
150 "$nrp", "$ccs", "$usp", "$spc",
151 };
152
153 /* We need this table to handle preg-moves with implicit width. */
154 static int preg_sizes[] = {
155 1, /* bz. */
156 1, /* vr. */
157 4, /* pid. */
158 1, /* srs. */
159 2, /* wz. */
160 4, 4, 4,
161 4, 4, 4, 4,
162 4, 4, 4, 4,
163 };
164
165 #define t_gen_mov_TN_env(tn, member) \
166 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
167 #define t_gen_mov_env_TN(member, tn) \
168 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
169
170 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
171 {
172 assert(r >= 0 && r <= 15);
173 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
174 tcg_gen_mov_tl(tn, tcg_const_tl(0));
175 } else if (r == PR_VR) {
176 tcg_gen_mov_tl(tn, tcg_const_tl(32));
177 } else {
178 tcg_gen_mov_tl(tn, cpu_PR[r]);
179 }
180 }
181 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
182 {
183 assert(r >= 0 && r <= 15);
184 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
185 return;
186 } else if (r == PR_SRS) {
187 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
188 } else {
189 if (r == PR_PID) {
190 gen_helper_tlb_flush_pid(cpu_env, tn);
191 }
192 if (dc->tb_flags & S_FLAG && r == PR_SPC) {
193 gen_helper_spc_write(cpu_env, tn);
194 } else if (r == PR_CCS) {
195 dc->cpustate_changed = 1;
196 }
197 tcg_gen_mov_tl(cpu_PR[r], tn);
198 }
199 }
200
201 /* Sign extend at translation time. */
202 static int sign_extend(unsigned int val, unsigned int width)
203 {
204 int sval;
205
206 /* LSL. */
207 val <<= 31 - width;
208 sval = val;
209 /* ASR. */
210 sval >>= 31 - width;
211 return sval;
212 }
213
214 static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
215 unsigned int size, unsigned int sign)
216 {
217 int r;
218
219 switch (size) {
220 case 4:
221 {
222 r = cpu_ldl_code(env, addr);
223 break;
224 }
225 case 2:
226 {
227 if (sign) {
228 r = cpu_ldsw_code(env, addr);
229 } else {
230 r = cpu_lduw_code(env, addr);
231 }
232 break;
233 }
234 case 1:
235 {
236 if (sign) {
237 r = cpu_ldsb_code(env, addr);
238 } else {
239 r = cpu_ldub_code(env, addr);
240 }
241 break;
242 }
243 default:
244 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
245 break;
246 }
247 return r;
248 }
249
250 static void cris_lock_irq(DisasContext *dc)
251 {
252 dc->clear_locked_irq = 0;
253 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
254 }
255
256 static inline void t_gen_raise_exception(uint32_t index)
257 {
258 TCGv_i32 tmp = tcg_const_i32(index);
259 gen_helper_raise_exception(cpu_env, tmp);
260 tcg_temp_free_i32(tmp);
261 }
262
263 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
264 {
265 TCGv t0, t_31;
266
267 t0 = tcg_temp_new();
268 t_31 = tcg_const_tl(31);
269 tcg_gen_shl_tl(d, a, b);
270
271 tcg_gen_sub_tl(t0, t_31, b);
272 tcg_gen_sar_tl(t0, t0, t_31);
273 tcg_gen_and_tl(t0, t0, d);
274 tcg_gen_xor_tl(d, d, t0);
275 tcg_temp_free(t0);
276 tcg_temp_free(t_31);
277 }
278
279 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
280 {
281 TCGv t0, t_31;
282
283 t0 = tcg_temp_new();
284 t_31 = tcg_temp_new();
285 tcg_gen_shr_tl(d, a, b);
286
287 tcg_gen_movi_tl(t_31, 31);
288 tcg_gen_sub_tl(t0, t_31, b);
289 tcg_gen_sar_tl(t0, t0, t_31);
290 tcg_gen_and_tl(t0, t0, d);
291 tcg_gen_xor_tl(d, d, t0);
292 tcg_temp_free(t0);
293 tcg_temp_free(t_31);
294 }
295
296 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
297 {
298 TCGv t0, t_31;
299
300 t0 = tcg_temp_new();
301 t_31 = tcg_temp_new();
302 tcg_gen_sar_tl(d, a, b);
303
304 tcg_gen_movi_tl(t_31, 31);
305 tcg_gen_sub_tl(t0, t_31, b);
306 tcg_gen_sar_tl(t0, t0, t_31);
307 tcg_gen_or_tl(d, d, t0);
308 tcg_temp_free(t0);
309 tcg_temp_free(t_31);
310 }
311
312 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
313 {
314 TCGLabel *l1 = gen_new_label();
315
316 /*
317 * d <<= 1
318 * if (d >= s)
319 * d -= s;
320 */
321 tcg_gen_shli_tl(d, a, 1);
322 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
323 tcg_gen_sub_tl(d, d, b);
324 gen_set_label(l1);
325 }
326
327 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
328 {
329 TCGv t;
330
331 /*
332 * d <<= 1
333 * if (n)
334 * d += s;
335 */
336 t = tcg_temp_new();
337 tcg_gen_shli_tl(d, a, 1);
338 tcg_gen_shli_tl(t, ccs, 31 - 3);
339 tcg_gen_sari_tl(t, t, 31);
340 tcg_gen_and_tl(t, t, b);
341 tcg_gen_add_tl(d, d, t);
342 tcg_temp_free(t);
343 }
344
345 /* Extended arithmetics on CRIS. */
346 static inline void t_gen_add_flag(TCGv d, int flag)
347 {
348 TCGv c;
349
350 c = tcg_temp_new();
351 t_gen_mov_TN_preg(c, PR_CCS);
352 /* Propagate carry into d. */
353 tcg_gen_andi_tl(c, c, 1 << flag);
354 if (flag) {
355 tcg_gen_shri_tl(c, c, flag);
356 }
357 tcg_gen_add_tl(d, d, c);
358 tcg_temp_free(c);
359 }
360
361 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
362 {
363 if (dc->flagx_known) {
364 if (dc->flags_x) {
365 TCGv c;
366
367 c = tcg_temp_new();
368 t_gen_mov_TN_preg(c, PR_CCS);
369 /* C flag is already at bit 0. */
370 tcg_gen_andi_tl(c, c, C_FLAG);
371 tcg_gen_add_tl(d, d, c);
372 tcg_temp_free(c);
373 }
374 } else {
375 TCGv x, c;
376
377 x = tcg_temp_new();
378 c = tcg_temp_new();
379 t_gen_mov_TN_preg(x, PR_CCS);
380 tcg_gen_mov_tl(c, x);
381
382 /* Propagate carry into d if X is set. Branch free. */
383 tcg_gen_andi_tl(c, c, C_FLAG);
384 tcg_gen_andi_tl(x, x, X_FLAG);
385 tcg_gen_shri_tl(x, x, 4);
386
387 tcg_gen_and_tl(x, x, c);
388 tcg_gen_add_tl(d, d, x);
389 tcg_temp_free(x);
390 tcg_temp_free(c);
391 }
392 }
393
394 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
395 {
396 if (dc->flagx_known) {
397 if (dc->flags_x) {
398 TCGv c;
399
400 c = tcg_temp_new();
401 t_gen_mov_TN_preg(c, PR_CCS);
402 /* C flag is already at bit 0. */
403 tcg_gen_andi_tl(c, c, C_FLAG);
404 tcg_gen_sub_tl(d, d, c);
405 tcg_temp_free(c);
406 }
407 } else {
408 TCGv x, c;
409
410 x = tcg_temp_new();
411 c = tcg_temp_new();
412 t_gen_mov_TN_preg(x, PR_CCS);
413 tcg_gen_mov_tl(c, x);
414
415 /* Propagate carry into d if X is set. Branch free. */
416 tcg_gen_andi_tl(c, c, C_FLAG);
417 tcg_gen_andi_tl(x, x, X_FLAG);
418 tcg_gen_shri_tl(x, x, 4);
419
420 tcg_gen_and_tl(x, x, c);
421 tcg_gen_sub_tl(d, d, x);
422 tcg_temp_free(x);
423 tcg_temp_free(c);
424 }
425 }
426
427 /* Swap the two bytes within each half word of the s operand.
428 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
429 static inline void t_gen_swapb(TCGv d, TCGv s)
430 {
431 TCGv t, org_s;
432
433 t = tcg_temp_new();
434 org_s = tcg_temp_new();
435
436 /* d and s may refer to the same object. */
437 tcg_gen_mov_tl(org_s, s);
438 tcg_gen_shli_tl(t, org_s, 8);
439 tcg_gen_andi_tl(d, t, 0xff00ff00);
440 tcg_gen_shri_tl(t, org_s, 8);
441 tcg_gen_andi_tl(t, t, 0x00ff00ff);
442 tcg_gen_or_tl(d, d, t);
443 tcg_temp_free(t);
444 tcg_temp_free(org_s);
445 }
446
447 /* Swap the halfwords of the s operand. */
448 static inline void t_gen_swapw(TCGv d, TCGv s)
449 {
450 TCGv t;
451 /* d and s refer the same object. */
452 t = tcg_temp_new();
453 tcg_gen_mov_tl(t, s);
454 tcg_gen_shli_tl(d, t, 16);
455 tcg_gen_shri_tl(t, t, 16);
456 tcg_gen_or_tl(d, d, t);
457 tcg_temp_free(t);
458 }
459
460 /* Reverse the within each byte.
461 T0 = (((T0 << 7) & 0x80808080) |
462 ((T0 << 5) & 0x40404040) |
463 ((T0 << 3) & 0x20202020) |
464 ((T0 << 1) & 0x10101010) |
465 ((T0 >> 1) & 0x08080808) |
466 ((T0 >> 3) & 0x04040404) |
467 ((T0 >> 5) & 0x02020202) |
468 ((T0 >> 7) & 0x01010101));
469 */
470 static inline void t_gen_swapr(TCGv d, TCGv s)
471 {
472 struct {
473 int shift; /* LSL when positive, LSR when negative. */
474 uint32_t mask;
475 } bitrev[] = {
476 {7, 0x80808080},
477 {5, 0x40404040},
478 {3, 0x20202020},
479 {1, 0x10101010},
480 {-1, 0x08080808},
481 {-3, 0x04040404},
482 {-5, 0x02020202},
483 {-7, 0x01010101}
484 };
485 int i;
486 TCGv t, org_s;
487
488 /* d and s refer the same object. */
489 t = tcg_temp_new();
490 org_s = tcg_temp_new();
491 tcg_gen_mov_tl(org_s, s);
492
493 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
494 tcg_gen_andi_tl(d, t, bitrev[0].mask);
495 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
496 if (bitrev[i].shift >= 0) {
497 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
498 } else {
499 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
500 }
501 tcg_gen_andi_tl(t, t, bitrev[i].mask);
502 tcg_gen_or_tl(d, d, t);
503 }
504 tcg_temp_free(t);
505 tcg_temp_free(org_s);
506 }
507
508 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
509 {
510 TCGLabel *l1 = gen_new_label();
511
512 /* Conditional jmp. */
513 tcg_gen_mov_tl(env_pc, pc_false);
514 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
515 tcg_gen_mov_tl(env_pc, pc_true);
516 gen_set_label(l1);
517 }
518
519 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
520 {
521 TranslationBlock *tb;
522 tb = dc->tb;
523 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
524 tcg_gen_goto_tb(n);
525 tcg_gen_movi_tl(env_pc, dest);
526 tcg_gen_exit_tb((uintptr_t)tb + n);
527 } else {
528 tcg_gen_movi_tl(env_pc, dest);
529 tcg_gen_exit_tb(0);
530 }
531 }
532
533 static inline void cris_clear_x_flag(DisasContext *dc)
534 {
535 if (dc->flagx_known && dc->flags_x) {
536 dc->flags_uptodate = 0;
537 }
538
539 dc->flagx_known = 1;
540 dc->flags_x = 0;
541 }
542
543 static void cris_flush_cc_state(DisasContext *dc)
544 {
545 if (dc->cc_size_uptodate != dc->cc_size) {
546 tcg_gen_movi_tl(cc_size, dc->cc_size);
547 dc->cc_size_uptodate = dc->cc_size;
548 }
549 tcg_gen_movi_tl(cc_op, dc->cc_op);
550 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
551 }
552
553 static void cris_evaluate_flags(DisasContext *dc)
554 {
555 if (dc->flags_uptodate) {
556 return;
557 }
558
559 cris_flush_cc_state(dc);
560
561 switch (dc->cc_op) {
562 case CC_OP_MCP:
563 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
564 cpu_PR[PR_CCS], cc_src,
565 cc_dest, cc_result);
566 break;
567 case CC_OP_MULS:
568 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
569 cpu_PR[PR_CCS], cc_result,
570 cpu_PR[PR_MOF]);
571 break;
572 case CC_OP_MULU:
573 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
574 cpu_PR[PR_CCS], cc_result,
575 cpu_PR[PR_MOF]);
576 break;
577 case CC_OP_MOVE:
578 case CC_OP_AND:
579 case CC_OP_OR:
580 case CC_OP_XOR:
581 case CC_OP_ASR:
582 case CC_OP_LSR:
583 case CC_OP_LSL:
584 switch (dc->cc_size) {
585 case 4:
586 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
587 cpu_env, cpu_PR[PR_CCS], cc_result);
588 break;
589 case 2:
590 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
591 cpu_env, cpu_PR[PR_CCS], cc_result);
592 break;
593 default:
594 gen_helper_evaluate_flags(cpu_env);
595 break;
596 }
597 break;
598 case CC_OP_FLAGS:
599 /* live. */
600 break;
601 case CC_OP_SUB:
602 case CC_OP_CMP:
603 if (dc->cc_size == 4) {
604 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
605 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
606 } else {
607 gen_helper_evaluate_flags(cpu_env);
608 }
609
610 break;
611 default:
612 switch (dc->cc_size) {
613 case 4:
614 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
615 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
616 break;
617 default:
618 gen_helper_evaluate_flags(cpu_env);
619 break;
620 }
621 break;
622 }
623
624 if (dc->flagx_known) {
625 if (dc->flags_x) {
626 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);
627 } else if (dc->cc_op == CC_OP_FLAGS) {
628 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
629 }
630 }
631 dc->flags_uptodate = 1;
632 }
633
634 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
635 {
636 uint32_t ovl;
637
638 if (!mask) {
639 dc->update_cc = 0;
640 return;
641 }
642
643 /* Check if we need to evaluate the condition codes due to
644 CC overlaying. */
645 ovl = (dc->cc_mask ^ mask) & ~mask;
646 if (ovl) {
647 /* TODO: optimize this case. It trigs all the time. */
648 cris_evaluate_flags(dc);
649 }
650 dc->cc_mask = mask;
651 dc->update_cc = 1;
652 }
653
654 static void cris_update_cc_op(DisasContext *dc, int op, int size)
655 {
656 dc->cc_op = op;
657 dc->cc_size = size;
658 dc->flags_uptodate = 0;
659 }
660
661 static inline void cris_update_cc_x(DisasContext *dc)
662 {
663 /* Save the x flag state at the time of the cc snapshot. */
664 if (dc->flagx_known) {
665 if (dc->cc_x_uptodate == (2 | dc->flags_x)) {
666 return;
667 }
668 tcg_gen_movi_tl(cc_x, dc->flags_x);
669 dc->cc_x_uptodate = 2 | dc->flags_x;
670 } else {
671 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
672 dc->cc_x_uptodate = 1;
673 }
674 }
675
676 /* Update cc prior to executing ALU op. Needs source operands untouched. */
677 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
678 TCGv dst, TCGv src, int size)
679 {
680 if (dc->update_cc) {
681 cris_update_cc_op(dc, op, size);
682 tcg_gen_mov_tl(cc_src, src);
683
684 if (op != CC_OP_MOVE
685 && op != CC_OP_AND
686 && op != CC_OP_OR
687 && op != CC_OP_XOR
688 && op != CC_OP_ASR
689 && op != CC_OP_LSR
690 && op != CC_OP_LSL) {
691 tcg_gen_mov_tl(cc_dest, dst);
692 }
693
694 cris_update_cc_x(dc);
695 }
696 }
697
698 /* Update cc after executing ALU op. needs the result. */
699 static inline void cris_update_result(DisasContext *dc, TCGv res)
700 {
701 if (dc->update_cc) {
702 tcg_gen_mov_tl(cc_result, res);
703 }
704 }
705
706 /* Returns one if the write back stage should execute. */
707 static void cris_alu_op_exec(DisasContext *dc, int op,
708 TCGv dst, TCGv a, TCGv b, int size)
709 {
710 /* Emit the ALU insns. */
711 switch (op) {
712 case CC_OP_ADD:
713 tcg_gen_add_tl(dst, a, b);
714 /* Extended arithmetics. */
715 t_gen_addx_carry(dc, dst);
716 break;
717 case CC_OP_ADDC:
718 tcg_gen_add_tl(dst, a, b);
719 t_gen_add_flag(dst, 0); /* C_FLAG. */
720 break;
721 case CC_OP_MCP:
722 tcg_gen_add_tl(dst, a, b);
723 t_gen_add_flag(dst, 8); /* R_FLAG. */
724 break;
725 case CC_OP_SUB:
726 tcg_gen_sub_tl(dst, a, b);
727 /* Extended arithmetics. */
728 t_gen_subx_carry(dc, dst);
729 break;
730 case CC_OP_MOVE:
731 tcg_gen_mov_tl(dst, b);
732 break;
733 case CC_OP_OR:
734 tcg_gen_or_tl(dst, a, b);
735 break;
736 case CC_OP_AND:
737 tcg_gen_and_tl(dst, a, b);
738 break;
739 case CC_OP_XOR:
740 tcg_gen_xor_tl(dst, a, b);
741 break;
742 case CC_OP_LSL:
743 t_gen_lsl(dst, a, b);
744 break;
745 case CC_OP_LSR:
746 t_gen_lsr(dst, a, b);
747 break;
748 case CC_OP_ASR:
749 t_gen_asr(dst, a, b);
750 break;
751 case CC_OP_NEG:
752 tcg_gen_neg_tl(dst, b);
753 /* Extended arithmetics. */
754 t_gen_subx_carry(dc, dst);
755 break;
756 case CC_OP_LZ:
757 gen_helper_lz(dst, b);
758 break;
759 case CC_OP_MULS:
760 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
761 break;
762 case CC_OP_MULU:
763 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
764 break;
765 case CC_OP_DSTEP:
766 t_gen_cris_dstep(dst, a, b);
767 break;
768 case CC_OP_MSTEP:
769 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
770 break;
771 case CC_OP_BOUND:
772 {
773 TCGLabel *l1 = gen_new_label();
774 tcg_gen_mov_tl(dst, a);
775 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
776 tcg_gen_mov_tl(dst, b);
777 gen_set_label(l1);
778 }
779 break;
780 case CC_OP_CMP:
781 tcg_gen_sub_tl(dst, a, b);
782 /* Extended arithmetics. */
783 t_gen_subx_carry(dc, dst);
784 break;
785 default:
786 qemu_log("illegal ALU op.\n");
787 BUG();
788 break;
789 }
790
791 if (size == 1) {
792 tcg_gen_andi_tl(dst, dst, 0xff);
793 } else if (size == 2) {
794 tcg_gen_andi_tl(dst, dst, 0xffff);
795 }
796 }
797
798 static void cris_alu(DisasContext *dc, int op,
799 TCGv d, TCGv op_a, TCGv op_b, int size)
800 {
801 TCGv tmp;
802 int writeback;
803
804 writeback = 1;
805
806 if (op == CC_OP_CMP) {
807 tmp = tcg_temp_new();
808 writeback = 0;
809 } else if (size == 4) {
810 tmp = d;
811 writeback = 0;
812 } else {
813 tmp = tcg_temp_new();
814 }
815
816
817 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
818 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
819 cris_update_result(dc, tmp);
820
821 /* Writeback. */
822 if (writeback) {
823 if (size == 1) {
824 tcg_gen_andi_tl(d, d, ~0xff);
825 } else {
826 tcg_gen_andi_tl(d, d, ~0xffff);
827 }
828 tcg_gen_or_tl(d, d, tmp);
829 }
830 if (!TCGV_EQUAL(tmp, d)) {
831 tcg_temp_free(tmp);
832 }
833 }
834
835 static int arith_cc(DisasContext *dc)
836 {
837 if (dc->update_cc) {
838 switch (dc->cc_op) {
839 case CC_OP_ADDC: return 1;
840 case CC_OP_ADD: return 1;
841 case CC_OP_SUB: return 1;
842 case CC_OP_DSTEP: return 1;
843 case CC_OP_LSL: return 1;
844 case CC_OP_LSR: return 1;
845 case CC_OP_ASR: return 1;
846 case CC_OP_CMP: return 1;
847 case CC_OP_NEG: return 1;
848 case CC_OP_OR: return 1;
849 case CC_OP_AND: return 1;
850 case CC_OP_XOR: return 1;
851 case CC_OP_MULU: return 1;
852 case CC_OP_MULS: return 1;
853 default:
854 return 0;
855 }
856 }
857 return 0;
858 }
859
860 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
861 {
862 int arith_opt, move_opt;
863
864 /* TODO: optimize more condition codes. */
865
866 /*
867 * If the flags are live, we've gotta look into the bits of CCS.
868 * Otherwise, if we just did an arithmetic operation we try to
869 * evaluate the condition code faster.
870 *
871 * When this function is done, T0 should be non-zero if the condition
872 * code is true.
873 */
874 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
875 move_opt = (dc->cc_op == CC_OP_MOVE);
876 switch (cond) {
877 case CC_EQ:
878 if ((arith_opt || move_opt)
879 && dc->cc_x_uptodate != (2 | X_FLAG)) {
880 tcg_gen_setcond_tl(TCG_COND_EQ, cc,
881 cc_result, tcg_const_tl(0));
882 } else {
883 cris_evaluate_flags(dc);
884 tcg_gen_andi_tl(cc,
885 cpu_PR[PR_CCS], Z_FLAG);
886 }
887 break;
888 case CC_NE:
889 if ((arith_opt || move_opt)
890 && dc->cc_x_uptodate != (2 | X_FLAG)) {
891 tcg_gen_mov_tl(cc, cc_result);
892 } else {
893 cris_evaluate_flags(dc);
894 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
895 Z_FLAG);
896 tcg_gen_andi_tl(cc, cc, Z_FLAG);
897 }
898 break;
899 case CC_CS:
900 cris_evaluate_flags(dc);
901 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
902 break;
903 case CC_CC:
904 cris_evaluate_flags(dc);
905 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
906 tcg_gen_andi_tl(cc, cc, C_FLAG);
907 break;
908 case CC_VS:
909 cris_evaluate_flags(dc);
910 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
911 break;
912 case CC_VC:
913 cris_evaluate_flags(dc);
914 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
915 V_FLAG);
916 tcg_gen_andi_tl(cc, cc, V_FLAG);
917 break;
918 case CC_PL:
919 if (arith_opt || move_opt) {
920 int bits = 31;
921
922 if (dc->cc_size == 1) {
923 bits = 7;
924 } else if (dc->cc_size == 2) {
925 bits = 15;
926 }
927
928 tcg_gen_shri_tl(cc, cc_result, bits);
929 tcg_gen_xori_tl(cc, cc, 1);
930 } else {
931 cris_evaluate_flags(dc);
932 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
933 N_FLAG);
934 tcg_gen_andi_tl(cc, cc, N_FLAG);
935 }
936 break;
937 case CC_MI:
938 if (arith_opt || move_opt) {
939 int bits = 31;
940
941 if (dc->cc_size == 1) {
942 bits = 7;
943 } else if (dc->cc_size == 2) {
944 bits = 15;
945 }
946
947 tcg_gen_shri_tl(cc, cc_result, bits);
948 tcg_gen_andi_tl(cc, cc, 1);
949 } else {
950 cris_evaluate_flags(dc);
951 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
952 N_FLAG);
953 }
954 break;
955 case CC_LS:
956 cris_evaluate_flags(dc);
957 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
958 C_FLAG | Z_FLAG);
959 break;
960 case CC_HI:
961 cris_evaluate_flags(dc);
962 {
963 TCGv tmp;
964
965 tmp = tcg_temp_new();
966 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
967 C_FLAG | Z_FLAG);
968 /* Overlay the C flag on top of the Z. */
969 tcg_gen_shli_tl(cc, tmp, 2);
970 tcg_gen_and_tl(cc, tmp, cc);
971 tcg_gen_andi_tl(cc, cc, Z_FLAG);
972
973 tcg_temp_free(tmp);
974 }
975 break;
976 case CC_GE:
977 cris_evaluate_flags(dc);
978 /* Overlay the V flag on top of the N. */
979 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
980 tcg_gen_xor_tl(cc,
981 cpu_PR[PR_CCS], cc);
982 tcg_gen_andi_tl(cc, cc, N_FLAG);
983 tcg_gen_xori_tl(cc, cc, N_FLAG);
984 break;
985 case CC_LT:
986 cris_evaluate_flags(dc);
987 /* Overlay the V flag on top of the N. */
988 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
989 tcg_gen_xor_tl(cc,
990 cpu_PR[PR_CCS], cc);
991 tcg_gen_andi_tl(cc, cc, N_FLAG);
992 break;
993 case CC_GT:
994 cris_evaluate_flags(dc);
995 {
996 TCGv n, z;
997
998 n = tcg_temp_new();
999 z = tcg_temp_new();
1000
1001 /* To avoid a shift we overlay everything on
1002 the V flag. */
1003 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1004 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1005 /* invert Z. */
1006 tcg_gen_xori_tl(z, z, 2);
1007
1008 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1009 tcg_gen_xori_tl(n, n, 2);
1010 tcg_gen_and_tl(cc, z, n);
1011 tcg_gen_andi_tl(cc, cc, 2);
1012
1013 tcg_temp_free(n);
1014 tcg_temp_free(z);
1015 }
1016 break;
1017 case CC_LE:
1018 cris_evaluate_flags(dc);
1019 {
1020 TCGv n, z;
1021
1022 n = tcg_temp_new();
1023 z = tcg_temp_new();
1024
1025 /* To avoid a shift we overlay everything on
1026 the V flag. */
1027 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1028 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1029
1030 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1031 tcg_gen_or_tl(cc, z, n);
1032 tcg_gen_andi_tl(cc, cc, 2);
1033
1034 tcg_temp_free(n);
1035 tcg_temp_free(z);
1036 }
1037 break;
1038 case CC_P:
1039 cris_evaluate_flags(dc);
1040 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1041 break;
1042 case CC_A:
1043 tcg_gen_movi_tl(cc, 1);
1044 break;
1045 default:
1046 BUG();
1047 break;
1048 };
1049 }
1050
1051 static void cris_store_direct_jmp(DisasContext *dc)
1052 {
1053 /* Store the direct jmp state into the cpu-state. */
1054 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1055 if (dc->jmp == JMP_DIRECT) {
1056 tcg_gen_movi_tl(env_btaken, 1);
1057 }
1058 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1059 dc->jmp = JMP_INDIRECT;
1060 }
1061 }
1062
1063 static void cris_prepare_cc_branch (DisasContext *dc,
1064 int offset, int cond)
1065 {
1066 /* This helps us re-schedule the micro-code to insns in delay-slots
1067 before the actual jump. */
1068 dc->delayed_branch = 2;
1069 dc->jmp = JMP_DIRECT_CC;
1070 dc->jmp_pc = dc->pc + offset;
1071
1072 gen_tst_cc(dc, env_btaken, cond);
1073 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1074 }
1075
1076
1077 /* jumps, when the dest is in a live reg for example. Direct should be set
1078 when the dest addr is constant to allow tb chaining. */
1079 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1080 {
1081 /* This helps us re-schedule the micro-code to insns in delay-slots
1082 before the actual jump. */
1083 dc->delayed_branch = 2;
1084 dc->jmp = type;
1085 if (type == JMP_INDIRECT) {
1086 tcg_gen_movi_tl(env_btaken, 1);
1087 }
1088 }
1089
1090 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1091 {
1092 int mem_index = cpu_mmu_index(&dc->cpu->env);
1093
1094 /* If we get a fault on a delayslot we must keep the jmp state in
1095 the cpu-state to be able to re-execute the jmp. */
1096 if (dc->delayed_branch == 1) {
1097 cris_store_direct_jmp(dc);
1098 }
1099
1100 tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ);
1101 }
1102
1103 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1104 unsigned int size, int sign)
1105 {
1106 int mem_index = cpu_mmu_index(&dc->cpu->env);
1107
1108 /* If we get a fault on a delayslot we must keep the jmp state in
1109 the cpu-state to be able to re-execute the jmp. */
1110 if (dc->delayed_branch == 1) {
1111 cris_store_direct_jmp(dc);
1112 }
1113
1114 tcg_gen_qemu_ld_tl(dst, addr, mem_index,
1115 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
1116 }
1117
1118 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1119 unsigned int size)
1120 {
1121 int mem_index = cpu_mmu_index(&dc->cpu->env);
1122
1123 /* If we get a fault on a delayslot we must keep the jmp state in
1124 the cpu-state to be able to re-execute the jmp. */
1125 if (dc->delayed_branch == 1) {
1126 cris_store_direct_jmp(dc);
1127 }
1128
1129
1130 /* Conditional writes. We only support the kind were X and P are known
1131 at translation time. */
1132 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1133 dc->postinc = 0;
1134 cris_evaluate_flags(dc);
1135 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1136 return;
1137 }
1138
1139 tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
1140
1141 if (dc->flagx_known && dc->flags_x) {
1142 cris_evaluate_flags(dc);
1143 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1144 }
1145 }
1146
1147 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1148 {
1149 if (size == 1) {
1150 tcg_gen_ext8s_i32(d, s);
1151 } else if (size == 2) {
1152 tcg_gen_ext16s_i32(d, s);
1153 } else if (!TCGV_EQUAL(d, s)) {
1154 tcg_gen_mov_tl(d, s);
1155 }
1156 }
1157
1158 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1159 {
1160 if (size == 1) {
1161 tcg_gen_ext8u_i32(d, s);
1162 } else if (size == 2) {
1163 tcg_gen_ext16u_i32(d, s);
1164 } else if (!TCGV_EQUAL(d, s)) {
1165 tcg_gen_mov_tl(d, s);
1166 }
1167 }
1168
1169 #if DISAS_CRIS
1170 static char memsize_char(int size)
1171 {
1172 switch (size) {
1173 case 1: return 'b'; break;
1174 case 2: return 'w'; break;
1175 case 4: return 'd'; break;
1176 default:
1177 return 'x';
1178 break;
1179 }
1180 }
1181 #endif
1182
1183 static inline unsigned int memsize_z(DisasContext *dc)
1184 {
1185 return dc->zsize + 1;
1186 }
1187
1188 static inline unsigned int memsize_zz(DisasContext *dc)
1189 {
1190 switch (dc->zzsize) {
1191 case 0: return 1;
1192 case 1: return 2;
1193 default:
1194 return 4;
1195 }
1196 }
1197
1198 static inline void do_postinc (DisasContext *dc, int size)
1199 {
1200 if (dc->postinc) {
1201 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1202 }
1203 }
1204
1205 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1206 int size, int s_ext, TCGv dst)
1207 {
1208 if (s_ext) {
1209 t_gen_sext(dst, cpu_R[rs], size);
1210 } else {
1211 t_gen_zext(dst, cpu_R[rs], size);
1212 }
1213 }
1214
1215 /* Prepare T0 and T1 for a register alu operation.
1216 s_ext decides if the operand1 should be sign-extended or zero-extended when
1217 needed. */
1218 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1219 int size, int s_ext, TCGv dst, TCGv src)
1220 {
1221 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1222
1223 if (s_ext) {
1224 t_gen_sext(dst, cpu_R[rd], size);
1225 } else {
1226 t_gen_zext(dst, cpu_R[rd], size);
1227 }
1228 }
1229
1230 static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
1231 int s_ext, int memsize, TCGv dst)
1232 {
1233 unsigned int rs;
1234 uint32_t imm;
1235 int is_imm;
1236 int insn_len = 2;
1237
1238 rs = dc->op1;
1239 is_imm = rs == 15 && dc->postinc;
1240
1241 /* Load [$rs] onto T1. */
1242 if (is_imm) {
1243 insn_len = 2 + memsize;
1244 if (memsize == 1) {
1245 insn_len++;
1246 }
1247
1248 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
1249 tcg_gen_movi_tl(dst, imm);
1250 dc->postinc = 0;
1251 } else {
1252 cris_flush_cc_state(dc);
1253 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1254 if (s_ext) {
1255 t_gen_sext(dst, dst, memsize);
1256 } else {
1257 t_gen_zext(dst, dst, memsize);
1258 }
1259 }
1260 return insn_len;
1261 }
1262
1263 /* Prepare T0 and T1 for a memory + alu operation.
1264 s_ext decides if the operand1 should be sign-extended or zero-extended when
1265 needed. */
1266 static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
1267 int s_ext, int memsize, TCGv dst, TCGv src)
1268 {
1269 int insn_len;
1270
1271 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
1272 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1273 return insn_len;
1274 }
1275
1276 #if DISAS_CRIS
1277 static const char *cc_name(int cc)
1278 {
1279 static const char *cc_names[16] = {
1280 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1281 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1282 };
1283 assert(cc < 16);
1284 return cc_names[cc];
1285 }
1286 #endif
1287
1288 /* Start of insn decoders. */
1289
1290 static int dec_bccq(CPUCRISState *env, DisasContext *dc)
1291 {
1292 int32_t offset;
1293 int sign;
1294 uint32_t cond = dc->op2;
1295
1296 offset = EXTRACT_FIELD(dc->ir, 1, 7);
1297 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1298
1299 offset *= 2;
1300 offset |= sign << 8;
1301 offset = sign_extend(offset, 8);
1302
1303 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1304
1305 /* op2 holds the condition-code. */
1306 cris_cc_mask(dc, 0);
1307 cris_prepare_cc_branch(dc, offset, cond);
1308 return 2;
1309 }
1310 static int dec_addoq(CPUCRISState *env, DisasContext *dc)
1311 {
1312 int32_t imm;
1313
1314 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1315 imm = sign_extend(dc->op1, 7);
1316
1317 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1318 cris_cc_mask(dc, 0);
1319 /* Fetch register operand, */
1320 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1321
1322 return 2;
1323 }
1324 static int dec_addq(CPUCRISState *env, DisasContext *dc)
1325 {
1326 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1327
1328 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1329
1330 cris_cc_mask(dc, CC_MASK_NZVC);
1331
1332 cris_alu(dc, CC_OP_ADD,
1333 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1334 return 2;
1335 }
1336 static int dec_moveq(CPUCRISState *env, DisasContext *dc)
1337 {
1338 uint32_t imm;
1339
1340 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1341 imm = sign_extend(dc->op1, 5);
1342 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1343
1344 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1345 return 2;
1346 }
1347 static int dec_subq(CPUCRISState *env, DisasContext *dc)
1348 {
1349 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1350
1351 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1352
1353 cris_cc_mask(dc, CC_MASK_NZVC);
1354 cris_alu(dc, CC_OP_SUB,
1355 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1356 return 2;
1357 }
1358 static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
1359 {
1360 uint32_t imm;
1361 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1362 imm = sign_extend(dc->op1, 5);
1363
1364 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1365 cris_cc_mask(dc, CC_MASK_NZVC);
1366
1367 cris_alu(dc, CC_OP_CMP,
1368 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1369 return 2;
1370 }
1371 static int dec_andq(CPUCRISState *env, DisasContext *dc)
1372 {
1373 uint32_t imm;
1374 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1375 imm = sign_extend(dc->op1, 5);
1376
1377 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1378 cris_cc_mask(dc, CC_MASK_NZ);
1379
1380 cris_alu(dc, CC_OP_AND,
1381 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1382 return 2;
1383 }
1384 static int dec_orq(CPUCRISState *env, DisasContext *dc)
1385 {
1386 uint32_t imm;
1387 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1388 imm = sign_extend(dc->op1, 5);
1389 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1390 cris_cc_mask(dc, CC_MASK_NZ);
1391
1392 cris_alu(dc, CC_OP_OR,
1393 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1394 return 2;
1395 }
1396 static int dec_btstq(CPUCRISState *env, DisasContext *dc)
1397 {
1398 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1399 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1400
1401 cris_cc_mask(dc, CC_MASK_NZ);
1402 cris_evaluate_flags(dc);
1403 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1404 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1405 cris_alu(dc, CC_OP_MOVE,
1406 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1407 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1408 dc->flags_uptodate = 1;
1409 return 2;
1410 }
1411 static int dec_asrq(CPUCRISState *env, DisasContext *dc)
1412 {
1413 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1414 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1415 cris_cc_mask(dc, CC_MASK_NZ);
1416
1417 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1418 cris_alu(dc, CC_OP_MOVE,
1419 cpu_R[dc->op2],
1420 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1421 return 2;
1422 }
1423 static int dec_lslq(CPUCRISState *env, DisasContext *dc)
1424 {
1425 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1426 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1427
1428 cris_cc_mask(dc, CC_MASK_NZ);
1429
1430 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1431
1432 cris_alu(dc, CC_OP_MOVE,
1433 cpu_R[dc->op2],
1434 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1435 return 2;
1436 }
1437 static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
1438 {
1439 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1440 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1441
1442 cris_cc_mask(dc, CC_MASK_NZ);
1443
1444 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1445 cris_alu(dc, CC_OP_MOVE,
1446 cpu_R[dc->op2],
1447 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1448 return 2;
1449 }
1450
1451 static int dec_move_r(CPUCRISState *env, DisasContext *dc)
1452 {
1453 int size = memsize_zz(dc);
1454
1455 LOG_DIS("move.%c $r%u, $r%u\n",
1456 memsize_char(size), dc->op1, dc->op2);
1457
1458 cris_cc_mask(dc, CC_MASK_NZ);
1459 if (size == 4) {
1460 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1461 cris_cc_mask(dc, CC_MASK_NZ);
1462 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1463 cris_update_cc_x(dc);
1464 cris_update_result(dc, cpu_R[dc->op2]);
1465 } else {
1466 TCGv t0;
1467
1468 t0 = tcg_temp_new();
1469 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1470 cris_alu(dc, CC_OP_MOVE,
1471 cpu_R[dc->op2],
1472 cpu_R[dc->op2], t0, size);
1473 tcg_temp_free(t0);
1474 }
1475 return 2;
1476 }
1477
1478 static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
1479 {
1480 int cond = dc->op2;
1481
1482 LOG_DIS("s%s $r%u\n",
1483 cc_name(cond), dc->op1);
1484
1485 if (cond != CC_A) {
1486 TCGLabel *l1 = gen_new_label();
1487 gen_tst_cc(dc, cpu_R[dc->op1], cond);
1488 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1489 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1490 gen_set_label(l1);
1491 } else {
1492 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1493 }
1494
1495 cris_cc_mask(dc, 0);
1496 return 2;
1497 }
1498
1499 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1500 {
1501 if (size == 4) {
1502 t[0] = cpu_R[dc->op2];
1503 t[1] = cpu_R[dc->op1];
1504 } else {
1505 t[0] = tcg_temp_new();
1506 t[1] = tcg_temp_new();
1507 }
1508 }
1509
1510 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1511 {
1512 if (size != 4) {
1513 tcg_temp_free(t[0]);
1514 tcg_temp_free(t[1]);
1515 }
1516 }
1517
1518 static int dec_and_r(CPUCRISState *env, DisasContext *dc)
1519 {
1520 TCGv t[2];
1521 int size = memsize_zz(dc);
1522
1523 LOG_DIS("and.%c $r%u, $r%u\n",
1524 memsize_char(size), dc->op1, dc->op2);
1525
1526 cris_cc_mask(dc, CC_MASK_NZ);
1527
1528 cris_alu_alloc_temps(dc, size, t);
1529 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1530 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1531 cris_alu_free_temps(dc, size, t);
1532 return 2;
1533 }
1534
1535 static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
1536 {
1537 TCGv t0;
1538 LOG_DIS("lz $r%u, $r%u\n",
1539 dc->op1, dc->op2);
1540 cris_cc_mask(dc, CC_MASK_NZ);
1541 t0 = tcg_temp_new();
1542 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1543 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1544 tcg_temp_free(t0);
1545 return 2;
1546 }
1547
1548 static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
1549 {
1550 TCGv t[2];
1551 int size = memsize_zz(dc);
1552
1553 LOG_DIS("lsl.%c $r%u, $r%u\n",
1554 memsize_char(size), dc->op1, dc->op2);
1555
1556 cris_cc_mask(dc, CC_MASK_NZ);
1557 cris_alu_alloc_temps(dc, size, t);
1558 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1559 tcg_gen_andi_tl(t[1], t[1], 63);
1560 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1561 cris_alu_alloc_temps(dc, size, t);
1562 return 2;
1563 }
1564
1565 static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
1566 {
1567 TCGv t[2];
1568 int size = memsize_zz(dc);
1569
1570 LOG_DIS("lsr.%c $r%u, $r%u\n",
1571 memsize_char(size), dc->op1, dc->op2);
1572
1573 cris_cc_mask(dc, CC_MASK_NZ);
1574 cris_alu_alloc_temps(dc, size, t);
1575 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1576 tcg_gen_andi_tl(t[1], t[1], 63);
1577 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1578 cris_alu_free_temps(dc, size, t);
1579 return 2;
1580 }
1581
1582 static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
1583 {
1584 TCGv t[2];
1585 int size = memsize_zz(dc);
1586
1587 LOG_DIS("asr.%c $r%u, $r%u\n",
1588 memsize_char(size), dc->op1, dc->op2);
1589
1590 cris_cc_mask(dc, CC_MASK_NZ);
1591 cris_alu_alloc_temps(dc, size, t);
1592 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1593 tcg_gen_andi_tl(t[1], t[1], 63);
1594 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1595 cris_alu_free_temps(dc, size, t);
1596 return 2;
1597 }
1598
1599 static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
1600 {
1601 TCGv t[2];
1602 int size = memsize_zz(dc);
1603
1604 LOG_DIS("muls.%c $r%u, $r%u\n",
1605 memsize_char(size), dc->op1, dc->op2);
1606 cris_cc_mask(dc, CC_MASK_NZV);
1607 cris_alu_alloc_temps(dc, size, t);
1608 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1609
1610 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1611 cris_alu_free_temps(dc, size, t);
1612 return 2;
1613 }
1614
1615 static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
1616 {
1617 TCGv t[2];
1618 int size = memsize_zz(dc);
1619
1620 LOG_DIS("mulu.%c $r%u, $r%u\n",
1621 memsize_char(size), dc->op1, dc->op2);
1622 cris_cc_mask(dc, CC_MASK_NZV);
1623 cris_alu_alloc_temps(dc, size, t);
1624 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1625
1626 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1627 cris_alu_alloc_temps(dc, size, t);
1628 return 2;
1629 }
1630
1631
1632 static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
1633 {
1634 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1635 cris_cc_mask(dc, CC_MASK_NZ);
1636 cris_alu(dc, CC_OP_DSTEP,
1637 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1638 return 2;
1639 }
1640
1641 static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
1642 {
1643 TCGv t[2];
1644 int size = memsize_zz(dc);
1645 LOG_DIS("xor.%c $r%u, $r%u\n",
1646 memsize_char(size), dc->op1, dc->op2);
1647 BUG_ON(size != 4); /* xor is dword. */
1648 cris_cc_mask(dc, CC_MASK_NZ);
1649 cris_alu_alloc_temps(dc, size, t);
1650 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1651
1652 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1653 cris_alu_free_temps(dc, size, t);
1654 return 2;
1655 }
1656
1657 static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
1658 {
1659 TCGv l0;
1660 int size = memsize_zz(dc);
1661 LOG_DIS("bound.%c $r%u, $r%u\n",
1662 memsize_char(size), dc->op1, dc->op2);
1663 cris_cc_mask(dc, CC_MASK_NZ);
1664 l0 = tcg_temp_local_new();
1665 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1666 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1667 tcg_temp_free(l0);
1668 return 2;
1669 }
1670
1671 static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
1672 {
1673 TCGv t[2];
1674 int size = memsize_zz(dc);
1675 LOG_DIS("cmp.%c $r%u, $r%u\n",
1676 memsize_char(size), dc->op1, dc->op2);
1677 cris_cc_mask(dc, CC_MASK_NZVC);
1678 cris_alu_alloc_temps(dc, size, t);
1679 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1680
1681 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1682 cris_alu_free_temps(dc, size, t);
1683 return 2;
1684 }
1685
1686 static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
1687 {
1688 TCGv t0;
1689
1690 LOG_DIS("abs $r%u, $r%u\n",
1691 dc->op1, dc->op2);
1692 cris_cc_mask(dc, CC_MASK_NZ);
1693
1694 t0 = tcg_temp_new();
1695 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1696 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1697 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1698 tcg_temp_free(t0);
1699
1700 cris_alu(dc, CC_OP_MOVE,
1701 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1702 return 2;
1703 }
1704
1705 static int dec_add_r(CPUCRISState *env, DisasContext *dc)
1706 {
1707 TCGv t[2];
1708 int size = memsize_zz(dc);
1709 LOG_DIS("add.%c $r%u, $r%u\n",
1710 memsize_char(size), dc->op1, dc->op2);
1711 cris_cc_mask(dc, CC_MASK_NZVC);
1712 cris_alu_alloc_temps(dc, size, t);
1713 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1714
1715 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1716 cris_alu_free_temps(dc, size, t);
1717 return 2;
1718 }
1719
1720 static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
1721 {
1722 LOG_DIS("addc $r%u, $r%u\n",
1723 dc->op1, dc->op2);
1724 cris_evaluate_flags(dc);
1725 /* Set for this insn. */
1726 dc->flagx_known = 1;
1727 dc->flags_x = X_FLAG;
1728
1729 cris_cc_mask(dc, CC_MASK_NZVC);
1730 cris_alu(dc, CC_OP_ADDC,
1731 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1732 return 2;
1733 }
1734
1735 static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
1736 {
1737 LOG_DIS("mcp $p%u, $r%u\n",
1738 dc->op2, dc->op1);
1739 cris_evaluate_flags(dc);
1740 cris_cc_mask(dc, CC_MASK_RNZV);
1741 cris_alu(dc, CC_OP_MCP,
1742 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1743 return 2;
1744 }
1745
1746 #if DISAS_CRIS
1747 static char * swapmode_name(int mode, char *modename) {
1748 int i = 0;
1749 if (mode & 8) {
1750 modename[i++] = 'n';
1751 }
1752 if (mode & 4) {
1753 modename[i++] = 'w';
1754 }
1755 if (mode & 2) {
1756 modename[i++] = 'b';
1757 }
1758 if (mode & 1) {
1759 modename[i++] = 'r';
1760 }
1761 modename[i++] = 0;
1762 return modename;
1763 }
1764 #endif
1765
1766 static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
1767 {
1768 TCGv t0;
1769 #if DISAS_CRIS
1770 char modename[4];
1771 #endif
1772 LOG_DIS("swap%s $r%u\n",
1773 swapmode_name(dc->op2, modename), dc->op1);
1774
1775 cris_cc_mask(dc, CC_MASK_NZ);
1776 t0 = tcg_temp_new();
1777 tcg_gen_mov_tl(t0, cpu_R[dc->op1]);
1778 if (dc->op2 & 8) {
1779 tcg_gen_not_tl(t0, t0);
1780 }
1781 if (dc->op2 & 4) {
1782 t_gen_swapw(t0, t0);
1783 }
1784 if (dc->op2 & 2) {
1785 t_gen_swapb(t0, t0);
1786 }
1787 if (dc->op2 & 1) {
1788 t_gen_swapr(t0, t0);
1789 }
1790 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1791 tcg_temp_free(t0);
1792 return 2;
1793 }
1794
1795 static int dec_or_r(CPUCRISState *env, DisasContext *dc)
1796 {
1797 TCGv t[2];
1798 int size = memsize_zz(dc);
1799 LOG_DIS("or.%c $r%u, $r%u\n",
1800 memsize_char(size), dc->op1, dc->op2);
1801 cris_cc_mask(dc, CC_MASK_NZ);
1802 cris_alu_alloc_temps(dc, size, t);
1803 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1804 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1805 cris_alu_free_temps(dc, size, t);
1806 return 2;
1807 }
1808
1809 static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
1810 {
1811 TCGv t0;
1812 LOG_DIS("addi.%c $r%u, $r%u\n",
1813 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1814 cris_cc_mask(dc, 0);
1815 t0 = tcg_temp_new();
1816 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1817 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1818 tcg_temp_free(t0);
1819 return 2;
1820 }
1821
1822 static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
1823 {
1824 TCGv t0;
1825 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1826 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1827 cris_cc_mask(dc, 0);
1828 t0 = tcg_temp_new();
1829 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1830 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1831 tcg_temp_free(t0);
1832 return 2;
1833 }
1834
1835 static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
1836 {
1837 TCGv t[2];
1838 int size = memsize_zz(dc);
1839 LOG_DIS("neg.%c $r%u, $r%u\n",
1840 memsize_char(size), dc->op1, dc->op2);
1841 cris_cc_mask(dc, CC_MASK_NZVC);
1842 cris_alu_alloc_temps(dc, size, t);
1843 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1844
1845 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1846 cris_alu_free_temps(dc, size, t);
1847 return 2;
1848 }
1849
1850 static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
1851 {
1852 LOG_DIS("btst $r%u, $r%u\n",
1853 dc->op1, dc->op2);
1854 cris_cc_mask(dc, CC_MASK_NZ);
1855 cris_evaluate_flags(dc);
1856 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1857 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1858 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1859 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1860 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1861 dc->flags_uptodate = 1;
1862 return 2;
1863 }
1864
1865 static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
1866 {
1867 TCGv t[2];
1868 int size = memsize_zz(dc);
1869 LOG_DIS("sub.%c $r%u, $r%u\n",
1870 memsize_char(size), dc->op1, dc->op2);
1871 cris_cc_mask(dc, CC_MASK_NZVC);
1872 cris_alu_alloc_temps(dc, size, t);
1873 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1874 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1875 cris_alu_free_temps(dc, size, t);
1876 return 2;
1877 }
1878
1879 /* Zero extension. From size to dword. */
1880 static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
1881 {
1882 TCGv t0;
1883 int size = memsize_z(dc);
1884 LOG_DIS("movu.%c $r%u, $r%u\n",
1885 memsize_char(size),
1886 dc->op1, dc->op2);
1887
1888 cris_cc_mask(dc, CC_MASK_NZ);
1889 t0 = tcg_temp_new();
1890 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1891 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1892 tcg_temp_free(t0);
1893 return 2;
1894 }
1895
1896 /* Sign extension. From size to dword. */
1897 static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
1898 {
1899 TCGv t0;
1900 int size = memsize_z(dc);
1901 LOG_DIS("movs.%c $r%u, $r%u\n",
1902 memsize_char(size),
1903 dc->op1, dc->op2);
1904
1905 cris_cc_mask(dc, CC_MASK_NZ);
1906 t0 = tcg_temp_new();
1907 /* Size can only be qi or hi. */
1908 t_gen_sext(t0, cpu_R[dc->op1], size);
1909 cris_alu(dc, CC_OP_MOVE,
1910 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1911 tcg_temp_free(t0);
1912 return 2;
1913 }
1914
1915 /* zero extension. From size to dword. */
1916 static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
1917 {
1918 TCGv t0;
1919 int size = memsize_z(dc);
1920 LOG_DIS("addu.%c $r%u, $r%u\n",
1921 memsize_char(size),
1922 dc->op1, dc->op2);
1923
1924 cris_cc_mask(dc, CC_MASK_NZVC);
1925 t0 = tcg_temp_new();
1926 /* Size can only be qi or hi. */
1927 t_gen_zext(t0, cpu_R[dc->op1], size);
1928 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1929 tcg_temp_free(t0);
1930 return 2;
1931 }
1932
1933 /* Sign extension. From size to dword. */
1934 static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
1935 {
1936 TCGv t0;
1937 int size = memsize_z(dc);
1938 LOG_DIS("adds.%c $r%u, $r%u\n",
1939 memsize_char(size),
1940 dc->op1, dc->op2);
1941
1942 cris_cc_mask(dc, CC_MASK_NZVC);
1943 t0 = tcg_temp_new();
1944 /* Size can only be qi or hi. */
1945 t_gen_sext(t0, cpu_R[dc->op1], size);
1946 cris_alu(dc, CC_OP_ADD,
1947 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1948 tcg_temp_free(t0);
1949 return 2;
1950 }
1951
1952 /* Zero extension. From size to dword. */
1953 static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
1954 {
1955 TCGv t0;
1956 int size = memsize_z(dc);
1957 LOG_DIS("subu.%c $r%u, $r%u\n",
1958 memsize_char(size),
1959 dc->op1, dc->op2);
1960
1961 cris_cc_mask(dc, CC_MASK_NZVC);
1962 t0 = tcg_temp_new();
1963 /* Size can only be qi or hi. */
1964 t_gen_zext(t0, cpu_R[dc->op1], size);
1965 cris_alu(dc, CC_OP_SUB,
1966 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1967 tcg_temp_free(t0);
1968 return 2;
1969 }
1970
1971 /* Sign extension. From size to dword. */
1972 static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
1973 {
1974 TCGv t0;
1975 int size = memsize_z(dc);
1976 LOG_DIS("subs.%c $r%u, $r%u\n",
1977 memsize_char(size),
1978 dc->op1, dc->op2);
1979
1980 cris_cc_mask(dc, CC_MASK_NZVC);
1981 t0 = tcg_temp_new();
1982 /* Size can only be qi or hi. */
1983 t_gen_sext(t0, cpu_R[dc->op1], size);
1984 cris_alu(dc, CC_OP_SUB,
1985 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1986 tcg_temp_free(t0);
1987 return 2;
1988 }
1989
1990 static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
1991 {
1992 uint32_t flags;
1993 int set = (~dc->opcode >> 2) & 1;
1994
1995
1996 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1997 | EXTRACT_FIELD(dc->ir, 0, 3);
1998 if (set && flags == 0) {
1999 LOG_DIS("nop\n");
2000 return 2;
2001 } else if (!set && (flags & 0x20)) {
2002 LOG_DIS("di\n");
2003 } else {
2004 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags);
2005 }
2006
2007 /* User space is not allowed to touch these. Silently ignore. */
2008 if (dc->tb_flags & U_FLAG) {
2009 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2010 }
2011
2012 if (flags & X_FLAG) {
2013 dc->flagx_known = 1;
2014 if (set) {
2015 dc->flags_x = X_FLAG;
2016 } else {
2017 dc->flags_x = 0;
2018 }
2019 }
2020
2021 /* Break the TB if any of the SPI flag changes. */
2022 if (flags & (P_FLAG | S_FLAG)) {
2023 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2024 dc->is_jmp = DISAS_UPDATE;
2025 dc->cpustate_changed = 1;
2026 }
2027
2028 /* For the I flag, only act on posedge. */
2029 if ((flags & I_FLAG)) {
2030 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2031 dc->is_jmp = DISAS_UPDATE;
2032 dc->cpustate_changed = 1;
2033 }
2034
2035
2036 /* Simply decode the flags. */
2037 cris_evaluate_flags(dc);
2038 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2039 cris_update_cc_x(dc);
2040 tcg_gen_movi_tl(cc_op, dc->cc_op);
2041
2042 if (set) {
2043 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2044 /* Enter user mode. */
2045 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2046 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2047 dc->cpustate_changed = 1;
2048 }
2049 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2050 } else {
2051 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2052 }
2053
2054 dc->flags_uptodate = 1;
2055 dc->clear_x = 0;
2056 return 2;
2057 }
2058
2059 static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
2060 {
2061 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2062 cris_cc_mask(dc, 0);
2063 gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
2064 tcg_const_tl(dc->op1));
2065 return 2;
2066 }
2067 static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
2068 {
2069 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2070 cris_cc_mask(dc, 0);
2071 gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
2072 tcg_const_tl(dc->op2));
2073 return 2;
2074 }
2075
2076 static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
2077 {
2078 TCGv t[2];
2079 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2080 cris_cc_mask(dc, 0);
2081
2082 t[0] = tcg_temp_new();
2083 if (dc->op2 == PR_CCS) {
2084 cris_evaluate_flags(dc);
2085 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2086 if (dc->tb_flags & U_FLAG) {
2087 t[1] = tcg_temp_new();
2088 /* User space is not allowed to touch all flags. */
2089 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2090 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2091 tcg_gen_or_tl(t[0], t[1], t[0]);
2092 tcg_temp_free(t[1]);
2093 }
2094 } else {
2095 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2096 }
2097
2098 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2099 if (dc->op2 == PR_CCS) {
2100 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2101 dc->flags_uptodate = 1;
2102 }
2103 tcg_temp_free(t[0]);
2104 return 2;
2105 }
2106 static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
2107 {
2108 TCGv t0;
2109 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2110 cris_cc_mask(dc, 0);
2111
2112 if (dc->op2 == PR_CCS) {
2113 cris_evaluate_flags(dc);
2114 }
2115
2116 if (dc->op2 == PR_DZ) {
2117 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2118 } else {
2119 t0 = tcg_temp_new();
2120 t_gen_mov_TN_preg(t0, dc->op2);
2121 cris_alu(dc, CC_OP_MOVE,
2122 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2123 preg_sizes[dc->op2]);
2124 tcg_temp_free(t0);
2125 }
2126 return 2;
2127 }
2128
2129 static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
2130 {
2131 int memsize = memsize_zz(dc);
2132 int insn_len;
2133 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2134 memsize_char(memsize),
2135 dc->op1, dc->postinc ? "+]" : "]",
2136 dc->op2);
2137
2138 if (memsize == 4) {
2139 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
2140 cris_cc_mask(dc, CC_MASK_NZ);
2141 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2142 cris_update_cc_x(dc);
2143 cris_update_result(dc, cpu_R[dc->op2]);
2144 } else {
2145 TCGv t0;
2146
2147 t0 = tcg_temp_new();
2148 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
2149 cris_cc_mask(dc, CC_MASK_NZ);
2150 cris_alu(dc, CC_OP_MOVE,
2151 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2152 tcg_temp_free(t0);
2153 }
2154 do_postinc(dc, memsize);
2155 return insn_len;
2156 }
2157
2158 static inline void cris_alu_m_alloc_temps(TCGv *t)
2159 {
2160 t[0] = tcg_temp_new();
2161 t[1] = tcg_temp_new();
2162 }
2163
2164 static inline void cris_alu_m_free_temps(TCGv *t)
2165 {
2166 tcg_temp_free(t[0]);
2167 tcg_temp_free(t[1]);
2168 }
2169
2170 static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
2171 {
2172 TCGv t[2];
2173 int memsize = memsize_z(dc);
2174 int insn_len;
2175 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2176 memsize_char(memsize),
2177 dc->op1, dc->postinc ? "+]" : "]",
2178 dc->op2);
2179
2180 cris_alu_m_alloc_temps(t);
2181 /* sign extend. */
2182 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2183 cris_cc_mask(dc, CC_MASK_NZ);
2184 cris_alu(dc, CC_OP_MOVE,
2185 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2186 do_postinc(dc, memsize);
2187 cris_alu_m_free_temps(t);
2188 return insn_len;
2189 }
2190
2191 static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
2192 {
2193 TCGv t[2];
2194 int memsize = memsize_z(dc);
2195 int insn_len;
2196 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2197 memsize_char(memsize),
2198 dc->op1, dc->postinc ? "+]" : "]",
2199 dc->op2);
2200
2201 cris_alu_m_alloc_temps(t);
2202 /* sign extend. */
2203 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2204 cris_cc_mask(dc, CC_MASK_NZVC);
2205 cris_alu(dc, CC_OP_ADD,
2206 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2207 do_postinc(dc, memsize);
2208 cris_alu_m_free_temps(t);
2209 return insn_len;
2210 }
2211
2212 static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
2213 {
2214 TCGv t[2];
2215 int memsize = memsize_z(dc);
2216 int insn_len;
2217 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2218 memsize_char(memsize),
2219 dc->op1, dc->postinc ? "+]" : "]",
2220 dc->op2);
2221
2222 cris_alu_m_alloc_temps(t);
2223 /* sign extend. */
2224 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2225 cris_cc_mask(dc, CC_MASK_NZVC);
2226 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2227 do_postinc(dc, memsize);
2228 cris_alu_m_free_temps(t);
2229 return insn_len;
2230 }
2231
2232 static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
2233 {
2234 TCGv t[2];
2235 int memsize = memsize_z(dc);
2236 int insn_len;
2237 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2238 memsize_char(memsize),
2239 dc->op1, dc->postinc ? "+]" : "]",
2240 dc->op2);
2241
2242 cris_alu_m_alloc_temps(t);
2243 /* sign extend. */
2244 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2245 cris_cc_mask(dc, CC_MASK_NZVC);
2246 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2247 do_postinc(dc, memsize);
2248 cris_alu_m_free_temps(t);
2249 return insn_len;
2250 }
2251
2252 static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
2253 {
2254 TCGv t[2];
2255 int memsize = memsize_z(dc);
2256 int insn_len;
2257 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2258 memsize_char(memsize),
2259 dc->op1, dc->postinc ? "+]" : "]",
2260 dc->op2);
2261
2262 cris_alu_m_alloc_temps(t);
2263 /* sign extend. */
2264 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2265 cris_cc_mask(dc, CC_MASK_NZVC);
2266 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2267 do_postinc(dc, memsize);
2268 cris_alu_m_free_temps(t);
2269 return insn_len;
2270 }
2271
2272 static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
2273 {
2274 TCGv t[2];
2275 int memsize = memsize_z(dc);
2276 int insn_len;
2277
2278 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2279 memsize_char(memsize),
2280 dc->op1, dc->postinc ? "+]" : "]",
2281 dc->op2);
2282
2283 cris_alu_m_alloc_temps(t);
2284 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2285 cris_cc_mask(dc, CC_MASK_NZ);
2286 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2287 do_postinc(dc, memsize);
2288 cris_alu_m_free_temps(t);
2289 return insn_len;
2290 }
2291
2292 static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
2293 {
2294 TCGv t[2];
2295 int memsize = memsize_z(dc);
2296 int insn_len;
2297 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2298 memsize_char(memsize),
2299 dc->op1, dc->postinc ? "+]" : "]",
2300 dc->op2);
2301
2302 cris_alu_m_alloc_temps(t);
2303 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2304 cris_cc_mask(dc, CC_MASK_NZVC);
2305 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2306 do_postinc(dc, memsize);
2307 cris_alu_m_free_temps(t);
2308 return insn_len;
2309 }
2310
2311 static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
2312 {
2313 TCGv t[2];
2314 int memsize = memsize_z(dc);
2315 int insn_len;
2316 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2317 memsize_char(memsize),
2318 dc->op1, dc->postinc ? "+]" : "]",
2319 dc->op2);
2320
2321 cris_alu_m_alloc_temps(t);
2322 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2323 cris_cc_mask(dc, CC_MASK_NZVC);
2324 cris_alu(dc, CC_OP_CMP,
2325 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2326 memsize_zz(dc));
2327 do_postinc(dc, memsize);
2328 cris_alu_m_free_temps(t);
2329 return insn_len;
2330 }
2331
2332 static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
2333 {
2334 TCGv t[2];
2335 int memsize = memsize_zz(dc);
2336 int insn_len;
2337 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2338 memsize_char(memsize),
2339 dc->op1, dc->postinc ? "+]" : "]",
2340 dc->op2);
2341
2342 cris_alu_m_alloc_temps(t);
2343 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2344 cris_cc_mask(dc, CC_MASK_NZVC);
2345 cris_alu(dc, CC_OP_CMP,
2346 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2347 memsize_zz(dc));
2348 do_postinc(dc, memsize);
2349 cris_alu_m_free_temps(t);
2350 return insn_len;
2351 }
2352
2353 static int dec_test_m(CPUCRISState *env, DisasContext *dc)
2354 {
2355 TCGv t[2];
2356 int memsize = memsize_zz(dc);
2357 int insn_len;
2358 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2359 memsize_char(memsize),
2360 dc->op1, dc->postinc ? "+]" : "]",
2361 dc->op2);
2362
2363 cris_evaluate_flags(dc);
2364
2365 cris_alu_m_alloc_temps(t);
2366 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2367 cris_cc_mask(dc, CC_MASK_NZ);
2368 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2369
2370 cris_alu(dc, CC_OP_CMP,
2371 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2372 do_postinc(dc, memsize);
2373 cris_alu_m_free_temps(t);
2374 return insn_len;
2375 }
2376
2377 static int dec_and_m(CPUCRISState *env, DisasContext *dc)
2378 {
2379 TCGv t[2];
2380 int memsize = memsize_zz(dc);
2381 int insn_len;
2382 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2383 memsize_char(memsize),
2384 dc->op1, dc->postinc ? "+]" : "]",
2385 dc->op2);
2386
2387 cris_alu_m_alloc_temps(t);
2388 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2389 cris_cc_mask(dc, CC_MASK_NZ);
2390 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2391 do_postinc(dc, memsize);
2392 cris_alu_m_free_temps(t);
2393 return insn_len;
2394 }
2395
2396 static int dec_add_m(CPUCRISState *env, DisasContext *dc)
2397 {
2398 TCGv t[2];
2399 int memsize = memsize_zz(dc);
2400 int insn_len;
2401 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2402 memsize_char(memsize),
2403 dc->op1, dc->postinc ? "+]" : "]",
2404 dc->op2);
2405
2406 cris_alu_m_alloc_temps(t);
2407 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2408 cris_cc_mask(dc, CC_MASK_NZVC);
2409 cris_alu(dc, CC_OP_ADD,
2410 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2411 do_postinc(dc, memsize);
2412 cris_alu_m_free_temps(t);
2413 return insn_len;
2414 }
2415
2416 static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
2417 {
2418 TCGv t[2];
2419 int memsize = memsize_zz(dc);
2420 int insn_len;
2421 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2422 memsize_char(memsize),
2423 dc->op1, dc->postinc ? "+]" : "]",
2424 dc->op2);
2425
2426 cris_alu_m_alloc_temps(t);
2427 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2428 cris_cc_mask(dc, 0);
2429 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2430 do_postinc(dc, memsize);
2431 cris_alu_m_free_temps(t);
2432 return insn_len;
2433 }
2434
2435 static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
2436 {
2437 TCGv l[2];
2438 int memsize = memsize_zz(dc);
2439 int insn_len;
2440 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2441 memsize_char(memsize),
2442 dc->op1, dc->postinc ? "+]" : "]",
2443 dc->op2);
2444
2445 l[0] = tcg_temp_local_new();
2446 l[1] = tcg_temp_local_new();
2447 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
2448 cris_cc_mask(dc, CC_MASK_NZ);
2449 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2450 do_postinc(dc, memsize);
2451 tcg_temp_free(l[0]);
2452 tcg_temp_free(l[1]);
2453 return insn_len;
2454 }
2455
2456 static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
2457 {
2458 TCGv t[2];
2459 int insn_len = 2;
2460 LOG_DIS("addc [$r%u%s, $r%u\n",
2461 dc->op1, dc->postinc ? "+]" : "]",
2462 dc->op2);
2463
2464 cris_evaluate_flags(dc);
2465
2466 /* Set for this insn. */
2467 dc->flagx_known = 1;
2468 dc->flags_x = X_FLAG;
2469
2470 cris_alu_m_alloc_temps(t);
2471 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
2472 cris_cc_mask(dc, CC_MASK_NZVC);
2473 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2474 do_postinc(dc, 4);
2475 cris_alu_m_free_temps(t);
2476 return insn_len;
2477 }
2478
2479 static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
2480 {
2481 TCGv t[2];
2482 int memsize = memsize_zz(dc);
2483 int insn_len;
2484 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2485 memsize_char(memsize),
2486 dc->op1, dc->postinc ? "+]" : "]",
2487 dc->op2, dc->ir, dc->zzsize);
2488
2489 cris_alu_m_alloc_temps(t);
2490 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2491 cris_cc_mask(dc, CC_MASK_NZVC);
2492 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2493 do_postinc(dc, memsize);
2494 cris_alu_m_free_temps(t);
2495 return insn_len;
2496 }
2497
2498 static int dec_or_m(CPUCRISState *env, DisasContext *dc)
2499 {
2500 TCGv t[2];
2501 int memsize = memsize_zz(dc);
2502 int insn_len;
2503 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2504 memsize_char(memsize),
2505 dc->op1, dc->postinc ? "+]" : "]",
2506 dc->op2, dc->pc);
2507
2508 cris_alu_m_alloc_temps(t);
2509 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2510 cris_cc_mask(dc, CC_MASK_NZ);
2511 cris_alu(dc, CC_OP_OR,
2512 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2513 do_postinc(dc, memsize);
2514 cris_alu_m_free_temps(t);
2515 return insn_len;
2516 }
2517
2518 static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
2519 {
2520 TCGv t[2];
2521 int memsize = memsize_zz(dc);
2522 int insn_len = 2;
2523
2524 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2525 memsize_char(memsize),
2526 dc->op1,
2527 dc->postinc ? "+]" : "]",
2528 dc->op2);
2529
2530 cris_alu_m_alloc_temps(t);
2531 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2532 cris_cc_mask(dc, 0);
2533 if (dc->op2 == PR_CCS) {
2534 cris_evaluate_flags(dc);
2535 if (dc->tb_flags & U_FLAG) {
2536 /* User space is not allowed to touch all flags. */
2537 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2538 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2539 tcg_gen_or_tl(t[1], t[0], t[1]);
2540 }
2541 }
2542
2543 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2544
2545 do_postinc(dc, memsize);
2546 cris_alu_m_free_temps(t);
2547 return insn_len;
2548 }
2549
2550 static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
2551 {
2552 TCGv t0;
2553 int memsize;
2554
2555 memsize = preg_sizes[dc->op2];
2556
2557 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2558 memsize_char(memsize),
2559 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2560
2561 /* prepare store. Address in T0, value in T1. */
2562 if (dc->op2 == PR_CCS) {
2563 cris_evaluate_flags(dc);
2564 }
2565 t0 = tcg_temp_new();
2566 t_gen_mov_TN_preg(t0, dc->op2);
2567 cris_flush_cc_state(dc);
2568 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2569 tcg_temp_free(t0);
2570
2571 cris_cc_mask(dc, 0);
2572 if (dc->postinc) {
2573 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2574 }
2575 return 2;
2576 }
2577
2578 static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
2579 {
2580 TCGv_i64 tmp[16];
2581 TCGv tmp32;
2582 TCGv addr;
2583 int i;
2584 int nr = dc->op2 + 1;
2585
2586 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2587 dc->postinc ? "+]" : "]", dc->op2);
2588
2589 addr = tcg_temp_new();
2590 /* There are probably better ways of doing this. */
2591 cris_flush_cc_state(dc);
2592 for (i = 0; i < (nr >> 1); i++) {
2593 tmp[i] = tcg_temp_new_i64();
2594 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2595 gen_load64(dc, tmp[i], addr);
2596 }
2597 if (nr & 1) {
2598 tmp32 = tcg_temp_new_i32();
2599 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2600 gen_load(dc, tmp32, addr, 4, 0);
2601 } else {
2602 TCGV_UNUSED(tmp32);
2603 }
2604 tcg_temp_free(addr);
2605
2606 for (i = 0; i < (nr >> 1); i++) {
2607 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2608 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2609 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2610 tcg_temp_free_i64(tmp[i]);
2611 }
2612 if (nr & 1) {
2613 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2614 tcg_temp_free(tmp32);
2615 }
2616
2617 /* writeback the updated pointer value. */
2618 if (dc->postinc) {
2619 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2620 }
2621
2622 /* gen_load might want to evaluate the previous insns flags. */
2623 cris_cc_mask(dc, 0);
2624 return 2;
2625 }
2626
2627 static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
2628 {
2629 TCGv tmp;
2630 TCGv addr;
2631 int i;
2632
2633 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2634 dc->postinc ? "+]" : "]");
2635
2636 cris_flush_cc_state(dc);
2637
2638 tmp = tcg_temp_new();
2639 addr = tcg_temp_new();
2640 tcg_gen_movi_tl(tmp, 4);
2641 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2642 for (i = 0; i <= dc->op2; i++) {
2643 /* Displace addr. */
2644 /* Perform the store. */
2645 gen_store(dc, addr, cpu_R[i], 4);
2646 tcg_gen_add_tl(addr, addr, tmp);
2647 }
2648 if (dc->postinc) {
2649 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2650 }
2651 cris_cc_mask(dc, 0);
2652 tcg_temp_free(tmp);
2653 tcg_temp_free(addr);
2654 return 2;
2655 }
2656
2657 static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
2658 {
2659 int memsize;
2660
2661 memsize = memsize_zz(dc);
2662
2663 LOG_DIS("move.%c $r%u, [$r%u]\n",
2664 memsize_char(memsize), dc->op2, dc->op1);
2665
2666 /* prepare store. */
2667 cris_flush_cc_state(dc);
2668 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2669
2670 if (dc->postinc) {
2671 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2672 }
2673 cris_cc_mask(dc, 0);
2674 return 2;
2675 }
2676
2677 static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
2678 {
2679 LOG_DIS("lapcq %x, $r%u\n",
2680 dc->pc + dc->op1*2, dc->op2);
2681 cris_cc_mask(dc, 0);
2682 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2683 return 2;
2684 }
2685
2686 static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
2687 {
2688 unsigned int rd;
2689 int32_t imm;
2690 int32_t pc;
2691
2692 rd = dc->op2;
2693
2694 cris_cc_mask(dc, 0);
2695 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2696 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2697
2698 pc = dc->pc;
2699 pc += imm;
2700 tcg_gen_movi_tl(cpu_R[rd], pc);
2701 return 6;
2702 }
2703
2704 /* Jump to special reg. */
2705 static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
2706 {
2707 LOG_DIS("jump $p%u\n", dc->op2);
2708
2709 if (dc->op2 == PR_CCS) {
2710 cris_evaluate_flags(dc);
2711 }
2712 t_gen_mov_TN_preg(env_btarget, dc->op2);
2713 /* rete will often have low bit set to indicate delayslot. */
2714 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2715 cris_cc_mask(dc, 0);
2716 cris_prepare_jmp(dc, JMP_INDIRECT);
2717 return 2;
2718 }
2719
2720 /* Jump and save. */
2721 static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
2722 {
2723 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2724 cris_cc_mask(dc, 0);
2725 /* Store the return address in Pd. */
2726 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2727 if (dc->op2 > 15) {
2728 abort();
2729 }
2730 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2731
2732 cris_prepare_jmp(dc, JMP_INDIRECT);
2733 return 2;
2734 }
2735
2736 static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
2737 {
2738 uint32_t imm;
2739
2740 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2741
2742 LOG_DIS("jas 0x%x\n", imm);
2743 cris_cc_mask(dc, 0);
2744 /* Store the return address in Pd. */
2745 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2746
2747 dc->jmp_pc = imm;
2748 cris_prepare_jmp(dc, JMP_DIRECT);
2749 return 6;
2750 }
2751
2752 static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
2753 {
2754 uint32_t imm;
2755
2756 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2757
2758 LOG_DIS("jasc 0x%x\n", imm);
2759 cris_cc_mask(dc, 0);
2760 /* Store the return address in Pd. */
2761 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2762
2763 dc->jmp_pc = imm;
2764 cris_prepare_jmp(dc, JMP_DIRECT);
2765 return 6;
2766 }
2767
2768 static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
2769 {
2770 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2771 cris_cc_mask(dc, 0);
2772 /* Store the return address in Pd. */
2773 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2774 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2775 cris_prepare_jmp(dc, JMP_INDIRECT);
2776 return 2;
2777 }
2778
2779 static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
2780 {
2781 int32_t offset;
2782 uint32_t cond = dc->op2;
2783
2784 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
2785
2786 LOG_DIS("b%s %d pc=%x dst=%x\n",
2787 cc_name(cond), offset,
2788 dc->pc, dc->pc + offset);
2789
2790 cris_cc_mask(dc, 0);
2791 /* op2 holds the condition-code. */
2792 cris_prepare_cc_branch(dc, offset, cond);
2793 return 4;
2794 }
2795
2796 static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
2797 {
2798 int32_t simm;
2799
2800 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2801
2802 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2803 cris_cc_mask(dc, 0);
2804 /* Store the return address in Pd. */
2805 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2806
2807 dc->jmp_pc = dc->pc + simm;
2808 cris_prepare_jmp(dc, JMP_DIRECT);
2809 return 6;
2810 }
2811
2812 static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
2813 {
2814 int32_t simm;
2815 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2816
2817 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2818 cris_cc_mask(dc, 0);
2819 /* Store the return address in Pd. */
2820 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2821
2822 dc->jmp_pc = dc->pc + simm;
2823 cris_prepare_jmp(dc, JMP_DIRECT);
2824 return 6;
2825 }
2826
2827 static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
2828 {
2829 cris_cc_mask(dc, 0);
2830
2831 if (dc->op2 == 15) {
2832 tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
2833 -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
2834 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2835 t_gen_raise_exception(EXCP_HLT);
2836 return 2;
2837 }
2838
2839 switch (dc->op2 & 7) {
2840 case 2:
2841 /* rfe. */
2842 LOG_DIS("rfe\n");
2843 cris_evaluate_flags(dc);
2844 gen_helper_rfe(cpu_env);
2845 dc->is_jmp = DISAS_UPDATE;
2846 break;
2847 case 5:
2848 /* rfn. */
2849 LOG_DIS("rfn\n");
2850 cris_evaluate_flags(dc);
2851 gen_helper_rfn(cpu_env);
2852 dc->is_jmp = DISAS_UPDATE;
2853 break;
2854 case 6:
2855 LOG_DIS("break %d\n", dc->op1);
2856 cris_evaluate_flags(dc);
2857 /* break. */
2858 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2859
2860 /* Breaks start at 16 in the exception vector. */
2861 t_gen_mov_env_TN(trap_vector,
2862 tcg_const_tl(dc->op1 + 16));
2863 t_gen_raise_exception(EXCP_BREAK);
2864 dc->is_jmp = DISAS_UPDATE;
2865 break;
2866 default:
2867 printf("op2=%x\n", dc->op2);
2868 BUG();
2869 break;
2870
2871 }
2872 return 2;
2873 }
2874
2875 static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
2876 {
2877 return 2;
2878 }
2879
2880 static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
2881 {
2882 return 2;
2883 }
2884
2885 static int dec_null(CPUCRISState *env, DisasContext *dc)
2886 {
2887 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2888 dc->pc, dc->opcode, dc->op1, dc->op2);
2889 fflush(NULL);
2890 BUG();
2891 return 2;
2892 }
2893
2894 static struct decoder_info {
2895 struct {
2896 uint32_t bits;
2897 uint32_t mask;
2898 };
2899 int (*dec)(CPUCRISState *env, DisasContext *dc);
2900 } decinfo[] = {
2901 /* Order matters here. */
2902 {DEC_MOVEQ, dec_moveq},
2903 {DEC_BTSTQ, dec_btstq},
2904 {DEC_CMPQ, dec_cmpq},
2905 {DEC_ADDOQ, dec_addoq},
2906 {DEC_ADDQ, dec_addq},
2907 {DEC_SUBQ, dec_subq},
2908 {DEC_ANDQ, dec_andq},
2909 {DEC_ORQ, dec_orq},
2910 {DEC_ASRQ, dec_asrq},
2911 {DEC_LSLQ, dec_lslq},
2912 {DEC_LSRQ, dec_lsrq},
2913 {DEC_BCCQ, dec_bccq},
2914
2915 {DEC_BCC_IM, dec_bcc_im},
2916 {DEC_JAS_IM, dec_jas_im},
2917 {DEC_JAS_R, dec_jas_r},
2918 {DEC_JASC_IM, dec_jasc_im},
2919 {DEC_JASC_R, dec_jasc_r},
2920 {DEC_BAS_IM, dec_bas_im},
2921 {DEC_BASC_IM, dec_basc_im},
2922 {DEC_JUMP_P, dec_jump_p},
2923 {DEC_LAPC_IM, dec_lapc_im},
2924 {DEC_LAPCQ, dec_lapcq},
2925
2926 {DEC_RFE_ETC, dec_rfe_etc},
2927 {DEC_ADDC_MR, dec_addc_mr},
2928
2929 {DEC_MOVE_MP, dec_move_mp},
2930 {DEC_MOVE_PM, dec_move_pm},
2931 {DEC_MOVEM_MR, dec_movem_mr},
2932 {DEC_MOVEM_RM, dec_movem_rm},
2933 {DEC_MOVE_PR, dec_move_pr},
2934 {DEC_SCC_R, dec_scc_r},
2935 {DEC_SETF, dec_setclrf},
2936 {DEC_CLEARF, dec_setclrf},
2937
2938 {DEC_MOVE_SR, dec_move_sr},
2939 {DEC_MOVE_RP, dec_move_rp},
2940 {DEC_SWAP_R, dec_swap_r},
2941 {DEC_ABS_R, dec_abs_r},
2942 {DEC_LZ_R, dec_lz_r},
2943 {DEC_MOVE_RS, dec_move_rs},
2944 {DEC_BTST_R, dec_btst_r},
2945 {DEC_ADDC_R, dec_addc_r},
2946
2947 {DEC_DSTEP_R, dec_dstep_r},
2948 {DEC_XOR_R, dec_xor_r},
2949 {DEC_MCP_R, dec_mcp_r},
2950 {DEC_CMP_R, dec_cmp_r},
2951
2952 {DEC_ADDI_R, dec_addi_r},
2953 {DEC_ADDI_ACR, dec_addi_acr},
2954
2955 {DEC_ADD_R, dec_add_r},
2956 {DEC_SUB_R, dec_sub_r},
2957
2958 {DEC_ADDU_R, dec_addu_r},
2959 {DEC_ADDS_R, dec_adds_r},
2960 {DEC_SUBU_R, dec_subu_r},
2961 {DEC_SUBS_R, dec_subs_r},
2962 {DEC_LSL_R, dec_lsl_r},
2963
2964 {DEC_AND_R, dec_and_r},
2965 {DEC_OR_R, dec_or_r},
2966 {DEC_BOUND_R, dec_bound_r},
2967 {DEC_ASR_R, dec_asr_r},
2968 {DEC_LSR_R, dec_lsr_r},
2969
2970 {DEC_MOVU_R, dec_movu_r},
2971 {DEC_MOVS_R, dec_movs_r},
2972 {DEC_NEG_R, dec_neg_r},
2973 {DEC_MOVE_R, dec_move_r},
2974
2975 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2976 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2977
2978 {DEC_MULS_R, dec_muls_r},
2979 {DEC_MULU_R, dec_mulu_r},
2980
2981 {DEC_ADDU_M, dec_addu_m},
2982 {DEC_ADDS_M, dec_adds_m},
2983 {DEC_SUBU_M, dec_subu_m},
2984 {DEC_SUBS_M, dec_subs_m},
2985
2986 {DEC_CMPU_M, dec_cmpu_m},
2987 {DEC_CMPS_M, dec_cmps_m},
2988 {DEC_MOVU_M, dec_movu_m},
2989 {DEC_MOVS_M, dec_movs_m},
2990
2991 {DEC_CMP_M, dec_cmp_m},
2992 {DEC_ADDO_M, dec_addo_m},
2993 {DEC_BOUND_M, dec_bound_m},
2994 {DEC_ADD_M, dec_add_m},
2995 {DEC_SUB_M, dec_sub_m},
2996 {DEC_AND_M, dec_and_m},
2997 {DEC_OR_M, dec_or_m},
2998 {DEC_MOVE_RM, dec_move_rm},
2999 {DEC_TEST_M, dec_test_m},
3000 {DEC_MOVE_MR, dec_move_mr},
3001
3002 {{0, 0}, dec_null}
3003 };
3004
3005 static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
3006 {
3007 int insn_len = 2;
3008 int i;
3009
3010 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
3011 tcg_gen_debug_insn_start(dc->pc);
3012 }
3013
3014 /* Load a halfword onto the instruction register. */
3015 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
3016
3017 /* Now decode it. */
3018 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3019 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3020 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3021 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3022 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3023 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3024
3025 /* Large switch for all insns. */
3026 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3027 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
3028 insn_len = decinfo[i].dec(env, dc);
3029 break;
3030 }
3031 }
3032
3033 #if !defined(CONFIG_USER_ONLY)
3034 /* Single-stepping ? */
3035 if (dc->tb_flags & S_FLAG) {
3036 TCGLabel *l1 = gen_new_label();
3037 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3038 /* We treat SPC as a break with an odd trap vector. */
3039 cris_evaluate_flags(dc);
3040 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3041 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3042 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3043 t_gen_raise_exception(EXCP_BREAK);
3044 gen_set_label(l1);
3045 }
3046 #endif
3047 return insn_len;
3048 }
3049
3050 static void check_breakpoint(CPUCRISState *env, DisasContext *dc)
3051 {
3052 CPUState *cs = CPU(cris_env_get_cpu(env));
3053 CPUBreakpoint *bp;
3054
3055 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
3056 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
3057 if (bp->pc == dc->pc) {
3058 cris_evaluate_flags(dc);
3059 tcg_gen_movi_tl(env_pc, dc->pc);
3060 t_gen_raise_exception(EXCP_DEBUG);
3061 dc->is_jmp = DISAS_UPDATE;
3062 }
3063 }
3064 }
3065 }
3066
3067 #include "translate_v10.c"
3068
3069 /*
3070 * Delay slots on QEMU/CRIS.
3071 *
3072 * If an exception hits on a delayslot, the core will let ERP (the Exception
3073 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3074 * to give SW a hint that the exception actually hit on the dslot.
3075 *
3076 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3077 * the core and any jmp to an odd addresses will mask off that lsb. It is
3078 * simply there to let sw know there was an exception on a dslot.
3079 *
3080 * When the software returns from an exception, the branch will re-execute.
3081 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3082 * and the branch and delayslot dont share pages.
3083 *
3084 * The TB contaning the branch insn will set up env->btarget and evaluate
3085 * env->btaken. When the translation loop exits we will note that the branch
3086 * sequence is broken and let env->dslot be the size of the branch insn (those
3087 * vary in length).
3088 *
3089 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3090 * set). It will also expect to have env->dslot setup with the size of the
3091 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3092 * will execute the dslot and take the branch, either to btarget or just one
3093 * insn ahead.
3094 *
3095 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3096 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3097 * branch and set lsb). Then env->dslot gets cleared so that the exception
3098 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3099 * masked off and we will reexecute the branch insn.
3100 *
3101 */
3102
3103 /* generate intermediate code for basic block 'tb'. */
3104 static inline void
3105 gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
3106 bool search_pc)
3107 {
3108 CPUState *cs = CPU(cpu);
3109 CPUCRISState *env = &cpu->env;
3110 uint32_t pc_start;
3111 unsigned int insn_len;
3112 int j, lj;
3113 struct DisasContext ctx;
3114 struct DisasContext *dc = &ctx;
3115 uint32_t next_page_start;
3116 target_ulong npc;
3117 int num_insns;
3118 int max_insns;
3119
3120 if (env->pregs[PR_VR] == 32) {
3121 dc->decoder = crisv32_decoder;
3122 dc->clear_locked_irq = 0;
3123 } else {
3124 dc->decoder = crisv10_decoder;
3125 dc->clear_locked_irq = 1;
3126 }
3127
3128 /* Odd PC indicates that branch is rexecuting due to exception in the
3129 * delayslot, like in real hw.
3130 */
3131 pc_start = tb->pc & ~1;
3132 dc->cpu = cpu;
3133 dc->tb = tb;
3134
3135 dc->is_jmp = DISAS_NEXT;
3136 dc->ppc = pc_start;
3137 dc->pc = pc_start;
3138 dc->singlestep_enabled = cs->singlestep_enabled;
3139 dc->flags_uptodate = 1;
3140 dc->flagx_known = 1;
3141 dc->flags_x = tb->flags & X_FLAG;
3142 dc->cc_x_uptodate = 0;
3143 dc->cc_mask = 0;
3144 dc->update_cc = 0;
3145 dc->clear_prefix = 0;
3146
3147 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3148 dc->cc_size_uptodate = -1;
3149
3150 /* Decode TB flags. */
3151 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3152 | X_FLAG | PFIX_FLAG);
3153 dc->delayed_branch = !!(tb->flags & 7);
3154 if (dc->delayed_branch) {
3155 dc->jmp = JMP_INDIRECT;
3156 } else {
3157 dc->jmp = JMP_NOJMP;
3158 }
3159
3160 dc->cpustate_changed = 0;
3161
3162 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3163 qemu_log(
3164 "srch=%d pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
3165 "pid=%x usp=%x\n"
3166 "%x.%x.%x.%x\n"
3167 "%x.%x.%x.%x\n"
3168 "%x.%x.%x.%x\n"
3169 "%x.%x.%x.%x\n",
3170 search_pc, dc->pc, dc->ppc,
3171 (uint64_t)tb->flags,
3172 env->btarget, (unsigned)tb->flags & 7,
3173 env->pregs[PR_CCS],
3174 env->pregs[PR_PID], env->pregs[PR_USP],
3175 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3176 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3177 env->regs[8], env->regs[9],
3178 env->regs[10], env->regs[11],
3179 env->regs[12], env->regs[13],
3180 env->regs[14], env->regs[15]);
3181 qemu_log("--------------\n");
3182 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3183 }
3184
3185 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3186 lj = -1;
3187 num_insns = 0;
3188 max_insns = tb->cflags & CF_COUNT_MASK;
3189 if (max_insns == 0) {
3190 max_insns = CF_COUNT_MASK;
3191 }
3192
3193 gen_tb_start(tb);
3194 do {
3195 check_breakpoint(env, dc);
3196
3197 if (search_pc) {
3198 j = tcg_op_buf_count();
3199 if (lj < j) {
3200 lj++;
3201 while (lj < j) {
3202 tcg_ctx.gen_opc_instr_start[lj++] = 0;
3203 }
3204 }
3205 if (dc->delayed_branch == 1) {
3206 tcg_ctx.gen_opc_pc[lj] = dc->ppc | 1;
3207 } else {
3208 tcg_ctx.gen_opc_pc[lj] = dc->pc;
3209 }
3210 tcg_ctx.gen_opc_instr_start[lj] = 1;
3211 tcg_ctx.gen_opc_icount[lj] = num_insns;
3212 }
3213
3214 /* Pretty disas. */
3215 LOG_DIS("%8.8x:\t", dc->pc);
3216
3217 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
3218 gen_io_start();
3219 }
3220 dc->clear_x = 1;
3221
3222 insn_len = dc->decoder(env, dc);
3223 dc->ppc = dc->pc;
3224 dc->pc += insn_len;
3225 if (dc->clear_x) {
3226 cris_clear_x_flag(dc);
3227 }
3228
3229 num_insns++;
3230 /* Check for delayed branches here. If we do it before
3231 actually generating any host code, the simulator will just
3232 loop doing nothing for on this program location. */
3233 if (dc->delayed_branch) {
3234 dc->delayed_branch--;
3235 if (dc->delayed_branch == 0) {
3236 if (tb->flags & 7) {
3237 t_gen_mov_env_TN(dslot, tcg_const_tl(0));
3238 }
3239 if (dc->cpustate_changed || !dc->flagx_known
3240 || (dc->flags_x != (tb->flags & X_FLAG))) {
3241 cris_store_direct_jmp(dc);
3242 }
3243
3244 if (dc->clear_locked_irq) {
3245 dc->clear_locked_irq = 0;
3246 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3247 }
3248
3249 if (dc->jmp == JMP_DIRECT_CC) {
3250 TCGLabel *l1 = gen_new_label();
3251 cris_evaluate_flags(dc);
3252
3253 /* Conditional jmp. */
3254 tcg_gen_brcondi_tl(TCG_COND_EQ,
3255 env_btaken, 0, l1);
3256 gen_goto_tb(dc, 1, dc->jmp_pc);
3257 gen_set_label(l1);
3258 gen_goto_tb(dc, 0, dc->pc);
3259 dc->is_jmp = DISAS_TB_JUMP;
3260 dc->jmp = JMP_NOJMP;
3261 } else if (dc->jmp == JMP_DIRECT) {
3262 cris_evaluate_flags(dc);
3263 gen_goto_tb(dc, 0, dc->jmp_pc);
3264 dc->is_jmp = DISAS_TB_JUMP;
3265 dc->jmp = JMP_NOJMP;
3266 } else {
3267 t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc));
3268 dc->is_jmp = DISAS_JUMP;
3269 }
3270 break;
3271 }
3272 }
3273
3274 /* If we are rexecuting a branch due to exceptions on
3275 delay slots dont break. */
3276 if (!(tb->pc & 1) && cs->singlestep_enabled) {
3277 break;
3278 }
3279 } while (!dc->is_jmp && !dc->cpustate_changed
3280 && !tcg_op_buf_full()
3281 && !singlestep
3282 && (dc->pc < next_page_start)
3283 && num_insns < max_insns);
3284
3285 if (dc->clear_locked_irq) {
3286 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3287 }
3288
3289 npc = dc->pc;
3290
3291 if (tb->cflags & CF_LAST_IO)
3292 gen_io_end();
3293 /* Force an update if the per-tb cpu state has changed. */
3294 if (dc->is_jmp == DISAS_NEXT
3295 && (dc->cpustate_changed || !dc->flagx_known
3296 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3297 dc->is_jmp = DISAS_UPDATE;
3298 tcg_gen_movi_tl(env_pc, npc);
3299 }
3300 /* Broken branch+delayslot sequence. */
3301 if (dc->delayed_branch == 1) {
3302 /* Set env->dslot to the size of the branch insn. */
3303 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3304 cris_store_direct_jmp(dc);
3305 }
3306
3307 cris_evaluate_flags(dc);
3308
3309 if (unlikely(cs->singlestep_enabled)) {
3310 if (dc->is_jmp == DISAS_NEXT) {
3311 tcg_gen_movi_tl(env_pc, npc);
3312 }
3313 t_gen_raise_exception(EXCP_DEBUG);
3314 } else {
3315 switch (dc->is_jmp) {
3316 case DISAS_NEXT:
3317 gen_goto_tb(dc, 1, npc);
3318 break;
3319 default:
3320 case DISAS_JUMP:
3321 case DISAS_UPDATE:
3322 /* indicate that the hash table must be used
3323 to find the next TB */
3324 tcg_gen_exit_tb(0);
3325 break;
3326 case DISAS_SWI:
3327 case DISAS_TB_JUMP:
3328 /* nothing more to generate */
3329 break;
3330 }
3331 }
3332 gen_tb_end(tb, num_insns);
3333
3334 if (search_pc) {
3335 j = tcg_op_buf_count();
3336 lj++;
3337 while (lj <= j) {
3338 tcg_ctx.gen_opc_instr_start[lj++] = 0;
3339 }
3340 } else {
3341 tb->size = dc->pc - pc_start;
3342 tb->icount = num_insns;
3343 }
3344
3345 #ifdef DEBUG_DISAS
3346 #if !DISAS_CRIS
3347 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3348 log_target_disas(cs, pc_start, dc->pc - pc_start,
3349 env->pregs[PR_VR]);
3350 qemu_log("\nisize=%d osize=%d\n",
3351 dc->pc - pc_start, tcg_op_buf_count());
3352 }
3353 #endif
3354 #endif
3355 }
3356
3357 void gen_intermediate_code (CPUCRISState *env, struct TranslationBlock *tb)
3358 {
3359 gen_intermediate_code_internal(cris_env_get_cpu(env), tb, false);
3360 }
3361
3362 void gen_intermediate_code_pc (CPUCRISState *env, struct TranslationBlock *tb)
3363 {
3364 gen_intermediate_code_internal(cris_env_get_cpu(env), tb, true);
3365 }
3366
3367 void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3368 int flags)
3369 {
3370 CRISCPU *cpu = CRIS_CPU(cs);
3371 CPUCRISState *env = &cpu->env;
3372 int i;
3373 uint32_t srs;
3374
3375 if (!env || !f) {
3376 return;
3377 }
3378
3379 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3380 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3381 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3382 env->cc_op,
3383 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3384
3385
3386 for (i = 0; i < 16; i++) {
3387 cpu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]);
3388 if ((i + 1) % 4 == 0) {
3389 cpu_fprintf(f, "\n");
3390 }
3391 }
3392 cpu_fprintf(f, "\nspecial regs:\n");
3393 for (i = 0; i < 16; i++) {
3394 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3395 if ((i + 1) % 4 == 0) {
3396 cpu_fprintf(f, "\n");
3397 }
3398 }
3399 srs = env->pregs[PR_SRS];
3400 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3401 if (srs < ARRAY_SIZE(env->sregs)) {
3402 for (i = 0; i < 16; i++) {
3403 cpu_fprintf(f, "s%2.2d=%8.8x ",
3404 i, env->sregs[srs][i]);
3405 if ((i + 1) % 4 == 0) {
3406 cpu_fprintf(f, "\n");
3407 }
3408 }
3409 }
3410 cpu_fprintf(f, "\n\n");
3411
3412 }
3413
3414 void cris_initialize_tcg(void)
3415 {
3416 int i;
3417
3418 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3419 cc_x = tcg_global_mem_new(TCG_AREG0,
3420 offsetof(CPUCRISState, cc_x), "cc_x");
3421 cc_src = tcg_global_mem_new(TCG_AREG0,
3422 offsetof(CPUCRISState, cc_src), "cc_src");
3423 cc_dest = tcg_global_mem_new(TCG_AREG0,
3424 offsetof(CPUCRISState, cc_dest),
3425 "cc_dest");
3426 cc_result = tcg_global_mem_new(TCG_AREG0,
3427 offsetof(CPUCRISState, cc_result),
3428 "cc_result");
3429 cc_op = tcg_global_mem_new(TCG_AREG0,
3430 offsetof(CPUCRISState, cc_op), "cc_op");
3431 cc_size = tcg_global_mem_new(TCG_AREG0,
3432 offsetof(CPUCRISState, cc_size),
3433 "cc_size");
3434 cc_mask = tcg_global_mem_new(TCG_AREG0,
3435 offsetof(CPUCRISState, cc_mask),
3436 "cc_mask");
3437
3438 env_pc = tcg_global_mem_new(TCG_AREG0,
3439 offsetof(CPUCRISState, pc),
3440 "pc");
3441 env_btarget = tcg_global_mem_new(TCG_AREG0,
3442 offsetof(CPUCRISState, btarget),
3443 "btarget");
3444 env_btaken = tcg_global_mem_new(TCG_AREG0,
3445 offsetof(CPUCRISState, btaken),
3446 "btaken");
3447 for (i = 0; i < 16; i++) {
3448 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3449 offsetof(CPUCRISState, regs[i]),
3450 regnames[i]);
3451 }
3452 for (i = 0; i < 16; i++) {
3453 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3454 offsetof(CPUCRISState, pregs[i]),
3455 pregnames[i]);
3456 }
3457 }
3458
3459 void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos)
3460 {
3461 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
3462 }
AR7 emulation for QEMU