2 * vfio based device assignment support
4 * Copyright Red Hat, Inc. 2012
7 * Alex Williamson <alex.williamson@redhat.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
12 * Based on qemu-kvm device-assignment:
13 * Adapted for KVM by Qumranet.
14 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com)
15 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com)
16 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com)
17 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com)
18 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com)
22 #include <linux/vfio.h>
23 #include <sys/ioctl.h>
26 #include <sys/types.h>
30 #include "exec/address-spaces.h"
31 #include "exec/memory.h"
32 #include "hw/pci/msi.h"
33 #include "hw/pci/msix.h"
34 #include "hw/pci/pci.h"
35 #include "qemu-common.h"
36 #include "qemu/error-report.h"
37 #include "qemu/event_notifier.h"
38 #include "qemu/queue.h"
39 #include "qemu/range.h"
40 #include "sysemu/kvm.h"
41 #include "sysemu/sysemu.h"
43 #include "hw/vfio/vfio.h"
44 #include "hw/vfio/vfio-common.h"
48 typedef struct VFIOQuirk
{
50 struct VFIOPCIDevice
*vdev
;
51 QLIST_ENTRY(VFIOQuirk
) next
;
53 uint32_t base_offset
:TARGET_PAGE_BITS
;
54 uint32_t address_offset
:TARGET_PAGE_BITS
;
55 uint32_t address_size
:3;
58 uint32_t address_match
;
59 uint32_t address_mask
;
61 uint32_t address_val
:TARGET_PAGE_BITS
;
62 uint32_t data_offset
:TARGET_PAGE_BITS
;
71 typedef struct VFIOBAR
{
75 QLIST_HEAD(, VFIOQuirk
) quirks
;
78 typedef struct VFIOVGARegion
{
82 QLIST_HEAD(, VFIOQuirk
) quirks
;
85 typedef struct VFIOVGA
{
88 VFIOVGARegion region
[QEMU_PCI_VGA_NUM_REGIONS
];
91 typedef struct VFIOINTx
{
92 bool pending
; /* interrupt pending */
93 bool kvm_accel
; /* set when QEMU bypass through KVM enabled */
94 uint8_t pin
; /* which pin to pull for qemu_set_irq */
95 EventNotifier interrupt
; /* eventfd triggered on interrupt */
96 EventNotifier unmask
; /* eventfd for unmask on QEMU bypass */
97 PCIINTxRoute route
; /* routing info for QEMU bypass */
98 uint32_t mmap_timeout
; /* delay to re-enable mmaps after interrupt */
99 QEMUTimer
*mmap_timer
; /* enable mmaps after periods w/o interrupts */
102 typedef struct VFIOMSIVector
{
104 * Two interrupt paths are configured per vector. The first, is only used
105 * for interrupts injected via QEMU. This is typically the non-accel path,
106 * but may also be used when we want QEMU to handle masking and pending
107 * bits. The KVM path bypasses QEMU and is therefore higher performance,
108 * but requires masking at the device. virq is used to track the MSI route
109 * through KVM, thus kvm_interrupt is only available when virq is set to a
110 * valid (>= 0) value.
112 EventNotifier interrupt
;
113 EventNotifier kvm_interrupt
;
114 struct VFIOPCIDevice
*vdev
; /* back pointer to device */
126 /* Cache of MSI-X setup plus extra mmap and memory region for split BAR map */
127 typedef struct VFIOMSIXInfo
{
131 uint32_t table_offset
;
133 MemoryRegion mmap_mem
;
137 typedef struct VFIOPCIDevice
{
141 unsigned int config_size
;
142 uint8_t *emulated_config_bits
; /* QEMU emulated bits, little-endian */
143 off_t config_offset
; /* Offset of config space region within device fd */
144 unsigned int rom_size
;
145 off_t rom_offset
; /* Offset of ROM region within device fd */
148 VFIOMSIVector
*msi_vectors
;
150 int nr_vectors
; /* Number of MSI/MSIX vectors currently in use */
151 int interrupt
; /* Current interrupt type */
152 VFIOBAR bars
[PCI_NUM_REGIONS
- 1]; /* No ROM */
153 VFIOVGA vga
; /* 0xa0000, 0x3b0, 0x3c0 */
154 PCIHostDeviceAddress host
;
155 EventNotifier err_notifier
;
156 EventNotifier req_notifier
;
157 int (*resetfn
)(struct VFIOPCIDevice
*);
159 #define VFIO_FEATURE_ENABLE_VGA_BIT 0
160 #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
161 #define VFIO_FEATURE_ENABLE_REQ_BIT 1
162 #define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT)
170 bool rom_read_failed
;
173 typedef struct VFIORomBlacklistEntry
{
176 } VFIORomBlacklistEntry
;
179 * List of device ids/vendor ids for which to disable
180 * option rom loading. This avoids the guest hangs during rom
181 * execution as noticed with the BCM 57810 card for lack of a
182 * more better way to handle such issues.
183 * The user can still override by specifying a romfile or
185 * Please see https://bugs.launchpad.net/qemu/+bug/1284874
186 * for an analysis of the 57810 card hang. When adding
187 * a new vendor id/device id combination below, please also add
188 * your card/environment details and information that could
189 * help in debugging to the bug tracking this issue
191 static const VFIORomBlacklistEntry romblacklist
[] = {
192 /* Broadcom BCM 57810 */
196 #define MSIX_CAP_LENGTH 12
198 static void vfio_disable_interrupts(VFIOPCIDevice
*vdev
);
199 static uint32_t vfio_pci_read_config(PCIDevice
*pdev
, uint32_t addr
, int len
);
200 static void vfio_pci_write_config(PCIDevice
*pdev
, uint32_t addr
,
201 uint32_t val
, int len
);
202 static void vfio_mmap_set_enabled(VFIOPCIDevice
*vdev
, bool enabled
);
205 * Disabling BAR mmaping can be slow, but toggling it around INTx can
206 * also be a huge overhead. We try to get the best of both worlds by
207 * waiting until an interrupt to disable mmaps (subsequent transitions
208 * to the same state are effectively no overhead). If the interrupt has
209 * been serviced and the time gap is long enough, we re-enable mmaps for
210 * performance. This works well for things like graphics cards, which
211 * may not use their interrupt at all and are penalized to an unusable
212 * level by read/write BAR traps. Other devices, like NICs, have more
213 * regular interrupts and see much better latency by staying in non-mmap
214 * mode. We therefore set the default mmap_timeout such that a ping
215 * is just enough to keep the mmap disabled. Users can experiment with
216 * other options with the x-intx-mmap-timeout-ms parameter (a value of
217 * zero disables the timer).
219 static void vfio_intx_mmap_enable(void *opaque
)
221 VFIOPCIDevice
*vdev
= opaque
;
223 if (vdev
->intx
.pending
) {
224 timer_mod(vdev
->intx
.mmap_timer
,
225 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + vdev
->intx
.mmap_timeout
);
229 vfio_mmap_set_enabled(vdev
, true);
232 static void vfio_intx_interrupt(void *opaque
)
234 VFIOPCIDevice
*vdev
= opaque
;
236 if (!event_notifier_test_and_clear(&vdev
->intx
.interrupt
)) {
240 trace_vfio_intx_interrupt(vdev
->vbasedev
.name
, 'A' + vdev
->intx
.pin
);
242 vdev
->intx
.pending
= true;
243 pci_irq_assert(&vdev
->pdev
);
244 vfio_mmap_set_enabled(vdev
, false);
245 if (vdev
->intx
.mmap_timeout
) {
246 timer_mod(vdev
->intx
.mmap_timer
,
247 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + vdev
->intx
.mmap_timeout
);
251 static void vfio_eoi(VFIODevice
*vbasedev
)
253 VFIOPCIDevice
*vdev
= container_of(vbasedev
, VFIOPCIDevice
, vbasedev
);
255 if (!vdev
->intx
.pending
) {
259 trace_vfio_eoi(vbasedev
->name
);
261 vdev
->intx
.pending
= false;
262 pci_irq_deassert(&vdev
->pdev
);
263 vfio_unmask_single_irqindex(vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
266 static void vfio_enable_intx_kvm(VFIOPCIDevice
*vdev
)
269 struct kvm_irqfd irqfd
= {
270 .fd
= event_notifier_get_fd(&vdev
->intx
.interrupt
),
271 .gsi
= vdev
->intx
.route
.irq
,
272 .flags
= KVM_IRQFD_FLAG_RESAMPLE
,
274 struct vfio_irq_set
*irq_set
;
278 if (!VFIO_ALLOW_KVM_INTX
|| !kvm_irqfds_enabled() ||
279 vdev
->intx
.route
.mode
!= PCI_INTX_ENABLED
||
280 !kvm_resamplefds_enabled()) {
284 /* Get to a known interrupt state */
285 qemu_set_fd_handler(irqfd
.fd
, NULL
, NULL
, vdev
);
286 vfio_mask_single_irqindex(&vdev
->vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
287 vdev
->intx
.pending
= false;
288 pci_irq_deassert(&vdev
->pdev
);
290 /* Get an eventfd for resample/unmask */
291 if (event_notifier_init(&vdev
->intx
.unmask
, 0)) {
292 error_report("vfio: Error: event_notifier_init failed eoi");
296 /* KVM triggers it, VFIO listens for it */
297 irqfd
.resamplefd
= event_notifier_get_fd(&vdev
->intx
.unmask
);
299 if (kvm_vm_ioctl(kvm_state
, KVM_IRQFD
, &irqfd
)) {
300 error_report("vfio: Error: Failed to setup resample irqfd: %m");
304 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
306 irq_set
= g_malloc0(argsz
);
307 irq_set
->argsz
= argsz
;
308 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
| VFIO_IRQ_SET_ACTION_UNMASK
;
309 irq_set
->index
= VFIO_PCI_INTX_IRQ_INDEX
;
312 pfd
= (int32_t *)&irq_set
->data
;
314 *pfd
= irqfd
.resamplefd
;
316 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
319 error_report("vfio: Error: Failed to setup INTx unmask fd: %m");
324 vfio_unmask_single_irqindex(&vdev
->vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
326 vdev
->intx
.kvm_accel
= true;
328 trace_vfio_enable_intx_kvm(vdev
->vbasedev
.name
);
333 irqfd
.flags
= KVM_IRQFD_FLAG_DEASSIGN
;
334 kvm_vm_ioctl(kvm_state
, KVM_IRQFD
, &irqfd
);
336 event_notifier_cleanup(&vdev
->intx
.unmask
);
338 qemu_set_fd_handler(irqfd
.fd
, vfio_intx_interrupt
, NULL
, vdev
);
339 vfio_unmask_single_irqindex(&vdev
->vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
343 static void vfio_disable_intx_kvm(VFIOPCIDevice
*vdev
)
346 struct kvm_irqfd irqfd
= {
347 .fd
= event_notifier_get_fd(&vdev
->intx
.interrupt
),
348 .gsi
= vdev
->intx
.route
.irq
,
349 .flags
= KVM_IRQFD_FLAG_DEASSIGN
,
352 if (!vdev
->intx
.kvm_accel
) {
357 * Get to a known state, hardware masked, QEMU ready to accept new
358 * interrupts, QEMU IRQ de-asserted.
360 vfio_mask_single_irqindex(&vdev
->vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
361 vdev
->intx
.pending
= false;
362 pci_irq_deassert(&vdev
->pdev
);
364 /* Tell KVM to stop listening for an INTx irqfd */
365 if (kvm_vm_ioctl(kvm_state
, KVM_IRQFD
, &irqfd
)) {
366 error_report("vfio: Error: Failed to disable INTx irqfd: %m");
369 /* We only need to close the eventfd for VFIO to cleanup the kernel side */
370 event_notifier_cleanup(&vdev
->intx
.unmask
);
372 /* QEMU starts listening for interrupt events. */
373 qemu_set_fd_handler(irqfd
.fd
, vfio_intx_interrupt
, NULL
, vdev
);
375 vdev
->intx
.kvm_accel
= false;
377 /* If we've missed an event, let it re-fire through QEMU */
378 vfio_unmask_single_irqindex(&vdev
->vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
380 trace_vfio_disable_intx_kvm(vdev
->vbasedev
.name
);
384 static void vfio_update_irq(PCIDevice
*pdev
)
386 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
389 if (vdev
->interrupt
!= VFIO_INT_INTx
) {
393 route
= pci_device_route_intx_to_irq(&vdev
->pdev
, vdev
->intx
.pin
);
395 if (!pci_intx_route_changed(&vdev
->intx
.route
, &route
)) {
396 return; /* Nothing changed */
399 trace_vfio_update_irq(vdev
->vbasedev
.name
,
400 vdev
->intx
.route
.irq
, route
.irq
);
402 vfio_disable_intx_kvm(vdev
);
404 vdev
->intx
.route
= route
;
406 if (route
.mode
!= PCI_INTX_ENABLED
) {
410 vfio_enable_intx_kvm(vdev
);
412 /* Re-enable the interrupt in cased we missed an EOI */
413 vfio_eoi(&vdev
->vbasedev
);
416 static int vfio_enable_intx(VFIOPCIDevice
*vdev
)
418 uint8_t pin
= vfio_pci_read_config(&vdev
->pdev
, PCI_INTERRUPT_PIN
, 1);
420 struct vfio_irq_set
*irq_set
;
427 vfio_disable_interrupts(vdev
);
429 vdev
->intx
.pin
= pin
- 1; /* Pin A (1) -> irq[0] */
430 pci_config_set_interrupt_pin(vdev
->pdev
.config
, pin
);
434 * Only conditional to avoid generating error messages on platforms
435 * where we won't actually use the result anyway.
437 if (kvm_irqfds_enabled() && kvm_resamplefds_enabled()) {
438 vdev
->intx
.route
= pci_device_route_intx_to_irq(&vdev
->pdev
,
443 ret
= event_notifier_init(&vdev
->intx
.interrupt
, 0);
445 error_report("vfio: Error: event_notifier_init failed");
449 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
451 irq_set
= g_malloc0(argsz
);
452 irq_set
->argsz
= argsz
;
453 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
| VFIO_IRQ_SET_ACTION_TRIGGER
;
454 irq_set
->index
= VFIO_PCI_INTX_IRQ_INDEX
;
457 pfd
= (int32_t *)&irq_set
->data
;
459 *pfd
= event_notifier_get_fd(&vdev
->intx
.interrupt
);
460 qemu_set_fd_handler(*pfd
, vfio_intx_interrupt
, NULL
, vdev
);
462 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
465 error_report("vfio: Error: Failed to setup INTx fd: %m");
466 qemu_set_fd_handler(*pfd
, NULL
, NULL
, vdev
);
467 event_notifier_cleanup(&vdev
->intx
.interrupt
);
471 vfio_enable_intx_kvm(vdev
);
473 vdev
->interrupt
= VFIO_INT_INTx
;
475 trace_vfio_enable_intx(vdev
->vbasedev
.name
);
480 static void vfio_disable_intx(VFIOPCIDevice
*vdev
)
484 timer_del(vdev
->intx
.mmap_timer
);
485 vfio_disable_intx_kvm(vdev
);
486 vfio_disable_irqindex(&vdev
->vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
487 vdev
->intx
.pending
= false;
488 pci_irq_deassert(&vdev
->pdev
);
489 vfio_mmap_set_enabled(vdev
, true);
491 fd
= event_notifier_get_fd(&vdev
->intx
.interrupt
);
492 qemu_set_fd_handler(fd
, NULL
, NULL
, vdev
);
493 event_notifier_cleanup(&vdev
->intx
.interrupt
);
495 vdev
->interrupt
= VFIO_INT_NONE
;
497 trace_vfio_disable_intx(vdev
->vbasedev
.name
);
503 static void vfio_msi_interrupt(void *opaque
)
505 VFIOMSIVector
*vector
= opaque
;
506 VFIOPCIDevice
*vdev
= vector
->vdev
;
507 int nr
= vector
- vdev
->msi_vectors
;
509 if (!event_notifier_test_and_clear(&vector
->interrupt
)) {
516 if (vdev
->interrupt
== VFIO_INT_MSIX
) {
517 msg
= msix_get_message(&vdev
->pdev
, nr
);
518 } else if (vdev
->interrupt
== VFIO_INT_MSI
) {
519 msg
= msi_get_message(&vdev
->pdev
, nr
);
524 trace_vfio_msi_interrupt(vdev
->vbasedev
.name
, nr
, msg
.address
, msg
.data
);
527 if (vdev
->interrupt
== VFIO_INT_MSIX
) {
528 msix_notify(&vdev
->pdev
, nr
);
529 } else if (vdev
->interrupt
== VFIO_INT_MSI
) {
530 msi_notify(&vdev
->pdev
, nr
);
532 error_report("vfio: MSI interrupt receieved, but not enabled?");
536 static int vfio_enable_vectors(VFIOPCIDevice
*vdev
, bool msix
)
538 struct vfio_irq_set
*irq_set
;
539 int ret
= 0, i
, argsz
;
542 argsz
= sizeof(*irq_set
) + (vdev
->nr_vectors
* sizeof(*fds
));
544 irq_set
= g_malloc0(argsz
);
545 irq_set
->argsz
= argsz
;
546 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
| VFIO_IRQ_SET_ACTION_TRIGGER
;
547 irq_set
->index
= msix
? VFIO_PCI_MSIX_IRQ_INDEX
: VFIO_PCI_MSI_IRQ_INDEX
;
549 irq_set
->count
= vdev
->nr_vectors
;
550 fds
= (int32_t *)&irq_set
->data
;
552 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
556 * MSI vs MSI-X - The guest has direct access to MSI mask and pending
557 * bits, therefore we always use the KVM signaling path when setup.
558 * MSI-X mask and pending bits are emulated, so we want to use the
559 * KVM signaling path only when configured and unmasked.
561 if (vdev
->msi_vectors
[i
].use
) {
562 if (vdev
->msi_vectors
[i
].virq
< 0 ||
563 (msix
&& msix_is_masked(&vdev
->pdev
, i
))) {
564 fd
= event_notifier_get_fd(&vdev
->msi_vectors
[i
].interrupt
);
566 fd
= event_notifier_get_fd(&vdev
->msi_vectors
[i
].kvm_interrupt
);
573 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
580 static void vfio_add_kvm_msi_virq(VFIOMSIVector
*vector
, MSIMessage
*msg
,
585 if ((msix
&& !VFIO_ALLOW_KVM_MSIX
) ||
586 (!msix
&& !VFIO_ALLOW_KVM_MSI
) || !msg
) {
590 if (event_notifier_init(&vector
->kvm_interrupt
, 0)) {
594 virq
= kvm_irqchip_add_msi_route(kvm_state
, *msg
);
596 event_notifier_cleanup(&vector
->kvm_interrupt
);
600 if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state
, &vector
->kvm_interrupt
,
602 kvm_irqchip_release_virq(kvm_state
, virq
);
603 event_notifier_cleanup(&vector
->kvm_interrupt
);
610 static void vfio_remove_kvm_msi_virq(VFIOMSIVector
*vector
)
612 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state
, &vector
->kvm_interrupt
,
614 kvm_irqchip_release_virq(kvm_state
, vector
->virq
);
616 event_notifier_cleanup(&vector
->kvm_interrupt
);
619 static void vfio_update_kvm_msi_virq(VFIOMSIVector
*vector
, MSIMessage msg
)
621 kvm_irqchip_update_msi_route(kvm_state
, vector
->virq
, msg
);
624 static int vfio_msix_vector_do_use(PCIDevice
*pdev
, unsigned int nr
,
625 MSIMessage
*msg
, IOHandler
*handler
)
627 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
628 VFIOMSIVector
*vector
;
631 trace_vfio_msix_vector_do_use(vdev
->vbasedev
.name
, nr
);
633 vector
= &vdev
->msi_vectors
[nr
];
638 if (event_notifier_init(&vector
->interrupt
, 0)) {
639 error_report("vfio: Error: event_notifier_init failed");
642 msix_vector_use(pdev
, nr
);
645 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
646 handler
, NULL
, vector
);
649 * Attempt to enable route through KVM irqchip,
650 * default to userspace handling if unavailable.
652 if (vector
->virq
>= 0) {
654 vfio_remove_kvm_msi_virq(vector
);
656 vfio_update_kvm_msi_virq(vector
, *msg
);
659 vfio_add_kvm_msi_virq(vector
, msg
, true);
663 * We don't want to have the host allocate all possible MSI vectors
664 * for a device if they're not in use, so we shutdown and incrementally
665 * increase them as needed.
667 if (vdev
->nr_vectors
< nr
+ 1) {
668 vfio_disable_irqindex(&vdev
->vbasedev
, VFIO_PCI_MSIX_IRQ_INDEX
);
669 vdev
->nr_vectors
= nr
+ 1;
670 ret
= vfio_enable_vectors(vdev
, true);
672 error_report("vfio: failed to enable vectors, %d", ret
);
676 struct vfio_irq_set
*irq_set
;
679 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
681 irq_set
= g_malloc0(argsz
);
682 irq_set
->argsz
= argsz
;
683 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
684 VFIO_IRQ_SET_ACTION_TRIGGER
;
685 irq_set
->index
= VFIO_PCI_MSIX_IRQ_INDEX
;
688 pfd
= (int32_t *)&irq_set
->data
;
690 if (vector
->virq
>= 0) {
691 *pfd
= event_notifier_get_fd(&vector
->kvm_interrupt
);
693 *pfd
= event_notifier_get_fd(&vector
->interrupt
);
696 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
699 error_report("vfio: failed to modify vector, %d", ret
);
706 static int vfio_msix_vector_use(PCIDevice
*pdev
,
707 unsigned int nr
, MSIMessage msg
)
709 return vfio_msix_vector_do_use(pdev
, nr
, &msg
, vfio_msi_interrupt
);
712 static void vfio_msix_vector_release(PCIDevice
*pdev
, unsigned int nr
)
714 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
715 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[nr
];
717 trace_vfio_msix_vector_release(vdev
->vbasedev
.name
, nr
);
720 * There are still old guests that mask and unmask vectors on every
721 * interrupt. If we're using QEMU bypass with a KVM irqfd, leave all of
722 * the KVM setup in place, simply switch VFIO to use the non-bypass
723 * eventfd. We'll then fire the interrupt through QEMU and the MSI-X
724 * core will mask the interrupt and set pending bits, allowing it to
725 * be re-asserted on unmask. Nothing to do if already using QEMU mode.
727 if (vector
->virq
>= 0) {
729 struct vfio_irq_set
*irq_set
;
732 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
734 irq_set
= g_malloc0(argsz
);
735 irq_set
->argsz
= argsz
;
736 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
737 VFIO_IRQ_SET_ACTION_TRIGGER
;
738 irq_set
->index
= VFIO_PCI_MSIX_IRQ_INDEX
;
741 pfd
= (int32_t *)&irq_set
->data
;
743 *pfd
= event_notifier_get_fd(&vector
->interrupt
);
745 ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
751 static void vfio_enable_msix(VFIOPCIDevice
*vdev
)
753 vfio_disable_interrupts(vdev
);
755 vdev
->msi_vectors
= g_malloc0(vdev
->msix
->entries
* sizeof(VFIOMSIVector
));
757 vdev
->interrupt
= VFIO_INT_MSIX
;
760 * Some communication channels between VF & PF or PF & fw rely on the
761 * physical state of the device and expect that enabling MSI-X from the
762 * guest enables the same on the host. When our guest is Linux, the
763 * guest driver call to pci_enable_msix() sets the enabling bit in the
764 * MSI-X capability, but leaves the vector table masked. We therefore
765 * can't rely on a vector_use callback (from request_irq() in the guest)
766 * to switch the physical device into MSI-X mode because that may come a
767 * long time after pci_enable_msix(). This code enables vector 0 with
768 * triggering to userspace, then immediately release the vector, leaving
769 * the physical device with no vectors enabled, but MSI-X enabled, just
770 * like the guest view.
772 vfio_msix_vector_do_use(&vdev
->pdev
, 0, NULL
, NULL
);
773 vfio_msix_vector_release(&vdev
->pdev
, 0);
775 if (msix_set_vector_notifiers(&vdev
->pdev
, vfio_msix_vector_use
,
776 vfio_msix_vector_release
, NULL
)) {
777 error_report("vfio: msix_set_vector_notifiers failed");
780 trace_vfio_enable_msix(vdev
->vbasedev
.name
);
783 static void vfio_enable_msi(VFIOPCIDevice
*vdev
)
787 vfio_disable_interrupts(vdev
);
789 vdev
->nr_vectors
= msi_nr_vectors_allocated(&vdev
->pdev
);
791 vdev
->msi_vectors
= g_malloc0(vdev
->nr_vectors
* sizeof(VFIOMSIVector
));
793 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
794 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
795 MSIMessage msg
= msi_get_message(&vdev
->pdev
, i
);
801 if (event_notifier_init(&vector
->interrupt
, 0)) {
802 error_report("vfio: Error: event_notifier_init failed");
805 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
806 vfio_msi_interrupt
, NULL
, vector
);
809 * Attempt to enable route through KVM irqchip,
810 * default to userspace handling if unavailable.
812 vfio_add_kvm_msi_virq(vector
, &msg
, false);
815 /* Set interrupt type prior to possible interrupts */
816 vdev
->interrupt
= VFIO_INT_MSI
;
818 ret
= vfio_enable_vectors(vdev
, false);
821 error_report("vfio: Error: Failed to setup MSI fds: %m");
822 } else if (ret
!= vdev
->nr_vectors
) {
823 error_report("vfio: Error: Failed to enable %d "
824 "MSI vectors, retry with %d", vdev
->nr_vectors
, ret
);
827 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
828 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
829 if (vector
->virq
>= 0) {
830 vfio_remove_kvm_msi_virq(vector
);
832 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
834 event_notifier_cleanup(&vector
->interrupt
);
837 g_free(vdev
->msi_vectors
);
839 if (ret
> 0 && ret
!= vdev
->nr_vectors
) {
840 vdev
->nr_vectors
= ret
;
843 vdev
->nr_vectors
= 0;
846 * Failing to setup MSI doesn't really fall within any specification.
847 * Let's try leaving interrupts disabled and hope the guest figures
848 * out to fall back to INTx for this device.
850 error_report("vfio: Error: Failed to enable MSI");
851 vdev
->interrupt
= VFIO_INT_NONE
;
856 trace_vfio_enable_msi(vdev
->vbasedev
.name
, vdev
->nr_vectors
);
859 static void vfio_disable_msi_common(VFIOPCIDevice
*vdev
)
863 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
864 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
865 if (vdev
->msi_vectors
[i
].use
) {
866 if (vector
->virq
>= 0) {
867 vfio_remove_kvm_msi_virq(vector
);
869 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
871 event_notifier_cleanup(&vector
->interrupt
);
875 g_free(vdev
->msi_vectors
);
876 vdev
->msi_vectors
= NULL
;
877 vdev
->nr_vectors
= 0;
878 vdev
->interrupt
= VFIO_INT_NONE
;
880 vfio_enable_intx(vdev
);
883 static void vfio_disable_msix(VFIOPCIDevice
*vdev
)
887 msix_unset_vector_notifiers(&vdev
->pdev
);
890 * MSI-X will only release vectors if MSI-X is still enabled on the
891 * device, check through the rest and release it ourselves if necessary.
893 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
894 if (vdev
->msi_vectors
[i
].use
) {
895 vfio_msix_vector_release(&vdev
->pdev
, i
);
896 msix_vector_unuse(&vdev
->pdev
, i
);
900 if (vdev
->nr_vectors
) {
901 vfio_disable_irqindex(&vdev
->vbasedev
, VFIO_PCI_MSIX_IRQ_INDEX
);
904 vfio_disable_msi_common(vdev
);
906 trace_vfio_disable_msix(vdev
->vbasedev
.name
);
909 static void vfio_disable_msi(VFIOPCIDevice
*vdev
)
911 vfio_disable_irqindex(&vdev
->vbasedev
, VFIO_PCI_MSI_IRQ_INDEX
);
912 vfio_disable_msi_common(vdev
);
914 trace_vfio_disable_msi(vdev
->vbasedev
.name
);
917 static void vfio_update_msi(VFIOPCIDevice
*vdev
)
921 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
922 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
925 if (!vector
->use
|| vector
->virq
< 0) {
929 msg
= msi_get_message(&vdev
->pdev
, i
);
930 vfio_update_kvm_msi_virq(vector
, msg
);
934 static void vfio_pci_load_rom(VFIOPCIDevice
*vdev
)
936 struct vfio_region_info reg_info
= {
937 .argsz
= sizeof(reg_info
),
938 .index
= VFIO_PCI_ROM_REGION_INDEX
944 if (ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_GET_REGION_INFO
, ®_info
)) {
945 error_report("vfio: Error getting ROM info: %m");
949 trace_vfio_pci_load_rom(vdev
->vbasedev
.name
, (unsigned long)reg_info
.size
,
950 (unsigned long)reg_info
.offset
,
951 (unsigned long)reg_info
.flags
);
953 vdev
->rom_size
= size
= reg_info
.size
;
954 vdev
->rom_offset
= reg_info
.offset
;
956 if (!vdev
->rom_size
) {
957 vdev
->rom_read_failed
= true;
958 error_report("vfio-pci: Cannot read device rom at "
959 "%s", vdev
->vbasedev
.name
);
960 error_printf("Device option ROM contents are probably invalid "
961 "(check dmesg).\nSkip option ROM probe with rombar=0, "
962 "or load from file with romfile=\n");
966 vdev
->rom
= g_malloc(size
);
967 memset(vdev
->rom
, 0xff, size
);
970 bytes
= pread(vdev
->vbasedev
.fd
, vdev
->rom
+ off
,
971 size
, vdev
->rom_offset
+ off
);
974 } else if (bytes
> 0) {
978 if (errno
== EINTR
|| errno
== EAGAIN
) {
981 error_report("vfio: Error reading device ROM: %m");
987 static uint64_t vfio_rom_read(void *opaque
, hwaddr addr
, unsigned size
)
989 VFIOPCIDevice
*vdev
= opaque
;
998 /* Load the ROM lazily when the guest tries to read it */
999 if (unlikely(!vdev
->rom
&& !vdev
->rom_read_failed
)) {
1000 vfio_pci_load_rom(vdev
);
1003 memcpy(&val
, vdev
->rom
+ addr
,
1004 (addr
< vdev
->rom_size
) ? MIN(size
, vdev
->rom_size
- addr
) : 0);
1011 data
= le16_to_cpu(val
.word
);
1014 data
= le32_to_cpu(val
.dword
);
1017 hw_error("vfio: unsupported read size, %d bytes\n", size
);
1021 trace_vfio_rom_read(vdev
->vbasedev
.name
, addr
, size
, data
);
1026 static void vfio_rom_write(void *opaque
, hwaddr addr
,
1027 uint64_t data
, unsigned size
)
1031 static const MemoryRegionOps vfio_rom_ops
= {
1032 .read
= vfio_rom_read
,
1033 .write
= vfio_rom_write
,
1034 .endianness
= DEVICE_LITTLE_ENDIAN
,
1037 static bool vfio_blacklist_opt_rom(VFIOPCIDevice
*vdev
)
1039 PCIDevice
*pdev
= &vdev
->pdev
;
1040 uint16_t vendor_id
, device_id
;
1043 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1044 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
1046 while (count
< ARRAY_SIZE(romblacklist
)) {
1047 if (romblacklist
[count
].vendor_id
== vendor_id
&&
1048 romblacklist
[count
].device_id
== device_id
) {
1057 static void vfio_pci_size_rom(VFIOPCIDevice
*vdev
)
1059 uint32_t orig
, size
= cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK
);
1060 off_t offset
= vdev
->config_offset
+ PCI_ROM_ADDRESS
;
1061 DeviceState
*dev
= DEVICE(vdev
);
1063 int fd
= vdev
->vbasedev
.fd
;
1065 if (vdev
->pdev
.romfile
|| !vdev
->pdev
.rom_bar
) {
1066 /* Since pci handles romfile, just print a message and return */
1067 if (vfio_blacklist_opt_rom(vdev
) && vdev
->pdev
.romfile
) {
1068 error_printf("Warning : Device at %04x:%02x:%02x.%x "
1069 "is known to cause system instability issues during "
1070 "option rom execution. "
1071 "Proceeding anyway since user specified romfile\n",
1072 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1073 vdev
->host
.function
);
1079 * Use the same size ROM BAR as the physical device. The contents
1080 * will get filled in later when the guest tries to read it.
1082 if (pread(fd
, &orig
, 4, offset
) != 4 ||
1083 pwrite(fd
, &size
, 4, offset
) != 4 ||
1084 pread(fd
, &size
, 4, offset
) != 4 ||
1085 pwrite(fd
, &orig
, 4, offset
) != 4) {
1086 error_report("%s(%04x:%02x:%02x.%x) failed: %m",
1087 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
1088 vdev
->host
.slot
, vdev
->host
.function
);
1092 size
= ~(le32_to_cpu(size
) & PCI_ROM_ADDRESS_MASK
) + 1;
1098 if (vfio_blacklist_opt_rom(vdev
)) {
1099 if (dev
->opts
&& qemu_opt_get(dev
->opts
, "rombar")) {
1100 error_printf("Warning : Device at %04x:%02x:%02x.%x "
1101 "is known to cause system instability issues during "
1102 "option rom execution. "
1103 "Proceeding anyway since user specified non zero value for "
1105 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1106 vdev
->host
.function
);
1108 error_printf("Warning : Rom loading for device at "
1109 "%04x:%02x:%02x.%x has been disabled due to "
1110 "system instability issues. "
1111 "Specify rombar=1 or romfile to force\n",
1112 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1113 vdev
->host
.function
);
1118 trace_vfio_pci_size_rom(vdev
->vbasedev
.name
, size
);
1120 snprintf(name
, sizeof(name
), "vfio[%04x:%02x:%02x.%x].rom",
1121 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1122 vdev
->host
.function
);
1124 memory_region_init_io(&vdev
->pdev
.rom
, OBJECT(vdev
),
1125 &vfio_rom_ops
, vdev
, name
, size
);
1127 pci_register_bar(&vdev
->pdev
, PCI_ROM_SLOT
,
1128 PCI_BASE_ADDRESS_SPACE_MEMORY
, &vdev
->pdev
.rom
);
1130 vdev
->pdev
.has_rom
= true;
1131 vdev
->rom_read_failed
= false;
1134 static void vfio_vga_write(void *opaque
, hwaddr addr
,
1135 uint64_t data
, unsigned size
)
1137 VFIOVGARegion
*region
= opaque
;
1138 VFIOVGA
*vga
= container_of(region
, VFIOVGA
, region
[region
->nr
]);
1145 off_t offset
= vga
->fd_offset
+ region
->offset
+ addr
;
1152 buf
.word
= cpu_to_le16(data
);
1155 buf
.dword
= cpu_to_le32(data
);
1158 hw_error("vfio: unsupported write size, %d bytes", size
);
1162 if (pwrite(vga
->fd
, &buf
, size
, offset
) != size
) {
1163 error_report("%s(,0x%"HWADDR_PRIx
", 0x%"PRIx64
", %d) failed: %m",
1164 __func__
, region
->offset
+ addr
, data
, size
);
1167 trace_vfio_vga_write(region
->offset
+ addr
, data
, size
);
1170 static uint64_t vfio_vga_read(void *opaque
, hwaddr addr
, unsigned size
)
1172 VFIOVGARegion
*region
= opaque
;
1173 VFIOVGA
*vga
= container_of(region
, VFIOVGA
, region
[region
->nr
]);
1181 off_t offset
= vga
->fd_offset
+ region
->offset
+ addr
;
1183 if (pread(vga
->fd
, &buf
, size
, offset
) != size
) {
1184 error_report("%s(,0x%"HWADDR_PRIx
", %d) failed: %m",
1185 __func__
, region
->offset
+ addr
, size
);
1186 return (uint64_t)-1;
1194 data
= le16_to_cpu(buf
.word
);
1197 data
= le32_to_cpu(buf
.dword
);
1200 hw_error("vfio: unsupported read size, %d bytes", size
);
1204 trace_vfio_vga_read(region
->offset
+ addr
, size
, data
);
1209 static const MemoryRegionOps vfio_vga_ops
= {
1210 .read
= vfio_vga_read
,
1211 .write
= vfio_vga_write
,
1212 .endianness
= DEVICE_LITTLE_ENDIAN
,
1216 * Device specific quirks
1219 /* Is range1 fully contained within range2? */
1220 static bool vfio_range_contained(uint64_t first1
, uint64_t len1
,
1221 uint64_t first2
, uint64_t len2
) {
1222 return (first1
>= first2
&& first1
+ len1
<= first2
+ len2
);
1225 static bool vfio_flags_enabled(uint8_t flags
, uint8_t mask
)
1227 return (mask
&& (flags
& mask
) == mask
);
1230 static uint64_t vfio_generic_window_quirk_read(void *opaque
,
1231 hwaddr addr
, unsigned size
)
1233 VFIOQuirk
*quirk
= opaque
;
1234 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1237 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.read_flags
) &&
1238 ranges_overlap(addr
, size
,
1239 quirk
->data
.data_offset
, quirk
->data
.data_size
)) {
1240 hwaddr offset
= addr
- quirk
->data
.data_offset
;
1242 if (!vfio_range_contained(addr
, size
, quirk
->data
.data_offset
,
1243 quirk
->data
.data_size
)) {
1244 hw_error("%s: window data read not fully contained: %s",
1245 __func__
, memory_region_name(&quirk
->mem
));
1248 data
= vfio_pci_read_config(&vdev
->pdev
,
1249 quirk
->data
.address_val
+ offset
, size
);
1251 trace_vfio_generic_window_quirk_read(memory_region_name(&quirk
->mem
),
1252 vdev
->vbasedev
.name
,
1256 data
= vfio_region_read(&vdev
->bars
[quirk
->data
.bar
].region
,
1257 addr
+ quirk
->data
.base_offset
, size
);
1263 static void vfio_generic_window_quirk_write(void *opaque
, hwaddr addr
,
1264 uint64_t data
, unsigned size
)
1266 VFIOQuirk
*quirk
= opaque
;
1267 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1269 if (ranges_overlap(addr
, size
,
1270 quirk
->data
.address_offset
, quirk
->data
.address_size
)) {
1272 if (addr
!= quirk
->data
.address_offset
) {
1273 hw_error("%s: offset write into address window: %s",
1274 __func__
, memory_region_name(&quirk
->mem
));
1277 if ((data
& ~quirk
->data
.address_mask
) == quirk
->data
.address_match
) {
1278 quirk
->data
.flags
|= quirk
->data
.write_flags
|
1279 quirk
->data
.read_flags
;
1280 quirk
->data
.address_val
= data
& quirk
->data
.address_mask
;
1282 quirk
->data
.flags
&= ~(quirk
->data
.write_flags
|
1283 quirk
->data
.read_flags
);
1287 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.write_flags
) &&
1288 ranges_overlap(addr
, size
,
1289 quirk
->data
.data_offset
, quirk
->data
.data_size
)) {
1290 hwaddr offset
= addr
- quirk
->data
.data_offset
;
1292 if (!vfio_range_contained(addr
, size
, quirk
->data
.data_offset
,
1293 quirk
->data
.data_size
)) {
1294 hw_error("%s: window data write not fully contained: %s",
1295 __func__
, memory_region_name(&quirk
->mem
));
1298 vfio_pci_write_config(&vdev
->pdev
,
1299 quirk
->data
.address_val
+ offset
, data
, size
);
1300 trace_vfio_generic_window_quirk_write(memory_region_name(&quirk
->mem
),
1301 vdev
->vbasedev
.name
,
1307 vfio_region_write(&vdev
->bars
[quirk
->data
.bar
].region
,
1308 addr
+ quirk
->data
.base_offset
, data
, size
);
1311 static const MemoryRegionOps vfio_generic_window_quirk
= {
1312 .read
= vfio_generic_window_quirk_read
,
1313 .write
= vfio_generic_window_quirk_write
,
1314 .endianness
= DEVICE_LITTLE_ENDIAN
,
1317 static uint64_t vfio_generic_quirk_read(void *opaque
,
1318 hwaddr addr
, unsigned size
)
1320 VFIOQuirk
*quirk
= opaque
;
1321 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1322 hwaddr base
= quirk
->data
.address_match
& TARGET_PAGE_MASK
;
1323 hwaddr offset
= quirk
->data
.address_match
& ~TARGET_PAGE_MASK
;
1326 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.read_flags
) &&
1327 ranges_overlap(addr
, size
, offset
, quirk
->data
.address_mask
+ 1)) {
1328 if (!vfio_range_contained(addr
, size
, offset
,
1329 quirk
->data
.address_mask
+ 1)) {
1330 hw_error("%s: read not fully contained: %s",
1331 __func__
, memory_region_name(&quirk
->mem
));
1334 data
= vfio_pci_read_config(&vdev
->pdev
, addr
- offset
, size
);
1336 trace_vfio_generic_quirk_read(memory_region_name(&quirk
->mem
),
1337 vdev
->vbasedev
.name
, quirk
->data
.bar
,
1338 addr
+ base
, size
, data
);
1340 data
= vfio_region_read(&vdev
->bars
[quirk
->data
.bar
].region
,
1347 static void vfio_generic_quirk_write(void *opaque
, hwaddr addr
,
1348 uint64_t data
, unsigned size
)
1350 VFIOQuirk
*quirk
= opaque
;
1351 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1352 hwaddr base
= quirk
->data
.address_match
& TARGET_PAGE_MASK
;
1353 hwaddr offset
= quirk
->data
.address_match
& ~TARGET_PAGE_MASK
;
1355 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.write_flags
) &&
1356 ranges_overlap(addr
, size
, offset
, quirk
->data
.address_mask
+ 1)) {
1357 if (!vfio_range_contained(addr
, size
, offset
,
1358 quirk
->data
.address_mask
+ 1)) {
1359 hw_error("%s: write not fully contained: %s",
1360 __func__
, memory_region_name(&quirk
->mem
));
1363 vfio_pci_write_config(&vdev
->pdev
, addr
- offset
, data
, size
);
1365 trace_vfio_generic_quirk_write(memory_region_name(&quirk
->mem
),
1366 vdev
->vbasedev
.name
, quirk
->data
.bar
,
1367 addr
+ base
, data
, size
);
1369 vfio_region_write(&vdev
->bars
[quirk
->data
.bar
].region
,
1370 addr
+ base
, data
, size
);
1374 static const MemoryRegionOps vfio_generic_quirk
= {
1375 .read
= vfio_generic_quirk_read
,
1376 .write
= vfio_generic_quirk_write
,
1377 .endianness
= DEVICE_LITTLE_ENDIAN
,
1380 #define PCI_VENDOR_ID_ATI 0x1002
1383 * Radeon HD cards (HD5450 & HD7850) report the upper byte of the I/O port BAR
1384 * through VGA register 0x3c3. On newer cards, the I/O port BAR is always
1385 * BAR4 (older cards like the X550 used BAR1, but we don't care to support
1386 * those). Note that on bare metal, a read of 0x3c3 doesn't always return the
1387 * I/O port BAR address. Originally this was coded to return the virtual BAR
1388 * address only if the physical register read returns the actual BAR address,
1389 * but users have reported greater success if we return the virtual address
1392 static uint64_t vfio_ati_3c3_quirk_read(void *opaque
,
1393 hwaddr addr
, unsigned size
)
1395 VFIOQuirk
*quirk
= opaque
;
1396 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1397 uint64_t data
= vfio_pci_read_config(&vdev
->pdev
,
1398 PCI_BASE_ADDRESS_0
+ (4 * 4) + 1,
1400 trace_vfio_ati_3c3_quirk_read(data
);
1405 static const MemoryRegionOps vfio_ati_3c3_quirk
= {
1406 .read
= vfio_ati_3c3_quirk_read
,
1407 .endianness
= DEVICE_LITTLE_ENDIAN
,
1410 static void vfio_vga_probe_ati_3c3_quirk(VFIOPCIDevice
*vdev
)
1412 PCIDevice
*pdev
= &vdev
->pdev
;
1415 if (pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_ATI
) {
1420 * As long as the BAR is >= 256 bytes it will be aligned such that the
1421 * lower byte is always zero. Filter out anything else, if it exists.
1423 if (!vdev
->bars
[4].ioport
|| vdev
->bars
[4].region
.size
< 256) {
1427 quirk
= g_malloc0(sizeof(*quirk
));
1430 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_ati_3c3_quirk
, quirk
,
1431 "vfio-ati-3c3-quirk", 1);
1432 memory_region_add_subregion(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
,
1433 3 /* offset 3 bytes from 0x3c0 */, &quirk
->mem
);
1435 QLIST_INSERT_HEAD(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].quirks
,
1438 trace_vfio_vga_probe_ati_3c3_quirk(vdev
->vbasedev
.name
);
1442 * Newer ATI/AMD devices, including HD5450 and HD7850, have a window to PCI
1443 * config space through MMIO BAR2 at offset 0x4000. Nothing seems to access
1444 * the MMIO space directly, but a window to this space is provided through
1445 * I/O port BAR4. Offset 0x0 is the address register and offset 0x4 is the
1446 * data register. When the address is programmed to a range of 0x4000-0x4fff
1447 * PCI configuration space is available. Experimentation seems to indicate
1448 * that only read-only access is provided, but we drop writes when the window
1449 * is enabled to config space nonetheless.
1451 static void vfio_probe_ati_bar4_window_quirk(VFIOPCIDevice
*vdev
, int nr
)
1453 PCIDevice
*pdev
= &vdev
->pdev
;
1456 if (!vdev
->has_vga
|| nr
!= 4 ||
1457 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_ATI
) {
1461 quirk
= g_malloc0(sizeof(*quirk
));
1463 quirk
->data
.address_size
= 4;
1464 quirk
->data
.data_offset
= 4;
1465 quirk
->data
.data_size
= 4;
1466 quirk
->data
.address_match
= 0x4000;
1467 quirk
->data
.address_mask
= PCIE_CONFIG_SPACE_SIZE
- 1;
1468 quirk
->data
.bar
= nr
;
1469 quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1471 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
),
1472 &vfio_generic_window_quirk
, quirk
,
1473 "vfio-ati-bar4-window-quirk", 8);
1474 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].region
.mem
,
1475 quirk
->data
.base_offset
, &quirk
->mem
, 1);
1477 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1479 trace_vfio_probe_ati_bar4_window_quirk(vdev
->vbasedev
.name
);
1482 #define PCI_VENDOR_ID_REALTEK 0x10ec
1485 * RTL8168 devices have a backdoor that can access the MSI-X table. At BAR2
1486 * offset 0x70 there is a dword data register, offset 0x74 is a dword address
1487 * register. According to the Linux r8169 driver, the MSI-X table is addressed
1488 * when the "type" portion of the address register is set to 0x1. This appears
1489 * to be bits 16:30. Bit 31 is both a write indicator and some sort of
1490 * "address latched" indicator. Bits 12:15 are a mask field, which we can
1491 * ignore because the MSI-X table should always be accessed as a dword (full
1492 * mask). Bits 0:11 is offset within the type.
1496 * Read from MSI-X table offset 0
1497 * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x74, 0x1f000, 4) // store read addr
1498 * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x74, 4) = 0x8001f000 // latch
1499 * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x70, 4) = 0xfee00398 // read data
1501 * Write 0xfee00000 to MSI-X table offset 0
1502 * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x70, 0xfee00000, 4) // write data
1503 * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x74, 0x8001f000, 4) // do write
1504 * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x74, 4) = 0x1f000 // complete
1507 static uint64_t vfio_rtl8168_window_quirk_read(void *opaque
,
1508 hwaddr addr
, unsigned size
)
1510 VFIOQuirk
*quirk
= opaque
;
1511 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1514 case 4: /* address */
1515 if (quirk
->data
.flags
) {
1516 trace_vfio_rtl8168_window_quirk_read_fake(
1517 memory_region_name(&quirk
->mem
),
1518 vdev
->vbasedev
.name
);
1520 return quirk
->data
.address_match
^ 0x10000000U
;
1524 if (quirk
->data
.flags
) {
1527 trace_vfio_rtl8168_window_quirk_read_table(
1528 memory_region_name(&quirk
->mem
),
1529 vdev
->vbasedev
.name
);
1531 if (!(vdev
->pdev
.cap_present
& QEMU_PCI_CAP_MSIX
)) {
1535 memory_region_dispatch_read(&vdev
->pdev
.msix_table_mmio
,
1536 (hwaddr
)(quirk
->data
.address_match
1540 MEMTXATTRS_UNSPECIFIED
);
1545 trace_vfio_rtl8168_window_quirk_read_direct(memory_region_name(&quirk
->mem
),
1546 vdev
->vbasedev
.name
);
1548 return vfio_region_read(&vdev
->bars
[quirk
->data
.bar
].region
,
1552 static void vfio_rtl8168_window_quirk_write(void *opaque
, hwaddr addr
,
1553 uint64_t data
, unsigned size
)
1555 VFIOQuirk
*quirk
= opaque
;
1556 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1559 case 4: /* address */
1560 if ((data
& 0x7fff0000) == 0x10000) {
1561 if (data
& 0x10000000U
&&
1562 vdev
->pdev
.cap_present
& QEMU_PCI_CAP_MSIX
) {
1564 trace_vfio_rtl8168_window_quirk_write_table(
1565 memory_region_name(&quirk
->mem
),
1566 vdev
->vbasedev
.name
);
1568 memory_region_dispatch_write(&vdev
->pdev
.msix_table_mmio
,
1569 (hwaddr
)(quirk
->data
.address_match
1573 MEMTXATTRS_UNSPECIFIED
);
1576 quirk
->data
.flags
= 1;
1577 quirk
->data
.address_match
= data
;
1581 quirk
->data
.flags
= 0;
1584 quirk
->data
.address_mask
= data
;
1588 trace_vfio_rtl8168_window_quirk_write_direct(
1589 memory_region_name(&quirk
->mem
),
1590 vdev
->vbasedev
.name
);
1592 vfio_region_write(&vdev
->bars
[quirk
->data
.bar
].region
,
1593 addr
+ 0x70, data
, size
);
1596 static const MemoryRegionOps vfio_rtl8168_window_quirk
= {
1597 .read
= vfio_rtl8168_window_quirk_read
,
1598 .write
= vfio_rtl8168_window_quirk_write
,
1600 .min_access_size
= 4,
1601 .max_access_size
= 4,
1604 .endianness
= DEVICE_LITTLE_ENDIAN
,
1607 static void vfio_probe_rtl8168_bar2_window_quirk(VFIOPCIDevice
*vdev
, int nr
)
1609 PCIDevice
*pdev
= &vdev
->pdev
;
1612 if (pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_REALTEK
||
1613 pci_get_word(pdev
->config
+ PCI_DEVICE_ID
) != 0x8168 || nr
!= 2) {
1617 quirk
= g_malloc0(sizeof(*quirk
));
1619 quirk
->data
.bar
= nr
;
1621 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_rtl8168_window_quirk
,
1622 quirk
, "vfio-rtl8168-window-quirk", 8);
1623 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].region
.mem
,
1624 0x70, &quirk
->mem
, 1);
1626 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1628 trace_vfio_probe_rtl8168_bar2_window_quirk(vdev
->vbasedev
.name
);
1631 * Trap the BAR2 MMIO window to config space as well.
1633 static void vfio_probe_ati_bar2_4000_quirk(VFIOPCIDevice
*vdev
, int nr
)
1635 PCIDevice
*pdev
= &vdev
->pdev
;
1638 /* Only enable on newer devices where BAR2 is 64bit */
1639 if (!vdev
->has_vga
|| nr
!= 2 || !vdev
->bars
[2].mem64
||
1640 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_ATI
) {
1644 quirk
= g_malloc0(sizeof(*quirk
));
1646 quirk
->data
.flags
= quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1647 quirk
->data
.address_match
= 0x4000;
1648 quirk
->data
.address_mask
= PCIE_CONFIG_SPACE_SIZE
- 1;
1649 quirk
->data
.bar
= nr
;
1651 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_generic_quirk
, quirk
,
1652 "vfio-ati-bar2-4000-quirk",
1653 TARGET_PAGE_ALIGN(quirk
->data
.address_mask
+ 1));
1654 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].region
.mem
,
1655 quirk
->data
.address_match
& TARGET_PAGE_MASK
,
1658 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1660 trace_vfio_probe_ati_bar2_4000_quirk(vdev
->vbasedev
.name
);
1664 * Older ATI/AMD cards like the X550 have a similar window to that above.
1665 * I/O port BAR1 provides a window to a mirror of PCI config space located
1666 * in BAR2 at offset 0xf00. We don't care to support such older cards, but
1667 * note it for future reference.
1670 #define PCI_VENDOR_ID_NVIDIA 0x10de
1673 * Nvidia has several different methods to get to config space, the
1674 * nouveu project has several of these documented here:
1675 * https://github.com/pathscale/envytools/tree/master/hwdocs
1677 * The first quirk is actually not documented in envytools and is found
1678 * on 10de:01d1 (NVIDIA Corporation G72 [GeForce 7300 LE]). This is an
1679 * NV46 chipset. The backdoor uses the legacy VGA I/O ports to access
1680 * the mirror of PCI config space found at BAR0 offset 0x1800. The access
1681 * sequence first writes 0x338 to I/O port 0x3d4. The target offset is
1682 * then written to 0x3d0. Finally 0x538 is written for a read and 0x738
1683 * is written for a write to 0x3d4. The BAR0 offset is then accessible
1684 * through 0x3d0. This quirk doesn't seem to be necessary on newer cards
1685 * that use the I/O port BAR5 window but it doesn't hurt to leave it.
1695 static uint64_t vfio_nvidia_3d0_quirk_read(void *opaque
,
1696 hwaddr addr
, unsigned size
)
1698 VFIOQuirk
*quirk
= opaque
;
1699 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1700 PCIDevice
*pdev
= &vdev
->pdev
;
1701 uint64_t data
= vfio_vga_read(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
],
1702 addr
+ quirk
->data
.base_offset
, size
);
1704 if (quirk
->data
.flags
== NV_3D0_READ
&& addr
== quirk
->data
.data_offset
) {
1705 data
= vfio_pci_read_config(pdev
, quirk
->data
.address_val
, size
);
1706 trace_vfio_nvidia_3d0_quirk_read(size
, data
);
1709 quirk
->data
.flags
= NV_3D0_NONE
;
1714 static void vfio_nvidia_3d0_quirk_write(void *opaque
, hwaddr addr
,
1715 uint64_t data
, unsigned size
)
1717 VFIOQuirk
*quirk
= opaque
;
1718 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1719 PCIDevice
*pdev
= &vdev
->pdev
;
1721 switch (quirk
->data
.flags
) {
1723 if (addr
== quirk
->data
.address_offset
&& data
== 0x338) {
1724 quirk
->data
.flags
= NV_3D0_SELECT
;
1728 quirk
->data
.flags
= NV_3D0_NONE
;
1729 if (addr
== quirk
->data
.data_offset
&&
1730 (data
& ~quirk
->data
.address_mask
) == quirk
->data
.address_match
) {
1731 quirk
->data
.flags
= NV_3D0_WINDOW
;
1732 quirk
->data
.address_val
= data
& quirk
->data
.address_mask
;
1736 quirk
->data
.flags
= NV_3D0_NONE
;
1737 if (addr
== quirk
->data
.address_offset
) {
1738 if (data
== 0x538) {
1739 quirk
->data
.flags
= NV_3D0_READ
;
1740 } else if (data
== 0x738) {
1741 quirk
->data
.flags
= NV_3D0_WRITE
;
1746 quirk
->data
.flags
= NV_3D0_NONE
;
1747 if (addr
== quirk
->data
.data_offset
) {
1748 vfio_pci_write_config(pdev
, quirk
->data
.address_val
, data
, size
);
1749 trace_vfio_nvidia_3d0_quirk_write(data
, size
);
1755 vfio_vga_write(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
],
1756 addr
+ quirk
->data
.base_offset
, data
, size
);
1759 static const MemoryRegionOps vfio_nvidia_3d0_quirk
= {
1760 .read
= vfio_nvidia_3d0_quirk_read
,
1761 .write
= vfio_nvidia_3d0_quirk_write
,
1762 .endianness
= DEVICE_LITTLE_ENDIAN
,
1765 static void vfio_vga_probe_nvidia_3d0_quirk(VFIOPCIDevice
*vdev
)
1767 PCIDevice
*pdev
= &vdev
->pdev
;
1770 if (pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
||
1771 !vdev
->bars
[1].region
.size
) {
1775 quirk
= g_malloc0(sizeof(*quirk
));
1777 quirk
->data
.base_offset
= 0x10;
1778 quirk
->data
.address_offset
= 4;
1779 quirk
->data
.address_size
= 2;
1780 quirk
->data
.address_match
= 0x1800;
1781 quirk
->data
.address_mask
= PCI_CONFIG_SPACE_SIZE
- 1;
1782 quirk
->data
.data_offset
= 0;
1783 quirk
->data
.data_size
= 4;
1785 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_nvidia_3d0_quirk
,
1786 quirk
, "vfio-nvidia-3d0-quirk", 6);
1787 memory_region_add_subregion(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
,
1788 quirk
->data
.base_offset
, &quirk
->mem
);
1790 QLIST_INSERT_HEAD(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].quirks
,
1793 trace_vfio_vga_probe_nvidia_3d0_quirk(vdev
->vbasedev
.name
);
1797 * The second quirk is documented in envytools. The I/O port BAR5 is just
1798 * a set of address/data ports to the MMIO BARs. The BAR we care about is
1799 * again BAR0. This backdoor is apparently a bit newer than the one above
1800 * so we need to not only trap 256 bytes @0x1800, but all of PCI config
1801 * space, including extended space is available at the 4k @0x88000.
1804 NV_BAR5_ADDRESS
= 0x1,
1805 NV_BAR5_ENABLE
= 0x2,
1806 NV_BAR5_MASTER
= 0x4,
1807 NV_BAR5_VALID
= 0x7,
1810 static void vfio_nvidia_bar5_window_quirk_write(void *opaque
, hwaddr addr
,
1811 uint64_t data
, unsigned size
)
1813 VFIOQuirk
*quirk
= opaque
;
1818 quirk
->data
.flags
|= NV_BAR5_MASTER
;
1820 quirk
->data
.flags
&= ~NV_BAR5_MASTER
;
1825 quirk
->data
.flags
|= NV_BAR5_ENABLE
;
1827 quirk
->data
.flags
&= ~NV_BAR5_ENABLE
;
1831 if (quirk
->data
.flags
& NV_BAR5_MASTER
) {
1832 if ((data
& ~0xfff) == 0x88000) {
1833 quirk
->data
.flags
|= NV_BAR5_ADDRESS
;
1834 quirk
->data
.address_val
= data
& 0xfff;
1835 } else if ((data
& ~0xff) == 0x1800) {
1836 quirk
->data
.flags
|= NV_BAR5_ADDRESS
;
1837 quirk
->data
.address_val
= data
& 0xff;
1839 quirk
->data
.flags
&= ~NV_BAR5_ADDRESS
;
1845 vfio_generic_window_quirk_write(opaque
, addr
, data
, size
);
1848 static const MemoryRegionOps vfio_nvidia_bar5_window_quirk
= {
1849 .read
= vfio_generic_window_quirk_read
,
1850 .write
= vfio_nvidia_bar5_window_quirk_write
,
1851 .valid
.min_access_size
= 4,
1852 .endianness
= DEVICE_LITTLE_ENDIAN
,
1855 static void vfio_probe_nvidia_bar5_window_quirk(VFIOPCIDevice
*vdev
, int nr
)
1857 PCIDevice
*pdev
= &vdev
->pdev
;
1860 if (!vdev
->has_vga
|| nr
!= 5 ||
1861 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
) {
1865 quirk
= g_malloc0(sizeof(*quirk
));
1867 quirk
->data
.read_flags
= quirk
->data
.write_flags
= NV_BAR5_VALID
;
1868 quirk
->data
.address_offset
= 0x8;
1869 quirk
->data
.address_size
= 0; /* actually 4, but avoids generic code */
1870 quirk
->data
.data_offset
= 0xc;
1871 quirk
->data
.data_size
= 4;
1872 quirk
->data
.bar
= nr
;
1874 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
),
1875 &vfio_nvidia_bar5_window_quirk
, quirk
,
1876 "vfio-nvidia-bar5-window-quirk", 16);
1877 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].region
.mem
,
1880 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1882 trace_vfio_probe_nvidia_bar5_window_quirk(vdev
->vbasedev
.name
);
1885 static void vfio_nvidia_88000_quirk_write(void *opaque
, hwaddr addr
,
1886 uint64_t data
, unsigned size
)
1888 VFIOQuirk
*quirk
= opaque
;
1889 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1890 PCIDevice
*pdev
= &vdev
->pdev
;
1891 hwaddr base
= quirk
->data
.address_match
& TARGET_PAGE_MASK
;
1893 vfio_generic_quirk_write(opaque
, addr
, data
, size
);
1896 * Nvidia seems to acknowledge MSI interrupts by writing 0xff to the
1897 * MSI capability ID register. Both the ID and next register are
1898 * read-only, so we allow writes covering either of those to real hw.
1899 * NB - only fixed for the 0x88000 MMIO window.
1901 if ((pdev
->cap_present
& QEMU_PCI_CAP_MSI
) &&
1902 vfio_range_contained(addr
, size
, pdev
->msi_cap
, PCI_MSI_FLAGS
)) {
1903 vfio_region_write(&vdev
->bars
[quirk
->data
.bar
].region
,
1904 addr
+ base
, data
, size
);
1908 static const MemoryRegionOps vfio_nvidia_88000_quirk
= {
1909 .read
= vfio_generic_quirk_read
,
1910 .write
= vfio_nvidia_88000_quirk_write
,
1911 .endianness
= DEVICE_LITTLE_ENDIAN
,
1915 * Finally, BAR0 itself. We want to redirect any accesses to either
1916 * 0x1800 or 0x88000 through the PCI config space access functions.
1918 * NB - quirk at a page granularity or else they don't seem to work when
1921 * Here's offset 0x88000...
1923 static void vfio_probe_nvidia_bar0_88000_quirk(VFIOPCIDevice
*vdev
, int nr
)
1925 PCIDevice
*pdev
= &vdev
->pdev
;
1927 uint16_t vendor
, class;
1929 vendor
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1930 class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1932 if (nr
!= 0 || vendor
!= PCI_VENDOR_ID_NVIDIA
||
1933 class != PCI_CLASS_DISPLAY_VGA
) {
1937 quirk
= g_malloc0(sizeof(*quirk
));
1939 quirk
->data
.flags
= quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1940 quirk
->data
.address_match
= 0x88000;
1941 quirk
->data
.address_mask
= PCIE_CONFIG_SPACE_SIZE
- 1;
1942 quirk
->data
.bar
= nr
;
1944 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_nvidia_88000_quirk
,
1945 quirk
, "vfio-nvidia-bar0-88000-quirk",
1946 TARGET_PAGE_ALIGN(quirk
->data
.address_mask
+ 1));
1947 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].region
.mem
,
1948 quirk
->data
.address_match
& TARGET_PAGE_MASK
,
1951 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1953 trace_vfio_probe_nvidia_bar0_88000_quirk(vdev
->vbasedev
.name
);
1957 * And here's the same for BAR0 offset 0x1800...
1959 static void vfio_probe_nvidia_bar0_1800_quirk(VFIOPCIDevice
*vdev
, int nr
)
1961 PCIDevice
*pdev
= &vdev
->pdev
;
1964 if (!vdev
->has_vga
|| nr
!= 0 ||
1965 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
) {
1969 /* Log the chipset ID */
1970 trace_vfio_probe_nvidia_bar0_1800_quirk_id(
1971 (unsigned int)(vfio_region_read(&vdev
->bars
[0].region
, 0, 4) >> 20)
1974 quirk
= g_malloc0(sizeof(*quirk
));
1976 quirk
->data
.flags
= quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1977 quirk
->data
.address_match
= 0x1800;
1978 quirk
->data
.address_mask
= PCI_CONFIG_SPACE_SIZE
- 1;
1979 quirk
->data
.bar
= nr
;
1981 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_generic_quirk
, quirk
,
1982 "vfio-nvidia-bar0-1800-quirk",
1983 TARGET_PAGE_ALIGN(quirk
->data
.address_mask
+ 1));
1984 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].region
.mem
,
1985 quirk
->data
.address_match
& TARGET_PAGE_MASK
,
1988 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1990 trace_vfio_probe_nvidia_bar0_1800_quirk(vdev
->vbasedev
.name
);
1994 * TODO - Some Nvidia devices provide config access to their companion HDA
1995 * device and even to their parent bridge via these config space mirrors.
1996 * Add quirks for those regions.
2000 * Common quirk probe entry points.
2002 static void vfio_vga_quirk_setup(VFIOPCIDevice
*vdev
)
2004 vfio_vga_probe_ati_3c3_quirk(vdev
);
2005 vfio_vga_probe_nvidia_3d0_quirk(vdev
);
2008 static void vfio_vga_quirk_teardown(VFIOPCIDevice
*vdev
)
2013 for (i
= 0; i
< ARRAY_SIZE(vdev
->vga
.region
); i
++) {
2014 QLIST_FOREACH(quirk
, &vdev
->vga
.region
[i
].quirks
, next
) {
2015 memory_region_del_subregion(&vdev
->vga
.region
[i
].mem
, &quirk
->mem
);
2020 static void vfio_vga_quirk_free(VFIOPCIDevice
*vdev
)
2024 for (i
= 0; i
< ARRAY_SIZE(vdev
->vga
.region
); i
++) {
2025 while (!QLIST_EMPTY(&vdev
->vga
.region
[i
].quirks
)) {
2026 VFIOQuirk
*quirk
= QLIST_FIRST(&vdev
->vga
.region
[i
].quirks
);
2027 object_unparent(OBJECT(&quirk
->mem
));
2028 QLIST_REMOVE(quirk
, next
);
2034 static void vfio_bar_quirk_setup(VFIOPCIDevice
*vdev
, int nr
)
2036 vfio_probe_ati_bar4_window_quirk(vdev
, nr
);
2037 vfio_probe_ati_bar2_4000_quirk(vdev
, nr
);
2038 vfio_probe_nvidia_bar5_window_quirk(vdev
, nr
);
2039 vfio_probe_nvidia_bar0_88000_quirk(vdev
, nr
);
2040 vfio_probe_nvidia_bar0_1800_quirk(vdev
, nr
);
2041 vfio_probe_rtl8168_bar2_window_quirk(vdev
, nr
);
2044 static void vfio_bar_quirk_teardown(VFIOPCIDevice
*vdev
, int nr
)
2046 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2049 QLIST_FOREACH(quirk
, &bar
->quirks
, next
) {
2050 memory_region_del_subregion(&bar
->region
.mem
, &quirk
->mem
);
2054 static void vfio_bar_quirk_free(VFIOPCIDevice
*vdev
, int nr
)
2056 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2058 while (!QLIST_EMPTY(&bar
->quirks
)) {
2059 VFIOQuirk
*quirk
= QLIST_FIRST(&bar
->quirks
);
2060 object_unparent(OBJECT(&quirk
->mem
));
2061 QLIST_REMOVE(quirk
, next
);
2069 static uint32_t vfio_pci_read_config(PCIDevice
*pdev
, uint32_t addr
, int len
)
2071 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
2072 uint32_t emu_bits
= 0, emu_val
= 0, phys_val
= 0, val
;
2074 memcpy(&emu_bits
, vdev
->emulated_config_bits
+ addr
, len
);
2075 emu_bits
= le32_to_cpu(emu_bits
);
2078 emu_val
= pci_default_read_config(pdev
, addr
, len
);
2081 if (~emu_bits
& (0xffffffffU
>> (32 - len
* 8))) {
2084 ret
= pread(vdev
->vbasedev
.fd
, &phys_val
, len
,
2085 vdev
->config_offset
+ addr
);
2087 error_report("%s(%04x:%02x:%02x.%x, 0x%x, 0x%x) failed: %m",
2088 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
2089 vdev
->host
.slot
, vdev
->host
.function
, addr
, len
);
2092 phys_val
= le32_to_cpu(phys_val
);
2095 val
= (emu_val
& emu_bits
) | (phys_val
& ~emu_bits
);
2097 trace_vfio_pci_read_config(vdev
->vbasedev
.name
, addr
, len
, val
);
2102 static void vfio_pci_write_config(PCIDevice
*pdev
, uint32_t addr
,
2103 uint32_t val
, int len
)
2105 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
2106 uint32_t val_le
= cpu_to_le32(val
);
2108 trace_vfio_pci_write_config(vdev
->vbasedev
.name
, addr
, val
, len
);
2110 /* Write everything to VFIO, let it filter out what we can't write */
2111 if (pwrite(vdev
->vbasedev
.fd
, &val_le
, len
, vdev
->config_offset
+ addr
)
2113 error_report("%s(%04x:%02x:%02x.%x, 0x%x, 0x%x, 0x%x) failed: %m",
2114 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
2115 vdev
->host
.slot
, vdev
->host
.function
, addr
, val
, len
);
2118 /* MSI/MSI-X Enabling/Disabling */
2119 if (pdev
->cap_present
& QEMU_PCI_CAP_MSI
&&
2120 ranges_overlap(addr
, len
, pdev
->msi_cap
, vdev
->msi_cap_size
)) {
2121 int is_enabled
, was_enabled
= msi_enabled(pdev
);
2123 pci_default_write_config(pdev
, addr
, val
, len
);
2125 is_enabled
= msi_enabled(pdev
);
2129 vfio_enable_msi(vdev
);
2133 vfio_disable_msi(vdev
);
2135 vfio_update_msi(vdev
);
2138 } else if (pdev
->cap_present
& QEMU_PCI_CAP_MSIX
&&
2139 ranges_overlap(addr
, len
, pdev
->msix_cap
, MSIX_CAP_LENGTH
)) {
2140 int is_enabled
, was_enabled
= msix_enabled(pdev
);
2142 pci_default_write_config(pdev
, addr
, val
, len
);
2144 is_enabled
= msix_enabled(pdev
);
2146 if (!was_enabled
&& is_enabled
) {
2147 vfio_enable_msix(vdev
);
2148 } else if (was_enabled
&& !is_enabled
) {
2149 vfio_disable_msix(vdev
);
2152 /* Write everything to QEMU to keep emulated bits correct */
2153 pci_default_write_config(pdev
, addr
, val
, len
);
2160 static void vfio_disable_interrupts(VFIOPCIDevice
*vdev
)
2163 * More complicated than it looks. Disabling MSI/X transitions the
2164 * device to INTx mode (if supported). Therefore we need to first
2165 * disable MSI/X and then cleanup by disabling INTx.
2167 if (vdev
->interrupt
== VFIO_INT_MSIX
) {
2168 vfio_disable_msix(vdev
);
2169 } else if (vdev
->interrupt
== VFIO_INT_MSI
) {
2170 vfio_disable_msi(vdev
);
2173 if (vdev
->interrupt
== VFIO_INT_INTx
) {
2174 vfio_disable_intx(vdev
);
2178 static int vfio_setup_msi(VFIOPCIDevice
*vdev
, int pos
)
2181 bool msi_64bit
, msi_maskbit
;
2184 if (pread(vdev
->vbasedev
.fd
, &ctrl
, sizeof(ctrl
),
2185 vdev
->config_offset
+ pos
+ PCI_CAP_FLAGS
) != sizeof(ctrl
)) {
2188 ctrl
= le16_to_cpu(ctrl
);
2190 msi_64bit
= !!(ctrl
& PCI_MSI_FLAGS_64BIT
);
2191 msi_maskbit
= !!(ctrl
& PCI_MSI_FLAGS_MASKBIT
);
2192 entries
= 1 << ((ctrl
& PCI_MSI_FLAGS_QMASK
) >> 1);
2194 trace_vfio_setup_msi(vdev
->vbasedev
.name
, pos
);
2196 ret
= msi_init(&vdev
->pdev
, pos
, entries
, msi_64bit
, msi_maskbit
);
2198 if (ret
== -ENOTSUP
) {
2201 error_report("vfio: msi_init failed");
2204 vdev
->msi_cap_size
= 0xa + (msi_maskbit
? 0xa : 0) + (msi_64bit
? 0x4 : 0);
2210 * We don't have any control over how pci_add_capability() inserts
2211 * capabilities into the chain. In order to setup MSI-X we need a
2212 * MemoryRegion for the BAR. In order to setup the BAR and not
2213 * attempt to mmap the MSI-X table area, which VFIO won't allow, we
2214 * need to first look for where the MSI-X table lives. So we
2215 * unfortunately split MSI-X setup across two functions.
2217 static int vfio_early_setup_msix(VFIOPCIDevice
*vdev
)
2221 uint32_t table
, pba
;
2222 int fd
= vdev
->vbasedev
.fd
;
2224 pos
= pci_find_capability(&vdev
->pdev
, PCI_CAP_ID_MSIX
);
2229 if (pread(fd
, &ctrl
, sizeof(ctrl
),
2230 vdev
->config_offset
+ pos
+ PCI_CAP_FLAGS
) != sizeof(ctrl
)) {
2234 if (pread(fd
, &table
, sizeof(table
),
2235 vdev
->config_offset
+ pos
+ PCI_MSIX_TABLE
) != sizeof(table
)) {
2239 if (pread(fd
, &pba
, sizeof(pba
),
2240 vdev
->config_offset
+ pos
+ PCI_MSIX_PBA
) != sizeof(pba
)) {
2244 ctrl
= le16_to_cpu(ctrl
);
2245 table
= le32_to_cpu(table
);
2246 pba
= le32_to_cpu(pba
);
2248 vdev
->msix
= g_malloc0(sizeof(*(vdev
->msix
)));
2249 vdev
->msix
->table_bar
= table
& PCI_MSIX_FLAGS_BIRMASK
;
2250 vdev
->msix
->table_offset
= table
& ~PCI_MSIX_FLAGS_BIRMASK
;
2251 vdev
->msix
->pba_bar
= pba
& PCI_MSIX_FLAGS_BIRMASK
;
2252 vdev
->msix
->pba_offset
= pba
& ~PCI_MSIX_FLAGS_BIRMASK
;
2253 vdev
->msix
->entries
= (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
2256 * Test the size of the pba_offset variable and catch if it extends outside
2257 * of the specified BAR. If it is the case, we need to apply a hardware
2258 * specific quirk if the device is known or we have a broken configuration.
2260 if (vdev
->msix
->pba_offset
>=
2261 vdev
->bars
[vdev
->msix
->pba_bar
].region
.size
) {
2263 PCIDevice
*pdev
= &vdev
->pdev
;
2264 uint16_t vendor
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
2265 uint16_t device
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
2268 * Chelsio T5 Virtual Function devices are encoded as 0x58xx for T5
2269 * adapters. The T5 hardware returns an incorrect value of 0x8000 for
2270 * the VF PBA offset while the BAR itself is only 8k. The correct value
2271 * is 0x1000, so we hard code that here.
2273 if (vendor
== PCI_VENDOR_ID_CHELSIO
&& (device
& 0xff00) == 0x5800) {
2274 vdev
->msix
->pba_offset
= 0x1000;
2276 error_report("vfio: Hardware reports invalid configuration, "
2277 "MSIX PBA outside of specified BAR");
2282 trace_vfio_early_setup_msix(vdev
->vbasedev
.name
, pos
,
2283 vdev
->msix
->table_bar
,
2284 vdev
->msix
->table_offset
,
2285 vdev
->msix
->entries
);
2290 static int vfio_setup_msix(VFIOPCIDevice
*vdev
, int pos
)
2294 ret
= msix_init(&vdev
->pdev
, vdev
->msix
->entries
,
2295 &vdev
->bars
[vdev
->msix
->table_bar
].region
.mem
,
2296 vdev
->msix
->table_bar
, vdev
->msix
->table_offset
,
2297 &vdev
->bars
[vdev
->msix
->pba_bar
].region
.mem
,
2298 vdev
->msix
->pba_bar
, vdev
->msix
->pba_offset
, pos
);
2300 if (ret
== -ENOTSUP
) {
2303 error_report("vfio: msix_init failed");
2310 static void vfio_teardown_msi(VFIOPCIDevice
*vdev
)
2312 msi_uninit(&vdev
->pdev
);
2315 msix_uninit(&vdev
->pdev
,
2316 &vdev
->bars
[vdev
->msix
->table_bar
].region
.mem
,
2317 &vdev
->bars
[vdev
->msix
->pba_bar
].region
.mem
);
2324 static void vfio_mmap_set_enabled(VFIOPCIDevice
*vdev
, bool enabled
)
2328 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2329 VFIOBAR
*bar
= &vdev
->bars
[i
];
2331 if (!bar
->region
.size
) {
2335 memory_region_set_enabled(&bar
->region
.mmap_mem
, enabled
);
2336 if (vdev
->msix
&& vdev
->msix
->table_bar
== i
) {
2337 memory_region_set_enabled(&vdev
->msix
->mmap_mem
, enabled
);
2342 static void vfio_unregister_bar(VFIOPCIDevice
*vdev
, int nr
)
2344 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2346 if (!bar
->region
.size
) {
2350 vfio_bar_quirk_teardown(vdev
, nr
);
2352 memory_region_del_subregion(&bar
->region
.mem
, &bar
->region
.mmap_mem
);
2354 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2355 memory_region_del_subregion(&bar
->region
.mem
, &vdev
->msix
->mmap_mem
);
2359 static void vfio_unmap_bar(VFIOPCIDevice
*vdev
, int nr
)
2361 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2363 if (!bar
->region
.size
) {
2367 vfio_bar_quirk_free(vdev
, nr
);
2369 munmap(bar
->region
.mmap
, memory_region_size(&bar
->region
.mmap_mem
));
2371 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2372 munmap(vdev
->msix
->mmap
, memory_region_size(&vdev
->msix
->mmap_mem
));
2376 static void vfio_map_bar(VFIOPCIDevice
*vdev
, int nr
)
2378 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2379 uint64_t size
= bar
->region
.size
;
2385 /* Skip both unimplemented BARs and the upper half of 64bit BARS. */
2390 snprintf(name
, sizeof(name
), "VFIO %04x:%02x:%02x.%x BAR %d",
2391 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
2392 vdev
->host
.function
, nr
);
2394 /* Determine what type of BAR this is for registration */
2395 ret
= pread(vdev
->vbasedev
.fd
, &pci_bar
, sizeof(pci_bar
),
2396 vdev
->config_offset
+ PCI_BASE_ADDRESS_0
+ (4 * nr
));
2397 if (ret
!= sizeof(pci_bar
)) {
2398 error_report("vfio: Failed to read BAR %d (%m)", nr
);
2402 pci_bar
= le32_to_cpu(pci_bar
);
2403 bar
->ioport
= (pci_bar
& PCI_BASE_ADDRESS_SPACE_IO
);
2404 bar
->mem64
= bar
->ioport
? 0 : (pci_bar
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
2405 type
= pci_bar
& (bar
->ioport
? ~PCI_BASE_ADDRESS_IO_MASK
:
2406 ~PCI_BASE_ADDRESS_MEM_MASK
);
2408 /* A "slow" read/write mapping underlies all BARs */
2409 memory_region_init_io(&bar
->region
.mem
, OBJECT(vdev
), &vfio_region_ops
,
2411 pci_register_bar(&vdev
->pdev
, nr
, type
, &bar
->region
.mem
);
2414 * We can't mmap areas overlapping the MSIX vector table, so we
2415 * potentially insert a direct-mapped subregion before and after it.
2417 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2418 size
= vdev
->msix
->table_offset
& qemu_real_host_page_mask
;
2421 strncat(name
, " mmap", sizeof(name
) - strlen(name
) - 1);
2422 if (vfio_mmap_region(OBJECT(vdev
), &bar
->region
, &bar
->region
.mem
,
2423 &bar
->region
.mmap_mem
, &bar
->region
.mmap
,
2425 error_report("%s unsupported. Performance may be slow", name
);
2428 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2431 start
= REAL_HOST_PAGE_ALIGN((uint64_t)vdev
->msix
->table_offset
+
2432 (vdev
->msix
->entries
*
2433 PCI_MSIX_ENTRY_SIZE
));
2435 size
= start
< bar
->region
.size
? bar
->region
.size
- start
: 0;
2436 strncat(name
, " msix-hi", sizeof(name
) - strlen(name
) - 1);
2437 /* VFIOMSIXInfo contains another MemoryRegion for this mapping */
2438 if (vfio_mmap_region(OBJECT(vdev
), &bar
->region
, &bar
->region
.mem
,
2439 &vdev
->msix
->mmap_mem
,
2440 &vdev
->msix
->mmap
, size
, start
, name
)) {
2441 error_report("%s unsupported. Performance may be slow", name
);
2445 vfio_bar_quirk_setup(vdev
, nr
);
2448 static void vfio_map_bars(VFIOPCIDevice
*vdev
)
2452 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2453 vfio_map_bar(vdev
, i
);
2456 if (vdev
->has_vga
) {
2457 memory_region_init_io(&vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].mem
,
2458 OBJECT(vdev
), &vfio_vga_ops
,
2459 &vdev
->vga
.region
[QEMU_PCI_VGA_MEM
],
2460 "vfio-vga-mmio@0xa0000",
2461 QEMU_PCI_VGA_MEM_SIZE
);
2462 memory_region_init_io(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].mem
,
2463 OBJECT(vdev
), &vfio_vga_ops
,
2464 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
],
2465 "vfio-vga-io@0x3b0",
2466 QEMU_PCI_VGA_IO_LO_SIZE
);
2467 memory_region_init_io(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
,
2468 OBJECT(vdev
), &vfio_vga_ops
,
2469 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
],
2470 "vfio-vga-io@0x3c0",
2471 QEMU_PCI_VGA_IO_HI_SIZE
);
2473 pci_register_vga(&vdev
->pdev
, &vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].mem
,
2474 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].mem
,
2475 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
);
2476 vfio_vga_quirk_setup(vdev
);
2480 static void vfio_unregister_bars(VFIOPCIDevice
*vdev
)
2484 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2485 vfio_unregister_bar(vdev
, i
);
2488 if (vdev
->has_vga
) {
2489 vfio_vga_quirk_teardown(vdev
);
2490 pci_unregister_vga(&vdev
->pdev
);
2494 static void vfio_unmap_bars(VFIOPCIDevice
*vdev
)
2498 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2499 vfio_unmap_bar(vdev
, i
);
2502 if (vdev
->has_vga
) {
2503 vfio_vga_quirk_free(vdev
);
2510 static uint8_t vfio_std_cap_max_size(PCIDevice
*pdev
, uint8_t pos
)
2512 uint8_t tmp
, next
= 0xff;
2514 for (tmp
= pdev
->config
[PCI_CAPABILITY_LIST
]; tmp
;
2515 tmp
= pdev
->config
[tmp
+ 1]) {
2516 if (tmp
> pos
&& tmp
< next
) {
2524 static void vfio_set_word_bits(uint8_t *buf
, uint16_t val
, uint16_t mask
)
2526 pci_set_word(buf
, (pci_get_word(buf
) & ~mask
) | val
);
2529 static void vfio_add_emulated_word(VFIOPCIDevice
*vdev
, int pos
,
2530 uint16_t val
, uint16_t mask
)
2532 vfio_set_word_bits(vdev
->pdev
.config
+ pos
, val
, mask
);
2533 vfio_set_word_bits(vdev
->pdev
.wmask
+ pos
, ~mask
, mask
);
2534 vfio_set_word_bits(vdev
->emulated_config_bits
+ pos
, mask
, mask
);
2537 static void vfio_set_long_bits(uint8_t *buf
, uint32_t val
, uint32_t mask
)
2539 pci_set_long(buf
, (pci_get_long(buf
) & ~mask
) | val
);
2542 static void vfio_add_emulated_long(VFIOPCIDevice
*vdev
, int pos
,
2543 uint32_t val
, uint32_t mask
)
2545 vfio_set_long_bits(vdev
->pdev
.config
+ pos
, val
, mask
);
2546 vfio_set_long_bits(vdev
->pdev
.wmask
+ pos
, ~mask
, mask
);
2547 vfio_set_long_bits(vdev
->emulated_config_bits
+ pos
, mask
, mask
);
2550 static int vfio_setup_pcie_cap(VFIOPCIDevice
*vdev
, int pos
, uint8_t size
)
2555 flags
= pci_get_word(vdev
->pdev
.config
+ pos
+ PCI_CAP_FLAGS
);
2556 type
= (flags
& PCI_EXP_FLAGS_TYPE
) >> 4;
2558 if (type
!= PCI_EXP_TYPE_ENDPOINT
&&
2559 type
!= PCI_EXP_TYPE_LEG_END
&&
2560 type
!= PCI_EXP_TYPE_RC_END
) {
2562 error_report("vfio: Assignment of PCIe type 0x%x "
2563 "devices is not currently supported", type
);
2567 if (!pci_bus_is_express(vdev
->pdev
.bus
)) {
2569 * Use express capability as-is on PCI bus. It doesn't make much
2570 * sense to even expose, but some drivers (ex. tg3) depend on it
2571 * and guests don't seem to be particular about it. We'll need
2572 * to revist this or force express devices to express buses if we
2573 * ever expose an IOMMU to the guest.
2575 } else if (pci_bus_is_root(vdev
->pdev
.bus
)) {
2577 * On a Root Complex bus Endpoints become Root Complex Integrated
2578 * Endpoints, which changes the type and clears the LNK & LNK2 fields.
2580 if (type
== PCI_EXP_TYPE_ENDPOINT
) {
2581 vfio_add_emulated_word(vdev
, pos
+ PCI_CAP_FLAGS
,
2582 PCI_EXP_TYPE_RC_END
<< 4,
2583 PCI_EXP_FLAGS_TYPE
);
2585 /* Link Capabilities, Status, and Control goes away */
2586 if (size
> PCI_EXP_LNKCTL
) {
2587 vfio_add_emulated_long(vdev
, pos
+ PCI_EXP_LNKCAP
, 0, ~0);
2588 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKCTL
, 0, ~0);
2589 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKSTA
, 0, ~0);
2591 #ifndef PCI_EXP_LNKCAP2
2592 #define PCI_EXP_LNKCAP2 44
2594 #ifndef PCI_EXP_LNKSTA2
2595 #define PCI_EXP_LNKSTA2 50
2597 /* Link 2 Capabilities, Status, and Control goes away */
2598 if (size
> PCI_EXP_LNKCAP2
) {
2599 vfio_add_emulated_long(vdev
, pos
+ PCI_EXP_LNKCAP2
, 0, ~0);
2600 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKCTL2
, 0, ~0);
2601 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKSTA2
, 0, ~0);
2605 } else if (type
== PCI_EXP_TYPE_LEG_END
) {
2607 * Legacy endpoints don't belong on the root complex. Windows
2608 * seems to be happier with devices if we skip the capability.
2615 * Convert Root Complex Integrated Endpoints to regular endpoints.
2616 * These devices don't support LNK/LNK2 capabilities, so make them up.
2618 if (type
== PCI_EXP_TYPE_RC_END
) {
2619 vfio_add_emulated_word(vdev
, pos
+ PCI_CAP_FLAGS
,
2620 PCI_EXP_TYPE_ENDPOINT
<< 4,
2621 PCI_EXP_FLAGS_TYPE
);
2622 vfio_add_emulated_long(vdev
, pos
+ PCI_EXP_LNKCAP
,
2623 PCI_EXP_LNK_MLW_1
| PCI_EXP_LNK_LS_25
, ~0);
2624 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKCTL
, 0, ~0);
2627 /* Mark the Link Status bits as emulated to allow virtual negotiation */
2628 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKSTA
,
2629 pci_get_word(vdev
->pdev
.config
+ pos
+
2631 PCI_EXP_LNKCAP_MLW
| PCI_EXP_LNKCAP_SLS
);
2634 pos
= pci_add_capability(&vdev
->pdev
, PCI_CAP_ID_EXP
, pos
, size
);
2636 vdev
->pdev
.exp
.exp_cap
= pos
;
2642 static void vfio_check_pcie_flr(VFIOPCIDevice
*vdev
, uint8_t pos
)
2644 uint32_t cap
= pci_get_long(vdev
->pdev
.config
+ pos
+ PCI_EXP_DEVCAP
);
2646 if (cap
& PCI_EXP_DEVCAP_FLR
) {
2647 trace_vfio_check_pcie_flr(vdev
->vbasedev
.name
);
2648 vdev
->has_flr
= true;
2652 static void vfio_check_pm_reset(VFIOPCIDevice
*vdev
, uint8_t pos
)
2654 uint16_t csr
= pci_get_word(vdev
->pdev
.config
+ pos
+ PCI_PM_CTRL
);
2656 if (!(csr
& PCI_PM_CTRL_NO_SOFT_RESET
)) {
2657 trace_vfio_check_pm_reset(vdev
->vbasedev
.name
);
2658 vdev
->has_pm_reset
= true;
2662 static void vfio_check_af_flr(VFIOPCIDevice
*vdev
, uint8_t pos
)
2664 uint8_t cap
= pci_get_byte(vdev
->pdev
.config
+ pos
+ PCI_AF_CAP
);
2666 if ((cap
& PCI_AF_CAP_TP
) && (cap
& PCI_AF_CAP_FLR
)) {
2667 trace_vfio_check_af_flr(vdev
->vbasedev
.name
);
2668 vdev
->has_flr
= true;
2672 static int vfio_add_std_cap(VFIOPCIDevice
*vdev
, uint8_t pos
)
2674 PCIDevice
*pdev
= &vdev
->pdev
;
2675 uint8_t cap_id
, next
, size
;
2678 cap_id
= pdev
->config
[pos
];
2679 next
= pdev
->config
[pos
+ 1];
2682 * If it becomes important to configure capabilities to their actual
2683 * size, use this as the default when it's something we don't recognize.
2684 * Since QEMU doesn't actually handle many of the config accesses,
2685 * exact size doesn't seem worthwhile.
2687 size
= vfio_std_cap_max_size(pdev
, pos
);
2690 * pci_add_capability always inserts the new capability at the head
2691 * of the chain. Therefore to end up with a chain that matches the
2692 * physical device, we insert from the end by making this recursive.
2693 * This is also why we pre-caclulate size above as cached config space
2694 * will be changed as we unwind the stack.
2697 ret
= vfio_add_std_cap(vdev
, next
);
2702 /* Begin the rebuild, use QEMU emulated list bits */
2703 pdev
->config
[PCI_CAPABILITY_LIST
] = 0;
2704 vdev
->emulated_config_bits
[PCI_CAPABILITY_LIST
] = 0xff;
2705 vdev
->emulated_config_bits
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2708 /* Use emulated next pointer to allow dropping caps */
2709 pci_set_byte(vdev
->emulated_config_bits
+ pos
+ 1, 0xff);
2712 case PCI_CAP_ID_MSI
:
2713 ret
= vfio_setup_msi(vdev
, pos
);
2715 case PCI_CAP_ID_EXP
:
2716 vfio_check_pcie_flr(vdev
, pos
);
2717 ret
= vfio_setup_pcie_cap(vdev
, pos
, size
);
2719 case PCI_CAP_ID_MSIX
:
2720 ret
= vfio_setup_msix(vdev
, pos
);
2723 vfio_check_pm_reset(vdev
, pos
);
2725 ret
= pci_add_capability(pdev
, cap_id
, pos
, size
);
2728 vfio_check_af_flr(vdev
, pos
);
2729 ret
= pci_add_capability(pdev
, cap_id
, pos
, size
);
2732 ret
= pci_add_capability(pdev
, cap_id
, pos
, size
);
2737 error_report("vfio: %04x:%02x:%02x.%x Error adding PCI capability "
2738 "0x%x[0x%x]@0x%x: %d", vdev
->host
.domain
,
2739 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
2740 cap_id
, size
, pos
, ret
);
2747 static int vfio_add_capabilities(VFIOPCIDevice
*vdev
)
2749 PCIDevice
*pdev
= &vdev
->pdev
;
2751 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
) ||
2752 !pdev
->config
[PCI_CAPABILITY_LIST
]) {
2753 return 0; /* Nothing to add */
2756 return vfio_add_std_cap(vdev
, pdev
->config
[PCI_CAPABILITY_LIST
]);
2759 static void vfio_pci_pre_reset(VFIOPCIDevice
*vdev
)
2761 PCIDevice
*pdev
= &vdev
->pdev
;
2764 vfio_disable_interrupts(vdev
);
2766 /* Make sure the device is in D0 */
2771 pmcsr
= vfio_pci_read_config(pdev
, vdev
->pm_cap
+ PCI_PM_CTRL
, 2);
2772 state
= pmcsr
& PCI_PM_CTRL_STATE_MASK
;
2774 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
2775 vfio_pci_write_config(pdev
, vdev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
, 2);
2776 /* vfio handles the necessary delay here */
2777 pmcsr
= vfio_pci_read_config(pdev
, vdev
->pm_cap
+ PCI_PM_CTRL
, 2);
2778 state
= pmcsr
& PCI_PM_CTRL_STATE_MASK
;
2780 error_report("vfio: Unable to power on device, stuck in D%d",
2787 * Stop any ongoing DMA by disconecting I/O, MMIO, and bus master.
2788 * Also put INTx Disable in known state.
2790 cmd
= vfio_pci_read_config(pdev
, PCI_COMMAND
, 2);
2791 cmd
&= ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
2792 PCI_COMMAND_INTX_DISABLE
);
2793 vfio_pci_write_config(pdev
, PCI_COMMAND
, cmd
, 2);
2796 static void vfio_pci_post_reset(VFIOPCIDevice
*vdev
)
2798 vfio_enable_intx(vdev
);
2801 static bool vfio_pci_host_match(PCIHostDeviceAddress
*host1
,
2802 PCIHostDeviceAddress
*host2
)
2804 return (host1
->domain
== host2
->domain
&& host1
->bus
== host2
->bus
&&
2805 host1
->slot
== host2
->slot
&& host1
->function
== host2
->function
);
2808 static int vfio_pci_hot_reset(VFIOPCIDevice
*vdev
, bool single
)
2811 struct vfio_pci_hot_reset_info
*info
;
2812 struct vfio_pci_dependent_device
*devices
;
2813 struct vfio_pci_hot_reset
*reset
;
2818 trace_vfio_pci_hot_reset(vdev
->vbasedev
.name
, single
? "one" : "multi");
2820 vfio_pci_pre_reset(vdev
);
2821 vdev
->vbasedev
.needs_reset
= false;
2823 info
= g_malloc0(sizeof(*info
));
2824 info
->argsz
= sizeof(*info
);
2826 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO
, info
);
2827 if (ret
&& errno
!= ENOSPC
) {
2829 if (!vdev
->has_pm_reset
) {
2830 error_report("vfio: Cannot reset device %04x:%02x:%02x.%x, "
2831 "no available reset mechanism.", vdev
->host
.domain
,
2832 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
2837 count
= info
->count
;
2838 info
= g_realloc(info
, sizeof(*info
) + (count
* sizeof(*devices
)));
2839 info
->argsz
= sizeof(*info
) + (count
* sizeof(*devices
));
2840 devices
= &info
->devices
[0];
2842 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO
, info
);
2845 error_report("vfio: hot reset info failed: %m");
2849 trace_vfio_pci_hot_reset_has_dep_devices(vdev
->vbasedev
.name
);
2851 /* Verify that we have all the groups required */
2852 for (i
= 0; i
< info
->count
; i
++) {
2853 PCIHostDeviceAddress host
;
2855 VFIODevice
*vbasedev_iter
;
2857 host
.domain
= devices
[i
].segment
;
2858 host
.bus
= devices
[i
].bus
;
2859 host
.slot
= PCI_SLOT(devices
[i
].devfn
);
2860 host
.function
= PCI_FUNC(devices
[i
].devfn
);
2862 trace_vfio_pci_hot_reset_dep_devices(host
.domain
,
2863 host
.bus
, host
.slot
, host
.function
, devices
[i
].group_id
);
2865 if (vfio_pci_host_match(&host
, &vdev
->host
)) {
2869 QLIST_FOREACH(group
, &vfio_group_list
, next
) {
2870 if (group
->groupid
== devices
[i
].group_id
) {
2876 if (!vdev
->has_pm_reset
) {
2877 error_report("vfio: Cannot reset device %s, "
2878 "depends on group %d which is not owned.",
2879 vdev
->vbasedev
.name
, devices
[i
].group_id
);
2885 /* Prep dependent devices for reset and clear our marker. */
2886 QLIST_FOREACH(vbasedev_iter
, &group
->device_list
, next
) {
2887 if (vbasedev_iter
->type
!= VFIO_DEVICE_TYPE_PCI
) {
2890 tmp
= container_of(vbasedev_iter
, VFIOPCIDevice
, vbasedev
);
2891 if (vfio_pci_host_match(&host
, &tmp
->host
)) {
2896 vfio_pci_pre_reset(tmp
);
2897 tmp
->vbasedev
.needs_reset
= false;
2904 if (!single
&& !multi
) {
2909 /* Determine how many group fds need to be passed */
2911 QLIST_FOREACH(group
, &vfio_group_list
, next
) {
2912 for (i
= 0; i
< info
->count
; i
++) {
2913 if (group
->groupid
== devices
[i
].group_id
) {
2920 reset
= g_malloc0(sizeof(*reset
) + (count
* sizeof(*fds
)));
2921 reset
->argsz
= sizeof(*reset
) + (count
* sizeof(*fds
));
2922 fds
= &reset
->group_fds
[0];
2924 /* Fill in group fds */
2925 QLIST_FOREACH(group
, &vfio_group_list
, next
) {
2926 for (i
= 0; i
< info
->count
; i
++) {
2927 if (group
->groupid
== devices
[i
].group_id
) {
2928 fds
[reset
->count
++] = group
->fd
;
2935 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_PCI_HOT_RESET
, reset
);
2938 trace_vfio_pci_hot_reset_result(vdev
->vbasedev
.name
,
2939 ret
? "%m" : "Success");
2942 /* Re-enable INTx on affected devices */
2943 for (i
= 0; i
< info
->count
; i
++) {
2944 PCIHostDeviceAddress host
;
2946 VFIODevice
*vbasedev_iter
;
2948 host
.domain
= devices
[i
].segment
;
2949 host
.bus
= devices
[i
].bus
;
2950 host
.slot
= PCI_SLOT(devices
[i
].devfn
);
2951 host
.function
= PCI_FUNC(devices
[i
].devfn
);
2953 if (vfio_pci_host_match(&host
, &vdev
->host
)) {
2957 QLIST_FOREACH(group
, &vfio_group_list
, next
) {
2958 if (group
->groupid
== devices
[i
].group_id
) {
2967 QLIST_FOREACH(vbasedev_iter
, &group
->device_list
, next
) {
2968 if (vbasedev_iter
->type
!= VFIO_DEVICE_TYPE_PCI
) {
2971 tmp
= container_of(vbasedev_iter
, VFIOPCIDevice
, vbasedev
);
2972 if (vfio_pci_host_match(&host
, &tmp
->host
)) {
2973 vfio_pci_post_reset(tmp
);
2979 vfio_pci_post_reset(vdev
);
2986 * We want to differentiate hot reset of mulitple in-use devices vs hot reset
2987 * of a single in-use device. VFIO_DEVICE_RESET will already handle the case
2988 * of doing hot resets when there is only a single device per bus. The in-use
2989 * here refers to how many VFIODevices are affected. A hot reset that affects
2990 * multiple devices, but only a single in-use device, means that we can call
2991 * it from our bus ->reset() callback since the extent is effectively a single
2992 * device. This allows us to make use of it in the hotplug path. When there
2993 * are multiple in-use devices, we can only trigger the hot reset during a
2994 * system reset and thus from our reset handler. We separate _one vs _multi
2995 * here so that we don't overlap and do a double reset on the system reset
2996 * path where both our reset handler and ->reset() callback are used. Calling
2997 * _one() will only do a hot reset for the one in-use devices case, calling
2998 * _multi() will do nothing if a _one() would have been sufficient.
3000 static int vfio_pci_hot_reset_one(VFIOPCIDevice
*vdev
)
3002 return vfio_pci_hot_reset(vdev
, true);
3005 static int vfio_pci_hot_reset_multi(VFIODevice
*vbasedev
)
3007 VFIOPCIDevice
*vdev
= container_of(vbasedev
, VFIOPCIDevice
, vbasedev
);
3008 return vfio_pci_hot_reset(vdev
, false);
3011 static void vfio_pci_compute_needs_reset(VFIODevice
*vbasedev
)
3013 VFIOPCIDevice
*vdev
= container_of(vbasedev
, VFIOPCIDevice
, vbasedev
);
3014 if (!vbasedev
->reset_works
|| (!vdev
->has_flr
&& vdev
->has_pm_reset
)) {
3015 vbasedev
->needs_reset
= true;
3019 static VFIODeviceOps vfio_pci_ops
= {
3020 .vfio_compute_needs_reset
= vfio_pci_compute_needs_reset
,
3021 .vfio_hot_reset_multi
= vfio_pci_hot_reset_multi
,
3022 .vfio_eoi
= vfio_eoi
,
3025 static int vfio_populate_device(VFIOPCIDevice
*vdev
)
3027 VFIODevice
*vbasedev
= &vdev
->vbasedev
;
3028 struct vfio_region_info reg_info
= { .argsz
= sizeof(reg_info
) };
3029 struct vfio_irq_info irq_info
= { .argsz
= sizeof(irq_info
) };
3032 /* Sanity check device */
3033 if (!(vbasedev
->flags
& VFIO_DEVICE_FLAGS_PCI
)) {
3034 error_report("vfio: Um, this isn't a PCI device");
3038 if (vbasedev
->num_regions
< VFIO_PCI_CONFIG_REGION_INDEX
+ 1) {
3039 error_report("vfio: unexpected number of io regions %u",
3040 vbasedev
->num_regions
);
3044 if (vbasedev
->num_irqs
< VFIO_PCI_MSIX_IRQ_INDEX
+ 1) {
3045 error_report("vfio: unexpected number of irqs %u", vbasedev
->num_irqs
);
3049 for (i
= VFIO_PCI_BAR0_REGION_INDEX
; i
< VFIO_PCI_ROM_REGION_INDEX
; i
++) {
3052 ret
= ioctl(vbasedev
->fd
, VFIO_DEVICE_GET_REGION_INFO
, ®_info
);
3054 error_report("vfio: Error getting region %d info: %m", i
);
3058 trace_vfio_populate_device_region(vbasedev
->name
, i
,
3059 (unsigned long)reg_info
.size
,
3060 (unsigned long)reg_info
.offset
,
3061 (unsigned long)reg_info
.flags
);
3063 vdev
->bars
[i
].region
.vbasedev
= vbasedev
;
3064 vdev
->bars
[i
].region
.flags
= reg_info
.flags
;
3065 vdev
->bars
[i
].region
.size
= reg_info
.size
;
3066 vdev
->bars
[i
].region
.fd_offset
= reg_info
.offset
;
3067 vdev
->bars
[i
].region
.nr
= i
;
3068 QLIST_INIT(&vdev
->bars
[i
].quirks
);
3071 reg_info
.index
= VFIO_PCI_CONFIG_REGION_INDEX
;
3073 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_GET_REGION_INFO
, ®_info
);
3075 error_report("vfio: Error getting config info: %m");
3079 trace_vfio_populate_device_config(vdev
->vbasedev
.name
,
3080 (unsigned long)reg_info
.size
,
3081 (unsigned long)reg_info
.offset
,
3082 (unsigned long)reg_info
.flags
);
3084 vdev
->config_size
= reg_info
.size
;
3085 if (vdev
->config_size
== PCI_CONFIG_SPACE_SIZE
) {
3086 vdev
->pdev
.cap_present
&= ~QEMU_PCI_CAP_EXPRESS
;
3088 vdev
->config_offset
= reg_info
.offset
;
3090 if ((vdev
->features
& VFIO_FEATURE_ENABLE_VGA
) &&
3091 vbasedev
->num_regions
> VFIO_PCI_VGA_REGION_INDEX
) {
3092 struct vfio_region_info vga_info
= {
3093 .argsz
= sizeof(vga_info
),
3094 .index
= VFIO_PCI_VGA_REGION_INDEX
,
3097 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_GET_REGION_INFO
, &vga_info
);
3100 "vfio: Device does not support requested feature x-vga");
3104 if (!(vga_info
.flags
& VFIO_REGION_INFO_FLAG_READ
) ||
3105 !(vga_info
.flags
& VFIO_REGION_INFO_FLAG_WRITE
) ||
3106 vga_info
.size
< 0xbffff + 1) {
3107 error_report("vfio: Unexpected VGA info, flags 0x%lx, size 0x%lx",
3108 (unsigned long)vga_info
.flags
,
3109 (unsigned long)vga_info
.size
);
3113 vdev
->vga
.fd_offset
= vga_info
.offset
;
3114 vdev
->vga
.fd
= vdev
->vbasedev
.fd
;
3116 vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].offset
= QEMU_PCI_VGA_MEM_BASE
;
3117 vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].nr
= QEMU_PCI_VGA_MEM
;
3118 QLIST_INIT(&vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].quirks
);
3120 vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].offset
= QEMU_PCI_VGA_IO_LO_BASE
;
3121 vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].nr
= QEMU_PCI_VGA_IO_LO
;
3122 QLIST_INIT(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].quirks
);
3124 vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].offset
= QEMU_PCI_VGA_IO_HI_BASE
;
3125 vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].nr
= QEMU_PCI_VGA_IO_HI
;
3126 QLIST_INIT(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].quirks
);
3128 vdev
->has_vga
= true;
3131 irq_info
.index
= VFIO_PCI_ERR_IRQ_INDEX
;
3133 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_GET_IRQ_INFO
, &irq_info
);
3135 /* This can fail for an old kernel or legacy PCI dev */
3136 trace_vfio_populate_device_get_irq_info_failure();
3138 } else if (irq_info
.count
== 1) {
3139 vdev
->pci_aer
= true;
3141 error_report("vfio: %s "
3142 "Could not enable error recovery for the device",
3150 static void vfio_put_device(VFIOPCIDevice
*vdev
)
3152 g_free(vdev
->vbasedev
.name
);
3154 object_unparent(OBJECT(&vdev
->msix
->mmap_mem
));
3158 vfio_put_base_device(&vdev
->vbasedev
);
3161 static void vfio_err_notifier_handler(void *opaque
)
3163 VFIOPCIDevice
*vdev
= opaque
;
3165 if (!event_notifier_test_and_clear(&vdev
->err_notifier
)) {
3170 * TBD. Retrieve the error details and decide what action
3171 * needs to be taken. One of the actions could be to pass
3172 * the error to the guest and have the guest driver recover
3173 * from the error. This requires that PCIe capabilities be
3174 * exposed to the guest. For now, we just terminate the
3175 * guest to contain the error.
3178 error_report("%s(%04x:%02x:%02x.%x) Unrecoverable error detected. "
3179 "Please collect any data possible and then kill the guest",
3180 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
3181 vdev
->host
.slot
, vdev
->host
.function
);
3183 vm_stop(RUN_STATE_INTERNAL_ERROR
);
3187 * Registers error notifier for devices supporting error recovery.
3188 * If we encounter a failure in this function, we report an error
3189 * and continue after disabling error recovery support for the
3192 static void vfio_register_err_notifier(VFIOPCIDevice
*vdev
)
3196 struct vfio_irq_set
*irq_set
;
3199 if (!vdev
->pci_aer
) {
3203 if (event_notifier_init(&vdev
->err_notifier
, 0)) {
3204 error_report("vfio: Unable to init event notifier for error detection");
3205 vdev
->pci_aer
= false;
3209 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
3211 irq_set
= g_malloc0(argsz
);
3212 irq_set
->argsz
= argsz
;
3213 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
3214 VFIO_IRQ_SET_ACTION_TRIGGER
;
3215 irq_set
->index
= VFIO_PCI_ERR_IRQ_INDEX
;
3218 pfd
= (int32_t *)&irq_set
->data
;
3220 *pfd
= event_notifier_get_fd(&vdev
->err_notifier
);
3221 qemu_set_fd_handler(*pfd
, vfio_err_notifier_handler
, NULL
, vdev
);
3223 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
3225 error_report("vfio: Failed to set up error notification");
3226 qemu_set_fd_handler(*pfd
, NULL
, NULL
, vdev
);
3227 event_notifier_cleanup(&vdev
->err_notifier
);
3228 vdev
->pci_aer
= false;
3233 static void vfio_unregister_err_notifier(VFIOPCIDevice
*vdev
)
3236 struct vfio_irq_set
*irq_set
;
3240 if (!vdev
->pci_aer
) {
3244 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
3246 irq_set
= g_malloc0(argsz
);
3247 irq_set
->argsz
= argsz
;
3248 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
3249 VFIO_IRQ_SET_ACTION_TRIGGER
;
3250 irq_set
->index
= VFIO_PCI_ERR_IRQ_INDEX
;
3253 pfd
= (int32_t *)&irq_set
->data
;
3256 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
3258 error_report("vfio: Failed to de-assign error fd: %m");
3261 qemu_set_fd_handler(event_notifier_get_fd(&vdev
->err_notifier
),
3263 event_notifier_cleanup(&vdev
->err_notifier
);
3266 static void vfio_req_notifier_handler(void *opaque
)
3268 VFIOPCIDevice
*vdev
= opaque
;
3270 if (!event_notifier_test_and_clear(&vdev
->req_notifier
)) {
3274 qdev_unplug(&vdev
->pdev
.qdev
, NULL
);
3277 static void vfio_register_req_notifier(VFIOPCIDevice
*vdev
)
3279 struct vfio_irq_info irq_info
= { .argsz
= sizeof(irq_info
),
3280 .index
= VFIO_PCI_REQ_IRQ_INDEX
};
3282 struct vfio_irq_set
*irq_set
;
3285 if (!(vdev
->features
& VFIO_FEATURE_ENABLE_REQ
)) {
3289 if (ioctl(vdev
->vbasedev
.fd
,
3290 VFIO_DEVICE_GET_IRQ_INFO
, &irq_info
) < 0 || irq_info
.count
< 1) {
3294 if (event_notifier_init(&vdev
->req_notifier
, 0)) {
3295 error_report("vfio: Unable to init event notifier for device request");
3299 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
3301 irq_set
= g_malloc0(argsz
);
3302 irq_set
->argsz
= argsz
;
3303 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
3304 VFIO_IRQ_SET_ACTION_TRIGGER
;
3305 irq_set
->index
= VFIO_PCI_REQ_IRQ_INDEX
;
3308 pfd
= (int32_t *)&irq_set
->data
;
3310 *pfd
= event_notifier_get_fd(&vdev
->req_notifier
);
3311 qemu_set_fd_handler(*pfd
, vfio_req_notifier_handler
, NULL
, vdev
);
3313 if (ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
)) {
3314 error_report("vfio: Failed to set up device request notification");
3315 qemu_set_fd_handler(*pfd
, NULL
, NULL
, vdev
);
3316 event_notifier_cleanup(&vdev
->req_notifier
);
3318 vdev
->req_enabled
= true;
3324 static void vfio_unregister_req_notifier(VFIOPCIDevice
*vdev
)
3327 struct vfio_irq_set
*irq_set
;
3330 if (!vdev
->req_enabled
) {
3334 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
3336 irq_set
= g_malloc0(argsz
);
3337 irq_set
->argsz
= argsz
;
3338 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
3339 VFIO_IRQ_SET_ACTION_TRIGGER
;
3340 irq_set
->index
= VFIO_PCI_REQ_IRQ_INDEX
;
3343 pfd
= (int32_t *)&irq_set
->data
;
3346 if (ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
)) {
3347 error_report("vfio: Failed to de-assign device request fd: %m");
3350 qemu_set_fd_handler(event_notifier_get_fd(&vdev
->req_notifier
),
3352 event_notifier_cleanup(&vdev
->req_notifier
);
3354 vdev
->req_enabled
= false;
3358 * AMD Radeon PCI config reset, based on Linux:
3359 * drivers/gpu/drm/radeon/ci_smc.c:ci_is_smc_running()
3360 * drivers/gpu/drm/radeon/radeon_device.c:radeon_pci_config_reset
3361 * drivers/gpu/drm/radeon/ci_smc.c:ci_reset_smc()
3362 * drivers/gpu/drm/radeon/ci_smc.c:ci_stop_smc_clock()
3363 * IDs: include/drm/drm_pciids.h
3364 * Registers: http://cgit.freedesktop.org/~agd5f/linux/commit/?id=4e2aa447f6f0
3366 * Bonaire and Hawaii GPUs do not respond to a bus reset. This is a bug in the
3367 * hardware that should be fixed on future ASICs. The symptom of this is that
3368 * once the accerlated driver loads, Windows guests will bsod on subsequent
3369 * attmpts to load the driver, such as after VM reset or shutdown/restart. To
3370 * work around this, we do an AMD specific PCI config reset, followed by an SMC
3371 * reset. The PCI config reset only works if SMC firmware is running, so we
3372 * have a dependency on the state of the device as to whether this reset will
3373 * be effective. There are still cases where we won't be able to kick the
3374 * device into working, but this greatly improves the usability overall. The
3375 * config reset magic is relatively common on AMD GPUs, but the setup and SMC
3376 * poking is largely ASIC specific.
3378 static bool vfio_radeon_smc_is_running(VFIOPCIDevice
*vdev
)
3383 * Registers 200h and 204h are index and data registers for acessing
3384 * indirect configuration registers within the device.
3386 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0x80000004, 4);
3387 clk
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
3388 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0x80000370, 4);
3389 pc_c
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
3391 return (!(clk
& 1) && (0x20100 <= pc_c
));
3395 * The scope of a config reset is controlled by a mode bit in the misc register
3396 * and a fuse, exposed as a bit in another register. The fuse is the default
3397 * (0 = GFX, 1 = whole GPU), the misc bit is a toggle, with the forumula
3398 * scope = !(misc ^ fuse), where the resulting scope is defined the same as
3399 * the fuse. A truth table therefore tells us that if misc == fuse, we need
3400 * to flip the value of the bit in the misc register.
3402 static void vfio_radeon_set_gfx_only_reset(VFIOPCIDevice
*vdev
)
3404 uint32_t misc
, fuse
;
3407 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0xc00c0000, 4);
3408 fuse
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
3411 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0xc0000010, 4);
3412 misc
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
3416 vfio_region_write(&vdev
->bars
[5].region
, 0x204, misc
^ 2, 4);
3417 vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4); /* flush */
3421 static int vfio_radeon_reset(VFIOPCIDevice
*vdev
)
3423 PCIDevice
*pdev
= &vdev
->pdev
;
3427 /* Defer to a kernel implemented reset */
3428 if (vdev
->vbasedev
.reset_works
) {
3432 /* Enable only memory BAR access */
3433 vfio_pci_write_config(pdev
, PCI_COMMAND
, PCI_COMMAND_MEMORY
, 2);
3435 /* Reset only works if SMC firmware is loaded and running */
3436 if (!vfio_radeon_smc_is_running(vdev
)) {
3441 /* Make sure only the GFX function is reset */
3442 vfio_radeon_set_gfx_only_reset(vdev
);
3444 /* AMD PCI config reset */
3445 vfio_pci_write_config(pdev
, 0x7c, 0x39d5e86b, 4);
3448 /* Read back the memory size to make sure we're out of reset */
3449 for (i
= 0; i
< 100000; i
++) {
3450 if (vfio_region_read(&vdev
->bars
[5].region
, 0x5428, 4) != 0xffffffff) {
3457 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0x80000000, 4);
3458 data
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
3460 vfio_region_write(&vdev
->bars
[5].region
, 0x204, data
, 4);
3462 /* Disable SMC clock */
3463 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0x80000004, 4);
3464 data
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
3466 vfio_region_write(&vdev
->bars
[5].region
, 0x204, data
, 4);
3469 /* Restore PCI command register */
3470 vfio_pci_write_config(pdev
, PCI_COMMAND
, 0, 2);
3475 static void vfio_setup_resetfn(VFIOPCIDevice
*vdev
)
3477 PCIDevice
*pdev
= &vdev
->pdev
;
3478 uint16_t vendor
, device
;
3480 vendor
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
3481 device
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
3487 case 0x6649: /* Bonaire [FirePro W5100] */
3490 case 0x6658: /* Bonaire XTX [Radeon R7 260X] */
3491 case 0x665c: /* Bonaire XT [Radeon HD 7790/8770 / R9 260 OEM] */
3492 case 0x665d: /* Bonaire [Radeon R7 200 Series] */
3494 case 0x67A0: /* Hawaii XT GL [FirePro W9100] */
3495 case 0x67A1: /* Hawaii PRO GL [FirePro W8100] */
3500 case 0x67B0: /* Hawaii XT [Radeon R9 290X] */
3501 case 0x67B1: /* Hawaii PRO [Radeon R9 290] */
3506 vdev
->resetfn
= vfio_radeon_reset
;
3513 static int vfio_initfn(PCIDevice
*pdev
)
3515 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
3516 VFIODevice
*vbasedev_iter
;
3518 char path
[PATH_MAX
], iommu_group_path
[PATH_MAX
], *group_name
;
3524 /* Check that the host device exists */
3525 snprintf(path
, sizeof(path
),
3526 "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/",
3527 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
3528 vdev
->host
.function
);
3529 if (stat(path
, &st
) < 0) {
3530 error_report("vfio: error: no such host device: %s", path
);
3534 vdev
->vbasedev
.ops
= &vfio_pci_ops
;
3536 vdev
->vbasedev
.type
= VFIO_DEVICE_TYPE_PCI
;
3537 vdev
->vbasedev
.name
= g_strdup_printf("%04x:%02x:%02x.%01x",
3538 vdev
->host
.domain
, vdev
->host
.bus
,
3539 vdev
->host
.slot
, vdev
->host
.function
);
3541 strncat(path
, "iommu_group", sizeof(path
) - strlen(path
) - 1);
3543 len
= readlink(path
, iommu_group_path
, sizeof(path
));
3544 if (len
<= 0 || len
>= sizeof(path
)) {
3545 error_report("vfio: error no iommu_group for device");
3546 return len
< 0 ? -errno
: -ENAMETOOLONG
;
3549 iommu_group_path
[len
] = 0;
3550 group_name
= basename(iommu_group_path
);
3552 if (sscanf(group_name
, "%d", &groupid
) != 1) {
3553 error_report("vfio: error reading %s: %m", path
);
3557 trace_vfio_initfn(vdev
->vbasedev
.name
, groupid
);
3559 group
= vfio_get_group(groupid
, pci_device_iommu_address_space(pdev
));
3561 error_report("vfio: failed to get group %d", groupid
);
3565 snprintf(path
, sizeof(path
), "%04x:%02x:%02x.%01x",
3566 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
3567 vdev
->host
.function
);
3569 QLIST_FOREACH(vbasedev_iter
, &group
->device_list
, next
) {
3570 if (strcmp(vbasedev_iter
->name
, vdev
->vbasedev
.name
) == 0) {
3571 error_report("vfio: error: device %s is already attached", path
);
3572 vfio_put_group(group
);
3577 ret
= vfio_get_device(group
, path
, &vdev
->vbasedev
);
3579 error_report("vfio: failed to get device %s", path
);
3580 vfio_put_group(group
);
3584 ret
= vfio_populate_device(vdev
);
3589 /* Get a copy of config space */
3590 ret
= pread(vdev
->vbasedev
.fd
, vdev
->pdev
.config
,
3591 MIN(pci_config_size(&vdev
->pdev
), vdev
->config_size
),
3592 vdev
->config_offset
);
3593 if (ret
< (int)MIN(pci_config_size(&vdev
->pdev
), vdev
->config_size
)) {
3594 ret
= ret
< 0 ? -errno
: -EFAULT
;
3595 error_report("vfio: Failed to read device config space");
3599 /* vfio emulates a lot for us, but some bits need extra love */
3600 vdev
->emulated_config_bits
= g_malloc0(vdev
->config_size
);
3602 /* QEMU can choose to expose the ROM or not */
3603 memset(vdev
->emulated_config_bits
+ PCI_ROM_ADDRESS
, 0xff, 4);
3605 /* QEMU can change multi-function devices to single function, or reverse */
3606 vdev
->emulated_config_bits
[PCI_HEADER_TYPE
] =
3607 PCI_HEADER_TYPE_MULTI_FUNCTION
;
3609 /* Restore or clear multifunction, this is always controlled by QEMU */
3610 if (vdev
->pdev
.cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
3611 vdev
->pdev
.config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
3613 vdev
->pdev
.config
[PCI_HEADER_TYPE
] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
3617 * Clear host resource mapping info. If we choose not to register a
3618 * BAR, such as might be the case with the option ROM, we can get
3619 * confusing, unwritable, residual addresses from the host here.
3621 memset(&vdev
->pdev
.config
[PCI_BASE_ADDRESS_0
], 0, 24);
3622 memset(&vdev
->pdev
.config
[PCI_ROM_ADDRESS
], 0, 4);
3624 vfio_pci_size_rom(vdev
);
3626 ret
= vfio_early_setup_msix(vdev
);
3631 vfio_map_bars(vdev
);
3633 ret
= vfio_add_capabilities(vdev
);
3638 /* QEMU emulates all of MSI & MSIX */
3639 if (pdev
->cap_present
& QEMU_PCI_CAP_MSIX
) {
3640 memset(vdev
->emulated_config_bits
+ pdev
->msix_cap
, 0xff,
3644 if (pdev
->cap_present
& QEMU_PCI_CAP_MSI
) {
3645 memset(vdev
->emulated_config_bits
+ pdev
->msi_cap
, 0xff,
3646 vdev
->msi_cap_size
);
3649 if (vfio_pci_read_config(&vdev
->pdev
, PCI_INTERRUPT_PIN
, 1)) {
3650 vdev
->intx
.mmap_timer
= timer_new_ms(QEMU_CLOCK_VIRTUAL
,
3651 vfio_intx_mmap_enable
, vdev
);
3652 pci_device_set_intx_routing_notifier(&vdev
->pdev
, vfio_update_irq
);
3653 ret
= vfio_enable_intx(vdev
);
3659 vfio_register_err_notifier(vdev
);
3660 vfio_register_req_notifier(vdev
);
3661 vfio_setup_resetfn(vdev
);
3666 pci_device_set_intx_routing_notifier(&vdev
->pdev
, NULL
);
3667 vfio_teardown_msi(vdev
);
3668 vfio_unregister_bars(vdev
);
3672 static void vfio_instance_finalize(Object
*obj
)
3674 PCIDevice
*pci_dev
= PCI_DEVICE(obj
);
3675 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pci_dev
);
3676 VFIOGroup
*group
= vdev
->vbasedev
.group
;
3678 vfio_unmap_bars(vdev
);
3679 g_free(vdev
->emulated_config_bits
);
3681 vfio_put_device(vdev
);
3682 vfio_put_group(group
);
3685 static void vfio_exitfn(PCIDevice
*pdev
)
3687 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
3689 vfio_unregister_req_notifier(vdev
);
3690 vfio_unregister_err_notifier(vdev
);
3691 pci_device_set_intx_routing_notifier(&vdev
->pdev
, NULL
);
3692 vfio_disable_interrupts(vdev
);
3693 if (vdev
->intx
.mmap_timer
) {
3694 timer_free(vdev
->intx
.mmap_timer
);
3696 vfio_teardown_msi(vdev
);
3697 vfio_unregister_bars(vdev
);
3700 static void vfio_pci_reset(DeviceState
*dev
)
3702 PCIDevice
*pdev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
3703 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
3705 trace_vfio_pci_reset(vdev
->vbasedev
.name
);
3707 vfio_pci_pre_reset(vdev
);
3709 if (vdev
->resetfn
&& !vdev
->resetfn(vdev
)) {
3713 if (vdev
->vbasedev
.reset_works
&&
3714 (vdev
->has_flr
|| !vdev
->has_pm_reset
) &&
3715 !ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_RESET
)) {
3716 trace_vfio_pci_reset_flr(vdev
->vbasedev
.name
);
3720 /* See if we can do our own bus reset */
3721 if (!vfio_pci_hot_reset_one(vdev
)) {
3725 /* If nothing else works and the device supports PM reset, use it */
3726 if (vdev
->vbasedev
.reset_works
&& vdev
->has_pm_reset
&&
3727 !ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_RESET
)) {
3728 trace_vfio_pci_reset_pm(vdev
->vbasedev
.name
);
3733 vfio_pci_post_reset(vdev
);
3736 static void vfio_instance_init(Object
*obj
)
3738 PCIDevice
*pci_dev
= PCI_DEVICE(obj
);
3739 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, PCI_DEVICE(obj
));
3741 device_add_bootindex_property(obj
, &vdev
->bootindex
,
3743 &pci_dev
->qdev
, NULL
);
3746 static Property vfio_pci_dev_properties
[] = {
3747 DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIOPCIDevice
, host
),
3748 DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIOPCIDevice
,
3749 intx
.mmap_timeout
, 1100),
3750 DEFINE_PROP_BIT("x-vga", VFIOPCIDevice
, features
,
3751 VFIO_FEATURE_ENABLE_VGA_BIT
, false),
3752 DEFINE_PROP_BIT("x-req", VFIOPCIDevice
, features
,
3753 VFIO_FEATURE_ENABLE_REQ_BIT
, true),
3754 DEFINE_PROP_INT32("bootindex", VFIOPCIDevice
, bootindex
, -1),
3755 DEFINE_PROP_BOOL("x-mmap", VFIOPCIDevice
, vbasedev
.allow_mmap
, true),
3757 * TODO - support passed fds... is this necessary?
3758 * DEFINE_PROP_STRING("vfiofd", VFIOPCIDevice, vfiofd_name),
3759 * DEFINE_PROP_STRING("vfiogroupfd, VFIOPCIDevice, vfiogroupfd_name),
3761 DEFINE_PROP_END_OF_LIST(),
3764 static const VMStateDescription vfio_pci_vmstate
= {
3769 static void vfio_pci_dev_class_init(ObjectClass
*klass
, void *data
)
3771 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3772 PCIDeviceClass
*pdc
= PCI_DEVICE_CLASS(klass
);
3774 dc
->reset
= vfio_pci_reset
;
3775 dc
->props
= vfio_pci_dev_properties
;
3776 dc
->vmsd
= &vfio_pci_vmstate
;
3777 dc
->desc
= "VFIO-based PCI device assignment";
3778 set_bit(DEVICE_CATEGORY_MISC
, dc
->categories
);
3779 pdc
->init
= vfio_initfn
;
3780 pdc
->exit
= vfio_exitfn
;
3781 pdc
->config_read
= vfio_pci_read_config
;
3782 pdc
->config_write
= vfio_pci_write_config
;
3783 pdc
->is_express
= 1; /* We might be */
3786 static const TypeInfo vfio_pci_dev_info
= {
3788 .parent
= TYPE_PCI_DEVICE
,
3789 .instance_size
= sizeof(VFIOPCIDevice
),
3790 .class_init
= vfio_pci_dev_class_init
,
3791 .instance_init
= vfio_instance_init
,
3792 .instance_finalize
= vfio_instance_finalize
,
3795 static void register_vfio_pci_dev_type(void)
3797 type_register_static(&vfio_pci_dev_info
);
3800 type_init(register_vfio_pci_dev_type
)