hw/sparc64/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "qemu/error-report.h"
  28 #include "qapi/error.h"
  29 #include "qemu-common.h"
  30 #include "cpu.h"
  31 #include "hw/pci/pci.h"
  32 #include "hw/pci/pci_bridge.h"
  33 #include "hw/pci/pci_bus.h"
  34 #include "hw/pci/pci_host.h"
  35 #include "hw/qdev-properties.h"
  36 #include "hw/pci-host/sabre.h"
  37 #include "hw/char/serial.h"
  38 #include "hw/char/parallel.h"
  39 #include "hw/rtc/m48t59.h"
  40 #include "migration/vmstate.h"
  41 #include "hw/input/i8042.h"
  42 #include "hw/block/fdc.h"
  43 #include "net/net.h"
  44 #include "qemu/timer.h"
  45 #include "sysemu/runstate.h"
  46 #include "sysemu/sysemu.h"
  47 #include "hw/boards.h"
  48 #include "hw/nvram/sun_nvram.h"
  49 #include "hw/nvram/chrp_nvram.h"
  50 #include "hw/sparc/sparc64.h"
  51 #include "hw/nvram/fw_cfg.h"
  52 #include "hw/sysbus.h"
  53 #include "hw/ide.h"
  54 #include "hw/ide/pci.h"
  55 #include "hw/loader.h"
  56 #include "hw/fw-path-provider.h"
  57 #include "elf.h"
  58 #include "trace.h"
  59
  60 #define KERNEL_LOAD_ADDR     0x00404000
  61 #define CMDLINE_ADDR         0x003ff000
  62 #define PROM_SIZE_MAX        (4 * MiB)
  63 #define PROM_VADDR           0x000ffd00000ULL
  64 #define PBM_SPECIAL_BASE     0x1fe00000000ULL
  65 #define PBM_MEM_BASE         0x1ff00000000ULL
  66 #define PBM_PCI_IO_BASE      (PBM_SPECIAL_BASE + 0x02000000ULL)
  67 #define PROM_FILENAME        "openbios-sparc64"
  68 #define NVRAM_SIZE           0x2000
  69 #define MAX_IDE_BUS          2
  70 #define BIOS_CFG_IOPORT      0x510
  71 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  72 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  73 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  74
  75 #define IVEC_MAX             0x40
  76
  77 struct hwdef {
  78     uint16_t machine_id;
  79     uint64_t prom_addr;
  80     uint64_t console_serial_base;
  81 };
  82
  83 typedef struct EbusState {
  84     /*< private >*/
  85     PCIDevice parent_obj;
  86
  87     ISABus *isa_bus;
  88     qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
  89     uint64_t console_serial_base;
  90     MemoryRegion bar0;
  91     MemoryRegion bar1;
  92 } EbusState;
  93
  94 #define TYPE_EBUS "ebus"
  95 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
  96
  97 const char *fw_cfg_arch_key_name(uint16_t key)
  98 {
  99     static const struct {
 100         uint16_t key;
 101         const char *name;
 102     } fw_cfg_arch_wellknown_keys[] = {
 103         {FW_CFG_SPARC64_WIDTH, "width"},
 104         {FW_CFG_SPARC64_HEIGHT, "height"},
 105         {FW_CFG_SPARC64_DEPTH, "depth"},
 106     };
 107
 108     for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
 109         if (fw_cfg_arch_wellknown_keys[i].key == key) {
 110             return fw_cfg_arch_wellknown_keys[i].name;
 111         }
 112     }
 113     return NULL;
 114 }
 115
 116 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
 117                             Error **errp)
 118 {
 119     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 120 }
 121
 122 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
 123                                   const char *arch, ram_addr_t RAM_size,
 124                                   const char *boot_devices,
 125                                   uint32_t kernel_image, uint32_t kernel_size,
 126                                   const char *cmdline,
 127                                   uint32_t initrd_image, uint32_t initrd_size,
 128                                   uint32_t NVRAM_image,
 129                                   int width, int height, int depth,
 130                                   const uint8_t *macaddr)
 131 {
 132     unsigned int i;
 133     int sysp_end;
 134     uint8_t image[0x1ff0];
 135     NvramClass *k = NVRAM_GET_CLASS(nvram);
 136
 137     memset(image, '\0', sizeof(image));
 138
 139     /* OpenBIOS nvram variables partition */
 140     sysp_end = chrp_nvram_create_system_partition(image, 0);
 141
 142     /* Free space partition */
 143     chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
 144
 145     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 146
 147     for (i = 0; i < sizeof(image); i++) {
 148         (k->write)(nvram, i, image[i]);
 149     }
 150
 151     return 0;
 152 }
 153
 154 static uint64_t sun4u_load_kernel(const char *kernel_filename,
 155                                   const char *initrd_filename,
 156                                   ram_addr_t RAM_size, uint64_t *initrd_size,
 157                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
 158                                   uint64_t *kernel_entry)
 159 {
 160     int linux_boot;
 161     unsigned int i;
 162     long kernel_size;
 163     uint8_t *ptr;
 164     uint64_t kernel_top = 0;
 165
 166     linux_boot = (kernel_filename != NULL);
 167
 168     kernel_size = 0;
 169     if (linux_boot) {
 170         int bswap_needed;
 171
 172 #ifdef BSWAP_NEEDED
 173         bswap_needed = 1;
 174 #else
 175         bswap_needed = 0;
 176 #endif
 177         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry,
 178                                kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
 179         if (kernel_size < 0) {
 180             *kernel_addr = KERNEL_LOAD_ADDR;
 181             *kernel_entry = KERNEL_LOAD_ADDR;
 182             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 183                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 184                                     TARGET_PAGE_SIZE);
 185         }
 186         if (kernel_size < 0) {
 187             kernel_size = load_image_targphys(kernel_filename,
 188                                               KERNEL_LOAD_ADDR,
 189                                               RAM_size - KERNEL_LOAD_ADDR);
 190         }
 191         if (kernel_size < 0) {
 192             error_report("could not load kernel '%s'", kernel_filename);
 193             exit(1);
 194         }
 195         /* load initrd above kernel */
 196         *initrd_size = 0;
 197         if (initrd_filename && kernel_top) {
 198             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
 199
 200             *initrd_size = load_image_targphys(initrd_filename,
 201                                                *initrd_addr,
 202                                                RAM_size - *initrd_addr);
 203             if ((int)*initrd_size < 0) {
 204                 error_report("could not load initial ram disk '%s'",
 205                              initrd_filename);
 206                 exit(1);
 207             }
 208         }
 209         if (*initrd_size > 0) {
 210             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 211                 ptr = rom_ptr(*kernel_addr + i, 32);
 212                 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 213                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
 214                     stl_p(ptr + 28, *initrd_size);
 215                     break;
 216                 }
 217             }
 218         }
 219     }
 220     return kernel_size;
 221 }
 222
 223 typedef struct ResetData {
 224     SPARCCPU *cpu;
 225     uint64_t prom_addr;
 226 } ResetData;
 227
 228 #define TYPE_SUN4U_POWER "power"
 229 #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER)
 230
 231 typedef struct PowerDevice {
 232     SysBusDevice parent_obj;
 233
 234     MemoryRegion power_mmio;
 235 } PowerDevice;
 236
 237 /* Power */
 238 static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
 239 {
 240     return 0;
 241 }
 242
 243 static void power_mem_write(void *opaque, hwaddr addr,
 244                             uint64_t val, unsigned size)
 245 {
 246     /* According to a real Ultra 5, bit 24 controls the power */
 247     if (val & 0x1000000) {
 248         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 249     }
 250 }
 251
 252 static const MemoryRegionOps power_mem_ops = {
 253     .read = power_mem_read,
 254     .write = power_mem_write,
 255     .endianness = DEVICE_NATIVE_ENDIAN,
 256     .valid = {
 257         .min_access_size = 4,
 258         .max_access_size = 4,
 259     },
 260 };
 261
 262 static void power_realize(DeviceState *dev, Error **errp)
 263 {
 264     PowerDevice *d = SUN4U_POWER(dev);
 265     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 266
 267     memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
 268                           "power", sizeof(uint32_t));
 269
 270     sysbus_init_mmio(sbd, &d->power_mmio);
 271 }
 272
 273 static void power_class_init(ObjectClass *klass, void *data)
 274 {
 275     DeviceClass *dc = DEVICE_CLASS(klass);
 276
 277     dc->realize = power_realize;
 278 }
 279
 280 static const TypeInfo power_info = {
 281     .name          = TYPE_SUN4U_POWER,
 282     .parent        = TYPE_SYS_BUS_DEVICE,
 283     .instance_size = sizeof(PowerDevice),
 284     .class_init    = power_class_init,
 285 };
 286
 287 static void ebus_isa_irq_handler(void *opaque, int n, int level)
 288 {
 289     EbusState *s = EBUS(opaque);
 290     qemu_irq irq = s->isa_bus_irqs[n];
 291
 292     /* Pass ISA bus IRQs onto their gpio equivalent */
 293     trace_ebus_isa_irq_handler(n, level);
 294     if (irq) {
 295         qemu_set_irq(irq, level);
 296     }
 297 }
 298
 299 /* EBUS (Eight bit bus) bridge */
 300 static void ebus_realize(PCIDevice *pci_dev, Error **errp)
 301 {
 302     EbusState *s = EBUS(pci_dev);
 303     SysBusDevice *sbd;
 304     DeviceState *dev;
 305     qemu_irq *isa_irq;
 306     DriveInfo *fd[MAX_FD];
 307     int i;
 308
 309     s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
 310                              pci_address_space_io(pci_dev), errp);
 311     if (!s->isa_bus) {
 312         error_setg(errp, "unable to instantiate EBUS ISA bus");
 313         return;
 314     }
 315
 316     /* ISA bus */
 317     isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
 318     isa_bus_irqs(s->isa_bus, isa_irq);
 319     qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
 320                              ISA_NUM_IRQS);
 321
 322     /* Serial ports */
 323     i = 0;
 324     if (s->console_serial_base) {
 325         serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
 326                        0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
 327         i++;
 328     }
 329     serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
 330
 331     /* Parallel ports */
 332     parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
 333
 334     /* Keyboard */
 335     isa_create_simple(s->isa_bus, "i8042");
 336
 337     /* Floppy */
 338     for (i = 0; i < MAX_FD; i++) {
 339         fd[i] = drive_get(IF_FLOPPY, 0, i);
 340     }
 341     dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
 342     if (fd[0]) {
 343         qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
 344                             &error_abort);
 345     }
 346     if (fd[1]) {
 347         qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
 348                             &error_abort);
 349     }
 350     qdev_prop_set_uint32(dev, "dma", -1);
 351     qdev_init_nofail(dev);
 352
 353     /* Power */
 354     dev = qdev_create(NULL, TYPE_SUN4U_POWER);
 355     qdev_init_nofail(dev);
 356     sbd = SYS_BUS_DEVICE(dev);
 357     memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
 358                                 sysbus_mmio_get_region(sbd, 0));
 359
 360     /* PCI */
 361     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 362     pci_dev->config[0x05] = 0x00;
 363     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 364     pci_dev->config[0x07] = 0x03; // status = medium devsel
 365     pci_dev->config[0x09] = 0x00; // programming i/f
 366     pci_dev->config[0x0D] = 0x0a; // latency_timer
 367
 368     memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
 369                              0, 0x1000000);
 370     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 371     memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
 372                              0, 0x8000);
 373     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
 374 }
 375
 376 static Property ebus_properties[] = {
 377     DEFINE_PROP_UINT64("console-serial-base", EbusState,
 378                        console_serial_base, 0),
 379     DEFINE_PROP_END_OF_LIST(),
 380 };
 381
 382 static void ebus_class_init(ObjectClass *klass, void *data)
 383 {
 384     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 385     DeviceClass *dc = DEVICE_CLASS(klass);
 386
 387     k->realize = ebus_realize;
 388     k->vendor_id = PCI_VENDOR_ID_SUN;
 389     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 390     k->revision = 0x01;
 391     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 392     dc->props = ebus_properties;
 393 }
 394
 395 static const TypeInfo ebus_info = {
 396     .name          = TYPE_EBUS,
 397     .parent        = TYPE_PCI_DEVICE,
 398     .class_init    = ebus_class_init,
 399     .instance_size = sizeof(EbusState),
 400     .interfaces = (InterfaceInfo[]) {
 401         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 402         { },
 403     },
 404 };
 405
 406 #define TYPE_OPENPROM "openprom"
 407 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
 408
 409 typedef struct PROMState {
 410     SysBusDevice parent_obj;
 411
 412     MemoryRegion prom;
 413 } PROMState;
 414
 415 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 416 {
 417     hwaddr *base_addr = (hwaddr *)opaque;
 418     return addr + *base_addr - PROM_VADDR;
 419 }
 420
 421 /* Boot PROM (OpenBIOS) */
 422 static void prom_init(hwaddr addr, const char *bios_name)
 423 {
 424     DeviceState *dev;
 425     SysBusDevice *s;
 426     char *filename;
 427     int ret;
 428
 429     dev = qdev_create(NULL, TYPE_OPENPROM);
 430     qdev_init_nofail(dev);
 431     s = SYS_BUS_DEVICE(dev);
 432
 433     sysbus_mmio_map(s, 0, addr);
 434
 435     /* load boot prom */
 436     if (bios_name == NULL) {
 437         bios_name = PROM_FILENAME;
 438     }
 439     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 440     if (filename) {
 441         ret = load_elf(filename, NULL, translate_prom_address, &addr,
 442                        NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
 443         if (ret < 0 || ret > PROM_SIZE_MAX) {
 444             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 445         }
 446         g_free(filename);
 447     } else {
 448         ret = -1;
 449     }
 450     if (ret < 0 || ret > PROM_SIZE_MAX) {
 451         error_report("could not load prom '%s'", bios_name);
 452         exit(1);
 453     }
 454 }
 455
 456 static void prom_realize(DeviceState *ds, Error **errp)
 457 {
 458     PROMState *s = OPENPROM(ds);
 459     SysBusDevice *dev = SYS_BUS_DEVICE(ds);
 460     Error *local_err = NULL;
 461
 462     memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
 463                                      PROM_SIZE_MAX, &local_err);
 464     if (local_err) {
 465         error_propagate(errp, local_err);
 466         return;
 467     }
 468
 469     vmstate_register_ram_global(&s->prom);
 470     memory_region_set_readonly(&s->prom, true);
 471     sysbus_init_mmio(dev, &s->prom);
 472 }
 473
 474 static Property prom_properties[] = {
 475     {/* end of property list */},
 476 };
 477
 478 static void prom_class_init(ObjectClass *klass, void *data)
 479 {
 480     DeviceClass *dc = DEVICE_CLASS(klass);
 481
 482     dc->props = prom_properties;
 483     dc->realize = prom_realize;
 484 }
 485
 486 static const TypeInfo prom_info = {
 487     .name          = TYPE_OPENPROM,
 488     .parent        = TYPE_SYS_BUS_DEVICE,
 489     .instance_size = sizeof(PROMState),
 490     .class_init    = prom_class_init,
 491 };
 492
 493
 494 #define TYPE_SUN4U_MEMORY "memory"
 495 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
 496
 497 typedef struct RamDevice {
 498     SysBusDevice parent_obj;
 499
 500     MemoryRegion ram;
 501     uint64_t size;
 502 } RamDevice;
 503
 504 /* System RAM */
 505 static void ram_realize(DeviceState *dev, Error **errp)
 506 {
 507     RamDevice *d = SUN4U_RAM(dev);
 508     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 509
 510     memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
 511                            &error_fatal);
 512     vmstate_register_ram_global(&d->ram);
 513     sysbus_init_mmio(sbd, &d->ram);
 514 }
 515
 516 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
 517 {
 518     DeviceState *dev;
 519     SysBusDevice *s;
 520     RamDevice *d;
 521
 522     /* allocate RAM */
 523     dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
 524     s = SYS_BUS_DEVICE(dev);
 525
 526     d = SUN4U_RAM(dev);
 527     d->size = RAM_size;
 528     qdev_init_nofail(dev);
 529
 530     sysbus_mmio_map(s, 0, addr);
 531 }
 532
 533 static Property ram_properties[] = {
 534     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 535     DEFINE_PROP_END_OF_LIST(),
 536 };
 537
 538 static void ram_class_init(ObjectClass *klass, void *data)
 539 {
 540     DeviceClass *dc = DEVICE_CLASS(klass);
 541
 542     dc->realize = ram_realize;
 543     dc->props = ram_properties;
 544 }
 545
 546 static const TypeInfo ram_info = {
 547     .name          = TYPE_SUN4U_MEMORY,
 548     .parent        = TYPE_SYS_BUS_DEVICE,
 549     .instance_size = sizeof(RamDevice),
 550     .class_init    = ram_class_init,
 551 };
 552
 553 static void sun4uv_init(MemoryRegion *address_space_mem,
 554                         MachineState *machine,
 555                         const struct hwdef *hwdef)
 556 {
 557     SPARCCPU *cpu;
 558     Nvram *nvram;
 559     unsigned int i;
 560     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
 561     SabreState *sabre;
 562     PCIBus *pci_bus, *pci_busA, *pci_busB;
 563     PCIDevice *ebus, *pci_dev;
 564     SysBusDevice *s;
 565     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 566     DeviceState *iommu, *dev;
 567     FWCfgState *fw_cfg;
 568     NICInfo *nd;
 569     MACAddr macaddr;
 570     bool onboard_nic;
 571
 572     /* init CPUs */
 573     cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
 574
 575     /* IOMMU */
 576     iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
 577     qdev_init_nofail(iommu);
 578
 579     /* set up devices */
 580     ram_init(0, machine->ram_size);
 581
 582     prom_init(hwdef->prom_addr, bios_name);
 583
 584     /* Init sabre (PCI host bridge) */
 585     sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
 586     qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
 587     qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
 588     object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
 589                              &error_abort);
 590     qdev_init_nofail(DEVICE(sabre));
 591
 592     /* Wire up PCI interrupts to CPU */
 593     for (i = 0; i < IVEC_MAX; i++) {
 594         qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
 595             qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
 596     }
 597
 598     pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
 599     pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
 600     pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
 601
 602     /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
 603        reserved (leaving no slots free after on-board devices) however slots
 604        0-3 are free on busB */
 605     pci_bus->slot_reserved_mask = 0xfffffffc;
 606     pci_busA->slot_reserved_mask = 0xfffffff1;
 607     pci_busB->slot_reserved_mask = 0xfffffff0;
 608
 609     ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
 610     qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
 611                          hwdef->console_serial_base);
 612     qdev_init_nofail(DEVICE(ebus));
 613
 614     /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
 615     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
 616         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
 617     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
 618         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
 619     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
 620         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
 621     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
 622         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
 623     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
 624         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
 625
 626     switch (vga_interface_type) {
 627     case VGA_STD:
 628         pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
 629         break;
 630     case VGA_NONE:
 631         break;
 632     default:
 633         abort();   /* Should not happen - types are checked in vl.c already */
 634     }
 635
 636     memset(&macaddr, 0, sizeof(MACAddr));
 637     onboard_nic = false;
 638     for (i = 0; i < nb_nics; i++) {
 639         nd = &nd_table[i];
 640
 641         if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
 642             if (!onboard_nic) {
 643                 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
 644                                                    true, "sunhme");
 645                 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
 646                 onboard_nic = true;
 647             } else {
 648                 pci_dev = pci_create(pci_busB, -1, "sunhme");
 649             }
 650         } else {
 651             pci_dev = pci_create(pci_busB, -1, nd->model);
 652         }
 653
 654         dev = &pci_dev->qdev;
 655         qdev_set_nic_properties(dev, nd);
 656         qdev_init_nofail(dev);
 657     }
 658
 659     /* If we don't have an onboard NIC, grab a default MAC address so that
 660      * we have a valid machine id */
 661     if (!onboard_nic) {
 662         qemu_macaddr_default_if_unset(&macaddr);
 663     }
 664
 665     ide_drive_get(hd, ARRAY_SIZE(hd));
 666
 667     pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
 668     qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
 669     qdev_init_nofail(&pci_dev->qdev);
 670     pci_ide_create_devs(pci_dev, hd);
 671
 672     /* Map NVRAM into I/O (ebus) space */
 673     nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
 674     s = SYS_BUS_DEVICE(nvram);
 675     memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
 676                                 sysbus_mmio_get_region(s, 0));
 677
 678     initrd_size = 0;
 679     initrd_addr = 0;
 680     kernel_size = sun4u_load_kernel(machine->kernel_filename,
 681                                     machine->initrd_filename,
 682                                     ram_size, &initrd_size, &initrd_addr,
 683                                     &kernel_addr, &kernel_entry);
 684
 685     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
 686                            machine->boot_order,
 687                            kernel_addr, kernel_size,
 688                            machine->kernel_cmdline,
 689                            initrd_addr, initrd_size,
 690                            /* XXX: need an option to load a NVRAM image */
 691                            0,
 692                            graphic_width, graphic_height, graphic_depth,
 693                            (uint8_t *)&macaddr);
 694
 695     dev = qdev_create(NULL, TYPE_FW_CFG_IO);
 696     qdev_prop_set_bit(dev, "dma_enabled", false);
 697     object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
 698     qdev_init_nofail(dev);
 699     memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
 700                                 &FW_CFG_IO(dev)->comb_iomem);
 701
 702     fw_cfg = FW_CFG(dev);
 703     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
 704     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
 705     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 706     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 707     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
 708     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 709     if (machine->kernel_cmdline) {
 710         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 711                        strlen(machine->kernel_cmdline) + 1);
 712         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
 713     } else {
 714         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 715     }
 716     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 717     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 718     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
 719
 720     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 721     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 722     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 723
 724     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 725 }
 726
 727 enum {
 728     sun4u_id = 0,
 729     sun4v_id = 64,
 730 };
 731
 732 /*
 733  * Implementation of an interface to adjust firmware path
 734  * for the bootindex property handling.
 735  */
 736 static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
 737                                DeviceState *dev)
 738 {
 739     PCIDevice *pci;
 740     IDEBus *ide_bus;
 741     IDEState *ide_s;
 742     int bus_id;
 743
 744     if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
 745         pci = PCI_DEVICE(dev);
 746
 747         if (PCI_FUNC(pci->devfn)) {
 748             return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
 749                                    PCI_FUNC(pci->devfn));
 750         } else {
 751             return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
 752         }
 753     }
 754
 755     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
 756          ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
 757          ide_s = idebus_active_if(ide_bus);
 758          bus_id = ide_bus->bus_id;
 759
 760          if (ide_s->drive_kind == IDE_CD) {
 761              return g_strdup_printf("ide@%x/cdrom", bus_id);
 762          }
 763
 764          return g_strdup_printf("ide@%x/disk", bus_id);
 765     }
 766
 767     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
 768         return g_strdup("disk");
 769     }
 770
 771     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
 772         return g_strdup("cdrom");
 773     }
 774
 775     if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
 776         return g_strdup("disk");
 777     }
 778
 779     return NULL;
 780 }
 781
 782 static const struct hwdef hwdefs[] = {
 783     /* Sun4u generic PC-like machine */
 784     {
 785         .machine_id = sun4u_id,
 786         .prom_addr = 0x1fff0000000ULL,
 787         .console_serial_base = 0,
 788     },
 789     /* Sun4v generic PC-like machine */
 790     {
 791         .machine_id = sun4v_id,
 792         .prom_addr = 0x1fff0000000ULL,
 793         .console_serial_base = 0,
 794     },
 795 };
 796
 797 /* Sun4u hardware initialisation */
 798 static void sun4u_init(MachineState *machine)
 799 {
 800     sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
 801 }
 802
 803 /* Sun4v hardware initialisation */
 804 static void sun4v_init(MachineState *machine)
 805 {
 806     sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
 807 }
 808
 809 static void sun4u_class_init(ObjectClass *oc, void *data)
 810 {
 811     MachineClass *mc = MACHINE_CLASS(oc);
 812     FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
 813
 814     mc->desc = "Sun4u platform";
 815     mc->init = sun4u_init;
 816     mc->block_default_type = IF_IDE;
 817     mc->max_cpus = 1; /* XXX for now */
 818     mc->is_default = 1;
 819     mc->default_boot_order = "c";
 820     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
 821     mc->ignore_boot_device_suffixes = true;
 822     mc->default_display = "std";
 823     fwc->get_dev_path = sun4u_fw_dev_path;
 824 }
 825
 826 static const TypeInfo sun4u_type = {
 827     .name = MACHINE_TYPE_NAME("sun4u"),
 828     .parent = TYPE_MACHINE,
 829     .class_init = sun4u_class_init,
 830     .interfaces = (InterfaceInfo[]) {
 831         { TYPE_FW_PATH_PROVIDER },
 832         { }
 833     },
 834 };
 835
 836 static void sun4v_class_init(ObjectClass *oc, void *data)
 837 {
 838     MachineClass *mc = MACHINE_CLASS(oc);
 839
 840     mc->desc = "Sun4v platform";
 841     mc->init = sun4v_init;
 842     mc->block_default_type = IF_IDE;
 843     mc->max_cpus = 1; /* XXX for now */
 844     mc->default_boot_order = "c";
 845     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
 846     mc->default_display = "std";
 847 }
 848
 849 static const TypeInfo sun4v_type = {
 850     .name = MACHINE_TYPE_NAME("sun4v"),
 851     .parent = TYPE_MACHINE,
 852     .class_init = sun4v_class_init,
 853 };
 854
 855 static void sun4u_register_types(void)
 856 {
 857     type_register_static(&power_info);
 858     type_register_static(&ebus_info);
 859     type_register_static(&prom_info);
 860     type_register_static(&ram_info);
 861
 862     type_register_static(&sun4u_type);
 863     type_register_static(&sun4v_type);
 864 }
 865
 866 type_init(sun4u_register_types)