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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
[qemu/ar7.git] / target / arm / helper.c
blob138a1f15405eb2e59d6690e715ae796b45cf85b8
1 #include "qemu/osdep.h"
2 #include "target/arm/idau.h"
3 #include "trace.h"
4 #include "cpu.h"
5 #include "internals.h"
6 #include "exec/gdbstub.h"
7 #include "exec/helper-proto.h"
8 #include "qemu/host-utils.h"
9 #include "sysemu/arch_init.h"
10 #include "sysemu/sysemu.h"
11 #include "qemu/bitops.h"
12 #include "qemu/crc32c.h"
13 #include "exec/exec-all.h"
14 #include "exec/cpu_ldst.h"
15 #include "arm_ldst.h"
16 #include <zlib.h> /* For crc32 */
17 #include "exec/semihost.h"
18 #include "sysemu/kvm.h"
19 #include "fpu/softfloat.h"
20 #include "qemu/range.h"
21
22 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
23
24 #ifndef CONFIG_USER_ONLY
25 /* Cacheability and shareability attributes for a memory access */
26 typedef struct ARMCacheAttrs {
27 unsigned int attrs:8; /* as in the MAIR register encoding */
28 unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
29 } ARMCacheAttrs;
30
31 static bool get_phys_addr(CPUARMState *env, target_ulong address,
32 MMUAccessType access_type, ARMMMUIdx mmu_idx,
33 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
34 target_ulong *page_size,
35 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
36
37 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
38 MMUAccessType access_type, ARMMMUIdx mmu_idx,
39 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
40 target_ulong *page_size_ptr,
41 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
42
43 /* Security attributes for an address, as returned by v8m_security_lookup. */
44 typedef struct V8M_SAttributes {
45 bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
46 bool ns;
47 bool nsc;
48 uint8_t sregion;
49 bool srvalid;
50 uint8_t iregion;
51 bool irvalid;
52 } V8M_SAttributes;
53
54 static void v8m_security_lookup(CPUARMState *env, uint32_t address,
55 MMUAccessType access_type, ARMMMUIdx mmu_idx,
56 V8M_SAttributes *sattrs);
57 #endif
58
59 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
60 {
61 int nregs;
62
63 /* VFP data registers are always little-endian. */
64 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
65 if (reg < nregs) {
66 stq_le_p(buf, *aa32_vfp_dreg(env, reg));
67 return 8;
68 }
69 if (arm_feature(env, ARM_FEATURE_NEON)) {
70 /* Aliases for Q regs. */
71 nregs += 16;
72 if (reg < nregs) {
73 uint64_t *q = aa32_vfp_qreg(env, reg - 32);
74 stq_le_p(buf, q[0]);
75 stq_le_p(buf + 8, q[1]);
76 return 16;
77 }
78 }
79 switch (reg - nregs) {
80 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
81 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
82 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
83 }
84 return 0;
85 }
86
87 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
88 {
89 int nregs;
90
91 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
92 if (reg < nregs) {
93 *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
94 return 8;
95 }
96 if (arm_feature(env, ARM_FEATURE_NEON)) {
97 nregs += 16;
98 if (reg < nregs) {
99 uint64_t *q = aa32_vfp_qreg(env, reg - 32);
100 q[0] = ldq_le_p(buf);
101 q[1] = ldq_le_p(buf + 8);
102 return 16;
103 }
104 }
105 switch (reg - nregs) {
106 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
107 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
108 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
109 }
110 return 0;
111 }
112
113 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
114 {
115 switch (reg) {
116 case 0 ... 31:
117 /* 128 bit FP register */
118 {
119 uint64_t *q = aa64_vfp_qreg(env, reg);
120 stq_le_p(buf, q[0]);
121 stq_le_p(buf + 8, q[1]);
122 return 16;
123 }
124 case 32:
125 /* FPSR */
126 stl_p(buf, vfp_get_fpsr(env));
127 return 4;
128 case 33:
129 /* FPCR */
130 stl_p(buf, vfp_get_fpcr(env));
131 return 4;
132 default:
133 return 0;
134 }
135 }
136
137 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
138 {
139 switch (reg) {
140 case 0 ... 31:
141 /* 128 bit FP register */
142 {
143 uint64_t *q = aa64_vfp_qreg(env, reg);
144 q[0] = ldq_le_p(buf);
145 q[1] = ldq_le_p(buf + 8);
146 return 16;
147 }
148 case 32:
149 /* FPSR */
150 vfp_set_fpsr(env, ldl_p(buf));
151 return 4;
152 case 33:
153 /* FPCR */
154 vfp_set_fpcr(env, ldl_p(buf));
155 return 4;
156 default:
157 return 0;
158 }
159 }
160
161 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
162 {
163 assert(ri->fieldoffset);
164 if (cpreg_field_is_64bit(ri)) {
165 return CPREG_FIELD64(env, ri);
166 } else {
167 return CPREG_FIELD32(env, ri);
168 }
169 }
170
171 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
172 uint64_t value)
173 {
174 assert(ri->fieldoffset);
175 if (cpreg_field_is_64bit(ri)) {
176 CPREG_FIELD64(env, ri) = value;
177 } else {
178 CPREG_FIELD32(env, ri) = value;
179 }
180 }
181
182 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
183 {
184 return (char *)env + ri->fieldoffset;
185 }
186
187 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
188 {
189 /* Raw read of a coprocessor register (as needed for migration, etc). */
190 if (ri->type & ARM_CP_CONST) {
191 return ri->resetvalue;
192 } else if (ri->raw_readfn) {
193 return ri->raw_readfn(env, ri);
194 } else if (ri->readfn) {
195 return ri->readfn(env, ri);
196 } else {
197 return raw_read(env, ri);
198 }
199 }
200
201 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
202 uint64_t v)
203 {
204 /* Raw write of a coprocessor register (as needed for migration, etc).
205 * Note that constant registers are treated as write-ignored; the
206 * caller should check for success by whether a readback gives the
207 * value written.
208 */
209 if (ri->type & ARM_CP_CONST) {
210 return;
211 } else if (ri->raw_writefn) {
212 ri->raw_writefn(env, ri, v);
213 } else if (ri->writefn) {
214 ri->writefn(env, ri, v);
215 } else {
216 raw_write(env, ri, v);
217 }
218 }
219
220 static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg)
221 {
222 ARMCPU *cpu = arm_env_get_cpu(env);
223 const ARMCPRegInfo *ri;
224 uint32_t key;
225
226 key = cpu->dyn_xml.cpregs_keys[reg];
227 ri = get_arm_cp_reginfo(cpu->cp_regs, key);
228 if (ri) {
229 if (cpreg_field_is_64bit(ri)) {
230 return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
231 } else {
232 return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
233 }
234 }
235 return 0;
236 }
237
238 static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
239 {
240 return 0;
241 }
242
243 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
244 {
245 /* Return true if the regdef would cause an assertion if you called
246 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
247 * program bug for it not to have the NO_RAW flag).
248 * NB that returning false here doesn't necessarily mean that calling
249 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
250 * read/write access functions which are safe for raw use" from "has
251 * read/write access functions which have side effects but has forgotten
252 * to provide raw access functions".
253 * The tests here line up with the conditions in read/write_raw_cp_reg()
254 * and assertions in raw_read()/raw_write().
255 */
256 if ((ri->type & ARM_CP_CONST) ||
257 ri->fieldoffset ||
258 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
259 return false;
260 }
261 return true;
262 }
263
264 bool write_cpustate_to_list(ARMCPU *cpu)
265 {
266 /* Write the coprocessor state from cpu->env to the (index,value) list. */
267 int i;
268 bool ok = true;
269
270 for (i = 0; i < cpu->cpreg_array_len; i++) {
271 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
272 const ARMCPRegInfo *ri;
273
274 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
275 if (!ri) {
276 ok = false;
277 continue;
278 }
279 if (ri->type & ARM_CP_NO_RAW) {
280 continue;
281 }
282 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
283 }
284 return ok;
285 }
286
287 bool write_list_to_cpustate(ARMCPU *cpu)
288 {
289 int i;
290 bool ok = true;
291
292 for (i = 0; i < cpu->cpreg_array_len; i++) {
293 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
294 uint64_t v = cpu->cpreg_values[i];
295 const ARMCPRegInfo *ri;
296
297 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
298 if (!ri) {
299 ok = false;
300 continue;
301 }
302 if (ri->type & ARM_CP_NO_RAW) {
303 continue;
304 }
305 /* Write value and confirm it reads back as written
306 * (to catch read-only registers and partially read-only
307 * registers where the incoming migration value doesn't match)
308 */
309 write_raw_cp_reg(&cpu->env, ri, v);
310 if (read_raw_cp_reg(&cpu->env, ri) != v) {
311 ok = false;
312 }
313 }
314 return ok;
315 }
316
317 static void add_cpreg_to_list(gpointer key, gpointer opaque)
318 {
319 ARMCPU *cpu = opaque;
320 uint64_t regidx;
321 const ARMCPRegInfo *ri;
322
323 regidx = *(uint32_t *)key;
324 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
325
326 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
327 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
328 /* The value array need not be initialized at this point */
329 cpu->cpreg_array_len++;
330 }
331 }
332
333 static void count_cpreg(gpointer key, gpointer opaque)
334 {
335 ARMCPU *cpu = opaque;
336 uint64_t regidx;
337 const ARMCPRegInfo *ri;
338
339 regidx = *(uint32_t *)key;
340 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
341
342 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
343 cpu->cpreg_array_len++;
344 }
345 }
346
347 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
348 {
349 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
350 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
351
352 if (aidx > bidx) {
353 return 1;
354 }
355 if (aidx < bidx) {
356 return -1;
357 }
358 return 0;
359 }
360
361 void init_cpreg_list(ARMCPU *cpu)
362 {
363 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
364 * Note that we require cpreg_tuples[] to be sorted by key ID.
365 */
366 GList *keys;
367 int arraylen;
368
369 keys = g_hash_table_get_keys(cpu->cp_regs);
370 keys = g_list_sort(keys, cpreg_key_compare);
371
372 cpu->cpreg_array_len = 0;
373
374 g_list_foreach(keys, count_cpreg, cpu);
375
376 arraylen = cpu->cpreg_array_len;
377 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
378 cpu->cpreg_values = g_new(uint64_t, arraylen);
379 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
380 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
381 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
382 cpu->cpreg_array_len = 0;
383
384 g_list_foreach(keys, add_cpreg_to_list, cpu);
385
386 assert(cpu->cpreg_array_len == arraylen);
387
388 g_list_free(keys);
389 }
390
391 /*
392 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
393 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
394 *
395 * access_el3_aa32ns: Used to check AArch32 register views.
396 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
397 */
398 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
399 const ARMCPRegInfo *ri,
400 bool isread)
401 {
402 bool secure = arm_is_secure_below_el3(env);
403
404 assert(!arm_el_is_aa64(env, 3));
405 if (secure) {
406 return CP_ACCESS_TRAP_UNCATEGORIZED;
407 }
408 return CP_ACCESS_OK;
409 }
410
411 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
412 const ARMCPRegInfo *ri,
413 bool isread)
414 {
415 if (!arm_el_is_aa64(env, 3)) {
416 return access_el3_aa32ns(env, ri, isread);
417 }
418 return CP_ACCESS_OK;
419 }
420
421 /* Some secure-only AArch32 registers trap to EL3 if used from
422 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
423 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
424 * We assume that the .access field is set to PL1_RW.
425 */
426 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
427 const ARMCPRegInfo *ri,
428 bool isread)
429 {
430 if (arm_current_el(env) == 3) {
431 return CP_ACCESS_OK;
432 }
433 if (arm_is_secure_below_el3(env)) {
434 return CP_ACCESS_TRAP_EL3;
435 }
436 /* This will be EL1 NS and EL2 NS, which just UNDEF */
437 return CP_ACCESS_TRAP_UNCATEGORIZED;
438 }
439
440 /* Check for traps to "powerdown debug" registers, which are controlled
441 * by MDCR.TDOSA
442 */
443 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
444 bool isread)
445 {
446 int el = arm_current_el(env);
447 bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) ||
448 (env->cp15.mdcr_el2 & MDCR_TDE) ||
449 (env->cp15.hcr_el2 & HCR_TGE);
450
451 if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) {
452 return CP_ACCESS_TRAP_EL2;
453 }
454 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
455 return CP_ACCESS_TRAP_EL3;
456 }
457 return CP_ACCESS_OK;
458 }
459
460 /* Check for traps to "debug ROM" registers, which are controlled
461 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
462 */
463 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
464 bool isread)
465 {
466 int el = arm_current_el(env);
467 bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) ||
468 (env->cp15.mdcr_el2 & MDCR_TDE) ||
469 (env->cp15.hcr_el2 & HCR_TGE);
470
471 if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) {
472 return CP_ACCESS_TRAP_EL2;
473 }
474 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
475 return CP_ACCESS_TRAP_EL3;
476 }
477 return CP_ACCESS_OK;
478 }
479
480 /* Check for traps to general debug registers, which are controlled
481 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
482 */
483 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
484 bool isread)
485 {
486 int el = arm_current_el(env);
487 bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) ||
488 (env->cp15.mdcr_el2 & MDCR_TDE) ||
489 (env->cp15.hcr_el2 & HCR_TGE);
490
491 if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) {
492 return CP_ACCESS_TRAP_EL2;
493 }
494 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
495 return CP_ACCESS_TRAP_EL3;
496 }
497 return CP_ACCESS_OK;
498 }
499
500 /* Check for traps to performance monitor registers, which are controlled
501 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
502 */
503 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
504 bool isread)
505 {
506 int el = arm_current_el(env);
507
508 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
509 && !arm_is_secure_below_el3(env)) {
510 return CP_ACCESS_TRAP_EL2;
511 }
512 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
513 return CP_ACCESS_TRAP_EL3;
514 }
515 return CP_ACCESS_OK;
516 }
517
518 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
519 {
520 ARMCPU *cpu = arm_env_get_cpu(env);
521
522 raw_write(env, ri, value);
523 tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */
524 }
525
526 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
527 {
528 ARMCPU *cpu = arm_env_get_cpu(env);
529
530 if (raw_read(env, ri) != value) {
531 /* Unlike real hardware the qemu TLB uses virtual addresses,
532 * not modified virtual addresses, so this causes a TLB flush.
533 */
534 tlb_flush(CPU(cpu));
535 raw_write(env, ri, value);
536 }
537 }
538
539 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
540 uint64_t value)
541 {
542 ARMCPU *cpu = arm_env_get_cpu(env);
543
544 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
545 && !extended_addresses_enabled(env)) {
546 /* For VMSA (when not using the LPAE long descriptor page table
547 * format) this register includes the ASID, so do a TLB flush.
548 * For PMSA it is purely a process ID and no action is needed.
549 */
550 tlb_flush(CPU(cpu));
551 }
552 raw_write(env, ri, value);
553 }
554
555 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
556 uint64_t value)
557 {
558 /* Invalidate all (TLBIALL) */
559 ARMCPU *cpu = arm_env_get_cpu(env);
560
561 tlb_flush(CPU(cpu));
562 }
563
564 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
565 uint64_t value)
566 {
567 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
568 ARMCPU *cpu = arm_env_get_cpu(env);
569
570 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
571 }
572
573 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
574 uint64_t value)
575 {
576 /* Invalidate by ASID (TLBIASID) */
577 ARMCPU *cpu = arm_env_get_cpu(env);
578
579 tlb_flush(CPU(cpu));
580 }
581
582 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
583 uint64_t value)
584 {
585 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
586 ARMCPU *cpu = arm_env_get_cpu(env);
587
588 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
589 }
590
591 /* IS variants of TLB operations must affect all cores */
592 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
593 uint64_t value)
594 {
595 CPUState *cs = ENV_GET_CPU(env);
596
597 tlb_flush_all_cpus_synced(cs);
598 }
599
600 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
601 uint64_t value)
602 {
603 CPUState *cs = ENV_GET_CPU(env);
604
605 tlb_flush_all_cpus_synced(cs);
606 }
607
608 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
609 uint64_t value)
610 {
611 CPUState *cs = ENV_GET_CPU(env);
612
613 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
614 }
615
616 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
617 uint64_t value)
618 {
619 CPUState *cs = ENV_GET_CPU(env);
620
621 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
622 }
623
624 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
625 uint64_t value)
626 {
627 CPUState *cs = ENV_GET_CPU(env);
628
629 tlb_flush_by_mmuidx(cs,
630 ARMMMUIdxBit_S12NSE1 |
631 ARMMMUIdxBit_S12NSE0 |
632 ARMMMUIdxBit_S2NS);
633 }
634
635 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
636 uint64_t value)
637 {
638 CPUState *cs = ENV_GET_CPU(env);
639
640 tlb_flush_by_mmuidx_all_cpus_synced(cs,
641 ARMMMUIdxBit_S12NSE1 |
642 ARMMMUIdxBit_S12NSE0 |
643 ARMMMUIdxBit_S2NS);
644 }
645
646 static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
647 uint64_t value)
648 {
649 /* Invalidate by IPA. This has to invalidate any structures that
650 * contain only stage 2 translation information, but does not need
651 * to apply to structures that contain combined stage 1 and stage 2
652 * translation information.
653 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
654 */
655 CPUState *cs = ENV_GET_CPU(env);
656 uint64_t pageaddr;
657
658 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
659 return;
660 }
661
662 pageaddr = sextract64(value << 12, 0, 40);
663
664 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS);
665 }
666
667 static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
668 uint64_t value)
669 {
670 CPUState *cs = ENV_GET_CPU(env);
671 uint64_t pageaddr;
672
673 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
674 return;
675 }
676
677 pageaddr = sextract64(value << 12, 0, 40);
678
679 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
680 ARMMMUIdxBit_S2NS);
681 }
682
683 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
684 uint64_t value)
685 {
686 CPUState *cs = ENV_GET_CPU(env);
687
688 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
689 }
690
691 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
692 uint64_t value)
693 {
694 CPUState *cs = ENV_GET_CPU(env);
695
696 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
697 }
698
699 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
700 uint64_t value)
701 {
702 CPUState *cs = ENV_GET_CPU(env);
703 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
704
705 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
706 }
707
708 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
709 uint64_t value)
710 {
711 CPUState *cs = ENV_GET_CPU(env);
712 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
713
714 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
715 ARMMMUIdxBit_S1E2);
716 }
717
718 static const ARMCPRegInfo cp_reginfo[] = {
719 /* Define the secure and non-secure FCSE identifier CP registers
720 * separately because there is no secure bank in V8 (no _EL3). This allows
721 * the secure register to be properly reset and migrated. There is also no
722 * v8 EL1 version of the register so the non-secure instance stands alone.
723 */
724 { .name = "FCSEIDR",
725 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
726 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
727 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
728 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
729 { .name = "FCSEIDR_S",
730 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
731 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
732 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
733 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
734 /* Define the secure and non-secure context identifier CP registers
735 * separately because there is no secure bank in V8 (no _EL3). This allows
736 * the secure register to be properly reset and migrated. In the
737 * non-secure case, the 32-bit register will have reset and migration
738 * disabled during registration as it is handled by the 64-bit instance.
739 */
740 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
741 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
742 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
743 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
744 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
745 { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32,
746 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
747 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
748 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
749 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
750 REGINFO_SENTINEL
751 };
752
753 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
754 /* NB: Some of these registers exist in v8 but with more precise
755 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
756 */
757 /* MMU Domain access control / MPU write buffer control */
758 { .name = "DACR",
759 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
760 .access = PL1_RW, .resetvalue = 0,
761 .writefn = dacr_write, .raw_writefn = raw_write,
762 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
763 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
764 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
765 * For v6 and v5, these mappings are overly broad.
766 */
767 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
768 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
769 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
770 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
771 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
772 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
773 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
774 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
775 /* Cache maintenance ops; some of this space may be overridden later. */
776 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
777 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
778 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
779 REGINFO_SENTINEL
780 };
781
782 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
783 /* Not all pre-v6 cores implemented this WFI, so this is slightly
784 * over-broad.
785 */
786 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
787 .access = PL1_W, .type = ARM_CP_WFI },
788 REGINFO_SENTINEL
789 };
790
791 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
792 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
793 * is UNPREDICTABLE; we choose to NOP as most implementations do).
794 */
795 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
796 .access = PL1_W, .type = ARM_CP_WFI },
797 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
798 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
799 * OMAPCP will override this space.
800 */
801 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
802 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
803 .resetvalue = 0 },
804 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
805 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
806 .resetvalue = 0 },
807 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
808 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
809 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
810 .resetvalue = 0 },
811 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
812 * implementing it as RAZ means the "debug architecture version" bits
813 * will read as a reserved value, which should cause Linux to not try
814 * to use the debug hardware.
815 */
816 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
817 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
818 /* MMU TLB control. Note that the wildcarding means we cover not just
819 * the unified TLB ops but also the dside/iside/inner-shareable variants.
820 */
821 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
822 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
823 .type = ARM_CP_NO_RAW },
824 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
825 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
826 .type = ARM_CP_NO_RAW },
827 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
828 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
829 .type = ARM_CP_NO_RAW },
830 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
831 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
832 .type = ARM_CP_NO_RAW },
833 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
834 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
835 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
836 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
837 REGINFO_SENTINEL
838 };
839
840 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
841 uint64_t value)
842 {
843 uint32_t mask = 0;
844
845 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
846 if (!arm_feature(env, ARM_FEATURE_V8)) {
847 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
848 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
849 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
850 */
851 if (arm_feature(env, ARM_FEATURE_VFP)) {
852 /* VFP coprocessor: cp10 & cp11 [23:20] */
853 mask |= (1 << 31) | (1 << 30) | (0xf << 20);
854
855 if (!arm_feature(env, ARM_FEATURE_NEON)) {
856 /* ASEDIS [31] bit is RAO/WI */
857 value |= (1 << 31);
858 }
859
860 /* VFPv3 and upwards with NEON implement 32 double precision
861 * registers (D0-D31).
862 */
863 if (!arm_feature(env, ARM_FEATURE_NEON) ||
864 !arm_feature(env, ARM_FEATURE_VFP3)) {
865 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
866 value |= (1 << 30);
867 }
868 }
869 value &= mask;
870 }
871 env->cp15.cpacr_el1 = value;
872 }
873
874 static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
875 {
876 /* Call cpacr_write() so that we reset with the correct RAO bits set
877 * for our CPU features.
878 */
879 cpacr_write(env, ri, 0);
880 }
881
882 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
883 bool isread)
884 {
885 if (arm_feature(env, ARM_FEATURE_V8)) {
886 /* Check if CPACR accesses are to be trapped to EL2 */
887 if (arm_current_el(env) == 1 &&
888 (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
889 return CP_ACCESS_TRAP_EL2;
890 /* Check if CPACR accesses are to be trapped to EL3 */
891 } else if (arm_current_el(env) < 3 &&
892 (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
893 return CP_ACCESS_TRAP_EL3;
894 }
895 }
896
897 return CP_ACCESS_OK;
898 }
899
900 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
901 bool isread)
902 {
903 /* Check if CPTR accesses are set to trap to EL3 */
904 if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
905 return CP_ACCESS_TRAP_EL3;
906 }
907
908 return CP_ACCESS_OK;
909 }
910
911 static const ARMCPRegInfo v6_cp_reginfo[] = {
912 /* prefetch by MVA in v6, NOP in v7 */
913 { .name = "MVA_prefetch",
914 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
915 .access = PL1_W, .type = ARM_CP_NOP },
916 /* We need to break the TB after ISB to execute self-modifying code
917 * correctly and also to take any pending interrupts immediately.
918 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
919 */
920 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
921 .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
922 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
923 .access = PL0_W, .type = ARM_CP_NOP },
924 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
925 .access = PL0_W, .type = ARM_CP_NOP },
926 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
927 .access = PL1_RW,
928 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
929 offsetof(CPUARMState, cp15.ifar_ns) },
930 .resetvalue = 0, },
931 /* Watchpoint Fault Address Register : should actually only be present
932 * for 1136, 1176, 11MPCore.
933 */
934 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
935 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
936 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
937 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
938 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
939 .resetfn = cpacr_reset, .writefn = cpacr_write },
940 REGINFO_SENTINEL
941 };
942
943 /* Definitions for the PMU registers */
944 #define PMCRN_MASK 0xf800
945 #define PMCRN_SHIFT 11
946 #define PMCRD 0x8
947 #define PMCRC 0x4
948 #define PMCRE 0x1
949
950 static inline uint32_t pmu_num_counters(CPUARMState *env)
951 {
952 return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
953 }
954
955 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
956 static inline uint64_t pmu_counter_mask(CPUARMState *env)
957 {
958 return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
959 }
960
961 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
962 bool isread)
963 {
964 /* Performance monitor registers user accessibility is controlled
965 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
966 * trapping to EL2 or EL3 for other accesses.
967 */
968 int el = arm_current_el(env);
969
970 if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
971 return CP_ACCESS_TRAP;
972 }
973 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
974 && !arm_is_secure_below_el3(env)) {
975 return CP_ACCESS_TRAP_EL2;
976 }
977 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
978 return CP_ACCESS_TRAP_EL3;
979 }
980
981 return CP_ACCESS_OK;
982 }
983
984 static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
985 const ARMCPRegInfo *ri,
986 bool isread)
987 {
988 /* ER: event counter read trap control */
989 if (arm_feature(env, ARM_FEATURE_V8)
990 && arm_current_el(env) == 0
991 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0
992 && isread) {
993 return CP_ACCESS_OK;
994 }
995
996 return pmreg_access(env, ri, isread);
997 }
998
999 static CPAccessResult pmreg_access_swinc(CPUARMState *env,
1000 const ARMCPRegInfo *ri,
1001 bool isread)
1002 {
1003 /* SW: software increment write trap control */
1004 if (arm_feature(env, ARM_FEATURE_V8)
1005 && arm_current_el(env) == 0
1006 && (env->cp15.c9_pmuserenr & (1 << 1)) != 0
1007 && !isread) {
1008 return CP_ACCESS_OK;
1009 }
1010
1011 return pmreg_access(env, ri, isread);
1012 }
1013
1014 #ifndef CONFIG_USER_ONLY
1015
1016 static CPAccessResult pmreg_access_selr(CPUARMState *env,
1017 const ARMCPRegInfo *ri,
1018 bool isread)
1019 {
1020 /* ER: event counter read trap control */
1021 if (arm_feature(env, ARM_FEATURE_V8)
1022 && arm_current_el(env) == 0
1023 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) {
1024 return CP_ACCESS_OK;
1025 }
1026
1027 return pmreg_access(env, ri, isread);
1028 }
1029
1030 static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
1031 const ARMCPRegInfo *ri,
1032 bool isread)
1033 {
1034 /* CR: cycle counter read trap control */
1035 if (arm_feature(env, ARM_FEATURE_V8)
1036 && arm_current_el(env) == 0
1037 && (env->cp15.c9_pmuserenr & (1 << 2)) != 0
1038 && isread) {
1039 return CP_ACCESS_OK;
1040 }
1041
1042 return pmreg_access(env, ri, isread);
1043 }
1044
1045 static inline bool arm_ccnt_enabled(CPUARMState *env)
1046 {
1047 /* This does not support checking PMCCFILTR_EL0 register */
1048
1049 if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31))) {
1050 return false;
1051 }
1052
1053 return true;
1054 }
1055
1056 void pmccntr_sync(CPUARMState *env)
1057 {
1058 uint64_t temp_ticks;
1059
1060 temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
1061 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
1062
1063 if (env->cp15.c9_pmcr & PMCRD) {
1064 /* Increment once every 64 processor clock cycles */
1065 temp_ticks /= 64;
1066 }
1067
1068 if (arm_ccnt_enabled(env)) {
1069 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
1070 }
1071 }
1072
1073 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1074 uint64_t value)
1075 {
1076 pmccntr_sync(env);
1077
1078 if (value & PMCRC) {
1079 /* The counter has been reset */
1080 env->cp15.c15_ccnt = 0;
1081 }
1082
1083 /* only the DP, X, D and E bits are writable */
1084 env->cp15.c9_pmcr &= ~0x39;
1085 env->cp15.c9_pmcr |= (value & 0x39);
1086
1087 pmccntr_sync(env);
1088 }
1089
1090 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1091 {
1092 uint64_t total_ticks;
1093
1094 if (!arm_ccnt_enabled(env)) {
1095 /* Counter is disabled, do not change value */
1096 return env->cp15.c15_ccnt;
1097 }
1098
1099 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
1100 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
1101
1102 if (env->cp15.c9_pmcr & PMCRD) {
1103 /* Increment once every 64 processor clock cycles */
1104 total_ticks /= 64;
1105 }
1106 return total_ticks - env->cp15.c15_ccnt;
1107 }
1108
1109 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1110 uint64_t value)
1111 {
1112 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1113 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1114 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1115 * accessed.
1116 */
1117 env->cp15.c9_pmselr = value & 0x1f;
1118 }
1119
1120 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1121 uint64_t value)
1122 {
1123 uint64_t total_ticks;
1124
1125 if (!arm_ccnt_enabled(env)) {
1126 /* Counter is disabled, set the absolute value */
1127 env->cp15.c15_ccnt = value;
1128 return;
1129 }
1130
1131 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
1132 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
1133
1134 if (env->cp15.c9_pmcr & PMCRD) {
1135 /* Increment once every 64 processor clock cycles */
1136 total_ticks /= 64;
1137 }
1138 env->cp15.c15_ccnt = total_ticks - value;
1139 }
1140
1141 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
1142 uint64_t value)
1143 {
1144 uint64_t cur_val = pmccntr_read(env, NULL);
1145
1146 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
1147 }
1148
1149 #else /* CONFIG_USER_ONLY */
1150
1151 void pmccntr_sync(CPUARMState *env)
1152 {
1153 }
1154
1155 #endif
1156
1157 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1158 uint64_t value)
1159 {
1160 pmccntr_sync(env);
1161 env->cp15.pmccfiltr_el0 = value & 0xfc000000;
1162 pmccntr_sync(env);
1163 }
1164
1165 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1166 uint64_t value)
1167 {
1168 value &= pmu_counter_mask(env);
1169 env->cp15.c9_pmcnten |= value;
1170 }
1171
1172 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1173 uint64_t value)
1174 {
1175 value &= pmu_counter_mask(env);
1176 env->cp15.c9_pmcnten &= ~value;
1177 }
1178
1179 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1180 uint64_t value)
1181 {
1182 env->cp15.c9_pmovsr &= ~value;
1183 }
1184
1185 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
1186 uint64_t value)
1187 {
1188 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1189 * PMSELR value is equal to or greater than the number of implemented
1190 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1191 */
1192 if (env->cp15.c9_pmselr == 0x1f) {
1193 pmccfiltr_write(env, ri, value);
1194 }
1195 }
1196
1197 static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
1198 {
1199 /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1200 * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
1201 */
1202 if (env->cp15.c9_pmselr == 0x1f) {
1203 return env->cp15.pmccfiltr_el0;
1204 } else {
1205 return 0;
1206 }
1207 }
1208
1209 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1210 uint64_t value)
1211 {
1212 if (arm_feature(env, ARM_FEATURE_V8)) {
1213 env->cp15.c9_pmuserenr = value & 0xf;
1214 } else {
1215 env->cp15.c9_pmuserenr = value & 1;
1216 }
1217 }
1218
1219 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1220 uint64_t value)
1221 {
1222 /* We have no event counters so only the C bit can be changed */
1223 value &= pmu_counter_mask(env);
1224 env->cp15.c9_pminten |= value;
1225 }
1226
1227 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1228 uint64_t value)
1229 {
1230 value &= pmu_counter_mask(env);
1231 env->cp15.c9_pminten &= ~value;
1232 }
1233
1234 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1235 uint64_t value)
1236 {
1237 /* Note that even though the AArch64 view of this register has bits
1238 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1239 * architectural requirements for bits which are RES0 only in some
1240 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1241 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1242 */
1243 raw_write(env, ri, value & ~0x1FULL);
1244 }
1245
1246 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1247 {
1248 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
1249 * For bits that vary between AArch32/64, code needs to check the
1250 * current execution mode before directly using the feature bit.
1251 */
1252 uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
1253
1254 if (!arm_feature(env, ARM_FEATURE_EL2)) {
1255 valid_mask &= ~SCR_HCE;
1256
1257 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1258 * supported if EL2 exists. The bit is UNK/SBZP when
1259 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1260 * when EL2 is unavailable.
1261 * On ARMv8, this bit is always available.
1262 */
1263 if (arm_feature(env, ARM_FEATURE_V7) &&
1264 !arm_feature(env, ARM_FEATURE_V8)) {
1265 valid_mask &= ~SCR_SMD;
1266 }
1267 }
1268
1269 /* Clear all-context RES0 bits. */
1270 value &= valid_mask;
1271 raw_write(env, ri, value);
1272 }
1273
1274 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1275 {
1276 ARMCPU *cpu = arm_env_get_cpu(env);
1277
1278 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1279 * bank
1280 */
1281 uint32_t index = A32_BANKED_REG_GET(env, csselr,
1282 ri->secure & ARM_CP_SECSTATE_S);
1283
1284 return cpu->ccsidr[index];
1285 }
1286
1287 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1288 uint64_t value)
1289 {
1290 raw_write(env, ri, value & 0xf);
1291 }
1292
1293 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1294 {
1295 CPUState *cs = ENV_GET_CPU(env);
1296 uint64_t ret = 0;
1297
1298 if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
1299 ret |= CPSR_I;
1300 }
1301 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
1302 ret |= CPSR_F;
1303 }
1304 /* External aborts are not possible in QEMU so A bit is always clear */
1305 return ret;
1306 }
1307
1308 static const ARMCPRegInfo v7_cp_reginfo[] = {
1309 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1310 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
1311 .access = PL1_W, .type = ARM_CP_NOP },
1312 /* Performance monitors are implementation defined in v7,
1313 * but with an ARM recommended set of registers, which we
1314 * follow (although we don't actually implement any counters)
1315 *
1316 * Performance registers fall into three categories:
1317 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1318 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1319 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1320 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1321 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1322 */
1323 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
1324 .access = PL0_RW, .type = ARM_CP_ALIAS,
1325 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1326 .writefn = pmcntenset_write,
1327 .accessfn = pmreg_access,
1328 .raw_writefn = raw_write },
1329 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
1330 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
1331 .access = PL0_RW, .accessfn = pmreg_access,
1332 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
1333 .writefn = pmcntenset_write, .raw_writefn = raw_write },
1334 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
1335 .access = PL0_RW,
1336 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1337 .accessfn = pmreg_access,
1338 .writefn = pmcntenclr_write,
1339 .type = ARM_CP_ALIAS },
1340 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
1341 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
1342 .access = PL0_RW, .accessfn = pmreg_access,
1343 .type = ARM_CP_ALIAS,
1344 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
1345 .writefn = pmcntenclr_write },
1346 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
1347 .access = PL0_RW,
1348 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
1349 .accessfn = pmreg_access,
1350 .writefn = pmovsr_write,
1351 .raw_writefn = raw_write },
1352 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
1353 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
1354 .access = PL0_RW, .accessfn = pmreg_access,
1355 .type = ARM_CP_ALIAS,
1356 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1357 .writefn = pmovsr_write,
1358 .raw_writefn = raw_write },
1359 /* Unimplemented so WI. */
1360 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
1361 .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP },
1362 #ifndef CONFIG_USER_ONLY
1363 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
1364 .access = PL0_RW, .type = ARM_CP_ALIAS,
1365 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
1366 .accessfn = pmreg_access_selr, .writefn = pmselr_write,
1367 .raw_writefn = raw_write},
1368 { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
1369 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
1370 .access = PL0_RW, .accessfn = pmreg_access_selr,
1371 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
1372 .writefn = pmselr_write, .raw_writefn = raw_write, },
1373 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
1374 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
1375 .readfn = pmccntr_read, .writefn = pmccntr_write32,
1376 .accessfn = pmreg_access_ccntr },
1377 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
1378 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
1379 .access = PL0_RW, .accessfn = pmreg_access_ccntr,
1380 .type = ARM_CP_IO,
1381 .readfn = pmccntr_read, .writefn = pmccntr_write, },
1382 #endif
1383 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1384 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
1385 .writefn = pmccfiltr_write,
1386 .access = PL0_RW, .accessfn = pmreg_access,
1387 .type = ARM_CP_IO,
1388 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
1389 .resetvalue = 0, },
1390 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
1391 .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access,
1392 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
1393 { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
1394 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
1395 .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access,
1396 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
1397 /* Unimplemented, RAZ/WI. */
1398 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
1399 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1400 .accessfn = pmreg_access_xevcntr },
1401 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
1402 .access = PL0_R | PL1_RW, .accessfn = access_tpm,
1403 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr),
1404 .resetvalue = 0,
1405 .writefn = pmuserenr_write, .raw_writefn = raw_write },
1406 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
1407 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
1408 .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1409 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1410 .resetvalue = 0,
1411 .writefn = pmuserenr_write, .raw_writefn = raw_write },
1412 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
1413 .access = PL1_RW, .accessfn = access_tpm,
1414 .type = ARM_CP_ALIAS | ARM_CP_IO,
1415 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
1416 .resetvalue = 0,
1417 .writefn = pmintenset_write, .raw_writefn = raw_write },
1418 { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
1419 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
1420 .access = PL1_RW, .accessfn = access_tpm,
1421 .type = ARM_CP_IO,
1422 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1423 .writefn = pmintenset_write, .raw_writefn = raw_write,
1424 .resetvalue = 0x0 },
1425 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
1426 .access = PL1_RW, .accessfn = access_tpm,
1427 .type = ARM_CP_ALIAS | ARM_CP_IO,
1428 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1429 .writefn = pmintenclr_write, },
1430 { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
1431 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
1432 .access = PL1_RW, .accessfn = access_tpm,
1433 .type = ARM_CP_ALIAS | ARM_CP_IO,
1434 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1435 .writefn = pmintenclr_write },
1436 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
1437 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
1438 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
1439 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
1440 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1441 .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1442 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1443 offsetof(CPUARMState, cp15.csselr_ns) } },
1444 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1445 * just RAZ for all cores:
1446 */
1447 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1448 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1449 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1450 /* Auxiliary fault status registers: these also are IMPDEF, and we
1451 * choose to RAZ/WI for all cores.
1452 */
1453 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1454 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1455 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1456 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1457 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1458 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1459 /* MAIR can just read-as-written because we don't implement caches
1460 * and so don't need to care about memory attributes.
1461 */
1462 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1463 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1464 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1465 .resetvalue = 0 },
1466 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1467 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1468 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1469 .resetvalue = 0 },
1470 /* For non-long-descriptor page tables these are PRRR and NMRR;
1471 * regardless they still act as reads-as-written for QEMU.
1472 */
1473 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1474 * allows them to assign the correct fieldoffset based on the endianness
1475 * handled in the field definitions.
1476 */
1477 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1478 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1479 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1480 offsetof(CPUARMState, cp15.mair0_ns) },
1481 .resetfn = arm_cp_reset_ignore },
1482 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1483 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1484 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1485 offsetof(CPUARMState, cp15.mair1_ns) },
1486 .resetfn = arm_cp_reset_ignore },
1487 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1488 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1489 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1490 /* 32 bit ITLB invalidates */
1491 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1492 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1493 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1494 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1495 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1496 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1497 /* 32 bit DTLB invalidates */
1498 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1499 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1500 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1501 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1502 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1503 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1504 /* 32 bit TLB invalidates */
1505 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1506 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1507 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1508 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1509 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1510 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1511 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1512 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1513 REGINFO_SENTINEL
1514 };
1515
1516 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1517 /* 32 bit TLB invalidates, Inner Shareable */
1518 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1519 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1520 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1521 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1522 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1523 .type = ARM_CP_NO_RAW, .access = PL1_W,
1524 .writefn = tlbiasid_is_write },
1525 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1526 .type = ARM_CP_NO_RAW, .access = PL1_W,
1527 .writefn = tlbimvaa_is_write },
1528 REGINFO_SENTINEL
1529 };
1530
1531 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1532 uint64_t value)
1533 {
1534 value &= 1;
1535 env->teecr = value;
1536 }
1537
1538 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1539 bool isread)
1540 {
1541 if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1542 return CP_ACCESS_TRAP;
1543 }
1544 return CP_ACCESS_OK;
1545 }
1546
1547 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1548 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1549 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1550 .resetvalue = 0,
1551 .writefn = teecr_write },
1552 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1553 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1554 .accessfn = teehbr_access, .resetvalue = 0 },
1555 REGINFO_SENTINEL
1556 };
1557
1558 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1559 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1560 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1561 .access = PL0_RW,
1562 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1563 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1564 .access = PL0_RW,
1565 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1566 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1567 .resetfn = arm_cp_reset_ignore },
1568 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1569 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1570 .access = PL0_R|PL1_W,
1571 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1572 .resetvalue = 0},
1573 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1574 .access = PL0_R|PL1_W,
1575 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1576 offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1577 .resetfn = arm_cp_reset_ignore },
1578 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1579 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1580 .access = PL1_RW,
1581 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1582 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1583 .access = PL1_RW,
1584 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1585 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1586 .resetvalue = 0 },
1587 REGINFO_SENTINEL
1588 };
1589
1590 #ifndef CONFIG_USER_ONLY
1591
1592 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
1593 bool isread)
1594 {
1595 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1596 * Writable only at the highest implemented exception level.
1597 */
1598 int el = arm_current_el(env);
1599
1600 switch (el) {
1601 case 0:
1602 if (!extract32(env->cp15.c14_cntkctl, 0, 2)) {
1603 return CP_ACCESS_TRAP;
1604 }
1605 break;
1606 case 1:
1607 if (!isread && ri->state == ARM_CP_STATE_AA32 &&
1608 arm_is_secure_below_el3(env)) {
1609 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1610 return CP_ACCESS_TRAP_UNCATEGORIZED;
1611 }
1612 break;
1613 case 2:
1614 case 3:
1615 break;
1616 }
1617
1618 if (!isread && el < arm_highest_el(env)) {
1619 return CP_ACCESS_TRAP_UNCATEGORIZED;
1620 }
1621
1622 return CP_ACCESS_OK;
1623 }
1624
1625 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
1626 bool isread)
1627 {
1628 unsigned int cur_el = arm_current_el(env);
1629 bool secure = arm_is_secure(env);
1630
1631 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1632 if (cur_el == 0 &&
1633 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1634 return CP_ACCESS_TRAP;
1635 }
1636
1637 if (arm_feature(env, ARM_FEATURE_EL2) &&
1638 timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1639 !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1640 return CP_ACCESS_TRAP_EL2;
1641 }
1642 return CP_ACCESS_OK;
1643 }
1644
1645 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
1646 bool isread)
1647 {
1648 unsigned int cur_el = arm_current_el(env);
1649 bool secure = arm_is_secure(env);
1650
1651 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1652 * EL0[PV]TEN is zero.
1653 */
1654 if (cur_el == 0 &&
1655 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1656 return CP_ACCESS_TRAP;
1657 }
1658
1659 if (arm_feature(env, ARM_FEATURE_EL2) &&
1660 timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1661 !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1662 return CP_ACCESS_TRAP_EL2;
1663 }
1664 return CP_ACCESS_OK;
1665 }
1666
1667 static CPAccessResult gt_pct_access(CPUARMState *env,
1668 const ARMCPRegInfo *ri,
1669 bool isread)
1670 {
1671 return gt_counter_access(env, GTIMER_PHYS, isread);
1672 }
1673
1674 static CPAccessResult gt_vct_access(CPUARMState *env,
1675 const ARMCPRegInfo *ri,
1676 bool isread)
1677 {
1678 return gt_counter_access(env, GTIMER_VIRT, isread);
1679 }
1680
1681 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1682 bool isread)
1683 {
1684 return gt_timer_access(env, GTIMER_PHYS, isread);
1685 }
1686
1687 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1688 bool isread)
1689 {
1690 return gt_timer_access(env, GTIMER_VIRT, isread);
1691 }
1692
1693 static CPAccessResult gt_stimer_access(CPUARMState *env,
1694 const ARMCPRegInfo *ri,
1695 bool isread)
1696 {
1697 /* The AArch64 register view of the secure physical timer is
1698 * always accessible from EL3, and configurably accessible from
1699 * Secure EL1.
1700 */
1701 switch (arm_current_el(env)) {
1702 case 1:
1703 if (!arm_is_secure(env)) {
1704 return CP_ACCESS_TRAP;
1705 }
1706 if (!(env->cp15.scr_el3 & SCR_ST)) {
1707 return CP_ACCESS_TRAP_EL3;
1708 }
1709 return CP_ACCESS_OK;
1710 case 0:
1711 case 2:
1712 return CP_ACCESS_TRAP;
1713 case 3:
1714 return CP_ACCESS_OK;
1715 default:
1716 g_assert_not_reached();
1717 }
1718 }
1719
1720 static uint64_t gt_get_countervalue(CPUARMState *env)
1721 {
1722 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1723 }
1724
1725 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1726 {
1727 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1728
1729 if (gt->ctl & 1) {
1730 /* Timer enabled: calculate and set current ISTATUS, irq, and
1731 * reset timer to when ISTATUS next has to change
1732 */
1733 uint64_t offset = timeridx == GTIMER_VIRT ?
1734 cpu->env.cp15.cntvoff_el2 : 0;
1735 uint64_t count = gt_get_countervalue(&cpu->env);
1736 /* Note that this must be unsigned 64 bit arithmetic: */
1737 int istatus = count - offset >= gt->cval;
1738 uint64_t nexttick;
1739 int irqstate;
1740
1741 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1742
1743 irqstate = (istatus && !(gt->ctl & 2));
1744 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
1745
1746 if (istatus) {
1747 /* Next transition is when count rolls back over to zero */
1748 nexttick = UINT64_MAX;
1749 } else {
1750 /* Next transition is when we hit cval */
1751 nexttick = gt->cval + offset;
1752 }
1753 /* Note that the desired next expiry time might be beyond the
1754 * signed-64-bit range of a QEMUTimer -- in this case we just
1755 * set the timer for as far in the future as possible. When the
1756 * timer expires we will reset the timer for any remaining period.
1757 */
1758 if (nexttick > INT64_MAX / GTIMER_SCALE) {
1759 nexttick = INT64_MAX / GTIMER_SCALE;
1760 }
1761 timer_mod(cpu->gt_timer[timeridx], nexttick);
1762 trace_arm_gt_recalc(timeridx, irqstate, nexttick);
1763 } else {
1764 /* Timer disabled: ISTATUS and timer output always clear */
1765 gt->ctl &= ~4;
1766 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1767 timer_del(cpu->gt_timer[timeridx]);
1768 trace_arm_gt_recalc_disabled(timeridx);
1769 }
1770 }
1771
1772 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1773 int timeridx)
1774 {
1775 ARMCPU *cpu = arm_env_get_cpu(env);
1776
1777 timer_del(cpu->gt_timer[timeridx]);
1778 }
1779
1780 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1781 {
1782 return gt_get_countervalue(env);
1783 }
1784
1785 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1786 {
1787 return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1788 }
1789
1790 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1791 int timeridx,
1792 uint64_t value)
1793 {
1794 trace_arm_gt_cval_write(timeridx, value);
1795 env->cp15.c14_timer[timeridx].cval = value;
1796 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1797 }
1798
1799 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1800 int timeridx)
1801 {
1802 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1803
1804 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1805 (gt_get_countervalue(env) - offset));
1806 }
1807
1808 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1809 int timeridx,
1810 uint64_t value)
1811 {
1812 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1813
1814 trace_arm_gt_tval_write(timeridx, value);
1815 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1816 sextract64(value, 0, 32);
1817 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1818 }
1819
1820 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1821 int timeridx,
1822 uint64_t value)
1823 {
1824 ARMCPU *cpu = arm_env_get_cpu(env);
1825 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1826
1827 trace_arm_gt_ctl_write(timeridx, value);
1828 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1829 if ((oldval ^ value) & 1) {
1830 /* Enable toggled */
1831 gt_recalc_timer(cpu, timeridx);
1832 } else if ((oldval ^ value) & 2) {
1833 /* IMASK toggled: don't need to recalculate,
1834 * just set the interrupt line based on ISTATUS
1835 */
1836 int irqstate = (oldval & 4) && !(value & 2);
1837
1838 trace_arm_gt_imask_toggle(timeridx, irqstate);
1839 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
1840 }
1841 }
1842
1843 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1844 {
1845 gt_timer_reset(env, ri, GTIMER_PHYS);
1846 }
1847
1848 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1849 uint64_t value)
1850 {
1851 gt_cval_write(env, ri, GTIMER_PHYS, value);
1852 }
1853
1854 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1855 {
1856 return gt_tval_read(env, ri, GTIMER_PHYS);
1857 }
1858
1859 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1860 uint64_t value)
1861 {
1862 gt_tval_write(env, ri, GTIMER_PHYS, value);
1863 }
1864
1865 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1866 uint64_t value)
1867 {
1868 gt_ctl_write(env, ri, GTIMER_PHYS, value);
1869 }
1870
1871 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1872 {
1873 gt_timer_reset(env, ri, GTIMER_VIRT);
1874 }
1875
1876 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1877 uint64_t value)
1878 {
1879 gt_cval_write(env, ri, GTIMER_VIRT, value);
1880 }
1881
1882 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1883 {
1884 return gt_tval_read(env, ri, GTIMER_VIRT);
1885 }
1886
1887 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1888 uint64_t value)
1889 {
1890 gt_tval_write(env, ri, GTIMER_VIRT, value);
1891 }
1892
1893 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1894 uint64_t value)
1895 {
1896 gt_ctl_write(env, ri, GTIMER_VIRT, value);
1897 }
1898
1899 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1900 uint64_t value)
1901 {
1902 ARMCPU *cpu = arm_env_get_cpu(env);
1903
1904 trace_arm_gt_cntvoff_write(value);
1905 raw_write(env, ri, value);
1906 gt_recalc_timer(cpu, GTIMER_VIRT);
1907 }
1908
1909 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1910 {
1911 gt_timer_reset(env, ri, GTIMER_HYP);
1912 }
1913
1914 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1915 uint64_t value)
1916 {
1917 gt_cval_write(env, ri, GTIMER_HYP, value);
1918 }
1919
1920 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1921 {
1922 return gt_tval_read(env, ri, GTIMER_HYP);
1923 }
1924
1925 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1926 uint64_t value)
1927 {
1928 gt_tval_write(env, ri, GTIMER_HYP, value);
1929 }
1930
1931 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1932 uint64_t value)
1933 {
1934 gt_ctl_write(env, ri, GTIMER_HYP, value);
1935 }
1936
1937 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1938 {
1939 gt_timer_reset(env, ri, GTIMER_SEC);
1940 }
1941
1942 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1943 uint64_t value)
1944 {
1945 gt_cval_write(env, ri, GTIMER_SEC, value);
1946 }
1947
1948 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1949 {
1950 return gt_tval_read(env, ri, GTIMER_SEC);
1951 }
1952
1953 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1954 uint64_t value)
1955 {
1956 gt_tval_write(env, ri, GTIMER_SEC, value);
1957 }
1958
1959 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1960 uint64_t value)
1961 {
1962 gt_ctl_write(env, ri, GTIMER_SEC, value);
1963 }
1964
1965 void arm_gt_ptimer_cb(void *opaque)
1966 {
1967 ARMCPU *cpu = opaque;
1968
1969 gt_recalc_timer(cpu, GTIMER_PHYS);
1970 }
1971
1972 void arm_gt_vtimer_cb(void *opaque)
1973 {
1974 ARMCPU *cpu = opaque;
1975
1976 gt_recalc_timer(cpu, GTIMER_VIRT);
1977 }
1978
1979 void arm_gt_htimer_cb(void *opaque)
1980 {
1981 ARMCPU *cpu = opaque;
1982
1983 gt_recalc_timer(cpu, GTIMER_HYP);
1984 }
1985
1986 void arm_gt_stimer_cb(void *opaque)
1987 {
1988 ARMCPU *cpu = opaque;
1989
1990 gt_recalc_timer(cpu, GTIMER_SEC);
1991 }
1992
1993 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1994 /* Note that CNTFRQ is purely reads-as-written for the benefit
1995 * of software; writing it doesn't actually change the timer frequency.
1996 * Our reset value matches the fixed frequency we implement the timer at.
1997 */
1998 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1999 .type = ARM_CP_ALIAS,
2000 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
2001 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
2002 },
2003 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
2004 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
2005 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
2006 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
2007 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
2008 },
2009 /* overall control: mostly access permissions */
2010 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
2011 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
2012 .access = PL1_RW,
2013 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
2014 .resetvalue = 0,
2015 },
2016 /* per-timer control */
2017 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
2018 .secure = ARM_CP_SECSTATE_NS,
2019 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
2020 .accessfn = gt_ptimer_access,
2021 .fieldoffset = offsetoflow32(CPUARMState,
2022 cp15.c14_timer[GTIMER_PHYS].ctl),
2023 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
2024 },
2025 { .name = "CNTP_CTL_S",
2026 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
2027 .secure = ARM_CP_SECSTATE_S,
2028 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
2029 .accessfn = gt_ptimer_access,
2030 .fieldoffset = offsetoflow32(CPUARMState,
2031 cp15.c14_timer[GTIMER_SEC].ctl),
2032 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
2033 },
2034 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
2035 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
2036 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
2037 .accessfn = gt_ptimer_access,
2038 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
2039 .resetvalue = 0,
2040 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
2041 },
2042 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
2043 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
2044 .accessfn = gt_vtimer_access,
2045 .fieldoffset = offsetoflow32(CPUARMState,
2046 cp15.c14_timer[GTIMER_VIRT].ctl),
2047 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
2048 },
2049 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
2050 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
2051 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
2052 .accessfn = gt_vtimer_access,
2053 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
2054 .resetvalue = 0,
2055 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
2056 },
2057 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2058 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
2059 .secure = ARM_CP_SECSTATE_NS,
2060 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
2061 .accessfn = gt_ptimer_access,
2062 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
2063 },
2064 { .name = "CNTP_TVAL_S",
2065 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
2066 .secure = ARM_CP_SECSTATE_S,
2067 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
2068 .accessfn = gt_ptimer_access,
2069 .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
2070 },
2071 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
2072 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
2073 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
2074 .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
2075 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
2076 },
2077 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
2078 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
2079 .accessfn = gt_vtimer_access,
2080 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
2081 },
2082 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
2083 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
2084 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
2085 .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
2086 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
2087 },
2088 /* The counter itself */
2089 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
2090 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
2091 .accessfn = gt_pct_access,
2092 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
2093 },
2094 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
2095 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
2096 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2097 .accessfn = gt_pct_access, .readfn = gt_cnt_read,
2098 },
2099 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
2100 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
2101 .accessfn = gt_vct_access,
2102 .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
2103 },
2104 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
2105 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
2106 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2107 .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
2108 },
2109 /* Comparison value, indicating when the timer goes off */
2110 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
2111 .secure = ARM_CP_SECSTATE_NS,
2112 .access = PL1_RW | PL0_R,
2113 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
2114 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
2115 .accessfn = gt_ptimer_access,
2116 .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
2117 },
2118 { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2,
2119 .secure = ARM_CP_SECSTATE_S,
2120 .access = PL1_RW | PL0_R,
2121 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
2122 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
2123 .accessfn = gt_ptimer_access,
2124 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
2125 },
2126 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
2127 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
2128 .access = PL1_RW | PL0_R,
2129 .type = ARM_CP_IO,
2130 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
2131 .resetvalue = 0, .accessfn = gt_ptimer_access,
2132 .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
2133 },
2134 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
2135 .access = PL1_RW | PL0_R,
2136 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
2137 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
2138 .accessfn = gt_vtimer_access,
2139 .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
2140 },
2141 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
2142 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
2143 .access = PL1_RW | PL0_R,
2144 .type = ARM_CP_IO,
2145 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
2146 .resetvalue = 0, .accessfn = gt_vtimer_access,
2147 .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
2148 },
2149 /* Secure timer -- this is actually restricted to only EL3
2150 * and configurably Secure-EL1 via the accessfn.
2151 */
2152 { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
2153 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
2154 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
2155 .accessfn = gt_stimer_access,
2156 .readfn = gt_sec_tval_read,
2157 .writefn = gt_sec_tval_write,
2158 .resetfn = gt_sec_timer_reset,
2159 },
2160 { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
2161 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
2162 .type = ARM_CP_IO, .access = PL1_RW,
2163 .accessfn = gt_stimer_access,
2164 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
2165 .resetvalue = 0,
2166 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
2167 },
2168 { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
2169 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
2170 .type = ARM_CP_IO, .access = PL1_RW,
2171 .accessfn = gt_stimer_access,
2172 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
2173 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
2174 },
2175 REGINFO_SENTINEL
2176 };
2177
2178 #else
2179
2180 /* In user-mode most of the generic timer registers are inaccessible
2181 * however modern kernels (4.12+) allow access to cntvct_el0
2182 */
2183
2184 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
2185 {
2186 /* Currently we have no support for QEMUTimer in linux-user so we
2187 * can't call gt_get_countervalue(env), instead we directly
2188 * call the lower level functions.
2189 */
2190 return cpu_get_clock() / GTIMER_SCALE;
2191 }
2192
2193 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
2194 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
2195 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
2196 .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
2197 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
2198 .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE,
2199 },
2200 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
2201 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
2202 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2203 .readfn = gt_virt_cnt_read,
2204 },
2205 REGINFO_SENTINEL
2206 };
2207
2208 #endif
2209
2210 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2211 {
2212 if (arm_feature(env, ARM_FEATURE_LPAE)) {
2213 raw_write(env, ri, value);
2214 } else if (arm_feature(env, ARM_FEATURE_V7)) {
2215 raw_write(env, ri, value & 0xfffff6ff);
2216 } else {
2217 raw_write(env, ri, value & 0xfffff1ff);
2218 }
2219 }
2220
2221 #ifndef CONFIG_USER_ONLY
2222 /* get_phys_addr() isn't present for user-mode-only targets */
2223
2224 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
2225 bool isread)
2226 {
2227 if (ri->opc2 & 4) {
2228 /* The ATS12NSO* operations must trap to EL3 if executed in
2229 * Secure EL1 (which can only happen if EL3 is AArch64).
2230 * They are simply UNDEF if executed from NS EL1.
2231 * They function normally from EL2 or EL3.
2232 */
2233 if (arm_current_el(env) == 1) {
2234 if (arm_is_secure_below_el3(env)) {
2235 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
2236 }
2237 return CP_ACCESS_TRAP_UNCATEGORIZED;
2238 }
2239 }
2240 return CP_ACCESS_OK;
2241 }
2242
2243 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
2244 MMUAccessType access_type, ARMMMUIdx mmu_idx)
2245 {
2246 hwaddr phys_addr;
2247 target_ulong page_size;
2248 int prot;
2249 bool ret;
2250 uint64_t par64;
2251 bool format64 = false;
2252 MemTxAttrs attrs = {};
2253 ARMMMUFaultInfo fi = {};
2254 ARMCacheAttrs cacheattrs = {};
2255
2256 ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
2257 &prot, &page_size, &fi, &cacheattrs);
2258
2259 if (is_a64(env)) {
2260 format64 = true;
2261 } else if (arm_feature(env, ARM_FEATURE_LPAE)) {
2262 /*
2263 * ATS1Cxx:
2264 * * TTBCR.EAE determines whether the result is returned using the
2265 * 32-bit or the 64-bit PAR format
2266 * * Instructions executed in Hyp mode always use the 64bit format
2267 *
2268 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
2269 * * The Non-secure TTBCR.EAE bit is set to 1
2270 * * The implementation includes EL2, and the value of HCR.VM is 1
2271 *
2272 * ATS1Hx always uses the 64bit format (not supported yet).
2273 */
2274 format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
2275
2276 if (arm_feature(env, ARM_FEATURE_EL2)) {
2277 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
2278 format64 |= env->cp15.hcr_el2 & HCR_VM;
2279 } else {
2280 format64 |= arm_current_el(env) == 2;
2281 }
2282 }
2283 }
2284
2285 if (format64) {
2286 /* Create a 64-bit PAR */
2287 par64 = (1 << 11); /* LPAE bit always set */
2288 if (!ret) {
2289 par64 |= phys_addr & ~0xfffULL;
2290 if (!attrs.secure) {
2291 par64 |= (1 << 9); /* NS */
2292 }
2293 par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */
2294 par64 |= cacheattrs.shareability << 7; /* SH */
2295 } else {
2296 uint32_t fsr = arm_fi_to_lfsc(&fi);
2297
2298 par64 |= 1; /* F */
2299 par64 |= (fsr & 0x3f) << 1; /* FS */
2300 /* Note that S2WLK and FSTAGE are always zero, because we don't
2301 * implement virtualization and therefore there can't be a stage 2
2302 * fault.
2303 */
2304 }
2305 } else {
2306 /* fsr is a DFSR/IFSR value for the short descriptor
2307 * translation table format (with WnR always clear).
2308 * Convert it to a 32-bit PAR.
2309 */
2310 if (!ret) {
2311 /* We do not set any attribute bits in the PAR */
2312 if (page_size == (1 << 24)
2313 && arm_feature(env, ARM_FEATURE_V7)) {
2314 par64 = (phys_addr & 0xff000000) | (1 << 1);
2315 } else {
2316 par64 = phys_addr & 0xfffff000;
2317 }
2318 if (!attrs.secure) {
2319 par64 |= (1 << 9); /* NS */
2320 }
2321 } else {
2322 uint32_t fsr = arm_fi_to_sfsc(&fi);
2323
2324 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
2325 ((fsr & 0xf) << 1) | 1;
2326 }
2327 }
2328 return par64;
2329 }
2330
2331 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2332 {
2333 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
2334 uint64_t par64;
2335 ARMMMUIdx mmu_idx;
2336 int el = arm_current_el(env);
2337 bool secure = arm_is_secure_below_el3(env);
2338
2339 switch (ri->opc2 & 6) {
2340 case 0:
2341 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2342 switch (el) {
2343 case 3:
2344 mmu_idx = ARMMMUIdx_S1E3;
2345 break;
2346 case 2:
2347 mmu_idx = ARMMMUIdx_S1NSE1;
2348 break;
2349 case 1:
2350 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2351 break;
2352 default:
2353 g_assert_not_reached();
2354 }
2355 break;
2356 case 2:
2357 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2358 switch (el) {
2359 case 3:
2360 mmu_idx = ARMMMUIdx_S1SE0;
2361 break;
2362 case 2:
2363 mmu_idx = ARMMMUIdx_S1NSE0;
2364 break;
2365 case 1:
2366 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2367 break;
2368 default:
2369 g_assert_not_reached();
2370 }
2371 break;
2372 case 4:
2373 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2374 mmu_idx = ARMMMUIdx_S12NSE1;
2375 break;
2376 case 6:
2377 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2378 mmu_idx = ARMMMUIdx_S12NSE0;
2379 break;
2380 default:
2381 g_assert_not_reached();
2382 }
2383
2384 par64 = do_ats_write(env, value, access_type, mmu_idx);
2385
2386 A32_BANKED_CURRENT_REG_SET(env, par, par64);
2387 }
2388
2389 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
2390 uint64_t value)
2391 {
2392 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
2393 uint64_t par64;
2394
2395 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
2396
2397 A32_BANKED_CURRENT_REG_SET(env, par, par64);
2398 }
2399
2400 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
2401 bool isread)
2402 {
2403 if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
2404 return CP_ACCESS_TRAP;
2405 }
2406 return CP_ACCESS_OK;
2407 }
2408
2409 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
2410 uint64_t value)
2411 {
2412 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
2413 ARMMMUIdx mmu_idx;
2414 int secure = arm_is_secure_below_el3(env);
2415
2416 switch (ri->opc2 & 6) {
2417 case 0:
2418 switch (ri->opc1) {
2419 case 0: /* AT S1E1R, AT S1E1W */
2420 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2421 break;
2422 case 4: /* AT S1E2R, AT S1E2W */
2423 mmu_idx = ARMMMUIdx_S1E2;
2424 break;
2425 case 6: /* AT S1E3R, AT S1E3W */
2426 mmu_idx = ARMMMUIdx_S1E3;
2427 break;
2428 default:
2429 g_assert_not_reached();
2430 }
2431 break;
2432 case 2: /* AT S1E0R, AT S1E0W */
2433 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2434 break;
2435 case 4: /* AT S12E1R, AT S12E1W */
2436 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
2437 break;
2438 case 6: /* AT S12E0R, AT S12E0W */
2439 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
2440 break;
2441 default:
2442 g_assert_not_reached();
2443 }
2444
2445 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
2446 }
2447 #endif
2448
2449 static const ARMCPRegInfo vapa_cp_reginfo[] = {
2450 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
2451 .access = PL1_RW, .resetvalue = 0,
2452 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
2453 offsetoflow32(CPUARMState, cp15.par_ns) },
2454 .writefn = par_write },
2455 #ifndef CONFIG_USER_ONLY
2456 /* This underdecoding is safe because the reginfo is NO_RAW. */
2457 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
2458 .access = PL1_W, .accessfn = ats_access,
2459 .writefn = ats_write, .type = ARM_CP_NO_RAW },
2460 #endif
2461 REGINFO_SENTINEL
2462 };
2463
2464 /* Return basic MPU access permission bits. */
2465 static uint32_t simple_mpu_ap_bits(uint32_t val)
2466 {
2467 uint32_t ret;
2468 uint32_t mask;
2469 int i;
2470 ret = 0;
2471 mask = 3;
2472 for (i = 0; i < 16; i += 2) {
2473 ret |= (val >> i) & mask;
2474 mask <<= 2;
2475 }
2476 return ret;
2477 }
2478
2479 /* Pad basic MPU access permission bits to extended format. */
2480 static uint32_t extended_mpu_ap_bits(uint32_t val)
2481 {
2482 uint32_t ret;
2483 uint32_t mask;
2484 int i;
2485 ret = 0;
2486 mask = 3;
2487 for (i = 0; i < 16; i += 2) {
2488 ret |= (val & mask) << i;
2489 mask <<= 2;
2490 }
2491 return ret;
2492 }
2493
2494 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2495 uint64_t value)
2496 {
2497 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
2498 }
2499
2500 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2501 {
2502 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
2503 }
2504
2505 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2506 uint64_t value)
2507 {
2508 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
2509 }
2510
2511 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2512 {
2513 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
2514 }
2515
2516 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
2517 {
2518 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2519
2520 if (!u32p) {
2521 return 0;
2522 }
2523
2524 u32p += env->pmsav7.rnr[M_REG_NS];
2525 return *u32p;
2526 }
2527
2528 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
2529 uint64_t value)
2530 {
2531 ARMCPU *cpu = arm_env_get_cpu(env);
2532 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2533
2534 if (!u32p) {
2535 return;
2536 }
2537
2538 u32p += env->pmsav7.rnr[M_REG_NS];
2539 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
2540 *u32p = value;
2541 }
2542
2543 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2544 uint64_t value)
2545 {
2546 ARMCPU *cpu = arm_env_get_cpu(env);
2547 uint32_t nrgs = cpu->pmsav7_dregion;
2548
2549 if (value >= nrgs) {
2550 qemu_log_mask(LOG_GUEST_ERROR,
2551 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2552 " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2553 return;
2554 }
2555
2556 raw_write(env, ri, value);
2557 }
2558
2559 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2560 /* Reset for all these registers is handled in arm_cpu_reset(),
2561 * because the PMSAv7 is also used by M-profile CPUs, which do
2562 * not register cpregs but still need the state to be reset.
2563 */
2564 { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2565 .access = PL1_RW, .type = ARM_CP_NO_RAW,
2566 .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2567 .readfn = pmsav7_read, .writefn = pmsav7_write,
2568 .resetfn = arm_cp_reset_ignore },
2569 { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2570 .access = PL1_RW, .type = ARM_CP_NO_RAW,
2571 .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2572 .readfn = pmsav7_read, .writefn = pmsav7_write,
2573 .resetfn = arm_cp_reset_ignore },
2574 { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2575 .access = PL1_RW, .type = ARM_CP_NO_RAW,
2576 .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2577 .readfn = pmsav7_read, .writefn = pmsav7_write,
2578 .resetfn = arm_cp_reset_ignore },
2579 { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2580 .access = PL1_RW,
2581 .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
2582 .writefn = pmsav7_rgnr_write,
2583 .resetfn = arm_cp_reset_ignore },
2584 REGINFO_SENTINEL
2585 };
2586
2587 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2588 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2589 .access = PL1_RW, .type = ARM_CP_ALIAS,
2590 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2591 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2592 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2593 .access = PL1_RW, .type = ARM_CP_ALIAS,
2594 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2595 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2596 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2597 .access = PL1_RW,
2598 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2599 .resetvalue = 0, },
2600 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2601 .access = PL1_RW,
2602 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2603 .resetvalue = 0, },
2604 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2605 .access = PL1_RW,
2606 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2607 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2608 .access = PL1_RW,
2609 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2610 /* Protection region base and size registers */
2611 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2612 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2613 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2614 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2615 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2616 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2617 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2618 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2619 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2620 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2621 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2622 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2623 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2624 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2625 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2626 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2627 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2628 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2629 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2630 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2631 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2632 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2633 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2634 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2635 REGINFO_SENTINEL
2636 };
2637
2638 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2639 uint64_t value)
2640 {
2641 TCR *tcr = raw_ptr(env, ri);
2642 int maskshift = extract32(value, 0, 3);
2643
2644 if (!arm_feature(env, ARM_FEATURE_V8)) {
2645 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2646 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2647 * using Long-desciptor translation table format */
2648 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2649 } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2650 /* In an implementation that includes the Security Extensions
2651 * TTBCR has additional fields PD0 [4] and PD1 [5] for
2652 * Short-descriptor translation table format.
2653 */
2654 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2655 } else {
2656 value &= TTBCR_N;
2657 }
2658 }
2659
2660 /* Update the masks corresponding to the TCR bank being written
2661 * Note that we always calculate mask and base_mask, but
2662 * they are only used for short-descriptor tables (ie if EAE is 0);
2663 * for long-descriptor tables the TCR fields are used differently
2664 * and the mask and base_mask values are meaningless.
2665 */
2666 tcr->raw_tcr = value;
2667 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2668 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2669 }
2670
2671 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2672 uint64_t value)
2673 {
2674 ARMCPU *cpu = arm_env_get_cpu(env);
2675
2676 if (arm_feature(env, ARM_FEATURE_LPAE)) {
2677 /* With LPAE the TTBCR could result in a change of ASID
2678 * via the TTBCR.A1 bit, so do a TLB flush.
2679 */
2680 tlb_flush(CPU(cpu));
2681 }
2682 vmsa_ttbcr_raw_write(env, ri, value);
2683 }
2684
2685 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2686 {
2687 TCR *tcr = raw_ptr(env, ri);
2688
2689 /* Reset both the TCR as well as the masks corresponding to the bank of
2690 * the TCR being reset.
2691 */
2692 tcr->raw_tcr = 0;
2693 tcr->mask = 0;
2694 tcr->base_mask = 0xffffc000u;
2695 }
2696
2697 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2698 uint64_t value)
2699 {
2700 ARMCPU *cpu = arm_env_get_cpu(env);
2701 TCR *tcr = raw_ptr(env, ri);
2702
2703 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2704 tlb_flush(CPU(cpu));
2705 tcr->raw_tcr = value;
2706 }
2707
2708 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2709 uint64_t value)
2710 {
2711 /* 64 bit accesses to the TTBRs can change the ASID and so we
2712 * must flush the TLB.
2713 */
2714 if (cpreg_field_is_64bit(ri)) {
2715 ARMCPU *cpu = arm_env_get_cpu(env);
2716
2717 tlb_flush(CPU(cpu));
2718 }
2719 raw_write(env, ri, value);
2720 }
2721
2722 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2723 uint64_t value)
2724 {
2725 ARMCPU *cpu = arm_env_get_cpu(env);
2726 CPUState *cs = CPU(cpu);
2727
2728 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
2729 if (raw_read(env, ri) != value) {
2730 tlb_flush_by_mmuidx(cs,
2731 ARMMMUIdxBit_S12NSE1 |
2732 ARMMMUIdxBit_S12NSE0 |
2733 ARMMMUIdxBit_S2NS);
2734 raw_write(env, ri, value);
2735 }
2736 }
2737
2738 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2739 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2740 .access = PL1_RW, .type = ARM_CP_ALIAS,
2741 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2742 offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2743 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2744 .access = PL1_RW, .resetvalue = 0,
2745 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2746 offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2747 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2748 .access = PL1_RW, .resetvalue = 0,
2749 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2750 offsetof(CPUARMState, cp15.dfar_ns) } },
2751 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2752 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2753 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2754 .resetvalue = 0, },
2755 REGINFO_SENTINEL
2756 };
2757
2758 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2759 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2760 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2761 .access = PL1_RW,
2762 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2763 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2764 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2765 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2766 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2767 offsetof(CPUARMState, cp15.ttbr0_ns) } },
2768 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2769 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2770 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2771 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2772 offsetof(CPUARMState, cp15.ttbr1_ns) } },
2773 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2774 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2775 .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2776 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2777 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2778 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2779 .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2780 .raw_writefn = vmsa_ttbcr_raw_write,
2781 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2782 offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2783 REGINFO_SENTINEL
2784 };
2785
2786 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2787 uint64_t value)
2788 {
2789 env->cp15.c15_ticonfig = value & 0xe7;
2790 /* The OS_TYPE bit in this register changes the reported CPUID! */
2791 env->cp15.c0_cpuid = (value & (1 << 5)) ?
2792 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2793 }
2794
2795 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2796 uint64_t value)
2797 {
2798 env->cp15.c15_threadid = value & 0xffff;
2799 }
2800
2801 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2802 uint64_t value)
2803 {
2804 /* Wait-for-interrupt (deprecated) */
2805 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2806 }
2807
2808 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2809 uint64_t value)
2810 {
2811 /* On OMAP there are registers indicating the max/min index of dcache lines
2812 * containing a dirty line; cache flush operations have to reset these.
2813 */
2814 env->cp15.c15_i_max = 0x000;
2815 env->cp15.c15_i_min = 0xff0;
2816 }
2817
2818 static const ARMCPRegInfo omap_cp_reginfo[] = {
2819 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2820 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2821 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2822 .resetvalue = 0, },
2823 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2824 .access = PL1_RW, .type = ARM_CP_NOP },
2825 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2826 .access = PL1_RW,
2827 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2828 .writefn = omap_ticonfig_write },
2829 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2830 .access = PL1_RW,
2831 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2832 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2833 .access = PL1_RW, .resetvalue = 0xff0,
2834 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2835 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2836 .access = PL1_RW,
2837 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2838 .writefn = omap_threadid_write },
2839 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2840 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2841 .type = ARM_CP_NO_RAW,
2842 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2843 /* TODO: Peripheral port remap register:
2844 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2845 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2846 * when MMU is off.
2847 */
2848 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2849 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2850 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2851 .writefn = omap_cachemaint_write },
2852 { .name = "C9", .cp = 15, .crn = 9,
2853 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2854 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2855 REGINFO_SENTINEL
2856 };
2857
2858 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2859 uint64_t value)
2860 {
2861 env->cp15.c15_cpar = value & 0x3fff;
2862 }
2863
2864 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2865 { .name = "XSCALE_CPAR",
2866 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2867 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2868 .writefn = xscale_cpar_write, },
2869 { .name = "XSCALE_AUXCR",
2870 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2871 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2872 .resetvalue = 0, },
2873 /* XScale specific cache-lockdown: since we have no cache we NOP these
2874 * and hope the guest does not really rely on cache behaviour.
2875 */
2876 { .name = "XSCALE_LOCK_ICACHE_LINE",
2877 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2878 .access = PL1_W, .type = ARM_CP_NOP },
2879 { .name = "XSCALE_UNLOCK_ICACHE",
2880 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2881 .access = PL1_W, .type = ARM_CP_NOP },
2882 { .name = "XSCALE_DCACHE_LOCK",
2883 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2884 .access = PL1_RW, .type = ARM_CP_NOP },
2885 { .name = "XSCALE_UNLOCK_DCACHE",
2886 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2887 .access = PL1_W, .type = ARM_CP_NOP },
2888 REGINFO_SENTINEL
2889 };
2890
2891 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2892 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2893 * implementation of this implementation-defined space.
2894 * Ideally this should eventually disappear in favour of actually
2895 * implementing the correct behaviour for all cores.
2896 */
2897 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2898 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2899 .access = PL1_RW,
2900 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2901 .resetvalue = 0 },
2902 REGINFO_SENTINEL
2903 };
2904
2905 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2906 /* Cache status: RAZ because we have no cache so it's always clean */
2907 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2908 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2909 .resetvalue = 0 },
2910 REGINFO_SENTINEL
2911 };
2912
2913 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2914 /* We never have a a block transfer operation in progress */
2915 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2916 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2917 .resetvalue = 0 },
2918 /* The cache ops themselves: these all NOP for QEMU */
2919 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2920 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2921 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2922 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2923 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2924 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2925 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2926 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2927 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2928 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2929 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2930 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2931 REGINFO_SENTINEL
2932 };
2933
2934 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2935 /* The cache test-and-clean instructions always return (1 << 30)
2936 * to indicate that there are no dirty cache lines.
2937 */
2938 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2939 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2940 .resetvalue = (1 << 30) },
2941 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2942 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2943 .resetvalue = (1 << 30) },
2944 REGINFO_SENTINEL
2945 };
2946
2947 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2948 /* Ignore ReadBuffer accesses */
2949 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2950 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2951 .access = PL1_RW, .resetvalue = 0,
2952 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2953 REGINFO_SENTINEL
2954 };
2955
2956 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2957 {
2958 ARMCPU *cpu = arm_env_get_cpu(env);
2959 unsigned int cur_el = arm_current_el(env);
2960 bool secure = arm_is_secure(env);
2961
2962 if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2963 return env->cp15.vpidr_el2;
2964 }
2965 return raw_read(env, ri);
2966 }
2967
2968 static uint64_t mpidr_read_val(CPUARMState *env)
2969 {
2970 ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2971 uint64_t mpidr = cpu->mp_affinity;
2972
2973 if (arm_feature(env, ARM_FEATURE_V7MP)) {
2974 mpidr |= (1U << 31);
2975 /* Cores which are uniprocessor (non-coherent)
2976 * but still implement the MP extensions set
2977 * bit 30. (For instance, Cortex-R5).
2978 */
2979 if (cpu->mp_is_up) {
2980 mpidr |= (1u << 30);
2981 }
2982 }
2983 return mpidr;
2984 }
2985
2986 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2987 {
2988 unsigned int cur_el = arm_current_el(env);
2989 bool secure = arm_is_secure(env);
2990
2991 if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2992 return env->cp15.vmpidr_el2;
2993 }
2994 return mpidr_read_val(env);
2995 }
2996
2997 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2998 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2999 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
3000 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
3001 REGINFO_SENTINEL
3002 };
3003
3004 static const ARMCPRegInfo lpae_cp_reginfo[] = {
3005 /* NOP AMAIR0/1 */
3006 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
3007 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
3008 .access = PL1_RW, .type = ARM_CP_CONST,
3009 .resetvalue = 0 },
3010 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
3011 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
3012 .access = PL1_RW, .type = ARM_CP_CONST,
3013 .resetvalue = 0 },
3014 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
3015 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
3016 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
3017 offsetof(CPUARMState, cp15.par_ns)} },
3018 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
3019 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3020 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
3021 offsetof(CPUARMState, cp15.ttbr0_ns) },
3022 .writefn = vmsa_ttbr_write, },
3023 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
3024 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3025 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
3026 offsetof(CPUARMState, cp15.ttbr1_ns) },
3027 .writefn = vmsa_ttbr_write, },
3028 REGINFO_SENTINEL
3029 };
3030
3031 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
3032 {
3033 return vfp_get_fpcr(env);
3034 }
3035
3036 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3037 uint64_t value)
3038 {
3039 vfp_set_fpcr(env, value);
3040 }
3041
3042 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
3043 {
3044 return vfp_get_fpsr(env);
3045 }
3046
3047 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3048 uint64_t value)
3049 {
3050 vfp_set_fpsr(env, value);
3051 }
3052
3053 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
3054 bool isread)
3055 {
3056 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
3057 return CP_ACCESS_TRAP;
3058 }
3059 return CP_ACCESS_OK;
3060 }
3061
3062 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
3063 uint64_t value)
3064 {
3065 env->daif = value & PSTATE_DAIF;
3066 }
3067
3068 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
3069 const ARMCPRegInfo *ri,
3070 bool isread)
3071 {
3072 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
3073 * SCTLR_EL1.UCI is set.
3074 */
3075 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
3076 return CP_ACCESS_TRAP;
3077 }
3078 return CP_ACCESS_OK;
3079 }
3080
3081 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
3082 * Page D4-1736 (DDI0487A.b)
3083 */
3084
3085 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
3086 uint64_t value)
3087 {
3088 CPUState *cs = ENV_GET_CPU(env);
3089
3090 if (arm_is_secure_below_el3(env)) {
3091 tlb_flush_by_mmuidx(cs,
3092 ARMMMUIdxBit_S1SE1 |
3093 ARMMMUIdxBit_S1SE0);
3094 } else {
3095 tlb_flush_by_mmuidx(cs,
3096 ARMMMUIdxBit_S12NSE1 |
3097 ARMMMUIdxBit_S12NSE0);
3098 }
3099 }
3100
3101 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3102 uint64_t value)
3103 {
3104 CPUState *cs = ENV_GET_CPU(env);
3105 bool sec = arm_is_secure_below_el3(env);
3106
3107 if (sec) {
3108 tlb_flush_by_mmuidx_all_cpus_synced(cs,
3109 ARMMMUIdxBit_S1SE1 |
3110 ARMMMUIdxBit_S1SE0);
3111 } else {
3112 tlb_flush_by_mmuidx_all_cpus_synced(cs,
3113 ARMMMUIdxBit_S12NSE1 |
3114 ARMMMUIdxBit_S12NSE0);
3115 }
3116 }
3117
3118 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
3119 uint64_t value)
3120 {
3121 /* Note that the 'ALL' scope must invalidate both stage 1 and
3122 * stage 2 translations, whereas most other scopes only invalidate
3123 * stage 1 translations.
3124 */
3125 ARMCPU *cpu = arm_env_get_cpu(env);
3126 CPUState *cs = CPU(cpu);
3127
3128 if (arm_is_secure_below_el3(env)) {
3129 tlb_flush_by_mmuidx(cs,
3130 ARMMMUIdxBit_S1SE1 |
3131 ARMMMUIdxBit_S1SE0);
3132 } else {
3133 if (arm_feature(env, ARM_FEATURE_EL2)) {
3134 tlb_flush_by_mmuidx(cs,
3135 ARMMMUIdxBit_S12NSE1 |
3136 ARMMMUIdxBit_S12NSE0 |
3137 ARMMMUIdxBit_S2NS);
3138 } else {
3139 tlb_flush_by_mmuidx(cs,
3140 ARMMMUIdxBit_S12NSE1 |
3141 ARMMMUIdxBit_S12NSE0);
3142 }
3143 }
3144 }
3145
3146 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
3147 uint64_t value)
3148 {
3149 ARMCPU *cpu = arm_env_get_cpu(env);
3150 CPUState *cs = CPU(cpu);
3151
3152 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
3153 }
3154
3155 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
3156 uint64_t value)
3157 {
3158 ARMCPU *cpu = arm_env_get_cpu(env);
3159 CPUState *cs = CPU(cpu);
3160
3161 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3);
3162 }
3163
3164 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3165 uint64_t value)
3166 {
3167 /* Note that the 'ALL' scope must invalidate both stage 1 and
3168 * stage 2 translations, whereas most other scopes only invalidate
3169 * stage 1 translations.
3170 */
3171 CPUState *cs = ENV_GET_CPU(env);
3172 bool sec = arm_is_secure_below_el3(env);
3173 bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
3174
3175 if (sec) {
3176 tlb_flush_by_mmuidx_all_cpus_synced(cs,
3177 ARMMMUIdxBit_S1SE1 |
3178 ARMMMUIdxBit_S1SE0);
3179 } else if (has_el2) {
3180 tlb_flush_by_mmuidx_all_cpus_synced(cs,
3181 ARMMMUIdxBit_S12NSE1 |
3182 ARMMMUIdxBit_S12NSE0 |
3183 ARMMMUIdxBit_S2NS);
3184 } else {
3185 tlb_flush_by_mmuidx_all_cpus_synced(cs,
3186 ARMMMUIdxBit_S12NSE1 |
3187 ARMMMUIdxBit_S12NSE0);
3188 }
3189 }
3190
3191 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3192 uint64_t value)
3193 {
3194 CPUState *cs = ENV_GET_CPU(env);
3195
3196 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
3197 }
3198
3199 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3200 uint64_t value)
3201 {
3202 CPUState *cs = ENV_GET_CPU(env);
3203
3204 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3);
3205 }
3206
3207 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
3208 uint64_t value)
3209 {
3210 /* Invalidate by VA, EL1&0 (AArch64 version).
3211 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
3212 * since we don't support flush-for-specific-ASID-only or
3213 * flush-last-level-only.
3214 */
3215 ARMCPU *cpu = arm_env_get_cpu(env);
3216 CPUState *cs = CPU(cpu);
3217 uint64_t pageaddr = sextract64(value << 12, 0, 56);
3218
3219 if (arm_is_secure_below_el3(env)) {
3220 tlb_flush_page_by_mmuidx(cs, pageaddr,
3221 ARMMMUIdxBit_S1SE1 |
3222 ARMMMUIdxBit_S1SE0);
3223 } else {
3224 tlb_flush_page_by_mmuidx(cs, pageaddr,
3225 ARMMMUIdxBit_S12NSE1 |
3226 ARMMMUIdxBit_S12NSE0);
3227 }
3228 }
3229
3230 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
3231 uint64_t value)
3232 {
3233 /* Invalidate by VA, EL2
3234 * Currently handles both VAE2 and VALE2, since we don't support
3235 * flush-last-level-only.
3236 */
3237 ARMCPU *cpu = arm_env_get_cpu(env);
3238 CPUState *cs = CPU(cpu);
3239 uint64_t pageaddr = sextract64(value << 12, 0, 56);
3240
3241 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
3242 }
3243
3244 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
3245 uint64_t value)
3246 {
3247 /* Invalidate by VA, EL3
3248 * Currently handles both VAE3 and VALE3, since we don't support
3249 * flush-last-level-only.
3250 */
3251 ARMCPU *cpu = arm_env_get_cpu(env);
3252 CPUState *cs = CPU(cpu);
3253 uint64_t pageaddr = sextract64(value << 12, 0, 56);
3254
3255 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3);
3256 }
3257
3258 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3259 uint64_t value)
3260 {
3261 ARMCPU *cpu = arm_env_get_cpu(env);
3262 CPUState *cs = CPU(cpu);
3263 bool sec = arm_is_secure_below_el3(env);
3264 uint64_t pageaddr = sextract64(value << 12, 0, 56);
3265
3266 if (sec) {
3267 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
3268 ARMMMUIdxBit_S1SE1 |
3269 ARMMMUIdxBit_S1SE0);
3270 } else {
3271 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
3272 ARMMMUIdxBit_S12NSE1 |
3273 ARMMMUIdxBit_S12NSE0);
3274 }
3275 }
3276
3277 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3278 uint64_t value)
3279 {
3280 CPUState *cs = ENV_GET_CPU(env);
3281 uint64_t pageaddr = sextract64(value << 12, 0, 56);
3282
3283 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
3284 ARMMMUIdxBit_S1E2);
3285 }
3286
3287 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3288 uint64_t value)
3289 {
3290 CPUState *cs = ENV_GET_CPU(env);
3291 uint64_t pageaddr = sextract64(value << 12, 0, 56);
3292
3293 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
3294 ARMMMUIdxBit_S1E3);
3295 }
3296
3297 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
3298 uint64_t value)
3299 {
3300 /* Invalidate by IPA. This has to invalidate any structures that
3301 * contain only stage 2 translation information, but does not need
3302 * to apply to structures that contain combined stage 1 and stage 2
3303 * translation information.
3304 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
3305 */
3306 ARMCPU *cpu = arm_env_get_cpu(env);
3307 CPUState *cs = CPU(cpu);
3308 uint64_t pageaddr;
3309
3310 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
3311 return;
3312 }
3313
3314 pageaddr = sextract64(value << 12, 0, 48);
3315
3316 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS);
3317 }
3318
3319 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3320 uint64_t value)
3321 {
3322 CPUState *cs = ENV_GET_CPU(env);
3323 uint64_t pageaddr;
3324
3325 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
3326 return;
3327 }
3328
3329 pageaddr = sextract64(value << 12, 0, 48);
3330
3331 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
3332 ARMMMUIdxBit_S2NS);
3333 }
3334
3335 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
3336 bool isread)
3337 {
3338 /* We don't implement EL2, so the only control on DC ZVA is the
3339 * bit in the SCTLR which can prohibit access for EL0.
3340 */
3341 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
3342 return CP_ACCESS_TRAP;
3343 }
3344 return CP_ACCESS_OK;
3345 }
3346
3347 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
3348 {
3349 ARMCPU *cpu = arm_env_get_cpu(env);
3350 int dzp_bit = 1 << 4;
3351
3352 /* DZP indicates whether DC ZVA access is allowed */
3353 if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) {
3354 dzp_bit = 0;
3355 }
3356 return cpu->dcz_blocksize | dzp_bit;
3357 }
3358
3359 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3360 bool isread)
3361 {
3362 if (!(env->pstate & PSTATE_SP)) {
3363 /* Access to SP_EL0 is undefined if it's being used as
3364 * the stack pointer.
3365 */
3366 return CP_ACCESS_TRAP_UNCATEGORIZED;
3367 }
3368 return CP_ACCESS_OK;
3369 }
3370
3371 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
3372 {
3373 return env->pstate & PSTATE_SP;
3374 }
3375
3376 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
3377 {
3378 update_spsel(env, val);
3379 }
3380
3381 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3382 uint64_t value)
3383 {
3384 ARMCPU *cpu = arm_env_get_cpu(env);
3385
3386 if (raw_read(env, ri) == value) {
3387 /* Skip the TLB flush if nothing actually changed; Linux likes
3388 * to do a lot of pointless SCTLR writes.
3389 */
3390 return;
3391 }
3392
3393 if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
3394 /* M bit is RAZ/WI for PMSA with no MPU implemented */
3395 value &= ~SCTLR_M;
3396 }
3397
3398 raw_write(env, ri, value);
3399 /* ??? Lots of these bits are not implemented. */
3400 /* This may enable/disable the MMU, so do a TLB flush. */
3401 tlb_flush(CPU(cpu));
3402 }
3403
3404 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
3405 bool isread)
3406 {
3407 if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
3408 return CP_ACCESS_TRAP_FP_EL2;
3409 }
3410 if (env->cp15.cptr_el[3] & CPTR_TFP) {
3411 return CP_ACCESS_TRAP_FP_EL3;
3412 }
3413 return CP_ACCESS_OK;
3414 }
3415
3416 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3417 uint64_t value)
3418 {
3419 env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
3420 }
3421
3422 static const ARMCPRegInfo v8_cp_reginfo[] = {
3423 /* Minimal set of EL0-visible registers. This will need to be expanded
3424 * significantly for system emulation of AArch64 CPUs.
3425 */
3426 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
3427 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
3428 .access = PL0_RW, .type = ARM_CP_NZCV },
3429 { .name = "DAIF", .state = ARM_CP_STATE_AA64,
3430 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
3431 .type = ARM_CP_NO_RAW,
3432 .access = PL0_RW, .accessfn = aa64_daif_access,
3433 .fieldoffset = offsetof(CPUARMState, daif),
3434 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
3435 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
3436 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
3437 .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
3438 .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
3439 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
3440 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
3441 .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
3442 .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
3443 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
3444 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
3445 .access = PL0_R, .type = ARM_CP_NO_RAW,
3446 .readfn = aa64_dczid_read },
3447 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
3448 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
3449 .access = PL0_W, .type = ARM_CP_DC_ZVA,
3450 #ifndef CONFIG_USER_ONLY
3451 /* Avoid overhead of an access check that always passes in user-mode */
3452 .accessfn = aa64_zva_access,
3453 #endif
3454 },
3455 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
3456 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
3457 .access = PL1_R, .type = ARM_CP_CURRENTEL },
3458 /* Cache ops: all NOPs since we don't emulate caches */
3459 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
3460 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3461 .access = PL1_W, .type = ARM_CP_NOP },
3462 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
3463 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3464 .access = PL1_W, .type = ARM_CP_NOP },
3465 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
3466 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
3467 .access = PL0_W, .type = ARM_CP_NOP,
3468 .accessfn = aa64_cacheop_access },
3469 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
3470 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3471 .access = PL1_W, .type = ARM_CP_NOP },
3472 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
3473 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3474 .access = PL1_W, .type = ARM_CP_NOP },
3475 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
3476 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
3477 .access = PL0_W, .type = ARM_CP_NOP,
3478 .accessfn = aa64_cacheop_access },
3479 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
3480 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3481 .access = PL1_W, .type = ARM_CP_NOP },
3482 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
3483 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
3484 .access = PL0_W, .type = ARM_CP_NOP,
3485 .accessfn = aa64_cacheop_access },
3486 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
3487 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
3488 .access = PL0_W, .type = ARM_CP_NOP,
3489 .accessfn = aa64_cacheop_access },
3490 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
3491 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3492 .access = PL1_W, .type = ARM_CP_NOP },
3493 /* TLBI operations */
3494 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
3495 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
3496 .access = PL1_W, .type = ARM_CP_NO_RAW,
3497 .writefn = tlbi_aa64_vmalle1is_write },
3498 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
3499 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
3500 .access = PL1_W, .type = ARM_CP_NO_RAW,
3501 .writefn = tlbi_aa64_vae1is_write },
3502 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
3503 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
3504 .access = PL1_W, .type = ARM_CP_NO_RAW,
3505 .writefn = tlbi_aa64_vmalle1is_write },
3506 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
3507 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
3508 .access = PL1_W, .type = ARM_CP_NO_RAW,
3509 .writefn = tlbi_aa64_vae1is_write },
3510 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
3511 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3512 .access = PL1_W, .type = ARM_CP_NO_RAW,
3513 .writefn = tlbi_aa64_vae1is_write },
3514 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
3515 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3516 .access = PL1_W, .type = ARM_CP_NO_RAW,
3517 .writefn = tlbi_aa64_vae1is_write },
3518 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
3519 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
3520 .access = PL1_W, .type = ARM_CP_NO_RAW,
3521 .writefn = tlbi_aa64_vmalle1_write },
3522 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
3523 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
3524 .access = PL1_W, .type = ARM_CP_NO_RAW,
3525 .writefn = tlbi_aa64_vae1_write },
3526 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
3527 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
3528 .access = PL1_W, .type = ARM_CP_NO_RAW,
3529 .writefn = tlbi_aa64_vmalle1_write },
3530 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
3531 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
3532 .access = PL1_W, .type = ARM_CP_NO_RAW,
3533 .writefn = tlbi_aa64_vae1_write },
3534 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
3535 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3536 .access = PL1_W, .type = ARM_CP_NO_RAW,
3537 .writefn = tlbi_aa64_vae1_write },
3538 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
3539 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3540 .access = PL1_W, .type = ARM_CP_NO_RAW,
3541 .writefn = tlbi_aa64_vae1_write },
3542 { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
3543 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3544 .access = PL2_W, .type = ARM_CP_NO_RAW,
3545 .writefn = tlbi_aa64_ipas2e1is_write },
3546 { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
3547 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3548 .access = PL2_W, .type = ARM_CP_NO_RAW,
3549 .writefn = tlbi_aa64_ipas2e1is_write },
3550 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
3551 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
3552 .access = PL2_W, .type = ARM_CP_NO_RAW,
3553 .writefn = tlbi_aa64_alle1is_write },
3554 { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
3555 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
3556 .access = PL2_W, .type = ARM_CP_NO_RAW,
3557 .writefn = tlbi_aa64_alle1is_write },
3558 { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
3559 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3560 .access = PL2_W, .type = ARM_CP_NO_RAW,
3561 .writefn = tlbi_aa64_ipas2e1_write },
3562 { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
3563 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3564 .access = PL2_W, .type = ARM_CP_NO_RAW,
3565 .writefn = tlbi_aa64_ipas2e1_write },
3566 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
3567 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
3568 .access = PL2_W, .type = ARM_CP_NO_RAW,
3569 .writefn = tlbi_aa64_alle1_write },
3570 { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
3571 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
3572 .access = PL2_W, .type = ARM_CP_NO_RAW,
3573 .writefn = tlbi_aa64_alle1is_write },
3574 #ifndef CONFIG_USER_ONLY
3575 /* 64 bit address translation operations */
3576 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
3577 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
3578 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3579 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
3580 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
3581 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3582 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
3583 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
3584 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3585 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
3586 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
3587 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3588 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
3589 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
3590 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3591 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
3592 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
3593 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3594 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
3595 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
3596 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3597 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
3598 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
3599 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3600 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3601 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
3602 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
3603 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3604 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
3605 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
3606 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3607 { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
3608 .type = ARM_CP_ALIAS,
3609 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
3610 .access = PL1_RW, .resetvalue = 0,
3611 .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
3612 .writefn = par_write },
3613 #endif
3614 /* TLB invalidate last level of translation table walk */
3615 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3616 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3617 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3618 .type = ARM_CP_NO_RAW, .access = PL1_W,
3619 .writefn = tlbimvaa_is_write },
3620 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3621 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3622 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3623 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3624 { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3625 .type = ARM_CP_NO_RAW, .access = PL2_W,
3626 .writefn = tlbimva_hyp_write },
3627 { .name = "TLBIMVALHIS",
3628 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3629 .type = ARM_CP_NO_RAW, .access = PL2_W,
3630 .writefn = tlbimva_hyp_is_write },
3631 { .name = "TLBIIPAS2",
3632 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3633 .type = ARM_CP_NO_RAW, .access = PL2_W,
3634 .writefn = tlbiipas2_write },
3635 { .name = "TLBIIPAS2IS",
3636 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3637 .type = ARM_CP_NO_RAW, .access = PL2_W,
3638 .writefn = tlbiipas2_is_write },
3639 { .name = "TLBIIPAS2L",
3640 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3641 .type = ARM_CP_NO_RAW, .access = PL2_W,
3642 .writefn = tlbiipas2_write },
3643 { .name = "TLBIIPAS2LIS",
3644 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3645 .type = ARM_CP_NO_RAW, .access = PL2_W,
3646 .writefn = tlbiipas2_is_write },
3647 /* 32 bit cache operations */
3648 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3649 .type = ARM_CP_NOP, .access = PL1_W },
3650 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3651 .type = ARM_CP_NOP, .access = PL1_W },
3652 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3653 .type = ARM_CP_NOP, .access = PL1_W },
3654 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3655 .type = ARM_CP_NOP, .access = PL1_W },
3656 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3657 .type = ARM_CP_NOP, .access = PL1_W },
3658 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3659 .type = ARM_CP_NOP, .access = PL1_W },
3660 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3661 .type = ARM_CP_NOP, .access = PL1_W },
3662 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3663 .type = ARM_CP_NOP, .access = PL1_W },
3664 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3665 .type = ARM_CP_NOP, .access = PL1_W },
3666 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3667 .type = ARM_CP_NOP, .access = PL1_W },
3668 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3669 .type = ARM_CP_NOP, .access = PL1_W },
3670 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3671 .type = ARM_CP_NOP, .access = PL1_W },
3672 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3673 .type = ARM_CP_NOP, .access = PL1_W },
3674 /* MMU Domain access control / MPU write buffer control */
3675 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3676 .access = PL1_RW, .resetvalue = 0,
3677 .writefn = dacr_write, .raw_writefn = raw_write,
3678 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3679 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3680 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3681 .type = ARM_CP_ALIAS,
3682 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3683 .access = PL1_RW,
3684 .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3685 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3686 .type = ARM_CP_ALIAS,
3687 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3688 .access = PL1_RW,
3689 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
3690 /* We rely on the access checks not allowing the guest to write to the
3691 * state field when SPSel indicates that it's being used as the stack
3692 * pointer.
3693 */
3694 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3695 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3696 .access = PL1_RW, .accessfn = sp_el0_access,
3697 .type = ARM_CP_ALIAS,
3698 .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3699 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3700 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3701 .access = PL2_RW, .type = ARM_CP_ALIAS,
3702 .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3703 { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3704 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3705 .type = ARM_CP_NO_RAW,
3706 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3707 { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
3708 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
3709 .type = ARM_CP_ALIAS,
3710 .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
3711 .access = PL2_RW, .accessfn = fpexc32_access },
3712 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3713 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3714 .access = PL2_RW, .resetvalue = 0,
3715 .writefn = dacr_write, .raw_writefn = raw_write,
3716 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3717 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3718 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3719 .access = PL2_RW, .resetvalue = 0,
3720 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3721 { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
3722 .type = ARM_CP_ALIAS,
3723 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
3724 .access = PL2_RW,
3725 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
3726 { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
3727 .type = ARM_CP_ALIAS,
3728 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
3729 .access = PL2_RW,
3730 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
3731 { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
3732 .type = ARM_CP_ALIAS,
3733 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
3734 .access = PL2_RW,
3735 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
3736 { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
3737 .type = ARM_CP_ALIAS,
3738 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
3739 .access = PL2_RW,
3740 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
3741 { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
3742 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
3743 .resetvalue = 0,
3744 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
3745 { .name = "SDCR", .type = ARM_CP_ALIAS,
3746 .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
3747 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3748 .writefn = sdcr_write,
3749 .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
3750 REGINFO_SENTINEL
3751 };
3752
3753 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
3754 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3755 { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
3756 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3757 .access = PL2_RW,
3758 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3759 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
3760 .type = ARM_CP_NO_RAW,
3761 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3762 .access = PL2_RW,
3763 .type = ARM_CP_CONST, .resetvalue = 0 },
3764 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
3765 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3766 .access = PL2_RW,
3767 .type = ARM_CP_CONST, .resetvalue = 0 },
3768 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3769 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3770 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3771 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3772 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3773 .access = PL2_RW, .type = ARM_CP_CONST,
3774 .resetvalue = 0 },
3775 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3776 .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3777 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3778 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3779 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3780 .access = PL2_RW, .type = ARM_CP_CONST,
3781 .resetvalue = 0 },
3782 { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
3783 .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3784 .access = PL2_RW, .type = ARM_CP_CONST,
3785 .resetvalue = 0 },
3786 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3787 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3788 .access = PL2_RW, .type = ARM_CP_CONST,
3789 .resetvalue = 0 },
3790 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3791 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3792 .access = PL2_RW, .type = ARM_CP_CONST,
3793 .resetvalue = 0 },
3794 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3795 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3796 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3797 { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
3798 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3799 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3800 .type = ARM_CP_CONST, .resetvalue = 0 },
3801 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3802 .cp = 15, .opc1 = 6, .crm = 2,
3803 .access = PL2_RW, .accessfn = access_el3_aa32ns,
3804 .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
3805 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3806 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3807 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3808 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3809 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3810 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3811 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3812 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3813 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3814 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3815 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3816 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3817 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3818 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3819 .resetvalue = 0 },
3820 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3821 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3822 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3823 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3824 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3825 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3826 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3827 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3828 .resetvalue = 0 },
3829 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3830 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3831 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3832 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3833 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3834 .resetvalue = 0 },
3835 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3836 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3837 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3838 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3839 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3840 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3841 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3842 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3843 .access = PL2_RW, .accessfn = access_tda,
3844 .type = ARM_CP_CONST, .resetvalue = 0 },
3845 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
3846 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3847 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3848 .type = ARM_CP_CONST, .resetvalue = 0 },
3849 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
3850 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
3851 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3852 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
3853 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3854 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3855 { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
3856 .type = ARM_CP_CONST,
3857 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
3858 .access = PL2_RW, .resetvalue = 0 },
3859 REGINFO_SENTINEL
3860 };
3861
3862 /* Ditto, but for registers which exist in ARMv8 but not v7 */
3863 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
3864 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
3865 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
3866 .access = PL2_RW,
3867 .type = ARM_CP_CONST, .resetvalue = 0 },
3868 REGINFO_SENTINEL
3869 };
3870
3871 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3872 {
3873 ARMCPU *cpu = arm_env_get_cpu(env);
3874 uint64_t valid_mask = HCR_MASK;
3875
3876 if (arm_feature(env, ARM_FEATURE_EL3)) {
3877 valid_mask &= ~HCR_HCD;
3878 } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
3879 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
3880 * However, if we're using the SMC PSCI conduit then QEMU is
3881 * effectively acting like EL3 firmware and so the guest at
3882 * EL2 should retain the ability to prevent EL1 from being
3883 * able to make SMC calls into the ersatz firmware, so in
3884 * that case HCR.TSC should be read/write.
3885 */
3886 valid_mask &= ~HCR_TSC;
3887 }
3888
3889 /* Clear RES0 bits. */
3890 value &= valid_mask;
3891
3892 /* These bits change the MMU setup:
3893 * HCR_VM enables stage 2 translation
3894 * HCR_PTW forbids certain page-table setups
3895 * HCR_DC Disables stage1 and enables stage2 translation
3896 */
3897 if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3898 tlb_flush(CPU(cpu));
3899 }
3900 env->cp15.hcr_el2 = value;
3901 }
3902
3903 static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri,
3904 uint64_t value)
3905 {
3906 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
3907 value = deposit64(env->cp15.hcr_el2, 32, 32, value);
3908 hcr_write(env, NULL, value);
3909 }
3910
3911 static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
3912 uint64_t value)
3913 {
3914 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
3915 value = deposit64(env->cp15.hcr_el2, 0, 32, value);
3916 hcr_write(env, NULL, value);
3917 }
3918
3919 static const ARMCPRegInfo el2_cp_reginfo[] = {
3920 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3921 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3922 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3923 .writefn = hcr_write },
3924 { .name = "HCR", .state = ARM_CP_STATE_AA32,
3925 .type = ARM_CP_ALIAS,
3926 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3927 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3928 .writefn = hcr_writelow },
3929 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3930 .type = ARM_CP_ALIAS,
3931 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3932 .access = PL2_RW,
3933 .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3934 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
3935 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3936 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3937 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
3938 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3939 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3940 { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
3941 .type = ARM_CP_ALIAS,
3942 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
3943 .access = PL2_RW,
3944 .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) },
3945 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3946 .type = ARM_CP_ALIAS,
3947 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3948 .access = PL2_RW,
3949 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
3950 { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
3951 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3952 .access = PL2_RW, .writefn = vbar_write,
3953 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3954 .resetvalue = 0 },
3955 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3956 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3957 .access = PL3_RW, .type = ARM_CP_ALIAS,
3958 .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3959 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3960 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3961 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3962 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3963 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3964 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3965 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3966 .resetvalue = 0 },
3967 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3968 .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3969 .access = PL2_RW, .type = ARM_CP_ALIAS,
3970 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3971 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3972 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3973 .access = PL2_RW, .type = ARM_CP_CONST,
3974 .resetvalue = 0 },
3975 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3976 { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
3977 .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3978 .access = PL2_RW, .type = ARM_CP_CONST,
3979 .resetvalue = 0 },
3980 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3981 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3982 .access = PL2_RW, .type = ARM_CP_CONST,
3983 .resetvalue = 0 },
3984 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3985 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3986 .access = PL2_RW, .type = ARM_CP_CONST,
3987 .resetvalue = 0 },
3988 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3989 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3990 .access = PL2_RW,
3991 /* no .writefn needed as this can't cause an ASID change;
3992 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3993 */
3994 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3995 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
3996 .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3997 .type = ARM_CP_ALIAS,
3998 .access = PL2_RW, .accessfn = access_el3_aa32ns,
3999 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
4000 { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
4001 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
4002 .access = PL2_RW,
4003 /* no .writefn needed as this can't cause an ASID change;
4004 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
4005 */
4006 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
4007 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
4008 .cp = 15, .opc1 = 6, .crm = 2,
4009 .type = ARM_CP_64BIT | ARM_CP_ALIAS,
4010 .access = PL2_RW, .accessfn = access_el3_aa32ns,
4011 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
4012 .writefn = vttbr_write },
4013 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
4014 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
4015 .access = PL2_RW, .writefn = vttbr_write,
4016 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
4017 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
4018 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
4019 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
4020 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
4021 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4022 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
4023 .access = PL2_RW, .resetvalue = 0,
4024 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
4025 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
4026 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
4027 .access = PL2_RW, .resetvalue = 0,
4028 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
4029 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
4030 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
4031 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
4032 { .name = "TLBIALLNSNH",
4033 .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
4034 .type = ARM_CP_NO_RAW, .access = PL2_W,
4035 .writefn = tlbiall_nsnh_write },
4036 { .name = "TLBIALLNSNHIS",
4037 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
4038 .type = ARM_CP_NO_RAW, .access = PL2_W,
4039 .writefn = tlbiall_nsnh_is_write },
4040 { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
4041 .type = ARM_CP_NO_RAW, .access = PL2_W,
4042 .writefn = tlbiall_hyp_write },
4043 { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
4044 .type = ARM_CP_NO_RAW, .access = PL2_W,
4045 .writefn = tlbiall_hyp_is_write },
4046 { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
4047 .type = ARM_CP_NO_RAW, .access = PL2_W,
4048 .writefn = tlbimva_hyp_write },
4049 { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
4050 .type = ARM_CP_NO_RAW, .access = PL2_W,
4051 .writefn = tlbimva_hyp_is_write },
4052 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
4053 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
4054 .type = ARM_CP_NO_RAW, .access = PL2_W,
4055 .writefn = tlbi_aa64_alle2_write },
4056 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
4057 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
4058 .type = ARM_CP_NO_RAW, .access = PL2_W,
4059 .writefn = tlbi_aa64_vae2_write },
4060 { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
4061 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
4062 .access = PL2_W, .type = ARM_CP_NO_RAW,
4063 .writefn = tlbi_aa64_vae2_write },
4064 { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
4065 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
4066 .access = PL2_W, .type = ARM_CP_NO_RAW,
4067 .writefn = tlbi_aa64_alle2is_write },
4068 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
4069 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
4070 .type = ARM_CP_NO_RAW, .access = PL2_W,
4071 .writefn = tlbi_aa64_vae2is_write },
4072 { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
4073 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
4074 .access = PL2_W, .type = ARM_CP_NO_RAW,
4075 .writefn = tlbi_aa64_vae2is_write },
4076 #ifndef CONFIG_USER_ONLY
4077 /* Unlike the other EL2-related AT operations, these must
4078 * UNDEF from EL3 if EL2 is not implemented, which is why we
4079 * define them here rather than with the rest of the AT ops.
4080 */
4081 { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
4082 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
4083 .access = PL2_W, .accessfn = at_s1e2_access,
4084 .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
4085 { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
4086 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
4087 .access = PL2_W, .accessfn = at_s1e2_access,
4088 .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
4089 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
4090 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
4091 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
4092 * to behave as if SCR.NS was 1.
4093 */
4094 { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
4095 .access = PL2_W,
4096 .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
4097 { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
4098 .access = PL2_W,
4099 .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
4100 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
4101 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
4102 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
4103 * reset values as IMPDEF. We choose to reset to 3 to comply with
4104 * both ARMv7 and ARMv8.
4105 */
4106 .access = PL2_RW, .resetvalue = 3,
4107 .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
4108 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
4109 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
4110 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
4111 .writefn = gt_cntvoff_write,
4112 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
4113 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
4114 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
4115 .writefn = gt_cntvoff_write,
4116 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
4117 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
4118 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
4119 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
4120 .type = ARM_CP_IO, .access = PL2_RW,
4121 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
4122 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
4123 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
4124 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
4125 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
4126 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
4127 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
4128 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
4129 .resetfn = gt_hyp_timer_reset,
4130 .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
4131 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
4132 .type = ARM_CP_IO,
4133 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
4134 .access = PL2_RW,
4135 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
4136 .resetvalue = 0,
4137 .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
4138 #endif
4139 /* The only field of MDCR_EL2 that has a defined architectural reset value
4140 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
4141 * don't impelment any PMU event counters, so using zero as a reset
4142 * value for MDCR_EL2 is okay
4143 */
4144 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
4145 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
4146 .access = PL2_RW, .resetvalue = 0,
4147 .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
4148 { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
4149 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
4150 .access = PL2_RW, .accessfn = access_el3_aa32ns,
4151 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
4152 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
4153 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
4154 .access = PL2_RW,
4155 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
4156 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
4157 .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
4158 .access = PL2_RW,
4159 .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
4160 REGINFO_SENTINEL
4161 };
4162
4163 static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
4164 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
4165 .type = ARM_CP_ALIAS,
4166 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
4167 .access = PL2_RW,
4168 .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
4169 .writefn = hcr_writehigh },
4170 REGINFO_SENTINEL
4171 };
4172
4173 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
4174 bool isread)
4175 {
4176 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
4177 * At Secure EL1 it traps to EL3.
4178 */
4179 if (arm_current_el(env) == 3) {
4180 return CP_ACCESS_OK;
4181 }
4182 if (arm_is_secure_below_el3(env)) {
4183 return CP_ACCESS_TRAP_EL3;
4184 }
4185 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
4186 if (isread) {
4187 return CP_ACCESS_OK;
4188 }
4189 return CP_ACCESS_TRAP_UNCATEGORIZED;
4190 }
4191
4192 static const ARMCPRegInfo el3_cp_reginfo[] = {
4193 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
4194 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
4195 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
4196 .resetvalue = 0, .writefn = scr_write },
4197 { .name = "SCR", .type = ARM_CP_ALIAS,
4198 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
4199 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
4200 .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
4201 .writefn = scr_write },
4202 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
4203 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
4204 .access = PL3_RW, .resetvalue = 0,
4205 .fieldoffset = offsetof(CPUARMState, cp15.sder) },
4206 { .name = "SDER",
4207 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
4208 .access = PL3_RW, .resetvalue = 0,
4209 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
4210 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4211 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
4212 .writefn = vbar_write, .resetvalue = 0,
4213 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
4214 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
4215 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
4216 .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
4217 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
4218 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
4219 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
4220 .access = PL3_RW,
4221 /* no .writefn needed as this can't cause an ASID change;
4222 * we must provide a .raw_writefn and .resetfn because we handle
4223 * reset and migration for the AArch32 TTBCR(S), which might be
4224 * using mask and base_mask.
4225 */
4226 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
4227 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
4228 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
4229 .type = ARM_CP_ALIAS,
4230 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
4231 .access = PL3_RW,
4232 .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
4233 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
4234 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
4235 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
4236 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
4237 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
4238 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
4239 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
4240 .type = ARM_CP_ALIAS,
4241 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
4242 .access = PL3_RW,
4243 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
4244 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
4245 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
4246 .access = PL3_RW, .writefn = vbar_write,
4247 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
4248 .resetvalue = 0 },
4249 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
4250 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
4251 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
4252 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
4253 { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
4254 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
4255 .access = PL3_RW, .resetvalue = 0,
4256 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
4257 { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
4258 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
4259 .access = PL3_RW, .type = ARM_CP_CONST,
4260 .resetvalue = 0 },
4261 { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
4262 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
4263 .access = PL3_RW, .type = ARM_CP_CONST,
4264 .resetvalue = 0 },
4265 { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
4266 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
4267 .access = PL3_RW, .type = ARM_CP_CONST,
4268 .resetvalue = 0 },
4269 { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
4270 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
4271 .access = PL3_W, .type = ARM_CP_NO_RAW,
4272 .writefn = tlbi_aa64_alle3is_write },
4273 { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
4274 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
4275 .access = PL3_W, .type = ARM_CP_NO_RAW,
4276 .writefn = tlbi_aa64_vae3is_write },
4277 { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
4278 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
4279 .access = PL3_W, .type = ARM_CP_NO_RAW,
4280 .writefn = tlbi_aa64_vae3is_write },
4281 { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
4282 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
4283 .access = PL3_W, .type = ARM_CP_NO_RAW,
4284 .writefn = tlbi_aa64_alle3_write },
4285 { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
4286 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
4287 .access = PL3_W, .type = ARM_CP_NO_RAW,
4288 .writefn = tlbi_aa64_vae3_write },
4289 { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
4290 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
4291 .access = PL3_W, .type = ARM_CP_NO_RAW,
4292 .writefn = tlbi_aa64_vae3_write },
4293 REGINFO_SENTINEL
4294 };
4295
4296 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
4297 bool isread)
4298 {
4299 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
4300 * but the AArch32 CTR has its own reginfo struct)
4301 */
4302 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
4303 return CP_ACCESS_TRAP;
4304 }
4305 return CP_ACCESS_OK;
4306 }
4307
4308 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
4309 uint64_t value)
4310 {
4311 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
4312 * read via a bit in OSLSR_EL1.
4313 */
4314 int oslock;
4315
4316 if (ri->state == ARM_CP_STATE_AA32) {
4317 oslock = (value == 0xC5ACCE55);
4318 } else {
4319 oslock = value & 1;
4320 }
4321
4322 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
4323 }
4324
4325 static const ARMCPRegInfo debug_cp_reginfo[] = {
4326 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
4327 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
4328 * unlike DBGDRAR it is never accessible from EL0.
4329 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
4330 * accessor.
4331 */
4332 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
4333 .access = PL0_R, .accessfn = access_tdra,
4334 .type = ARM_CP_CONST, .resetvalue = 0 },
4335 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
4336 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4337 .access = PL1_R, .accessfn = access_tdra,
4338 .type = ARM_CP_CONST, .resetvalue = 0 },
4339 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
4340 .access = PL0_R, .accessfn = access_tdra,
4341 .type = ARM_CP_CONST, .resetvalue = 0 },
4342 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
4343 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
4344 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4345 .access = PL1_RW, .accessfn = access_tda,
4346 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
4347 .resetvalue = 0 },
4348 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
4349 * We don't implement the configurable EL0 access.
4350 */
4351 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
4352 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4353 .type = ARM_CP_ALIAS,
4354 .access = PL1_R, .accessfn = access_tda,
4355 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
4356 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
4357 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
4358 .access = PL1_W, .type = ARM_CP_NO_RAW,
4359 .accessfn = access_tdosa,
4360 .writefn = oslar_write },
4361 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
4362 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
4363 .access = PL1_R, .resetvalue = 10,
4364 .accessfn = access_tdosa,
4365 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
4366 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
4367 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
4368 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
4369 .access = PL1_RW, .accessfn = access_tdosa,
4370 .type = ARM_CP_NOP },
4371 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
4372 * implement vector catch debug events yet.
4373 */
4374 { .name = "DBGVCR",
4375 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4376 .access = PL1_RW, .accessfn = access_tda,
4377 .type = ARM_CP_NOP },
4378 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
4379 * to save and restore a 32-bit guest's DBGVCR)
4380 */
4381 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
4382 .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
4383 .access = PL2_RW, .accessfn = access_tda,
4384 .type = ARM_CP_NOP },
4385 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
4386 * Channel but Linux may try to access this register. The 32-bit
4387 * alias is DBGDCCINT.
4388 */
4389 { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
4390 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4391 .access = PL1_RW, .accessfn = access_tda,
4392 .type = ARM_CP_NOP },
4393 REGINFO_SENTINEL
4394 };
4395
4396 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
4397 /* 64 bit access versions of the (dummy) debug registers */
4398 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
4399 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
4400 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
4401 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
4402 REGINFO_SENTINEL
4403 };
4404
4405 /* Return the exception level to which exceptions should be taken
4406 * via SVEAccessTrap. If an exception should be routed through
4407 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
4408 * take care of raising that exception.
4409 * C.f. the ARM pseudocode function CheckSVEEnabled.
4410 */
4411 int sve_exception_el(CPUARMState *env, int el)
4412 {
4413 #ifndef CONFIG_USER_ONLY
4414 if (el <= 1) {
4415 bool disabled = false;
4416
4417 /* The CPACR.ZEN controls traps to EL1:
4418 * 0, 2 : trap EL0 and EL1 accesses
4419 * 1 : trap only EL0 accesses
4420 * 3 : trap no accesses
4421 */
4422 if (!extract32(env->cp15.cpacr_el1, 16, 1)) {
4423 disabled = true;
4424 } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) {
4425 disabled = el == 0;
4426 }
4427 if (disabled) {
4428 /* route_to_el2 */
4429 return (arm_feature(env, ARM_FEATURE_EL2)
4430 && !arm_is_secure(env)
4431 && (env->cp15.hcr_el2 & HCR_TGE) ? 2 : 1);
4432 }
4433
4434 /* Check CPACR.FPEN. */
4435 if (!extract32(env->cp15.cpacr_el1, 20, 1)) {
4436 disabled = true;
4437 } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) {
4438 disabled = el == 0;
4439 }
4440 if (disabled) {
4441 return 0;
4442 }
4443 }
4444
4445 /* CPTR_EL2. Since TZ and TFP are positive,
4446 * they will be zero when EL2 is not present.
4447 */
4448 if (el <= 2 && !arm_is_secure_below_el3(env)) {
4449 if (env->cp15.cptr_el[2] & CPTR_TZ) {
4450 return 2;
4451 }
4452 if (env->cp15.cptr_el[2] & CPTR_TFP) {
4453 return 0;
4454 }
4455 }
4456
4457 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
4458 if (arm_feature(env, ARM_FEATURE_EL3)
4459 && !(env->cp15.cptr_el[3] & CPTR_EZ)) {
4460 return 3;
4461 }
4462 #endif
4463 return 0;
4464 }
4465
4466 /*
4467 * Given that SVE is enabled, return the vector length for EL.
4468 */
4469 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
4470 {
4471 ARMCPU *cpu = arm_env_get_cpu(env);
4472 uint32_t zcr_len = cpu->sve_max_vq - 1;
4473
4474 if (el <= 1) {
4475 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
4476 }
4477 if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
4478 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
4479 }
4480 if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
4481 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
4482 }
4483 return zcr_len;
4484 }
4485
4486 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4487 uint64_t value)
4488 {
4489 int cur_el = arm_current_el(env);
4490 int old_len = sve_zcr_len_for_el(env, cur_el);
4491 int new_len;
4492
4493 /* Bits other than [3:0] are RAZ/WI. */
4494 raw_write(env, ri, value & 0xf);
4495
4496 /*
4497 * Because we arrived here, we know both FP and SVE are enabled;
4498 * otherwise we would have trapped access to the ZCR_ELn register.
4499 */
4500 new_len = sve_zcr_len_for_el(env, cur_el);
4501 if (new_len < old_len) {
4502 aarch64_sve_narrow_vq(env, new_len + 1);
4503 }
4504 }
4505
4506 static const ARMCPRegInfo zcr_el1_reginfo = {
4507 .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
4508 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
4509 .access = PL1_RW, .type = ARM_CP_SVE,
4510 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
4511 .writefn = zcr_write, .raw_writefn = raw_write
4512 };
4513
4514 static const ARMCPRegInfo zcr_el2_reginfo = {
4515 .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
4516 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
4517 .access = PL2_RW, .type = ARM_CP_SVE,
4518 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
4519 .writefn = zcr_write, .raw_writefn = raw_write
4520 };
4521
4522 static const ARMCPRegInfo zcr_no_el2_reginfo = {
4523 .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
4524 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
4525 .access = PL2_RW, .type = ARM_CP_SVE,
4526 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
4527 };
4528
4529 static const ARMCPRegInfo zcr_el3_reginfo = {
4530 .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
4531 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
4532 .access = PL3_RW, .type = ARM_CP_SVE,
4533 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
4534 .writefn = zcr_write, .raw_writefn = raw_write
4535 };
4536
4537 void hw_watchpoint_update(ARMCPU *cpu, int n)
4538 {
4539 CPUARMState *env = &cpu->env;
4540 vaddr len = 0;
4541 vaddr wvr = env->cp15.dbgwvr[n];
4542 uint64_t wcr = env->cp15.dbgwcr[n];
4543 int mask;
4544 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
4545
4546 if (env->cpu_watchpoint[n]) {
4547 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
4548 env->cpu_watchpoint[n] = NULL;
4549 }
4550
4551 if (!extract64(wcr, 0, 1)) {
4552 /* E bit clear : watchpoint disabled */
4553 return;
4554 }
4555
4556 switch (extract64(wcr, 3, 2)) {
4557 case 0:
4558 /* LSC 00 is reserved and must behave as if the wp is disabled */
4559 return;
4560 case 1:
4561 flags |= BP_MEM_READ;
4562 break;
4563 case 2:
4564 flags |= BP_MEM_WRITE;
4565 break;
4566 case 3:
4567 flags |= BP_MEM_ACCESS;
4568 break;
4569 }
4570
4571 /* Attempts to use both MASK and BAS fields simultaneously are
4572 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
4573 * thus generating a watchpoint for every byte in the masked region.
4574 */
4575 mask = extract64(wcr, 24, 4);
4576 if (mask == 1 || mask == 2) {
4577 /* Reserved values of MASK; we must act as if the mask value was
4578 * some non-reserved value, or as if the watchpoint were disabled.
4579 * We choose the latter.
4580 */
4581 return;
4582 } else if (mask) {
4583 /* Watchpoint covers an aligned area up to 2GB in size */
4584 len = 1ULL << mask;
4585 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
4586 * whether the watchpoint fires when the unmasked bits match; we opt
4587 * to generate the exceptions.
4588 */
4589 wvr &= ~(len - 1);
4590 } else {
4591 /* Watchpoint covers bytes defined by the byte address select bits */
4592 int bas = extract64(wcr, 5, 8);
4593 int basstart;
4594
4595 if (bas == 0) {
4596 /* This must act as if the watchpoint is disabled */
4597 return;
4598 }
4599
4600 if (extract64(wvr, 2, 1)) {
4601 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
4602 * ignored, and BAS[3:0] define which bytes to watch.
4603 */
4604 bas &= 0xf;
4605 }
4606 /* The BAS bits are supposed to be programmed to indicate a contiguous
4607 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
4608 * we fire for each byte in the word/doubleword addressed by the WVR.
4609 * We choose to ignore any non-zero bits after the first range of 1s.
4610 */
4611 basstart = ctz32(bas);
4612 len = cto32(bas >> basstart);
4613 wvr += basstart;
4614 }
4615
4616 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
4617 &env->cpu_watchpoint[n]);
4618 }
4619
4620 void hw_watchpoint_update_all(ARMCPU *cpu)
4621 {
4622 int i;
4623 CPUARMState *env = &cpu->env;
4624
4625 /* Completely clear out existing QEMU watchpoints and our array, to
4626 * avoid possible stale entries following migration load.
4627 */
4628 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
4629 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
4630
4631 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
4632 hw_watchpoint_update(cpu, i);
4633 }
4634 }
4635
4636 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4637 uint64_t value)
4638 {
4639 ARMCPU *cpu = arm_env_get_cpu(env);
4640 int i = ri->crm;
4641
4642 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4643 * register reads and behaves as if values written are sign extended.
4644 * Bits [1:0] are RES0.
4645 */
4646 value = sextract64(value, 0, 49) & ~3ULL;
4647
4648 raw_write(env, ri, value);
4649 hw_watchpoint_update(cpu, i);
4650 }
4651
4652 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4653 uint64_t value)
4654 {
4655 ARMCPU *cpu = arm_env_get_cpu(env);
4656 int i = ri->crm;
4657
4658 raw_write(env, ri, value);
4659 hw_watchpoint_update(cpu, i);
4660 }
4661
4662 void hw_breakpoint_update(ARMCPU *cpu, int n)
4663 {
4664 CPUARMState *env = &cpu->env;
4665 uint64_t bvr = env->cp15.dbgbvr[n];
4666 uint64_t bcr = env->cp15.dbgbcr[n];
4667 vaddr addr;
4668 int bt;
4669 int flags = BP_CPU;
4670
4671 if (env->cpu_breakpoint[n]) {
4672 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
4673 env->cpu_breakpoint[n] = NULL;
4674 }
4675
4676 if (!extract64(bcr, 0, 1)) {
4677 /* E bit clear : watchpoint disabled */
4678 return;
4679 }
4680
4681 bt = extract64(bcr, 20, 4);
4682
4683 switch (bt) {
4684 case 4: /* unlinked address mismatch (reserved if AArch64) */
4685 case 5: /* linked address mismatch (reserved if AArch64) */
4686 qemu_log_mask(LOG_UNIMP,
4687 "arm: address mismatch breakpoint types not implemented\n");
4688 return;
4689 case 0: /* unlinked address match */
4690 case 1: /* linked address match */
4691 {
4692 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4693 * we behave as if the register was sign extended. Bits [1:0] are
4694 * RES0. The BAS field is used to allow setting breakpoints on 16
4695 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4696 * a bp will fire if the addresses covered by the bp and the addresses
4697 * covered by the insn overlap but the insn doesn't start at the
4698 * start of the bp address range. We choose to require the insn and
4699 * the bp to have the same address. The constraints on writing to
4700 * BAS enforced in dbgbcr_write mean we have only four cases:
4701 * 0b0000 => no breakpoint
4702 * 0b0011 => breakpoint on addr
4703 * 0b1100 => breakpoint on addr + 2
4704 * 0b1111 => breakpoint on addr
4705 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4706 */
4707 int bas = extract64(bcr, 5, 4);
4708 addr = sextract64(bvr, 0, 49) & ~3ULL;
4709 if (bas == 0) {
4710 return;
4711 }
4712 if (bas == 0xc) {
4713 addr += 2;
4714 }
4715 break;
4716 }
4717 case 2: /* unlinked context ID match */
4718 case 8: /* unlinked VMID match (reserved if no EL2) */
4719 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4720 qemu_log_mask(LOG_UNIMP,
4721 "arm: unlinked context breakpoint types not implemented\n");
4722 return;
4723 case 9: /* linked VMID match (reserved if no EL2) */
4724 case 11: /* linked context ID and VMID match (reserved if no EL2) */
4725 case 3: /* linked context ID match */
4726 default:
4727 /* We must generate no events for Linked context matches (unless
4728 * they are linked to by some other bp/wp, which is handled in
4729 * updates for the linking bp/wp). We choose to also generate no events
4730 * for reserved values.
4731 */
4732 return;
4733 }
4734
4735 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
4736 }
4737
4738 void hw_breakpoint_update_all(ARMCPU *cpu)
4739 {
4740 int i;
4741 CPUARMState *env = &cpu->env;
4742
4743 /* Completely clear out existing QEMU breakpoints and our array, to
4744 * avoid possible stale entries following migration load.
4745 */
4746 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
4747 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
4748
4749 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
4750 hw_breakpoint_update(cpu, i);
4751 }
4752 }
4753
4754 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4755 uint64_t value)
4756 {
4757 ARMCPU *cpu = arm_env_get_cpu(env);
4758 int i = ri->crm;
4759
4760 raw_write(env, ri, value);
4761 hw_breakpoint_update(cpu, i);
4762 }
4763
4764 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4765 uint64_t value)
4766 {
4767 ARMCPU *cpu = arm_env_get_cpu(env);
4768 int i = ri->crm;
4769
4770 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4771 * copy of BAS[0].
4772 */
4773 value = deposit64(value, 6, 1, extract64(value, 5, 1));
4774 value = deposit64(value, 8, 1, extract64(value, 7, 1));
4775
4776 raw_write(env, ri, value);
4777 hw_breakpoint_update(cpu, i);
4778 }
4779
4780 static void define_debug_regs(ARMCPU *cpu)
4781 {
4782 /* Define v7 and v8 architectural debug registers.
4783 * These are just dummy implementations for now.
4784 */
4785 int i;
4786 int wrps, brps, ctx_cmps;
4787 ARMCPRegInfo dbgdidr = {
4788 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
4789 .access = PL0_R, .accessfn = access_tda,
4790 .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
4791 };
4792
4793 /* Note that all these register fields hold "number of Xs minus 1". */
4794 brps = extract32(cpu->dbgdidr, 24, 4);
4795 wrps = extract32(cpu->dbgdidr, 28, 4);
4796 ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
4797
4798 assert(ctx_cmps <= brps);
4799
4800 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4801 * of the debug registers such as number of breakpoints;
4802 * check that if they both exist then they agree.
4803 */
4804 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
4805 assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
4806 assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
4807 assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
4808 }
4809
4810 define_one_arm_cp_reg(cpu, &dbgdidr);
4811 define_arm_cp_regs(cpu, debug_cp_reginfo);
4812
4813 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
4814 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
4815 }
4816
4817 for (i = 0; i < brps + 1; i++) {
4818 ARMCPRegInfo dbgregs[] = {
4819 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
4820 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
4821 .access = PL1_RW, .accessfn = access_tda,
4822 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
4823 .writefn = dbgbvr_write, .raw_writefn = raw_write
4824 },
4825 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
4826 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
4827 .access = PL1_RW, .accessfn = access_tda,
4828 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
4829 .writefn = dbgbcr_write, .raw_writefn = raw_write
4830 },
4831 REGINFO_SENTINEL
4832 };
4833 define_arm_cp_regs(cpu, dbgregs);
4834 }
4835
4836 for (i = 0; i < wrps + 1; i++) {
4837 ARMCPRegInfo dbgregs[] = {
4838 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
4839 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
4840 .access = PL1_RW, .accessfn = access_tda,
4841 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
4842 .writefn = dbgwvr_write, .raw_writefn = raw_write
4843 },
4844 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
4845 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
4846 .access = PL1_RW, .accessfn = access_tda,
4847 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
4848 .writefn = dbgwcr_write, .raw_writefn = raw_write
4849 },
4850 REGINFO_SENTINEL
4851 };
4852 define_arm_cp_regs(cpu, dbgregs);
4853 }
4854 }
4855
4856 /* We don't know until after realize whether there's a GICv3
4857 * attached, and that is what registers the gicv3 sysregs.
4858 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
4859 * at runtime.
4860 */
4861 static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
4862 {
4863 ARMCPU *cpu = arm_env_get_cpu(env);
4864 uint64_t pfr1 = cpu->id_pfr1;
4865
4866 if (env->gicv3state) {
4867 pfr1 |= 1 << 28;
4868 }
4869 return pfr1;
4870 }
4871
4872 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
4873 {
4874 ARMCPU *cpu = arm_env_get_cpu(env);
4875 uint64_t pfr0 = cpu->id_aa64pfr0;
4876
4877 if (env->gicv3state) {
4878 pfr0 |= 1 << 24;
4879 }
4880 return pfr0;
4881 }
4882
4883 void register_cp_regs_for_features(ARMCPU *cpu)
4884 {
4885 /* Register all the coprocessor registers based on feature bits */
4886 CPUARMState *env = &cpu->env;
4887 if (arm_feature(env, ARM_FEATURE_M)) {
4888 /* M profile has no coprocessor registers */
4889 return;
4890 }
4891
4892 define_arm_cp_regs(cpu, cp_reginfo);
4893 if (!arm_feature(env, ARM_FEATURE_V8)) {
4894 /* Must go early as it is full of wildcards that may be
4895 * overridden by later definitions.
4896 */
4897 define_arm_cp_regs(cpu, not_v8_cp_reginfo);
4898 }
4899
4900 if (arm_feature(env, ARM_FEATURE_V6)) {
4901 /* The ID registers all have impdef reset values */
4902 ARMCPRegInfo v6_idregs[] = {
4903 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
4904 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4905 .access = PL1_R, .type = ARM_CP_CONST,
4906 .resetvalue = cpu->id_pfr0 },
4907 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
4908 * the value of the GIC field until after we define these regs.
4909 */
4910 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
4911 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
4912 .access = PL1_R, .type = ARM_CP_NO_RAW,
4913 .readfn = id_pfr1_read,
4914 .writefn = arm_cp_write_ignore },
4915 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
4916 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
4917 .access = PL1_R, .type = ARM_CP_CONST,
4918 .resetvalue = cpu->id_dfr0 },
4919 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
4920 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
4921 .access = PL1_R, .type = ARM_CP_CONST,
4922 .resetvalue = cpu->id_afr0 },
4923 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
4924 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
4925 .access = PL1_R, .type = ARM_CP_CONST,
4926 .resetvalue = cpu->id_mmfr0 },
4927 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
4928 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
4929 .access = PL1_R, .type = ARM_CP_CONST,
4930 .resetvalue = cpu->id_mmfr1 },
4931 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
4932 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
4933 .access = PL1_R, .type = ARM_CP_CONST,
4934 .resetvalue = cpu->id_mmfr2 },
4935 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
4936 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
4937 .access = PL1_R, .type = ARM_CP_CONST,
4938 .resetvalue = cpu->id_mmfr3 },
4939 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
4940 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4941 .access = PL1_R, .type = ARM_CP_CONST,
4942 .resetvalue = cpu->id_isar0 },
4943 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
4944 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
4945 .access = PL1_R, .type = ARM_CP_CONST,
4946 .resetvalue = cpu->id_isar1 },
4947 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
4948 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4949 .access = PL1_R, .type = ARM_CP_CONST,
4950 .resetvalue = cpu->id_isar2 },
4951 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
4952 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
4953 .access = PL1_R, .type = ARM_CP_CONST,
4954 .resetvalue = cpu->id_isar3 },
4955 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
4956 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
4957 .access = PL1_R, .type = ARM_CP_CONST,
4958 .resetvalue = cpu->id_isar4 },
4959 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
4960 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
4961 .access = PL1_R, .type = ARM_CP_CONST,
4962 .resetvalue = cpu->id_isar5 },
4963 { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
4964 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
4965 .access = PL1_R, .type = ARM_CP_CONST,
4966 .resetvalue = cpu->id_mmfr4 },
4967 { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
4968 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
4969 .access = PL1_R, .type = ARM_CP_CONST,
4970 .resetvalue = cpu->id_isar6 },
4971 REGINFO_SENTINEL
4972 };
4973 define_arm_cp_regs(cpu, v6_idregs);
4974 define_arm_cp_regs(cpu, v6_cp_reginfo);
4975 } else {
4976 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
4977 }
4978 if (arm_feature(env, ARM_FEATURE_V6K)) {
4979 define_arm_cp_regs(cpu, v6k_cp_reginfo);
4980 }
4981 if (arm_feature(env, ARM_FEATURE_V7MP) &&
4982 !arm_feature(env, ARM_FEATURE_PMSA)) {
4983 define_arm_cp_regs(cpu, v7mp_cp_reginfo);
4984 }
4985 if (arm_feature(env, ARM_FEATURE_V7)) {
4986 /* v7 performance monitor control register: same implementor
4987 * field as main ID register, and we implement only the cycle
4988 * count register.
4989 */
4990 #ifndef CONFIG_USER_ONLY
4991 ARMCPRegInfo pmcr = {
4992 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
4993 .access = PL0_RW,
4994 .type = ARM_CP_IO | ARM_CP_ALIAS,
4995 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
4996 .accessfn = pmreg_access, .writefn = pmcr_write,
4997 .raw_writefn = raw_write,
4998 };
4999 ARMCPRegInfo pmcr64 = {
5000 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
5001 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
5002 .access = PL0_RW, .accessfn = pmreg_access,
5003 .type = ARM_CP_IO,
5004 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
5005 .resetvalue = cpu->midr & 0xff000000,
5006 .writefn = pmcr_write, .raw_writefn = raw_write,
5007 };
5008 define_one_arm_cp_reg(cpu, &pmcr);
5009 define_one_arm_cp_reg(cpu, &pmcr64);
5010 #endif
5011 ARMCPRegInfo clidr = {
5012 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
5013 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
5014 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
5015 };
5016 define_one_arm_cp_reg(cpu, &clidr);
5017 define_arm_cp_regs(cpu, v7_cp_reginfo);
5018 define_debug_regs(cpu);
5019 } else {
5020 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
5021 }
5022 if (arm_feature(env, ARM_FEATURE_V8)) {
5023 /* AArch64 ID registers, which all have impdef reset values.
5024 * Note that within the ID register ranges the unused slots
5025 * must all RAZ, not UNDEF; future architecture versions may
5026 * define new registers here.
5027 */
5028 ARMCPRegInfo v8_idregs[] = {
5029 /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
5030 * know the right value for the GIC field until after we
5031 * define these regs.
5032 */
5033 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
5034 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
5035 .access = PL1_R, .type = ARM_CP_NO_RAW,
5036 .readfn = id_aa64pfr0_read,
5037 .writefn = arm_cp_write_ignore },
5038 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
5039 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
5040 .access = PL1_R, .type = ARM_CP_CONST,
5041 .resetvalue = cpu->id_aa64pfr1},
5042 { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5043 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
5044 .access = PL1_R, .type = ARM_CP_CONST,
5045 .resetvalue = 0 },
5046 { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5047 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
5048 .access = PL1_R, .type = ARM_CP_CONST,
5049 .resetvalue = 0 },
5050 { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
5051 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
5052 .access = PL1_R, .type = ARM_CP_CONST,
5053 /* At present, only SVEver == 0 is defined anyway. */
5054 .resetvalue = 0 },
5055 { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5056 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
5057 .access = PL1_R, .type = ARM_CP_CONST,
5058 .resetvalue = 0 },
5059 { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5060 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
5061 .access = PL1_R, .type = ARM_CP_CONST,
5062 .resetvalue = 0 },
5063 { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5064 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
5065 .access = PL1_R, .type = ARM_CP_CONST,
5066 .resetvalue = 0 },
5067 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
5068 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
5069 .access = PL1_R, .type = ARM_CP_CONST,
5070 .resetvalue = cpu->id_aa64dfr0 },
5071 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
5072 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
5073 .access = PL1_R, .type = ARM_CP_CONST,
5074 .resetvalue = cpu->id_aa64dfr1 },
5075 { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5076 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
5077 .access = PL1_R, .type = ARM_CP_CONST,
5078 .resetvalue = 0 },
5079 { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5080 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
5081 .access = PL1_R, .type = ARM_CP_CONST,
5082 .resetvalue = 0 },
5083 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
5084 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
5085 .access = PL1_R, .type = ARM_CP_CONST,
5086 .resetvalue = cpu->id_aa64afr0 },
5087 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
5088 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
5089 .access = PL1_R, .type = ARM_CP_CONST,
5090 .resetvalue = cpu->id_aa64afr1 },
5091 { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5092 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
5093 .access = PL1_R, .type = ARM_CP_CONST,
5094 .resetvalue = 0 },
5095 { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5096 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
5097 .access = PL1_R, .type = ARM_CP_CONST,
5098 .resetvalue = 0 },
5099 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
5100 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
5101 .access = PL1_R, .type = ARM_CP_CONST,
5102 .resetvalue = cpu->id_aa64isar0 },
5103 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
5104 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
5105 .access = PL1_R, .type = ARM_CP_CONST,
5106 .resetvalue = cpu->id_aa64isar1 },
5107 { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5108 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
5109 .access = PL1_R, .type = ARM_CP_CONST,
5110 .resetvalue = 0 },
5111 { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5112 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
5113 .access = PL1_R, .type = ARM_CP_CONST,
5114 .resetvalue = 0 },
5115 { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5116 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
5117 .access = PL1_R, .type = ARM_CP_CONST,
5118 .resetvalue = 0 },
5119 { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5120 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
5121 .access = PL1_R, .type = ARM_CP_CONST,
5122 .resetvalue = 0 },
5123 { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5124 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
5125 .access = PL1_R, .type = ARM_CP_CONST,
5126 .resetvalue = 0 },
5127 { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5128 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
5129 .access = PL1_R, .type = ARM_CP_CONST,
5130 .resetvalue = 0 },
5131 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
5132 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
5133 .access = PL1_R, .type = ARM_CP_CONST,
5134 .resetvalue = cpu->id_aa64mmfr0 },
5135 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
5136 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
5137 .access = PL1_R, .type = ARM_CP_CONST,
5138 .resetvalue = cpu->id_aa64mmfr1 },
5139 { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5140 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
5141 .access = PL1_R, .type = ARM_CP_CONST,
5142 .resetvalue = 0 },
5143 { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5144 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
5145 .access = PL1_R, .type = ARM_CP_CONST,
5146 .resetvalue = 0 },
5147 { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5148 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
5149 .access = PL1_R, .type = ARM_CP_CONST,
5150 .resetvalue = 0 },
5151 { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5152 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
5153 .access = PL1_R, .type = ARM_CP_CONST,
5154 .resetvalue = 0 },
5155 { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5156 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
5157 .access = PL1_R, .type = ARM_CP_CONST,
5158 .resetvalue = 0 },
5159 { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5160 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
5161 .access = PL1_R, .type = ARM_CP_CONST,
5162 .resetvalue = 0 },
5163 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
5164 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
5165 .access = PL1_R, .type = ARM_CP_CONST,
5166 .resetvalue = cpu->mvfr0 },
5167 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
5168 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
5169 .access = PL1_R, .type = ARM_CP_CONST,
5170 .resetvalue = cpu->mvfr1 },
5171 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
5172 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
5173 .access = PL1_R, .type = ARM_CP_CONST,
5174 .resetvalue = cpu->mvfr2 },
5175 { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5176 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
5177 .access = PL1_R, .type = ARM_CP_CONST,
5178 .resetvalue = 0 },
5179 { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5180 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
5181 .access = PL1_R, .type = ARM_CP_CONST,
5182 .resetvalue = 0 },
5183 { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5184 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
5185 .access = PL1_R, .type = ARM_CP_CONST,
5186 .resetvalue = 0 },
5187 { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5188 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
5189 .access = PL1_R, .type = ARM_CP_CONST,
5190 .resetvalue = 0 },
5191 { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
5192 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
5193 .access = PL1_R, .type = ARM_CP_CONST,
5194 .resetvalue = 0 },
5195 { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
5196 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
5197 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
5198 .resetvalue = cpu->pmceid0 },
5199 { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
5200 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
5201 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
5202 .resetvalue = cpu->pmceid0 },
5203 { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
5204 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
5205 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
5206 .resetvalue = cpu->pmceid1 },
5207 { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
5208 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
5209 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
5210 .resetvalue = cpu->pmceid1 },
5211 REGINFO_SENTINEL
5212 };
5213 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
5214 if (!arm_feature(env, ARM_FEATURE_EL3) &&
5215 !arm_feature(env, ARM_FEATURE_EL2)) {
5216 ARMCPRegInfo rvbar = {
5217 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
5218 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
5219 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
5220 };
5221 define_one_arm_cp_reg(cpu, &rvbar);
5222 }
5223 define_arm_cp_regs(cpu, v8_idregs);
5224 define_arm_cp_regs(cpu, v8_cp_reginfo);
5225 }
5226 if (arm_feature(env, ARM_FEATURE_EL2)) {
5227 uint64_t vmpidr_def = mpidr_read_val(env);
5228 ARMCPRegInfo vpidr_regs[] = {
5229 { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
5230 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
5231 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5232 .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
5233 .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
5234 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
5235 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
5236 .access = PL2_RW, .resetvalue = cpu->midr,
5237 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
5238 { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
5239 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
5240 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5241 .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
5242 .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
5243 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
5244 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
5245 .access = PL2_RW,
5246 .resetvalue = vmpidr_def,
5247 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
5248 REGINFO_SENTINEL
5249 };
5250 define_arm_cp_regs(cpu, vpidr_regs);
5251 define_arm_cp_regs(cpu, el2_cp_reginfo);
5252 if (arm_feature(env, ARM_FEATURE_V8)) {
5253 define_arm_cp_regs(cpu, el2_v8_cp_reginfo);
5254 }
5255 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
5256 if (!arm_feature(env, ARM_FEATURE_EL3)) {
5257 ARMCPRegInfo rvbar = {
5258 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
5259 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
5260 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
5261 };
5262 define_one_arm_cp_reg(cpu, &rvbar);
5263 }
5264 } else {
5265 /* If EL2 is missing but higher ELs are enabled, we need to
5266 * register the no_el2 reginfos.
5267 */
5268 if (arm_feature(env, ARM_FEATURE_EL3)) {
5269 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
5270 * of MIDR_EL1 and MPIDR_EL1.
5271 */
5272 ARMCPRegInfo vpidr_regs[] = {
5273 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
5274 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
5275 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
5276 .type = ARM_CP_CONST, .resetvalue = cpu->midr,
5277 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
5278 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
5279 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
5280 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
5281 .type = ARM_CP_NO_RAW,
5282 .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
5283 REGINFO_SENTINEL
5284 };
5285 define_arm_cp_regs(cpu, vpidr_regs);
5286 define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
5287 if (arm_feature(env, ARM_FEATURE_V8)) {
5288 define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
5289 }
5290 }
5291 }
5292 if (arm_feature(env, ARM_FEATURE_EL3)) {
5293 define_arm_cp_regs(cpu, el3_cp_reginfo);
5294 ARMCPRegInfo el3_regs[] = {
5295 { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
5296 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
5297 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
5298 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
5299 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
5300 .access = PL3_RW,
5301 .raw_writefn = raw_write, .writefn = sctlr_write,
5302 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
5303 .resetvalue = cpu->reset_sctlr },
5304 REGINFO_SENTINEL
5305 };
5306
5307 define_arm_cp_regs(cpu, el3_regs);
5308 }
5309 /* The behaviour of NSACR is sufficiently various that we don't
5310 * try to describe it in a single reginfo:
5311 * if EL3 is 64 bit, then trap to EL3 from S EL1,
5312 * reads as constant 0xc00 from NS EL1 and NS EL2
5313 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
5314 * if v7 without EL3, register doesn't exist
5315 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
5316 */
5317 if (arm_feature(env, ARM_FEATURE_EL3)) {
5318 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
5319 ARMCPRegInfo nsacr = {
5320 .name = "NSACR", .type = ARM_CP_CONST,
5321 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
5322 .access = PL1_RW, .accessfn = nsacr_access,
5323 .resetvalue = 0xc00
5324 };
5325 define_one_arm_cp_reg(cpu, &nsacr);
5326 } else {
5327 ARMCPRegInfo nsacr = {
5328 .name = "NSACR",
5329 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
5330 .access = PL3_RW | PL1_R,
5331 .resetvalue = 0,
5332 .fieldoffset = offsetof(CPUARMState, cp15.nsacr)
5333 };
5334 define_one_arm_cp_reg(cpu, &nsacr);
5335 }
5336 } else {
5337 if (arm_feature(env, ARM_FEATURE_V8)) {
5338 ARMCPRegInfo nsacr = {
5339 .name = "NSACR", .type = ARM_CP_CONST,
5340 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
5341 .access = PL1_R,
5342 .resetvalue = 0xc00
5343 };
5344 define_one_arm_cp_reg(cpu, &nsacr);
5345 }
5346 }
5347
5348 if (arm_feature(env, ARM_FEATURE_PMSA)) {
5349 if (arm_feature(env, ARM_FEATURE_V6)) {
5350 /* PMSAv6 not implemented */
5351 assert(arm_feature(env, ARM_FEATURE_V7));
5352 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
5353 define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
5354 } else {
5355 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
5356 }
5357 } else {
5358 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
5359 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
5360 }
5361 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5362 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
5363 }
5364 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
5365 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
5366 }
5367 if (arm_feature(env, ARM_FEATURE_VAPA)) {
5368 define_arm_cp_regs(cpu, vapa_cp_reginfo);
5369 }
5370 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
5371 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
5372 }
5373 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
5374 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
5375 }
5376 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
5377 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
5378 }
5379 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
5380 define_arm_cp_regs(cpu, omap_cp_reginfo);
5381 }
5382 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
5383 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
5384 }
5385 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5386 define_arm_cp_regs(cpu, xscale_cp_reginfo);
5387 }
5388 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
5389 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
5390 }
5391 if (arm_feature(env, ARM_FEATURE_LPAE)) {
5392 define_arm_cp_regs(cpu, lpae_cp_reginfo);
5393 }
5394 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
5395 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
5396 * be read-only (ie write causes UNDEF exception).
5397 */
5398 {
5399 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
5400 /* Pre-v8 MIDR space.
5401 * Note that the MIDR isn't a simple constant register because
5402 * of the TI925 behaviour where writes to another register can
5403 * cause the MIDR value to change.
5404 *
5405 * Unimplemented registers in the c15 0 0 0 space default to
5406 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
5407 * and friends override accordingly.
5408 */
5409 { .name = "MIDR",
5410 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
5411 .access = PL1_R, .resetvalue = cpu->midr,
5412 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
5413 .readfn = midr_read,
5414 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
5415 .type = ARM_CP_OVERRIDE },
5416 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
5417 { .name = "DUMMY",
5418 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
5419 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
5420 { .name = "DUMMY",
5421 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
5422 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
5423 { .name = "DUMMY",
5424 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
5425 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
5426 { .name = "DUMMY",
5427 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
5428 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
5429 { .name = "DUMMY",
5430 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
5431 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
5432 REGINFO_SENTINEL
5433 };
5434 ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
5435 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
5436 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
5437 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
5438 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
5439 .readfn = midr_read },
5440 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
5441 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
5442 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
5443 .access = PL1_R, .resetvalue = cpu->midr },
5444 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
5445 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
5446 .access = PL1_R, .resetvalue = cpu->midr },
5447 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
5448 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
5449 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
5450 REGINFO_SENTINEL
5451 };
5452 ARMCPRegInfo id_cp_reginfo[] = {
5453 /* These are common to v8 and pre-v8 */
5454 { .name = "CTR",
5455 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
5456 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
5457 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
5458 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
5459 .access = PL0_R, .accessfn = ctr_el0_access,
5460 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
5461 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
5462 { .name = "TCMTR",
5463 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
5464 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
5465 REGINFO_SENTINEL
5466 };
5467 /* TLBTR is specific to VMSA */
5468 ARMCPRegInfo id_tlbtr_reginfo = {
5469 .name = "TLBTR",
5470 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
5471 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
5472 };
5473 /* MPUIR is specific to PMSA V6+ */
5474 ARMCPRegInfo id_mpuir_reginfo = {
5475 .name = "MPUIR",
5476 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
5477 .access = PL1_R, .type = ARM_CP_CONST,
5478 .resetvalue = cpu->pmsav7_dregion << 8
5479 };
5480 ARMCPRegInfo crn0_wi_reginfo = {
5481 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
5482 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
5483 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
5484 };
5485 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
5486 arm_feature(env, ARM_FEATURE_STRONGARM)) {
5487 ARMCPRegInfo *r;
5488 /* Register the blanket "writes ignored" value first to cover the
5489 * whole space. Then update the specific ID registers to allow write
5490 * access, so that they ignore writes rather than causing them to
5491 * UNDEF.
5492 */
5493 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
5494 for (r = id_pre_v8_midr_cp_reginfo;
5495 r->type != ARM_CP_SENTINEL; r++) {
5496 r->access = PL1_RW;
5497 }
5498 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
5499 r->access = PL1_RW;
5500 }
5501 id_mpuir_reginfo.access = PL1_RW;
5502 id_tlbtr_reginfo.access = PL1_RW;
5503 }
5504 if (arm_feature(env, ARM_FEATURE_V8)) {
5505 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
5506 } else {
5507 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
5508 }
5509 define_arm_cp_regs(cpu, id_cp_reginfo);
5510 if (!arm_feature(env, ARM_FEATURE_PMSA)) {
5511 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
5512 } else if (arm_feature(env, ARM_FEATURE_V7)) {
5513 define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
5514 }
5515 }
5516
5517 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
5518 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
5519 }
5520
5521 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
5522 ARMCPRegInfo auxcr_reginfo[] = {
5523 { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
5524 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
5525 .access = PL1_RW, .type = ARM_CP_CONST,
5526 .resetvalue = cpu->reset_auxcr },
5527 { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
5528 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
5529 .access = PL2_RW, .type = ARM_CP_CONST,
5530 .resetvalue = 0 },
5531 { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
5532 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
5533 .access = PL3_RW, .type = ARM_CP_CONST,
5534 .resetvalue = 0 },
5535 REGINFO_SENTINEL
5536 };
5537 define_arm_cp_regs(cpu, auxcr_reginfo);
5538 if (arm_feature(env, ARM_FEATURE_V8)) {
5539 /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */
5540 ARMCPRegInfo hactlr2_reginfo = {
5541 .name = "HACTLR2", .state = ARM_CP_STATE_AA32,
5542 .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
5543 .access = PL2_RW, .type = ARM_CP_CONST,
5544 .resetvalue = 0
5545 };
5546 define_one_arm_cp_reg(cpu, &hactlr2_reginfo);
5547 }
5548 }
5549
5550 if (arm_feature(env, ARM_FEATURE_CBAR)) {
5551 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
5552 /* 32 bit view is [31:18] 0...0 [43:32]. */
5553 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
5554 | extract64(cpu->reset_cbar, 32, 12);
5555 ARMCPRegInfo cbar_reginfo[] = {
5556 { .name = "CBAR",
5557 .type = ARM_CP_CONST,
5558 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
5559 .access = PL1_R, .resetvalue = cpu->reset_cbar },
5560 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
5561 .type = ARM_CP_CONST,
5562 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
5563 .access = PL1_R, .resetvalue = cbar32 },
5564 REGINFO_SENTINEL
5565 };
5566 /* We don't implement a r/w 64 bit CBAR currently */
5567 assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
5568 define_arm_cp_regs(cpu, cbar_reginfo);
5569 } else {
5570 ARMCPRegInfo cbar = {
5571 .name = "CBAR",
5572 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
5573 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
5574 .fieldoffset = offsetof(CPUARMState,
5575 cp15.c15_config_base_address)
5576 };
5577 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
5578 cbar.access = PL1_R;
5579 cbar.fieldoffset = 0;
5580 cbar.type = ARM_CP_CONST;
5581 }
5582 define_one_arm_cp_reg(cpu, &cbar);
5583 }
5584 }
5585
5586 if (arm_feature(env, ARM_FEATURE_VBAR)) {
5587 ARMCPRegInfo vbar_cp_reginfo[] = {
5588 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
5589 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
5590 .access = PL1_RW, .writefn = vbar_write,
5591 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
5592 offsetof(CPUARMState, cp15.vbar_ns) },
5593 .resetvalue = 0 },
5594 REGINFO_SENTINEL
5595 };
5596 define_arm_cp_regs(cpu, vbar_cp_reginfo);
5597 }
5598
5599 /* Generic registers whose values depend on the implementation */
5600 {
5601 ARMCPRegInfo sctlr = {
5602 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
5603 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
5604 .access = PL1_RW,
5605 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
5606 offsetof(CPUARMState, cp15.sctlr_ns) },
5607 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
5608 .raw_writefn = raw_write,
5609 };
5610 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5611 /* Normally we would always end the TB on an SCTLR write, but Linux
5612 * arch/arm/mach-pxa/sleep.S expects two instructions following
5613 * an MMU enable to execute from cache. Imitate this behaviour.
5614 */
5615 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
5616 }
5617 define_one_arm_cp_reg(cpu, &sctlr);
5618 }
5619
5620 if (arm_feature(env, ARM_FEATURE_SVE)) {
5621 define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
5622 if (arm_feature(env, ARM_FEATURE_EL2)) {
5623 define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
5624 } else {
5625 define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
5626 }
5627 if (arm_feature(env, ARM_FEATURE_EL3)) {
5628 define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
5629 }
5630 }
5631 }
5632
5633 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
5634 {
5635 CPUState *cs = CPU(cpu);
5636 CPUARMState *env = &cpu->env;
5637
5638 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
5639 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
5640 aarch64_fpu_gdb_set_reg,
5641 34, "aarch64-fpu.xml", 0);
5642 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
5643 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
5644 51, "arm-neon.xml", 0);
5645 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
5646 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
5647 35, "arm-vfp3.xml", 0);
5648 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
5649 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
5650 19, "arm-vfp.xml", 0);
5651 }
5652 gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
5653 arm_gen_dynamic_xml(cs),
5654 "system-registers.xml", 0);
5655 }
5656
5657 /* Sort alphabetically by type name, except for "any". */
5658 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5659 {
5660 ObjectClass *class_a = (ObjectClass *)a;
5661 ObjectClass *class_b = (ObjectClass *)b;
5662 const char *name_a, *name_b;
5663
5664 name_a = object_class_get_name(class_a);
5665 name_b = object_class_get_name(class_b);
5666 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
5667 return 1;
5668 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
5669 return -1;
5670 } else {
5671 return strcmp(name_a, name_b);
5672 }
5673 }
5674
5675 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
5676 {
5677 ObjectClass *oc = data;
5678 CPUListState *s = user_data;
5679 const char *typename;
5680 char *name;
5681
5682 typename = object_class_get_name(oc);
5683 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
5684 (*s->cpu_fprintf)(s->file, " %s\n",
5685 name);
5686 g_free(name);
5687 }
5688
5689 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
5690 {
5691 CPUListState s = {
5692 .file = f,
5693 .cpu_fprintf = cpu_fprintf,
5694 };
5695 GSList *list;
5696
5697 list = object_class_get_list(TYPE_ARM_CPU, false);
5698 list = g_slist_sort(list, arm_cpu_list_compare);
5699 (*cpu_fprintf)(f, "Available CPUs:\n");
5700 g_slist_foreach(list, arm_cpu_list_entry, &s);
5701 g_slist_free(list);
5702 }
5703
5704 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
5705 {
5706 ObjectClass *oc = data;
5707 CpuDefinitionInfoList **cpu_list = user_data;
5708 CpuDefinitionInfoList *entry;
5709 CpuDefinitionInfo *info;
5710 const char *typename;
5711
5712 typename = object_class_get_name(oc);
5713 info = g_malloc0(sizeof(*info));
5714 info->name = g_strndup(typename,
5715 strlen(typename) - strlen("-" TYPE_ARM_CPU));
5716 info->q_typename = g_strdup(typename);
5717
5718 entry = g_malloc0(sizeof(*entry));
5719 entry->value = info;
5720 entry->next = *cpu_list;
5721 *cpu_list = entry;
5722 }
5723
5724 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
5725 {
5726 CpuDefinitionInfoList *cpu_list = NULL;
5727 GSList *list;
5728
5729 list = object_class_get_list(TYPE_ARM_CPU, false);
5730 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
5731 g_slist_free(list);
5732
5733 return cpu_list;
5734 }
5735
5736 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
5737 void *opaque, int state, int secstate,
5738 int crm, int opc1, int opc2,
5739 const char *name)
5740 {
5741 /* Private utility function for define_one_arm_cp_reg_with_opaque():
5742 * add a single reginfo struct to the hash table.
5743 */
5744 uint32_t *key = g_new(uint32_t, 1);
5745 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
5746 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
5747 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
5748
5749 r2->name = g_strdup(name);
5750 /* Reset the secure state to the specific incoming state. This is
5751 * necessary as the register may have been defined with both states.
5752 */
5753 r2->secure = secstate;
5754
5755 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5756 /* Register is banked (using both entries in array).
5757 * Overwriting fieldoffset as the array is only used to define
5758 * banked registers but later only fieldoffset is used.
5759 */
5760 r2->fieldoffset = r->bank_fieldoffsets[ns];
5761 }
5762
5763 if (state == ARM_CP_STATE_AA32) {
5764 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5765 /* If the register is banked then we don't need to migrate or
5766 * reset the 32-bit instance in certain cases:
5767 *
5768 * 1) If the register has both 32-bit and 64-bit instances then we
5769 * can count on the 64-bit instance taking care of the
5770 * non-secure bank.
5771 * 2) If ARMv8 is enabled then we can count on a 64-bit version
5772 * taking care of the secure bank. This requires that separate
5773 * 32 and 64-bit definitions are provided.
5774 */
5775 if ((r->state == ARM_CP_STATE_BOTH && ns) ||
5776 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
5777 r2->type |= ARM_CP_ALIAS;
5778 }
5779 } else if ((secstate != r->secure) && !ns) {
5780 /* The register is not banked so we only want to allow migration of
5781 * the non-secure instance.
5782 */
5783 r2->type |= ARM_CP_ALIAS;
5784 }
5785
5786 if (r->state == ARM_CP_STATE_BOTH) {
5787 /* We assume it is a cp15 register if the .cp field is left unset.
5788 */
5789 if (r2->cp == 0) {
5790 r2->cp = 15;
5791 }
5792
5793 #ifdef HOST_WORDS_BIGENDIAN
5794 if (r2->fieldoffset) {
5795 r2->fieldoffset += sizeof(uint32_t);
5796 }
5797 #endif
5798 }
5799 }
5800 if (state == ARM_CP_STATE_AA64) {
5801 /* To allow abbreviation of ARMCPRegInfo
5802 * definitions, we treat cp == 0 as equivalent to
5803 * the value for "standard guest-visible sysreg".
5804 * STATE_BOTH definitions are also always "standard
5805 * sysreg" in their AArch64 view (the .cp value may
5806 * be non-zero for the benefit of the AArch32 view).
5807 */
5808 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
5809 r2->cp = CP_REG_ARM64_SYSREG_CP;
5810 }
5811 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
5812 r2->opc0, opc1, opc2);
5813 } else {
5814 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
5815 }
5816 if (opaque) {
5817 r2->opaque = opaque;
5818 }
5819 /* reginfo passed to helpers is correct for the actual access,
5820 * and is never ARM_CP_STATE_BOTH:
5821 */
5822 r2->state = state;
5823 /* Make sure reginfo passed to helpers for wildcarded regs
5824 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5825 */
5826 r2->crm = crm;
5827 r2->opc1 = opc1;
5828 r2->opc2 = opc2;
5829 /* By convention, for wildcarded registers only the first
5830 * entry is used for migration; the others are marked as
5831 * ALIAS so we don't try to transfer the register
5832 * multiple times. Special registers (ie NOP/WFI) are
5833 * never migratable and not even raw-accessible.
5834 */
5835 if ((r->type & ARM_CP_SPECIAL)) {
5836 r2->type |= ARM_CP_NO_RAW;
5837 }
5838 if (((r->crm == CP_ANY) && crm != 0) ||
5839 ((r->opc1 == CP_ANY) && opc1 != 0) ||
5840 ((r->opc2 == CP_ANY) && opc2 != 0)) {
5841 r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
5842 }
5843
5844 /* Check that raw accesses are either forbidden or handled. Note that
5845 * we can't assert this earlier because the setup of fieldoffset for
5846 * banked registers has to be done first.
5847 */
5848 if (!(r2->type & ARM_CP_NO_RAW)) {
5849 assert(!raw_accessors_invalid(r2));
5850 }
5851
5852 /* Overriding of an existing definition must be explicitly
5853 * requested.
5854 */
5855 if (!(r->type & ARM_CP_OVERRIDE)) {
5856 ARMCPRegInfo *oldreg;
5857 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
5858 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
5859 fprintf(stderr, "Register redefined: cp=%d %d bit "
5860 "crn=%d crm=%d opc1=%d opc2=%d, "
5861 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
5862 r2->crn, r2->crm, r2->opc1, r2->opc2,
5863 oldreg->name, r2->name);
5864 g_assert_not_reached();
5865 }
5866 }
5867 g_hash_table_insert(cpu->cp_regs, key, r2);
5868 }
5869
5870
5871 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
5872 const ARMCPRegInfo *r, void *opaque)
5873 {
5874 /* Define implementations of coprocessor registers.
5875 * We store these in a hashtable because typically
5876 * there are less than 150 registers in a space which
5877 * is 16*16*16*8*8 = 262144 in size.
5878 * Wildcarding is supported for the crm, opc1 and opc2 fields.
5879 * If a register is defined twice then the second definition is
5880 * used, so this can be used to define some generic registers and
5881 * then override them with implementation specific variations.
5882 * At least one of the original and the second definition should
5883 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5884 * against accidental use.
5885 *
5886 * The state field defines whether the register is to be
5887 * visible in the AArch32 or AArch64 execution state. If the
5888 * state is set to ARM_CP_STATE_BOTH then we synthesise a
5889 * reginfo structure for the AArch32 view, which sees the lower
5890 * 32 bits of the 64 bit register.
5891 *
5892 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5893 * be wildcarded. AArch64 registers are always considered to be 64
5894 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5895 * the register, if any.
5896 */
5897 int crm, opc1, opc2, state;
5898 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
5899 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
5900 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
5901 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
5902 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
5903 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
5904 /* 64 bit registers have only CRm and Opc1 fields */
5905 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
5906 /* op0 only exists in the AArch64 encodings */
5907 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
5908 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5909 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
5910 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5911 * encodes a minimum access level for the register. We roll this
5912 * runtime check into our general permission check code, so check
5913 * here that the reginfo's specified permissions are strict enough
5914 * to encompass the generic architectural permission check.
5915 */
5916 if (r->state != ARM_CP_STATE_AA32) {
5917 int mask = 0;
5918 switch (r->opc1) {
5919 case 0: case 1: case 2:
5920 /* min_EL EL1 */
5921 mask = PL1_RW;
5922 break;
5923 case 3:
5924 /* min_EL EL0 */
5925 mask = PL0_RW;
5926 break;
5927 case 4:
5928 /* min_EL EL2 */
5929 mask = PL2_RW;
5930 break;
5931 case 5:
5932 /* unallocated encoding, so not possible */
5933 assert(false);
5934 break;
5935 case 6:
5936 /* min_EL EL3 */
5937 mask = PL3_RW;
5938 break;
5939 case 7:
5940 /* min_EL EL1, secure mode only (we don't check the latter) */
5941 mask = PL1_RW;
5942 break;
5943 default:
5944 /* broken reginfo with out-of-range opc1 */
5945 assert(false);
5946 break;
5947 }
5948 /* assert our permissions are not too lax (stricter is fine) */
5949 assert((r->access & ~mask) == 0);
5950 }
5951
5952 /* Check that the register definition has enough info to handle
5953 * reads and writes if they are permitted.
5954 */
5955 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
5956 if (r->access & PL3_R) {
5957 assert((r->fieldoffset ||
5958 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5959 r->readfn);
5960 }
5961 if (r->access & PL3_W) {
5962 assert((r->fieldoffset ||
5963 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5964 r->writefn);
5965 }
5966 }
5967 /* Bad type field probably means missing sentinel at end of reg list */
5968 assert(cptype_valid(r->type));
5969 for (crm = crmmin; crm <= crmmax; crm++) {
5970 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
5971 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
5972 for (state = ARM_CP_STATE_AA32;
5973 state <= ARM_CP_STATE_AA64; state++) {
5974 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
5975 continue;
5976 }
5977 if (state == ARM_CP_STATE_AA32) {
5978 /* Under AArch32 CP registers can be common
5979 * (same for secure and non-secure world) or banked.
5980 */
5981 char *name;
5982
5983 switch (r->secure) {
5984 case ARM_CP_SECSTATE_S:
5985 case ARM_CP_SECSTATE_NS:
5986 add_cpreg_to_hashtable(cpu, r, opaque, state,
5987 r->secure, crm, opc1, opc2,
5988 r->name);
5989 break;
5990 default:
5991 name = g_strdup_printf("%s_S", r->name);
5992 add_cpreg_to_hashtable(cpu, r, opaque, state,
5993 ARM_CP_SECSTATE_S,
5994 crm, opc1, opc2, name);
5995 g_free(name);
5996 add_cpreg_to_hashtable(cpu, r, opaque, state,
5997 ARM_CP_SECSTATE_NS,
5998 crm, opc1, opc2, r->name);
5999 break;
6000 }
6001 } else {
6002 /* AArch64 registers get mapped to non-secure instance
6003 * of AArch32 */
6004 add_cpreg_to_hashtable(cpu, r, opaque, state,
6005 ARM_CP_SECSTATE_NS,
6006 crm, opc1, opc2, r->name);
6007 }
6008 }
6009 }
6010 }
6011 }
6012 }
6013
6014 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
6015 const ARMCPRegInfo *regs, void *opaque)
6016 {
6017 /* Define a whole list of registers */
6018 const ARMCPRegInfo *r;
6019 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
6020 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
6021 }
6022 }
6023
6024 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
6025 {
6026 return g_hash_table_lookup(cpregs, &encoded_cp);
6027 }
6028
6029 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
6030 uint64_t value)
6031 {
6032 /* Helper coprocessor write function for write-ignore registers */
6033 }
6034
6035 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
6036 {
6037 /* Helper coprocessor write function for read-as-zero registers */
6038 return 0;
6039 }
6040
6041 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
6042 {
6043 /* Helper coprocessor reset function for do-nothing-on-reset registers */
6044 }
6045
6046 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
6047 {
6048 /* Return true if it is not valid for us to switch to
6049 * this CPU mode (ie all the UNPREDICTABLE cases in
6050 * the ARM ARM CPSRWriteByInstr pseudocode).
6051 */
6052
6053 /* Changes to or from Hyp via MSR and CPS are illegal. */
6054 if (write_type == CPSRWriteByInstr &&
6055 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
6056 mode == ARM_CPU_MODE_HYP)) {
6057 return 1;
6058 }
6059
6060 switch (mode) {
6061 case ARM_CPU_MODE_USR:
6062 return 0;
6063 case ARM_CPU_MODE_SYS:
6064 case ARM_CPU_MODE_SVC:
6065 case ARM_CPU_MODE_ABT:
6066 case ARM_CPU_MODE_UND:
6067 case ARM_CPU_MODE_IRQ:
6068 case ARM_CPU_MODE_FIQ:
6069 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
6070 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
6071 */
6072 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
6073 * and CPS are treated as illegal mode changes.
6074 */
6075 if (write_type == CPSRWriteByInstr &&
6076 (env->cp15.hcr_el2 & HCR_TGE) &&
6077 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
6078 !arm_is_secure_below_el3(env)) {
6079 return 1;
6080 }
6081 return 0;
6082 case ARM_CPU_MODE_HYP:
6083 return !arm_feature(env, ARM_FEATURE_EL2)
6084 || arm_current_el(env) < 2 || arm_is_secure(env);
6085 case ARM_CPU_MODE_MON:
6086 return arm_current_el(env) < 3;
6087 default:
6088 return 1;
6089 }
6090 }
6091
6092 uint32_t cpsr_read(CPUARMState *env)
6093 {
6094 int ZF;
6095 ZF = (env->ZF == 0);
6096 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
6097 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
6098 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
6099 | ((env->condexec_bits & 0xfc) << 8)
6100 | (env->GE << 16) | (env->daif & CPSR_AIF);
6101 }
6102
6103 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
6104 CPSRWriteType write_type)
6105 {
6106 uint32_t changed_daif;
6107
6108 if (mask & CPSR_NZCV) {
6109 env->ZF = (~val) & CPSR_Z;
6110 env->NF = val;
6111 env->CF = (val >> 29) & 1;
6112 env->VF = (val << 3) & 0x80000000;
6113 }
6114 if (mask & CPSR_Q)
6115 env->QF = ((val & CPSR_Q) != 0);
6116 if (mask & CPSR_T)
6117 env->thumb = ((val & CPSR_T) != 0);
6118 if (mask & CPSR_IT_0_1) {
6119 env->condexec_bits &= ~3;
6120 env->condexec_bits |= (val >> 25) & 3;
6121 }
6122 if (mask & CPSR_IT_2_7) {
6123 env->condexec_bits &= 3;
6124 env->condexec_bits |= (val >> 8) & 0xfc;
6125 }
6126 if (mask & CPSR_GE) {
6127 env->GE = (val >> 16) & 0xf;
6128 }
6129
6130 /* In a V7 implementation that includes the security extensions but does
6131 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
6132 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
6133 * bits respectively.
6134 *
6135 * In a V8 implementation, it is permitted for privileged software to
6136 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
6137 */
6138 if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) &&
6139 arm_feature(env, ARM_FEATURE_EL3) &&
6140 !arm_feature(env, ARM_FEATURE_EL2) &&
6141 !arm_is_secure(env)) {
6142
6143 changed_daif = (env->daif ^ val) & mask;
6144
6145 if (changed_daif & CPSR_A) {
6146 /* Check to see if we are allowed to change the masking of async
6147 * abort exceptions from a non-secure state.
6148 */
6149 if (!(env->cp15.scr_el3 & SCR_AW)) {
6150 qemu_log_mask(LOG_GUEST_ERROR,
6151 "Ignoring attempt to switch CPSR_A flag from "
6152 "non-secure world with SCR.AW bit clear\n");
6153 mask &= ~CPSR_A;
6154 }
6155 }
6156
6157 if (changed_daif & CPSR_F) {
6158 /* Check to see if we are allowed to change the masking of FIQ
6159 * exceptions from a non-secure state.
6160 */
6161 if (!(env->cp15.scr_el3 & SCR_FW)) {
6162 qemu_log_mask(LOG_GUEST_ERROR,
6163 "Ignoring attempt to switch CPSR_F flag from "
6164 "non-secure world with SCR.FW bit clear\n");
6165 mask &= ~CPSR_F;
6166 }
6167
6168 /* Check whether non-maskable FIQ (NMFI) support is enabled.
6169 * If this bit is set software is not allowed to mask
6170 * FIQs, but is allowed to set CPSR_F to 0.
6171 */
6172 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
6173 (val & CPSR_F)) {
6174 qemu_log_mask(LOG_GUEST_ERROR,
6175 "Ignoring attempt to enable CPSR_F flag "
6176 "(non-maskable FIQ [NMFI] support enabled)\n");
6177 mask &= ~CPSR_F;
6178 }
6179 }
6180 }
6181
6182 env->daif &= ~(CPSR_AIF & mask);
6183 env->daif |= val & CPSR_AIF & mask;
6184
6185 if (write_type != CPSRWriteRaw &&
6186 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
6187 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
6188 /* Note that we can only get here in USR mode if this is a
6189 * gdb stub write; for this case we follow the architectural
6190 * behaviour for guest writes in USR mode of ignoring an attempt
6191 * to switch mode. (Those are caught by translate.c for writes
6192 * triggered by guest instructions.)
6193 */
6194 mask &= ~CPSR_M;
6195 } else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
6196 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
6197 * v7, and has defined behaviour in v8:
6198 * + leave CPSR.M untouched
6199 * + allow changes to the other CPSR fields
6200 * + set PSTATE.IL
6201 * For user changes via the GDB stub, we don't set PSTATE.IL,
6202 * as this would be unnecessarily harsh for a user error.
6203 */
6204 mask &= ~CPSR_M;
6205 if (write_type != CPSRWriteByGDBStub &&
6206 arm_feature(env, ARM_FEATURE_V8)) {
6207 mask |= CPSR_IL;
6208 val |= CPSR_IL;
6209 }
6210 } else {
6211 switch_mode(env, val & CPSR_M);
6212 }
6213 }
6214 mask &= ~CACHED_CPSR_BITS;
6215 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
6216 }
6217
6218 /* Sign/zero extend */
6219 uint32_t HELPER(sxtb16)(uint32_t x)
6220 {
6221 uint32_t res;
6222 res = (uint16_t)(int8_t)x;
6223 res |= (uint32_t)(int8_t)(x >> 16) << 16;
6224 return res;
6225 }
6226
6227 uint32_t HELPER(uxtb16)(uint32_t x)
6228 {
6229 uint32_t res;
6230 res = (uint16_t)(uint8_t)x;
6231 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
6232 return res;
6233 }
6234
6235 int32_t HELPER(sdiv)(int32_t num, int32_t den)
6236 {
6237 if (den == 0)
6238 return 0;
6239 if (num == INT_MIN && den == -1)
6240 return INT_MIN;
6241 return num / den;
6242 }
6243
6244 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
6245 {
6246 if (den == 0)
6247 return 0;
6248 return num / den;
6249 }
6250
6251 uint32_t HELPER(rbit)(uint32_t x)
6252 {
6253 return revbit32(x);
6254 }
6255
6256 #if defined(CONFIG_USER_ONLY)
6257
6258 /* These should probably raise undefined insn exceptions. */
6259 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
6260 {
6261 ARMCPU *cpu = arm_env_get_cpu(env);
6262
6263 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
6264 }
6265
6266 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
6267 {
6268 ARMCPU *cpu = arm_env_get_cpu(env);
6269
6270 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
6271 return 0;
6272 }
6273
6274 void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
6275 {
6276 /* translate.c should never generate calls here in user-only mode */
6277 g_assert_not_reached();
6278 }
6279
6280 void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
6281 {
6282 /* translate.c should never generate calls here in user-only mode */
6283 g_assert_not_reached();
6284 }
6285
6286 uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
6287 {
6288 /* The TT instructions can be used by unprivileged code, but in
6289 * user-only emulation we don't have the MPU.
6290 * Luckily since we know we are NonSecure unprivileged (and that in
6291 * turn means that the A flag wasn't specified), all the bits in the
6292 * register must be zero:
6293 * IREGION: 0 because IRVALID is 0
6294 * IRVALID: 0 because NS
6295 * S: 0 because NS
6296 * NSRW: 0 because NS
6297 * NSR: 0 because NS
6298 * RW: 0 because unpriv and A flag not set
6299 * R: 0 because unpriv and A flag not set
6300 * SRVALID: 0 because NS
6301 * MRVALID: 0 because unpriv and A flag not set
6302 * SREGION: 0 becaus SRVALID is 0
6303 * MREGION: 0 because MRVALID is 0
6304 */
6305 return 0;
6306 }
6307
6308 void switch_mode(CPUARMState *env, int mode)
6309 {
6310 ARMCPU *cpu = arm_env_get_cpu(env);
6311
6312 if (mode != ARM_CPU_MODE_USR) {
6313 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
6314 }
6315 }
6316
6317 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
6318 uint32_t cur_el, bool secure)
6319 {
6320 return 1;
6321 }
6322
6323 void aarch64_sync_64_to_32(CPUARMState *env)
6324 {
6325 g_assert_not_reached();
6326 }
6327
6328 #else
6329
6330 void switch_mode(CPUARMState *env, int mode)
6331 {
6332 int old_mode;
6333 int i;
6334
6335 old_mode = env->uncached_cpsr & CPSR_M;
6336 if (mode == old_mode)
6337 return;
6338
6339 if (old_mode == ARM_CPU_MODE_FIQ) {
6340 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
6341 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
6342 } else if (mode == ARM_CPU_MODE_FIQ) {
6343 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
6344 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
6345 }
6346
6347 i = bank_number(old_mode);
6348 env->banked_r13[i] = env->regs[13];
6349 env->banked_r14[i] = env->regs[14];
6350 env->banked_spsr[i] = env->spsr;
6351
6352 i = bank_number(mode);
6353 env->regs[13] = env->banked_r13[i];
6354 env->regs[14] = env->banked_r14[i];
6355 env->spsr = env->banked_spsr[i];
6356 }
6357
6358 /* Physical Interrupt Target EL Lookup Table
6359 *
6360 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
6361 *
6362 * The below multi-dimensional table is used for looking up the target
6363 * exception level given numerous condition criteria. Specifically, the
6364 * target EL is based on SCR and HCR routing controls as well as the
6365 * currently executing EL and secure state.
6366 *
6367 * Dimensions:
6368 * target_el_table[2][2][2][2][2][4]
6369 * | | | | | +--- Current EL
6370 * | | | | +------ Non-secure(0)/Secure(1)
6371 * | | | +--------- HCR mask override
6372 * | | +------------ SCR exec state control
6373 * | +--------------- SCR mask override
6374 * +------------------ 32-bit(0)/64-bit(1) EL3
6375 *
6376 * The table values are as such:
6377 * 0-3 = EL0-EL3
6378 * -1 = Cannot occur
6379 *
6380 * The ARM ARM target EL table includes entries indicating that an "exception
6381 * is not taken". The two cases where this is applicable are:
6382 * 1) An exception is taken from EL3 but the SCR does not have the exception
6383 * routed to EL3.
6384 * 2) An exception is taken from EL2 but the HCR does not have the exception
6385 * routed to EL2.
6386 * In these two cases, the below table contain a target of EL1. This value is
6387 * returned as it is expected that the consumer of the table data will check
6388 * for "target EL >= current EL" to ensure the exception is not taken.
6389 *
6390 * SCR HCR
6391 * 64 EA AMO From
6392 * BIT IRQ IMO Non-secure Secure
6393 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
6394 */
6395 static const int8_t target_el_table[2][2][2][2][2][4] = {
6396 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
6397 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
6398 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
6399 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
6400 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
6401 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
6402 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
6403 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
6404 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
6405 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
6406 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
6407 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
6408 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
6409 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
6410 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
6411 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
6412 };
6413
6414 /*
6415 * Determine the target EL for physical exceptions
6416 */
6417 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
6418 uint32_t cur_el, bool secure)
6419 {
6420 CPUARMState *env = cs->env_ptr;
6421 int rw;
6422 int scr;
6423 int hcr;
6424 int target_el;
6425 /* Is the highest EL AArch64? */
6426 int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
6427
6428 if (arm_feature(env, ARM_FEATURE_EL3)) {
6429 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
6430 } else {
6431 /* Either EL2 is the highest EL (and so the EL2 register width
6432 * is given by is64); or there is no EL2 or EL3, in which case
6433 * the value of 'rw' does not affect the table lookup anyway.
6434 */
6435 rw = is64;
6436 }
6437
6438 switch (excp_idx) {
6439 case EXCP_IRQ:
6440 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
6441 hcr = arm_hcr_el2_imo(env);
6442 break;
6443 case EXCP_FIQ:
6444 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
6445 hcr = arm_hcr_el2_fmo(env);
6446 break;
6447 default:
6448 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
6449 hcr = arm_hcr_el2_amo(env);
6450 break;
6451 };
6452
6453 /* If HCR.TGE is set then HCR is treated as being 1 */
6454 hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
6455
6456 /* Perform a table-lookup for the target EL given the current state */
6457 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
6458
6459 assert(target_el > 0);
6460
6461 return target_el;
6462 }
6463
6464 static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
6465 ARMMMUIdx mmu_idx, bool ignfault)
6466 {
6467 CPUState *cs = CPU(cpu);
6468 CPUARMState *env = &cpu->env;
6469 MemTxAttrs attrs = {};
6470 MemTxResult txres;
6471 target_ulong page_size;
6472 hwaddr physaddr;
6473 int prot;
6474 ARMMMUFaultInfo fi;
6475 bool secure = mmu_idx & ARM_MMU_IDX_M_S;
6476 int exc;
6477 bool exc_secure;
6478
6479 if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &physaddr,
6480 &attrs, &prot, &page_size, &fi, NULL)) {
6481 /* MPU/SAU lookup failed */
6482 if (fi.type == ARMFault_QEMU_SFault) {
6483 qemu_log_mask(CPU_LOG_INT,
6484 "...SecureFault with SFSR.AUVIOL during stacking\n");
6485 env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK;
6486 env->v7m.sfar = addr;
6487 exc = ARMV7M_EXCP_SECURE;
6488 exc_secure = false;
6489 } else {
6490 qemu_log_mask(CPU_LOG_INT, "...MemManageFault with CFSR.MSTKERR\n");
6491 env->v7m.cfsr[secure] |= R_V7M_CFSR_MSTKERR_MASK;
6492 exc = ARMV7M_EXCP_MEM;
6493 exc_secure = secure;
6494 }
6495 goto pend_fault;
6496 }
6497 address_space_stl_le(arm_addressspace(cs, attrs), physaddr, value,
6498 attrs, &txres);
6499 if (txres != MEMTX_OK) {
6500 /* BusFault trying to write the data */
6501 qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n");
6502 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_STKERR_MASK;
6503 exc = ARMV7M_EXCP_BUS;
6504 exc_secure = false;
6505 goto pend_fault;
6506 }
6507 return true;
6508
6509 pend_fault:
6510 /* By pending the exception at this point we are making
6511 * the IMPDEF choice "overridden exceptions pended" (see the
6512 * MergeExcInfo() pseudocode). The other choice would be to not
6513 * pend them now and then make a choice about which to throw away
6514 * later if we have two derived exceptions.
6515 * The only case when we must not pend the exception but instead
6516 * throw it away is if we are doing the push of the callee registers
6517 * and we've already generated a derived exception. Even in this
6518 * case we will still update the fault status registers.
6519 */
6520 if (!ignfault) {
6521 armv7m_nvic_set_pending_derived(env->nvic, exc, exc_secure);
6522 }
6523 return false;
6524 }
6525
6526 static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
6527 ARMMMUIdx mmu_idx)
6528 {
6529 CPUState *cs = CPU(cpu);
6530 CPUARMState *env = &cpu->env;
6531 MemTxAttrs attrs = {};
6532 MemTxResult txres;
6533 target_ulong page_size;
6534 hwaddr physaddr;
6535 int prot;
6536 ARMMMUFaultInfo fi;
6537 bool secure = mmu_idx & ARM_MMU_IDX_M_S;
6538 int exc;
6539 bool exc_secure;
6540 uint32_t value;
6541
6542 if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
6543 &attrs, &prot, &page_size, &fi, NULL)) {
6544 /* MPU/SAU lookup failed */
6545 if (fi.type == ARMFault_QEMU_SFault) {
6546 qemu_log_mask(CPU_LOG_INT,
6547 "...SecureFault with SFSR.AUVIOL during unstack\n");
6548 env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK;
6549 env->v7m.sfar = addr;
6550 exc = ARMV7M_EXCP_SECURE;
6551 exc_secure = false;
6552 } else {
6553 qemu_log_mask(CPU_LOG_INT,
6554 "...MemManageFault with CFSR.MUNSTKERR\n");
6555 env->v7m.cfsr[secure] |= R_V7M_CFSR_MUNSTKERR_MASK;
6556 exc = ARMV7M_EXCP_MEM;
6557 exc_secure = secure;
6558 }
6559 goto pend_fault;
6560 }
6561
6562 value = address_space_ldl(arm_addressspace(cs, attrs), physaddr,
6563 attrs, &txres);
6564 if (txres != MEMTX_OK) {
6565 /* BusFault trying to read the data */
6566 qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n");
6567 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_UNSTKERR_MASK;
6568 exc = ARMV7M_EXCP_BUS;
6569 exc_secure = false;
6570 goto pend_fault;
6571 }
6572
6573 *dest = value;
6574 return true;
6575
6576 pend_fault:
6577 /* By pending the exception at this point we are making
6578 * the IMPDEF choice "overridden exceptions pended" (see the
6579 * MergeExcInfo() pseudocode). The other choice would be to not
6580 * pend them now and then make a choice about which to throw away
6581 * later if we have two derived exceptions.
6582 */
6583 armv7m_nvic_set_pending(env->nvic, exc, exc_secure);
6584 return false;
6585 }
6586
6587 /* Write to v7M CONTROL.SPSEL bit for the specified security bank.
6588 * This may change the current stack pointer between Main and Process
6589 * stack pointers if it is done for the CONTROL register for the current
6590 * security state.
6591 */
6592 static void write_v7m_control_spsel_for_secstate(CPUARMState *env,
6593 bool new_spsel,
6594 bool secstate)
6595 {
6596 bool old_is_psp = v7m_using_psp(env);
6597
6598 env->v7m.control[secstate] =
6599 deposit32(env->v7m.control[secstate],
6600 R_V7M_CONTROL_SPSEL_SHIFT,
6601 R_V7M_CONTROL_SPSEL_LENGTH, new_spsel);
6602
6603 if (secstate == env->v7m.secure) {
6604 bool new_is_psp = v7m_using_psp(env);
6605 uint32_t tmp;
6606
6607 if (old_is_psp != new_is_psp) {
6608 tmp = env->v7m.other_sp;
6609 env->v7m.other_sp = env->regs[13];
6610 env->regs[13] = tmp;
6611 }
6612 }
6613 }
6614
6615 /* Write to v7M CONTROL.SPSEL bit. This may change the current
6616 * stack pointer between Main and Process stack pointers.
6617 */
6618 static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)
6619 {
6620 write_v7m_control_spsel_for_secstate(env, new_spsel, env->v7m.secure);
6621 }
6622
6623 void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
6624 {
6625 /* Write a new value to v7m.exception, thus transitioning into or out
6626 * of Handler mode; this may result in a change of active stack pointer.
6627 */
6628 bool new_is_psp, old_is_psp = v7m_using_psp(env);
6629 uint32_t tmp;
6630
6631 env->v7m.exception = new_exc;
6632
6633 new_is_psp = v7m_using_psp(env);
6634
6635 if (old_is_psp != new_is_psp) {
6636 tmp = env->v7m.other_sp;
6637 env->v7m.other_sp = env->regs[13];
6638 env->regs[13] = tmp;
6639 }
6640 }
6641
6642 /* Switch M profile security state between NS and S */
6643 static void switch_v7m_security_state(CPUARMState *env, bool new_secstate)
6644 {
6645 uint32_t new_ss_msp, new_ss_psp;
6646
6647 if (env->v7m.secure == new_secstate) {
6648 return;
6649 }
6650
6651 /* All the banked state is accessed by looking at env->v7m.secure
6652 * except for the stack pointer; rearrange the SP appropriately.
6653 */
6654 new_ss_msp = env->v7m.other_ss_msp;
6655 new_ss_psp = env->v7m.other_ss_psp;
6656
6657 if (v7m_using_psp(env)) {
6658 env->v7m.other_ss_psp = env->regs[13];
6659 env->v7m.other_ss_msp = env->v7m.other_sp;
6660 } else {
6661 env->v7m.other_ss_msp = env->regs[13];
6662 env->v7m.other_ss_psp = env->v7m.other_sp;
6663 }
6664
6665 env->v7m.secure = new_secstate;
6666
6667 if (v7m_using_psp(env)) {
6668 env->regs[13] = new_ss_psp;
6669 env->v7m.other_sp = new_ss_msp;
6670 } else {
6671 env->regs[13] = new_ss_msp;
6672 env->v7m.other_sp = new_ss_psp;
6673 }
6674 }
6675
6676 void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
6677 {
6678 /* Handle v7M BXNS:
6679 * - if the return value is a magic value, do exception return (like BX)
6680 * - otherwise bit 0 of the return value is the target security state
6681 */
6682 uint32_t min_magic;
6683
6684 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
6685 /* Covers FNC_RETURN and EXC_RETURN magic */
6686 min_magic = FNC_RETURN_MIN_MAGIC;
6687 } else {
6688 /* EXC_RETURN magic only */
6689 min_magic = EXC_RETURN_MIN_MAGIC;
6690 }
6691
6692 if (dest >= min_magic) {
6693 /* This is an exception return magic value; put it where
6694 * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
6695 * Note that if we ever add gen_ss_advance() singlestep support to
6696 * M profile this should count as an "instruction execution complete"
6697 * event (compare gen_bx_excret_final_code()).
6698 */
6699 env->regs[15] = dest & ~1;
6700 env->thumb = dest & 1;
6701 HELPER(exception_internal)(env, EXCP_EXCEPTION_EXIT);
6702 /* notreached */
6703 }
6704
6705 /* translate.c should have made BXNS UNDEF unless we're secure */
6706 assert(env->v7m.secure);
6707
6708 switch_v7m_security_state(env, dest & 1);
6709 env->thumb = 1;
6710 env->regs[15] = dest & ~1;
6711 }
6712
6713 void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
6714 {
6715 /* Handle v7M BLXNS:
6716 * - bit 0 of the destination address is the target security state
6717 */
6718
6719 /* At this point regs[15] is the address just after the BLXNS */
6720 uint32_t nextinst = env->regs[15] | 1;
6721 uint32_t sp = env->regs[13] - 8;
6722 uint32_t saved_psr;
6723
6724 /* translate.c will have made BLXNS UNDEF unless we're secure */
6725 assert(env->v7m.secure);
6726
6727 if (dest & 1) {
6728 /* target is Secure, so this is just a normal BLX,
6729 * except that the low bit doesn't indicate Thumb/not.
6730 */
6731 env->regs[14] = nextinst;
6732 env->thumb = 1;
6733 env->regs[15] = dest & ~1;
6734 return;
6735 }
6736
6737 /* Target is non-secure: first push a stack frame */
6738 if (!QEMU_IS_ALIGNED(sp, 8)) {
6739 qemu_log_mask(LOG_GUEST_ERROR,
6740 "BLXNS with misaligned SP is UNPREDICTABLE\n");
6741 }
6742
6743 if (sp < v7m_sp_limit(env)) {
6744 raise_exception(env, EXCP_STKOF, 0, 1);
6745 }
6746
6747 saved_psr = env->v7m.exception;
6748 if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) {
6749 saved_psr |= XPSR_SFPA;
6750 }
6751
6752 /* Note that these stores can throw exceptions on MPU faults */
6753 cpu_stl_data(env, sp, nextinst);
6754 cpu_stl_data(env, sp + 4, saved_psr);
6755
6756 env->regs[13] = sp;
6757 env->regs[14] = 0xfeffffff;
6758 if (arm_v7m_is_handler_mode(env)) {
6759 /* Write a dummy value to IPSR, to avoid leaking the current secure
6760 * exception number to non-secure code. This is guaranteed not
6761 * to cause write_v7m_exception() to actually change stacks.
6762 */
6763 write_v7m_exception(env, 1);
6764 }
6765 switch_v7m_security_state(env, 0);
6766 env->thumb = 1;
6767 env->regs[15] = dest;
6768 }
6769
6770 static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
6771 bool spsel)
6772 {
6773 /* Return a pointer to the location where we currently store the
6774 * stack pointer for the requested security state and thread mode.
6775 * This pointer will become invalid if the CPU state is updated
6776 * such that the stack pointers are switched around (eg changing
6777 * the SPSEL control bit).
6778 * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
6779 * Unlike that pseudocode, we require the caller to pass us in the
6780 * SPSEL control bit value; this is because we also use this
6781 * function in handling of pushing of the callee-saves registers
6782 * part of the v8M stack frame (pseudocode PushCalleeStack()),
6783 * and in the tailchain codepath the SPSEL bit comes from the exception
6784 * return magic LR value from the previous exception. The pseudocode
6785 * opencodes the stack-selection in PushCalleeStack(), but we prefer
6786 * to make this utility function generic enough to do the job.
6787 */
6788 bool want_psp = threadmode && spsel;
6789
6790 if (secure == env->v7m.secure) {
6791 if (want_psp == v7m_using_psp(env)) {
6792 return &env->regs[13];
6793 } else {
6794 return &env->v7m.other_sp;
6795 }
6796 } else {
6797 if (want_psp) {
6798 return &env->v7m.other_ss_psp;
6799 } else {
6800 return &env->v7m.other_ss_msp;
6801 }
6802 }
6803 }
6804
6805 static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
6806 uint32_t *pvec)
6807 {
6808 CPUState *cs = CPU(cpu);
6809 CPUARMState *env = &cpu->env;
6810 MemTxResult result;
6811 uint32_t addr = env->v7m.vecbase[targets_secure] + exc * 4;
6812 uint32_t vector_entry;
6813 MemTxAttrs attrs = {};
6814 ARMMMUIdx mmu_idx;
6815 bool exc_secure;
6816
6817 mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targets_secure, true);
6818
6819 /* We don't do a get_phys_addr() here because the rules for vector
6820 * loads are special: they always use the default memory map, and
6821 * the default memory map permits reads from all addresses.
6822 * Since there's no easy way to pass through to pmsav8_mpu_lookup()
6823 * that we want this special case which would always say "yes",
6824 * we just do the SAU lookup here followed by a direct physical load.
6825 */
6826 attrs.secure = targets_secure;
6827 attrs.user = false;
6828
6829 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
6830 V8M_SAttributes sattrs = {};
6831
6832 v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
6833 if (sattrs.ns) {
6834 attrs.secure = false;
6835 } else if (!targets_secure) {
6836 /* NS access to S memory */
6837 goto load_fail;
6838 }
6839 }
6840
6841 vector_entry = address_space_ldl(arm_addressspace(cs, attrs), addr,
6842 attrs, &result);
6843 if (result != MEMTX_OK) {
6844 goto load_fail;
6845 }
6846 *pvec = vector_entry;
6847 return true;
6848
6849 load_fail:
6850 /* All vector table fetch fails are reported as HardFault, with
6851 * HFSR.VECTTBL and .FORCED set. (FORCED is set because
6852 * technically the underlying exception is a MemManage or BusFault
6853 * that is escalated to HardFault.) This is a terminal exception,
6854 * so we will either take the HardFault immediately or else enter
6855 * lockup (the latter case is handled in armv7m_nvic_set_pending_derived()).
6856 */
6857 exc_secure = targets_secure ||
6858 !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
6859 env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK;
6860 armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure);
6861 return false;
6862 }
6863
6864 static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
6865 bool ignore_faults)
6866 {
6867 /* For v8M, push the callee-saves register part of the stack frame.
6868 * Compare the v8M pseudocode PushCalleeStack().
6869 * In the tailchaining case this may not be the current stack.
6870 */
6871 CPUARMState *env = &cpu->env;
6872 uint32_t *frame_sp_p;
6873 uint32_t frameptr;
6874 ARMMMUIdx mmu_idx;
6875 bool stacked_ok;
6876 uint32_t limit;
6877 bool want_psp;
6878
6879 if (dotailchain) {
6880 bool mode = lr & R_V7M_EXCRET_MODE_MASK;
6881 bool priv = !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_NPRIV_MASK) ||
6882 !mode;
6883
6884 mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv);
6885 frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode,
6886 lr & R_V7M_EXCRET_SPSEL_MASK);
6887 want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK);
6888 if (want_psp) {
6889 limit = env->v7m.psplim[M_REG_S];
6890 } else {
6891 limit = env->v7m.msplim[M_REG_S];
6892 }
6893 } else {
6894 mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
6895 frame_sp_p = &env->regs[13];
6896 limit = v7m_sp_limit(env);
6897 }
6898
6899 frameptr = *frame_sp_p - 0x28;
6900 if (frameptr < limit) {
6901 /*
6902 * Stack limit failure: set SP to the limit value, and generate
6903 * STKOF UsageFault. Stack pushes below the limit must not be
6904 * performed. It is IMPDEF whether pushes above the limit are
6905 * performed; we choose not to.
6906 */
6907 qemu_log_mask(CPU_LOG_INT,
6908 "...STKOF during callee-saves register stacking\n");
6909 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK;
6910 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
6911 env->v7m.secure);
6912 *frame_sp_p = limit;
6913 return true;
6914 }
6915
6916 /* Write as much of the stack frame as we can. A write failure may
6917 * cause us to pend a derived exception.
6918 */
6919 stacked_ok =
6920 v7m_stack_write(cpu, frameptr, 0xfefa125b, mmu_idx, ignore_faults) &&
6921 v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx,
6922 ignore_faults) &&
6923 v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx,
6924 ignore_faults) &&
6925 v7m_stack_write(cpu, frameptr + 0x10, env->regs[6], mmu_idx,
6926 ignore_faults) &&
6927 v7m_stack_write(cpu, frameptr + 0x14, env->regs[7], mmu_idx,
6928 ignore_faults) &&
6929 v7m_stack_write(cpu, frameptr + 0x18, env->regs[8], mmu_idx,
6930 ignore_faults) &&
6931 v7m_stack_write(cpu, frameptr + 0x1c, env->regs[9], mmu_idx,
6932 ignore_faults) &&
6933 v7m_stack_write(cpu, frameptr + 0x20, env->regs[10], mmu_idx,
6934 ignore_faults) &&
6935 v7m_stack_write(cpu, frameptr + 0x24, env->regs[11], mmu_idx,
6936 ignore_faults);
6937
6938 /* Update SP regardless of whether any of the stack accesses failed. */
6939 *frame_sp_p = frameptr;
6940
6941 return !stacked_ok;
6942 }
6943
6944 static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
6945 bool ignore_stackfaults)
6946 {
6947 /* Do the "take the exception" parts of exception entry,
6948 * but not the pushing of state to the stack. This is
6949 * similar to the pseudocode ExceptionTaken() function.
6950 */
6951 CPUARMState *env = &cpu->env;
6952 uint32_t addr;
6953 bool targets_secure;
6954 int exc;
6955 bool push_failed = false;
6956
6957 armv7m_nvic_get_pending_irq_info(env->nvic, &exc, &targets_secure);
6958 qemu_log_mask(CPU_LOG_INT, "...taking pending %s exception %d\n",
6959 targets_secure ? "secure" : "nonsecure", exc);
6960
6961 if (arm_feature(env, ARM_FEATURE_V8)) {
6962 if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
6963 (lr & R_V7M_EXCRET_S_MASK)) {
6964 /* The background code (the owner of the registers in the
6965 * exception frame) is Secure. This means it may either already
6966 * have or now needs to push callee-saves registers.
6967 */
6968 if (targets_secure) {
6969 if (dotailchain && !(lr & R_V7M_EXCRET_ES_MASK)) {
6970 /* We took an exception from Secure to NonSecure
6971 * (which means the callee-saved registers got stacked)
6972 * and are now tailchaining to a Secure exception.
6973 * Clear DCRS so eventual return from this Secure
6974 * exception unstacks the callee-saved registers.
6975 */
6976 lr &= ~R_V7M_EXCRET_DCRS_MASK;
6977 }
6978 } else {
6979 /* We're going to a non-secure exception; push the
6980 * callee-saves registers to the stack now, if they're
6981 * not already saved.
6982 */
6983 if (lr & R_V7M_EXCRET_DCRS_MASK &&
6984 !(dotailchain && !(lr & R_V7M_EXCRET_ES_MASK))) {
6985 push_failed = v7m_push_callee_stack(cpu, lr, dotailchain,
6986 ignore_stackfaults);
6987 }
6988 lr |= R_V7M_EXCRET_DCRS_MASK;
6989 }
6990 }
6991
6992 lr &= ~R_V7M_EXCRET_ES_MASK;
6993 if (targets_secure || !arm_feature(env, ARM_FEATURE_M_SECURITY)) {
6994 lr |= R_V7M_EXCRET_ES_MASK;
6995 }
6996 lr &= ~R_V7M_EXCRET_SPSEL_MASK;
6997 if (env->v7m.control[targets_secure] & R_V7M_CONTROL_SPSEL_MASK) {
6998 lr |= R_V7M_EXCRET_SPSEL_MASK;
6999 }
7000
7001 /* Clear registers if necessary to prevent non-secure exception
7002 * code being able to see register values from secure code.
7003 * Where register values become architecturally UNKNOWN we leave
7004 * them with their previous values.
7005 */
7006 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
7007 if (!targets_secure) {
7008 /* Always clear the caller-saved registers (they have been
7009 * pushed to the stack earlier in v7m_push_stack()).
7010 * Clear callee-saved registers if the background code is
7011 * Secure (in which case these regs were saved in
7012 * v7m_push_callee_stack()).
7013 */
7014 int i;
7015
7016 for (i = 0; i < 13; i++) {
7017 /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */
7018 if (i < 4 || i > 11 || (lr & R_V7M_EXCRET_S_MASK)) {
7019 env->regs[i] = 0;
7020 }
7021 }
7022 /* Clear EAPSR */
7023 xpsr_write(env, 0, XPSR_NZCV | XPSR_Q | XPSR_GE | XPSR_IT);
7024 }
7025 }
7026 }
7027
7028 if (push_failed && !ignore_stackfaults) {
7029 /* Derived exception on callee-saves register stacking:
7030 * we might now want to take a different exception which
7031 * targets a different security state, so try again from the top.
7032 */
7033 qemu_log_mask(CPU_LOG_INT,
7034 "...derived exception on callee-saves register stacking");
7035 v7m_exception_taken(cpu, lr, true, true);
7036 return;
7037 }
7038
7039 if (!arm_v7m_load_vector(cpu, exc, targets_secure, &addr)) {
7040 /* Vector load failed: derived exception */
7041 qemu_log_mask(CPU_LOG_INT, "...derived exception on vector table load");
7042 v7m_exception_taken(cpu, lr, true, true);
7043 return;
7044 }
7045
7046 /* Now we've done everything that might cause a derived exception
7047 * we can go ahead and activate whichever exception we're going to
7048 * take (which might now be the derived exception).
7049 */
7050 armv7m_nvic_acknowledge_irq(env->nvic);
7051
7052 /* Switch to target security state -- must do this before writing SPSEL */
7053 switch_v7m_security_state(env, targets_secure);
7054 write_v7m_control_spsel(env, 0);
7055 arm_clear_exclusive(env);
7056 /* Clear IT bits */
7057 env->condexec_bits = 0;
7058 env->regs[14] = lr;
7059 env->regs[15] = addr & 0xfffffffe;
7060 env->thumb = addr & 1;
7061 }
7062
7063 static bool v7m_push_stack(ARMCPU *cpu)
7064 {
7065 /* Do the "set up stack frame" part of exception entry,
7066 * similar to pseudocode PushStack().
7067 * Return true if we generate a derived exception (and so
7068 * should ignore further stack faults trying to process
7069 * that derived exception.)
7070 */
7071 bool stacked_ok;
7072 CPUARMState *env = &cpu->env;
7073 uint32_t xpsr = xpsr_read(env);
7074 uint32_t frameptr = env->regs[13];
7075 ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
7076
7077 /* Align stack pointer if the guest wants that */
7078 if ((frameptr & 4) &&
7079 (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) {
7080 frameptr -= 4;
7081 xpsr |= XPSR_SPREALIGN;
7082 }
7083
7084 frameptr -= 0x20;
7085
7086 if (arm_feature(env, ARM_FEATURE_V8)) {
7087 uint32_t limit = v7m_sp_limit(env);
7088
7089 if (frameptr < limit) {
7090 /*
7091 * Stack limit failure: set SP to the limit value, and generate
7092 * STKOF UsageFault. Stack pushes below the limit must not be
7093 * performed. It is IMPDEF whether pushes above the limit are
7094 * performed; we choose not to.
7095 */
7096 qemu_log_mask(CPU_LOG_INT,
7097 "...STKOF during stacking\n");
7098 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK;
7099 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
7100 env->v7m.secure);
7101 env->regs[13] = limit;
7102 return true;
7103 }
7104 }
7105
7106 /* Write as much of the stack frame as we can. If we fail a stack
7107 * write this will result in a derived exception being pended
7108 * (which may be taken in preference to the one we started with
7109 * if it has higher priority).
7110 */
7111 stacked_ok =
7112 v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, false) &&
7113 v7m_stack_write(cpu, frameptr + 4, env->regs[1], mmu_idx, false) &&
7114 v7m_stack_write(cpu, frameptr + 8, env->regs[2], mmu_idx, false) &&
7115 v7m_stack_write(cpu, frameptr + 12, env->regs[3], mmu_idx, false) &&
7116 v7m_stack_write(cpu, frameptr + 16, env->regs[12], mmu_idx, false) &&
7117 v7m_stack_write(cpu, frameptr + 20, env->regs[14], mmu_idx, false) &&
7118 v7m_stack_write(cpu, frameptr + 24, env->regs[15], mmu_idx, false) &&
7119 v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, false);
7120
7121 /* Update SP regardless of whether any of the stack accesses failed. */
7122 env->regs[13] = frameptr;
7123
7124 return !stacked_ok;
7125 }
7126
7127 static void do_v7m_exception_exit(ARMCPU *cpu)
7128 {
7129 CPUARMState *env = &cpu->env;
7130 uint32_t excret;
7131 uint32_t xpsr;
7132 bool ufault = false;
7133 bool sfault = false;
7134 bool return_to_sp_process;
7135 bool return_to_handler;
7136 bool rettobase = false;
7137 bool exc_secure = false;
7138 bool return_to_secure;
7139
7140 /* If we're not in Handler mode then jumps to magic exception-exit
7141 * addresses don't have magic behaviour. However for the v8M
7142 * security extensions the magic secure-function-return has to
7143 * work in thread mode too, so to avoid doing an extra check in
7144 * the generated code we allow exception-exit magic to also cause the
7145 * internal exception and bring us here in thread mode. Correct code
7146 * will never try to do this (the following insn fetch will always
7147 * fault) so we the overhead of having taken an unnecessary exception
7148 * doesn't matter.
7149 */
7150 if (!arm_v7m_is_handler_mode(env)) {
7151 return;
7152 }
7153
7154 /* In the spec pseudocode ExceptionReturn() is called directly
7155 * from BXWritePC() and gets the full target PC value including
7156 * bit zero. In QEMU's implementation we treat it as a normal
7157 * jump-to-register (which is then caught later on), and so split
7158 * the target value up between env->regs[15] and env->thumb in
7159 * gen_bx(). Reconstitute it.
7160 */
7161 excret = env->regs[15];
7162 if (env->thumb) {
7163 excret |= 1;
7164 }
7165
7166 qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32
7167 " previous exception %d\n",
7168 excret, env->v7m.exception);
7169
7170 if ((excret & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) {
7171 qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception "
7172 "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n",
7173 excret);
7174 }
7175
7176 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
7177 /* EXC_RETURN.ES validation check (R_SMFL). We must do this before
7178 * we pick which FAULTMASK to clear.
7179 */
7180 if (!env->v7m.secure &&
7181 ((excret & R_V7M_EXCRET_ES_MASK) ||
7182 !(excret & R_V7M_EXCRET_DCRS_MASK))) {
7183 sfault = 1;
7184 /* For all other purposes, treat ES as 0 (R_HXSR) */
7185 excret &= ~R_V7M_EXCRET_ES_MASK;
7186 }
7187 exc_secure = excret & R_V7M_EXCRET_ES_MASK;
7188 }
7189
7190 if (env->v7m.exception != ARMV7M_EXCP_NMI) {
7191 /* Auto-clear FAULTMASK on return from other than NMI.
7192 * If the security extension is implemented then this only
7193 * happens if the raw execution priority is >= 0; the
7194 * value of the ES bit in the exception return value indicates
7195 * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
7196 */
7197 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
7198 if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
7199 env->v7m.faultmask[exc_secure] = 0;
7200 }
7201 } else {
7202 env->v7m.faultmask[M_REG_NS] = 0;
7203 }
7204 }
7205
7206 switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception,
7207 exc_secure)) {
7208 case -1:
7209 /* attempt to exit an exception that isn't active */
7210 ufault = true;
7211 break;
7212 case 0:
7213 /* still an irq active now */
7214 break;
7215 case 1:
7216 /* we returned to base exception level, no nesting.
7217 * (In the pseudocode this is written using "NestedActivation != 1"
7218 * where we have 'rettobase == false'.)
7219 */
7220 rettobase = true;
7221 break;
7222 default:
7223 g_assert_not_reached();
7224 }
7225
7226 return_to_handler = !(excret & R_V7M_EXCRET_MODE_MASK);
7227 return_to_sp_process = excret & R_V7M_EXCRET_SPSEL_MASK;
7228 return_to_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
7229 (excret & R_V7M_EXCRET_S_MASK);
7230
7231 if (arm_feature(env, ARM_FEATURE_V8)) {
7232 if (!arm_feature(env, ARM_FEATURE_M_SECURITY)) {
7233 /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
7234 * we choose to take the UsageFault.
7235 */
7236 if ((excret & R_V7M_EXCRET_S_MASK) ||
7237 (excret & R_V7M_EXCRET_ES_MASK) ||
7238 !(excret & R_V7M_EXCRET_DCRS_MASK)) {
7239 ufault = true;
7240 }
7241 }
7242 if (excret & R_V7M_EXCRET_RES0_MASK) {
7243 ufault = true;
7244 }
7245 } else {
7246 /* For v7M we only recognize certain combinations of the low bits */
7247 switch (excret & 0xf) {
7248 case 1: /* Return to Handler */
7249 break;
7250 case 13: /* Return to Thread using Process stack */
7251 case 9: /* Return to Thread using Main stack */
7252 /* We only need to check NONBASETHRDENA for v7M, because in
7253 * v8M this bit does not exist (it is RES1).
7254 */
7255 if (!rettobase &&
7256 !(env->v7m.ccr[env->v7m.secure] &
7257 R_V7M_CCR_NONBASETHRDENA_MASK)) {
7258 ufault = true;
7259 }
7260 break;
7261 default:
7262 ufault = true;
7263 }
7264 }
7265
7266 /*
7267 * Set CONTROL.SPSEL from excret.SPSEL. Since we're still in
7268 * Handler mode (and will be until we write the new XPSR.Interrupt
7269 * field) this does not switch around the current stack pointer.
7270 * We must do this before we do any kind of tailchaining, including
7271 * for the derived exceptions on integrity check failures, or we will
7272 * give the guest an incorrect EXCRET.SPSEL value on exception entry.
7273 */
7274 write_v7m_control_spsel_for_secstate(env, return_to_sp_process, exc_secure);
7275
7276 if (sfault) {
7277 env->v7m.sfsr |= R_V7M_SFSR_INVER_MASK;
7278 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
7279 qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing "
7280 "stackframe: failed EXC_RETURN.ES validity check\n");
7281 v7m_exception_taken(cpu, excret, true, false);
7282 return;
7283 }
7284
7285 if (ufault) {
7286 /* Bad exception return: instead of popping the exception
7287 * stack, directly take a usage fault on the current stack.
7288 */
7289 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
7290 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
7291 qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
7292 "stackframe: failed exception return integrity check\n");
7293 v7m_exception_taken(cpu, excret, true, false);
7294 return;
7295 }
7296
7297 /*
7298 * Tailchaining: if there is currently a pending exception that
7299 * is high enough priority to preempt execution at the level we're
7300 * about to return to, then just directly take that exception now,
7301 * avoiding an unstack-and-then-stack. Note that now we have
7302 * deactivated the previous exception by calling armv7m_nvic_complete_irq()
7303 * our current execution priority is already the execution priority we are
7304 * returning to -- none of the state we would unstack or set based on
7305 * the EXCRET value affects it.
7306 */
7307 if (armv7m_nvic_can_take_pending_exception(env->nvic)) {
7308 qemu_log_mask(CPU_LOG_INT, "...tailchaining to pending exception\n");
7309 v7m_exception_taken(cpu, excret, true, false);
7310 return;
7311 }
7312
7313 switch_v7m_security_state(env, return_to_secure);
7314
7315 {
7316 /* The stack pointer we should be reading the exception frame from
7317 * depends on bits in the magic exception return type value (and
7318 * for v8M isn't necessarily the stack pointer we will eventually
7319 * end up resuming execution with). Get a pointer to the location
7320 * in the CPU state struct where the SP we need is currently being
7321 * stored; we will use and modify it in place.
7322 * We use this limited C variable scope so we don't accidentally
7323 * use 'frame_sp_p' after we do something that makes it invalid.
7324 */
7325 uint32_t *frame_sp_p = get_v7m_sp_ptr(env,
7326 return_to_secure,
7327 !return_to_handler,
7328 return_to_sp_process);
7329 uint32_t frameptr = *frame_sp_p;
7330 bool pop_ok = true;
7331 ARMMMUIdx mmu_idx;
7332 bool return_to_priv = return_to_handler ||
7333 !(env->v7m.control[return_to_secure] & R_V7M_CONTROL_NPRIV_MASK);
7334
7335 mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, return_to_secure,
7336 return_to_priv);
7337
7338 if (!QEMU_IS_ALIGNED(frameptr, 8) &&
7339 arm_feature(env, ARM_FEATURE_V8)) {
7340 qemu_log_mask(LOG_GUEST_ERROR,
7341 "M profile exception return with non-8-aligned SP "
7342 "for destination state is UNPREDICTABLE\n");
7343 }
7344
7345 /* Do we need to pop callee-saved registers? */
7346 if (return_to_secure &&
7347 ((excret & R_V7M_EXCRET_ES_MASK) == 0 ||
7348 (excret & R_V7M_EXCRET_DCRS_MASK) == 0)) {
7349 uint32_t expected_sig = 0xfefa125b;
7350 uint32_t actual_sig;
7351
7352 pop_ok = v7m_stack_read(cpu, &actual_sig, frameptr, mmu_idx);
7353
7354 if (pop_ok && expected_sig != actual_sig) {
7355 /* Take a SecureFault on the current stack */
7356 env->v7m.sfsr |= R_V7M_SFSR_INVIS_MASK;
7357 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
7358 qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing "
7359 "stackframe: failed exception return integrity "
7360 "signature check\n");
7361 v7m_exception_taken(cpu, excret, true, false);
7362 return;
7363 }
7364
7365 pop_ok = pop_ok &&
7366 v7m_stack_read(cpu, &env->regs[4], frameptr + 0x8, mmu_idx) &&
7367 v7m_stack_read(cpu, &env->regs[5], frameptr + 0xc, mmu_idx) &&
7368 v7m_stack_read(cpu, &env->regs[6], frameptr + 0x10, mmu_idx) &&
7369 v7m_stack_read(cpu, &env->regs[7], frameptr + 0x14, mmu_idx) &&
7370 v7m_stack_read(cpu, &env->regs[8], frameptr + 0x18, mmu_idx) &&
7371 v7m_stack_read(cpu, &env->regs[9], frameptr + 0x1c, mmu_idx) &&
7372 v7m_stack_read(cpu, &env->regs[10], frameptr + 0x20, mmu_idx) &&
7373 v7m_stack_read(cpu, &env->regs[11], frameptr + 0x24, mmu_idx);
7374
7375 frameptr += 0x28;
7376 }
7377
7378 /* Pop registers */
7379 pop_ok = pop_ok &&
7380 v7m_stack_read(cpu, &env->regs[0], frameptr, mmu_idx) &&
7381 v7m_stack_read(cpu, &env->regs[1], frameptr + 0x4, mmu_idx) &&
7382 v7m_stack_read(cpu, &env->regs[2], frameptr + 0x8, mmu_idx) &&
7383 v7m_stack_read(cpu, &env->regs[3], frameptr + 0xc, mmu_idx) &&
7384 v7m_stack_read(cpu, &env->regs[12], frameptr + 0x10, mmu_idx) &&
7385 v7m_stack_read(cpu, &env->regs[14], frameptr + 0x14, mmu_idx) &&
7386 v7m_stack_read(cpu, &env->regs[15], frameptr + 0x18, mmu_idx) &&
7387 v7m_stack_read(cpu, &xpsr, frameptr + 0x1c, mmu_idx);
7388
7389 if (!pop_ok) {
7390 /* v7m_stack_read() pended a fault, so take it (as a tail
7391 * chained exception on the same stack frame)
7392 */
7393 qemu_log_mask(CPU_LOG_INT, "...derived exception on unstacking\n");
7394 v7m_exception_taken(cpu, excret, true, false);
7395 return;
7396 }
7397
7398 /* Returning from an exception with a PC with bit 0 set is defined
7399 * behaviour on v8M (bit 0 is ignored), but for v7M it was specified
7400 * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
7401 * the lsbit, and there are several RTOSes out there which incorrectly
7402 * assume the r15 in the stack frame should be a Thumb-style "lsbit
7403 * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but
7404 * complain about the badly behaved guest.
7405 */
7406 if (env->regs[15] & 1) {
7407 env->regs[15] &= ~1U;
7408 if (!arm_feature(env, ARM_FEATURE_V8)) {
7409 qemu_log_mask(LOG_GUEST_ERROR,
7410 "M profile return from interrupt with misaligned "
7411 "PC is UNPREDICTABLE on v7M\n");
7412 }
7413 }
7414
7415 if (arm_feature(env, ARM_FEATURE_V8)) {
7416 /* For v8M we have to check whether the xPSR exception field
7417 * matches the EXCRET value for return to handler/thread
7418 * before we commit to changing the SP and xPSR.
7419 */
7420 bool will_be_handler = (xpsr & XPSR_EXCP) != 0;
7421 if (return_to_handler != will_be_handler) {
7422 /* Take an INVPC UsageFault on the current stack.
7423 * By this point we will have switched to the security state
7424 * for the background state, so this UsageFault will target
7425 * that state.
7426 */
7427 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
7428 env->v7m.secure);
7429 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
7430 qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
7431 "stackframe: failed exception return integrity "
7432 "check\n");
7433 v7m_exception_taken(cpu, excret, true, false);
7434 return;
7435 }
7436 }
7437
7438 /* Commit to consuming the stack frame */
7439 frameptr += 0x20;
7440 /* Undo stack alignment (the SPREALIGN bit indicates that the original
7441 * pre-exception SP was not 8-aligned and we added a padding word to
7442 * align it, so we undo this by ORing in the bit that increases it
7443 * from the current 8-aligned value to the 8-unaligned value. (Adding 4
7444 * would work too but a logical OR is how the pseudocode specifies it.)
7445 */
7446 if (xpsr & XPSR_SPREALIGN) {
7447 frameptr |= 4;
7448 }
7449 *frame_sp_p = frameptr;
7450 }
7451 /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */
7452 xpsr_write(env, xpsr, ~XPSR_SPREALIGN);
7453
7454 /* The restored xPSR exception field will be zero if we're
7455 * resuming in Thread mode. If that doesn't match what the
7456 * exception return excret specified then this is a UsageFault.
7457 * v7M requires we make this check here; v8M did it earlier.
7458 */
7459 if (return_to_handler != arm_v7m_is_handler_mode(env)) {
7460 /* Take an INVPC UsageFault by pushing the stack again;
7461 * we know we're v7M so this is never a Secure UsageFault.
7462 */
7463 bool ignore_stackfaults;
7464
7465 assert(!arm_feature(env, ARM_FEATURE_V8));
7466 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false);
7467 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
7468 ignore_stackfaults = v7m_push_stack(cpu);
7469 qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: "
7470 "failed exception return integrity check\n");
7471 v7m_exception_taken(cpu, excret, false, ignore_stackfaults);
7472 return;
7473 }
7474
7475 /* Otherwise, we have a successful exception exit. */
7476 arm_clear_exclusive(env);
7477 qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
7478 }
7479
7480 static bool do_v7m_function_return(ARMCPU *cpu)
7481 {
7482 /* v8M security extensions magic function return.
7483 * We may either:
7484 * (1) throw an exception (longjump)
7485 * (2) return true if we successfully handled the function return
7486 * (3) return false if we failed a consistency check and have
7487 * pended a UsageFault that needs to be taken now
7488 *
7489 * At this point the magic return value is split between env->regs[15]
7490 * and env->thumb. We don't bother to reconstitute it because we don't
7491 * need it (all values are handled the same way).
7492 */
7493 CPUARMState *env = &cpu->env;
7494 uint32_t newpc, newpsr, newpsr_exc;
7495
7496 qemu_log_mask(CPU_LOG_INT, "...really v7M secure function return\n");
7497
7498 {
7499 bool threadmode, spsel;
7500 TCGMemOpIdx oi;
7501 ARMMMUIdx mmu_idx;
7502 uint32_t *frame_sp_p;
7503 uint32_t frameptr;
7504
7505 /* Pull the return address and IPSR from the Secure stack */
7506 threadmode = !arm_v7m_is_handler_mode(env);
7507 spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
7508
7509 frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
7510 frameptr = *frame_sp_p;
7511
7512 /* These loads may throw an exception (for MPU faults). We want to
7513 * do them as secure, so work out what MMU index that is.
7514 */
7515 mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
7516 oi = make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx));
7517 newpc = helper_le_ldul_mmu(env, frameptr, oi, 0);
7518 newpsr = helper_le_ldul_mmu(env, frameptr + 4, oi, 0);
7519
7520 /* Consistency checks on new IPSR */
7521 newpsr_exc = newpsr & XPSR_EXCP;
7522 if (!((env->v7m.exception == 0 && newpsr_exc == 0) ||
7523 (env->v7m.exception == 1 && newpsr_exc != 0))) {
7524 /* Pend the fault and tell our caller to take it */
7525 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
7526 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
7527 env->v7m.secure);
7528 qemu_log_mask(CPU_LOG_INT,
7529 "...taking INVPC UsageFault: "
7530 "IPSR consistency check failed\n");
7531 return false;
7532 }
7533
7534 *frame_sp_p = frameptr + 8;
7535 }
7536
7537 /* This invalidates frame_sp_p */
7538 switch_v7m_security_state(env, true);
7539 env->v7m.exception = newpsr_exc;
7540 env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
7541 if (newpsr & XPSR_SFPA) {
7542 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_SFPA_MASK;
7543 }
7544 xpsr_write(env, 0, XPSR_IT);
7545 env->thumb = newpc & 1;
7546 env->regs[15] = newpc & ~1;
7547
7548 qemu_log_mask(CPU_LOG_INT, "...function return successful\n");
7549 return true;
7550 }
7551
7552 static void arm_log_exception(int idx)
7553 {
7554 if (qemu_loglevel_mask(CPU_LOG_INT)) {
7555 const char *exc = NULL;
7556 static const char * const excnames[] = {
7557 [EXCP_UDEF] = "Undefined Instruction",
7558 [EXCP_SWI] = "SVC",
7559 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
7560 [EXCP_DATA_ABORT] = "Data Abort",
7561 [EXCP_IRQ] = "IRQ",
7562 [EXCP_FIQ] = "FIQ",
7563 [EXCP_BKPT] = "Breakpoint",
7564 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
7565 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
7566 [EXCP_HVC] = "Hypervisor Call",
7567 [EXCP_HYP_TRAP] = "Hypervisor Trap",
7568 [EXCP_SMC] = "Secure Monitor Call",
7569 [EXCP_VIRQ] = "Virtual IRQ",
7570 [EXCP_VFIQ] = "Virtual FIQ",
7571 [EXCP_SEMIHOST] = "Semihosting call",
7572 [EXCP_NOCP] = "v7M NOCP UsageFault",
7573 [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
7574 [EXCP_STKOF] = "v8M STKOF UsageFault",
7575 };
7576
7577 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
7578 exc = excnames[idx];
7579 }
7580 if (!exc) {
7581 exc = "unknown";
7582 }
7583 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
7584 }
7585 }
7586
7587 static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
7588 uint32_t addr, uint16_t *insn)
7589 {
7590 /* Load a 16-bit portion of a v7M instruction, returning true on success,
7591 * or false on failure (in which case we will have pended the appropriate
7592 * exception).
7593 * We need to do the instruction fetch's MPU and SAU checks
7594 * like this because there is no MMU index that would allow
7595 * doing the load with a single function call. Instead we must
7596 * first check that the security attributes permit the load
7597 * and that they don't mismatch on the two halves of the instruction,
7598 * and then we do the load as a secure load (ie using the security
7599 * attributes of the address, not the CPU, as architecturally required).
7600 */
7601 CPUState *cs = CPU(cpu);
7602 CPUARMState *env = &cpu->env;
7603 V8M_SAttributes sattrs = {};
7604 MemTxAttrs attrs = {};
7605 ARMMMUFaultInfo fi = {};
7606 MemTxResult txres;
7607 target_ulong page_size;
7608 hwaddr physaddr;
7609 int prot;
7610
7611 v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
7612 if (!sattrs.nsc || sattrs.ns) {
7613 /* This must be the second half of the insn, and it straddles a
7614 * region boundary with the second half not being S&NSC.
7615 */
7616 env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
7617 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
7618 qemu_log_mask(CPU_LOG_INT,
7619 "...really SecureFault with SFSR.INVEP\n");
7620 return false;
7621 }
7622 if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx,
7623 &physaddr, &attrs, &prot, &page_size, &fi, NULL)) {
7624 /* the MPU lookup failed */
7625 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
7626 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure);
7627 qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n");
7628 return false;
7629 }
7630 *insn = address_space_lduw_le(arm_addressspace(cs, attrs), physaddr,
7631 attrs, &txres);
7632 if (txres != MEMTX_OK) {
7633 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
7634 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
7635 qemu_log_mask(CPU_LOG_INT, "...really BusFault with CFSR.IBUSERR\n");
7636 return false;
7637 }
7638 return true;
7639 }
7640
7641 static bool v7m_handle_execute_nsc(ARMCPU *cpu)
7642 {
7643 /* Check whether this attempt to execute code in a Secure & NS-Callable
7644 * memory region is for an SG instruction; if so, then emulate the
7645 * effect of the SG instruction and return true. Otherwise pend
7646 * the correct kind of exception and return false.
7647 */
7648 CPUARMState *env = &cpu->env;
7649 ARMMMUIdx mmu_idx;
7650 uint16_t insn;
7651
7652 /* We should never get here unless get_phys_addr_pmsav8() caused
7653 * an exception for NS executing in S&NSC memory.
7654 */
7655 assert(!env->v7m.secure);
7656 assert(arm_feature(env, ARM_FEATURE_M_SECURITY));
7657
7658 /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
7659 mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
7660
7661 if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) {
7662 return false;
7663 }
7664
7665 if (!env->thumb) {
7666 goto gen_invep;
7667 }
7668
7669 if (insn != 0xe97f) {
7670 /* Not an SG instruction first half (we choose the IMPDEF
7671 * early-SG-check option).
7672 */
7673 goto gen_invep;
7674 }
7675
7676 if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) {
7677 return false;
7678 }
7679
7680 if (insn != 0xe97f) {
7681 /* Not an SG instruction second half (yes, both halves of the SG
7682 * insn have the same hex value)
7683 */
7684 goto gen_invep;
7685 }
7686
7687 /* OK, we have confirmed that we really have an SG instruction.
7688 * We know we're NS in S memory so don't need to repeat those checks.
7689 */
7690 qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
7691 ", executing it\n", env->regs[15]);
7692 env->regs[14] &= ~1;
7693 switch_v7m_security_state(env, true);
7694 xpsr_write(env, 0, XPSR_IT);
7695 env->regs[15] += 4;
7696 return true;
7697
7698 gen_invep:
7699 env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
7700 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
7701 qemu_log_mask(CPU_LOG_INT,
7702 "...really SecureFault with SFSR.INVEP\n");
7703 return false;
7704 }
7705
7706 void arm_v7m_cpu_do_interrupt(CPUState *cs)
7707 {
7708 ARMCPU *cpu = ARM_CPU(cs);
7709 CPUARMState *env = &cpu->env;
7710 uint32_t lr;
7711 bool ignore_stackfaults;
7712
7713 arm_log_exception(cs->exception_index);
7714
7715 /* For exceptions we just mark as pending on the NVIC, and let that
7716 handle it. */
7717 switch (cs->exception_index) {
7718 case EXCP_UDEF:
7719 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
7720 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK;
7721 break;
7722 case EXCP_NOCP:
7723 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
7724 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK;
7725 break;
7726 case EXCP_INVSTATE:
7727 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
7728 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK;
7729 break;
7730 case EXCP_STKOF:
7731 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
7732 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK;
7733 break;
7734 case EXCP_SWI:
7735 /* The PC already points to the next instruction. */
7736 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure);
7737 break;
7738 case EXCP_PREFETCH_ABORT:
7739 case EXCP_DATA_ABORT:
7740 /* Note that for M profile we don't have a guest facing FSR, but
7741 * the env->exception.fsr will be populated by the code that
7742 * raises the fault, in the A profile short-descriptor format.
7743 */
7744 switch (env->exception.fsr & 0xf) {
7745 case M_FAKE_FSR_NSC_EXEC:
7746 /* Exception generated when we try to execute code at an address
7747 * which is marked as Secure & Non-Secure Callable and the CPU
7748 * is in the Non-Secure state. The only instruction which can
7749 * be executed like this is SG (and that only if both halves of
7750 * the SG instruction have the same security attributes.)
7751 * Everything else must generate an INVEP SecureFault, so we
7752 * emulate the SG instruction here.
7753 */
7754 if (v7m_handle_execute_nsc(cpu)) {
7755 return;
7756 }
7757 break;
7758 case M_FAKE_FSR_SFAULT:
7759 /* Various flavours of SecureFault for attempts to execute or
7760 * access data in the wrong security state.
7761 */
7762 switch (cs->exception_index) {
7763 case EXCP_PREFETCH_ABORT:
7764 if (env->v7m.secure) {
7765 env->v7m.sfsr |= R_V7M_SFSR_INVTRAN_MASK;
7766 qemu_log_mask(CPU_LOG_INT,
7767 "...really SecureFault with SFSR.INVTRAN\n");
7768 } else {
7769 env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK;
7770 qemu_log_mask(CPU_LOG_INT,
7771 "...really SecureFault with SFSR.INVEP\n");
7772 }
7773 break;
7774 case EXCP_DATA_ABORT:
7775 /* This must be an NS access to S memory */
7776 env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK;
7777 qemu_log_mask(CPU_LOG_INT,
7778 "...really SecureFault with SFSR.AUVIOL\n");
7779 break;
7780 }
7781 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
7782 break;
7783 case 0x8: /* External Abort */
7784 switch (cs->exception_index) {
7785 case EXCP_PREFETCH_ABORT:
7786 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
7787 qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n");
7788 break;
7789 case EXCP_DATA_ABORT:
7790 env->v7m.cfsr[M_REG_NS] |=
7791 (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
7792 env->v7m.bfar = env->exception.vaddress;
7793 qemu_log_mask(CPU_LOG_INT,
7794 "...with CFSR.PRECISERR and BFAR 0x%x\n",
7795 env->v7m.bfar);
7796 break;
7797 }
7798 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
7799 break;
7800 default:
7801 /* All other FSR values are either MPU faults or "can't happen
7802 * for M profile" cases.
7803 */
7804 switch (cs->exception_index) {
7805 case EXCP_PREFETCH_ABORT:
7806 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
7807 qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n");
7808 break;
7809 case EXCP_DATA_ABORT:
7810 env->v7m.cfsr[env->v7m.secure] |=
7811 (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK);
7812 env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress;
7813 qemu_log_mask(CPU_LOG_INT,
7814 "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
7815 env->v7m.mmfar[env->v7m.secure]);
7816 break;
7817 }
7818 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM,
7819 env->v7m.secure);
7820 break;
7821 }
7822 break;
7823 case EXCP_BKPT:
7824 if (semihosting_enabled()) {
7825 int nr;
7826 nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff;
7827 if (nr == 0xab) {
7828 env->regs[15] += 2;
7829 qemu_log_mask(CPU_LOG_INT,
7830 "...handling as semihosting call 0x%x\n",
7831 env->regs[0]);
7832 env->regs[0] = do_arm_semihosting(env);
7833 return;
7834 }
7835 }
7836 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);
7837 break;
7838 case EXCP_IRQ:
7839 break;
7840 case EXCP_EXCEPTION_EXIT:
7841 if (env->regs[15] < EXC_RETURN_MIN_MAGIC) {
7842 /* Must be v8M security extension function return */
7843 assert(env->regs[15] >= FNC_RETURN_MIN_MAGIC);
7844 assert(arm_feature(env, ARM_FEATURE_M_SECURITY));
7845 if (do_v7m_function_return(cpu)) {
7846 return;
7847 }
7848 } else {
7849 do_v7m_exception_exit(cpu);
7850 return;
7851 }
7852 break;
7853 default:
7854 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
7855 return; /* Never happens. Keep compiler happy. */
7856 }
7857
7858 if (arm_feature(env, ARM_FEATURE_V8)) {
7859 lr = R_V7M_EXCRET_RES1_MASK |
7860 R_V7M_EXCRET_DCRS_MASK |
7861 R_V7M_EXCRET_FTYPE_MASK;
7862 /* The S bit indicates whether we should return to Secure
7863 * or NonSecure (ie our current state).
7864 * The ES bit indicates whether we're taking this exception
7865 * to Secure or NonSecure (ie our target state). We set it
7866 * later, in v7m_exception_taken().
7867 * The SPSEL bit is also set in v7m_exception_taken() for v8M.
7868 * This corresponds to the ARM ARM pseudocode for v8M setting
7869 * some LR bits in PushStack() and some in ExceptionTaken();
7870 * the distinction matters for the tailchain cases where we
7871 * can take an exception without pushing the stack.
7872 */
7873 if (env->v7m.secure) {
7874 lr |= R_V7M_EXCRET_S_MASK;
7875 }
7876 } else {
7877 lr = R_V7M_EXCRET_RES1_MASK |
7878 R_V7M_EXCRET_S_MASK |
7879 R_V7M_EXCRET_DCRS_MASK |
7880 R_V7M_EXCRET_FTYPE_MASK |
7881 R_V7M_EXCRET_ES_MASK;
7882 if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) {
7883 lr |= R_V7M_EXCRET_SPSEL_MASK;
7884 }
7885 }
7886 if (!arm_v7m_is_handler_mode(env)) {
7887 lr |= R_V7M_EXCRET_MODE_MASK;
7888 }
7889
7890 ignore_stackfaults = v7m_push_stack(cpu);
7891 v7m_exception_taken(cpu, lr, false, ignore_stackfaults);
7892 }
7893
7894 /* Function used to synchronize QEMU's AArch64 register set with AArch32
7895 * register set. This is necessary when switching between AArch32 and AArch64
7896 * execution state.
7897 */
7898 void aarch64_sync_32_to_64(CPUARMState *env)
7899 {
7900 int i;
7901 uint32_t mode = env->uncached_cpsr & CPSR_M;
7902
7903 /* We can blanket copy R[0:7] to X[0:7] */
7904 for (i = 0; i < 8; i++) {
7905 env->xregs[i] = env->regs[i];
7906 }
7907
7908 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
7909 * Otherwise, they come from the banked user regs.
7910 */
7911 if (mode == ARM_CPU_MODE_FIQ) {
7912 for (i = 8; i < 13; i++) {
7913 env->xregs[i] = env->usr_regs[i - 8];
7914 }
7915 } else {
7916 for (i = 8; i < 13; i++) {
7917 env->xregs[i] = env->regs[i];
7918 }
7919 }
7920
7921 /* Registers x13-x23 are the various mode SP and FP registers. Registers
7922 * r13 and r14 are only copied if we are in that mode, otherwise we copy
7923 * from the mode banked register.
7924 */
7925 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
7926 env->xregs[13] = env->regs[13];
7927 env->xregs[14] = env->regs[14];
7928 } else {
7929 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
7930 /* HYP is an exception in that it is copied from r14 */
7931 if (mode == ARM_CPU_MODE_HYP) {
7932 env->xregs[14] = env->regs[14];
7933 } else {
7934 env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
7935 }
7936 }
7937
7938 if (mode == ARM_CPU_MODE_HYP) {
7939 env->xregs[15] = env->regs[13];
7940 } else {
7941 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
7942 }
7943
7944 if (mode == ARM_CPU_MODE_IRQ) {
7945 env->xregs[16] = env->regs[14];
7946 env->xregs[17] = env->regs[13];
7947 } else {
7948 env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
7949 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
7950 }
7951
7952 if (mode == ARM_CPU_MODE_SVC) {
7953 env->xregs[18] = env->regs[14];
7954 env->xregs[19] = env->regs[13];
7955 } else {
7956 env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
7957 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
7958 }
7959
7960 if (mode == ARM_CPU_MODE_ABT) {
7961 env->xregs[20] = env->regs[14];
7962 env->xregs[21] = env->regs[13];
7963 } else {
7964 env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
7965 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
7966 }
7967
7968 if (mode == ARM_CPU_MODE_UND) {
7969 env->xregs[22] = env->regs[14];
7970 env->xregs[23] = env->regs[13];
7971 } else {
7972 env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
7973 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
7974 }
7975
7976 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
7977 * mode, then we can copy from r8-r14. Otherwise, we copy from the
7978 * FIQ bank for r8-r14.
7979 */
7980 if (mode == ARM_CPU_MODE_FIQ) {
7981 for (i = 24; i < 31; i++) {
7982 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */
7983 }
7984 } else {
7985 for (i = 24; i < 29; i++) {
7986 env->xregs[i] = env->fiq_regs[i - 24];
7987 }
7988 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
7989 env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
7990 }
7991
7992 env->pc = env->regs[15];
7993 }
7994
7995 /* Function used to synchronize QEMU's AArch32 register set with AArch64
7996 * register set. This is necessary when switching between AArch32 and AArch64
7997 * execution state.
7998 */
7999 void aarch64_sync_64_to_32(CPUARMState *env)
8000 {
8001 int i;
8002 uint32_t mode = env->uncached_cpsr & CPSR_M;
8003
8004 /* We can blanket copy X[0:7] to R[0:7] */
8005 for (i = 0; i < 8; i++) {
8006 env->regs[i] = env->xregs[i];
8007 }
8008
8009 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
8010 * Otherwise, we copy x8-x12 into the banked user regs.
8011 */
8012 if (mode == ARM_CPU_MODE_FIQ) {
8013 for (i = 8; i < 13; i++) {
8014 env->usr_regs[i - 8] = env->xregs[i];
8015 }
8016 } else {
8017 for (i = 8; i < 13; i++) {
8018 env->regs[i] = env->xregs[i];
8019 }
8020 }
8021
8022 /* Registers r13 & r14 depend on the current mode.
8023 * If we are in a given mode, we copy the corresponding x registers to r13
8024 * and r14. Otherwise, we copy the x register to the banked r13 and r14
8025 * for the mode.
8026 */
8027 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
8028 env->regs[13] = env->xregs[13];
8029 env->regs[14] = env->xregs[14];
8030 } else {
8031 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
8032
8033 /* HYP is an exception in that it does not have its own banked r14 but
8034 * shares the USR r14
8035 */
8036 if (mode == ARM_CPU_MODE_HYP) {
8037 env->regs[14] = env->xregs[14];
8038 } else {
8039 env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
8040 }
8041 }
8042
8043 if (mode == ARM_CPU_MODE_HYP) {
8044 env->regs[13] = env->xregs[15];
8045 } else {
8046 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
8047 }
8048
8049 if (mode == ARM_CPU_MODE_IRQ) {
8050 env->regs[14] = env->xregs[16];
8051 env->regs[13] = env->xregs[17];
8052 } else {
8053 env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
8054 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
8055 }
8056
8057 if (mode == ARM_CPU_MODE_SVC) {
8058 env->regs[14] = env->xregs[18];
8059 env->regs[13] = env->xregs[19];
8060 } else {
8061 env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
8062 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
8063 }
8064
8065 if (mode == ARM_CPU_MODE_ABT) {
8066 env->regs[14] = env->xregs[20];
8067 env->regs[13] = env->xregs[21];
8068 } else {
8069 env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
8070 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
8071 }
8072
8073 if (mode == ARM_CPU_MODE_UND) {
8074 env->regs[14] = env->xregs[22];
8075 env->regs[13] = env->xregs[23];
8076 } else {
8077 env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
8078 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
8079 }
8080
8081 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
8082 * mode, then we can copy to r8-r14. Otherwise, we copy to the
8083 * FIQ bank for r8-r14.
8084 */
8085 if (mode == ARM_CPU_MODE_FIQ) {
8086 for (i = 24; i < 31; i++) {
8087 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */
8088 }
8089 } else {
8090 for (i = 24; i < 29; i++) {
8091 env->fiq_regs[i - 24] = env->xregs[i];
8092 }
8093 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
8094 env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
8095 }
8096
8097 env->regs[15] = env->pc;
8098 }
8099
8100 static void take_aarch32_exception(CPUARMState *env, int new_mode,
8101 uint32_t mask, uint32_t offset,
8102 uint32_t newpc)
8103 {
8104 /* Change the CPU state so as to actually take the exception. */
8105 switch_mode(env, new_mode);
8106 /*
8107 * For exceptions taken to AArch32 we must clear the SS bit in both
8108 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
8109 */
8110 env->uncached_cpsr &= ~PSTATE_SS;
8111 env->spsr = cpsr_read(env);
8112 /* Clear IT bits. */
8113 env->condexec_bits = 0;
8114 /* Switch to the new mode, and to the correct instruction set. */
8115 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
8116 /* Set new mode endianness */
8117 env->uncached_cpsr &= ~CPSR_E;
8118 if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
8119 env->uncached_cpsr |= CPSR_E;
8120 }
8121 /* J and IL must always be cleared for exception entry */
8122 env->uncached_cpsr &= ~(CPSR_IL | CPSR_J);
8123 env->daif |= mask;
8124
8125 if (new_mode == ARM_CPU_MODE_HYP) {
8126 env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0;
8127 env->elr_el[2] = env->regs[15];
8128 } else {
8129 /*
8130 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
8131 * and we should just guard the thumb mode on V4
8132 */
8133 if (arm_feature(env, ARM_FEATURE_V4T)) {
8134 env->thumb =
8135 (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
8136 }
8137 env->regs[14] = env->regs[15] + offset;
8138 }
8139 env->regs[15] = newpc;
8140 }
8141
8142 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
8143 {
8144 /*
8145 * Handle exception entry to Hyp mode; this is sufficiently
8146 * different to entry to other AArch32 modes that we handle it
8147 * separately here.
8148 *
8149 * The vector table entry used is always the 0x14 Hyp mode entry point,
8150 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
8151 * The offset applied to the preferred return address is always zero
8152 * (see DDI0487C.a section G1.12.3).
8153 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
8154 */
8155 uint32_t addr, mask;
8156 ARMCPU *cpu = ARM_CPU(cs);
8157 CPUARMState *env = &cpu->env;
8158
8159 switch (cs->exception_index) {
8160 case EXCP_UDEF:
8161 addr = 0x04;
8162 break;
8163 case EXCP_SWI:
8164 addr = 0x14;
8165 break;
8166 case EXCP_BKPT:
8167 /* Fall through to prefetch abort. */
8168 case EXCP_PREFETCH_ABORT:
8169 env->cp15.ifar_s = env->exception.vaddress;
8170 qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n",
8171 (uint32_t)env->exception.vaddress);
8172 addr = 0x0c;
8173 break;
8174 case EXCP_DATA_ABORT:
8175 env->cp15.dfar_s = env->exception.vaddress;
8176 qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n",
8177 (uint32_t)env->exception.vaddress);
8178 addr = 0x10;
8179 break;
8180 case EXCP_IRQ:
8181 addr = 0x18;
8182 break;
8183 case EXCP_FIQ:
8184 addr = 0x1c;
8185 break;
8186 case EXCP_HVC:
8187 addr = 0x08;
8188 break;
8189 case EXCP_HYP_TRAP:
8190 addr = 0x14;
8191 default:
8192 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
8193 }
8194
8195 if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) {
8196 env->cp15.esr_el[2] = env->exception.syndrome;
8197 }
8198
8199 if (arm_current_el(env) != 2 && addr < 0x14) {
8200 addr = 0x14;
8201 }
8202
8203 mask = 0;
8204 if (!(env->cp15.scr_el3 & SCR_EA)) {
8205 mask |= CPSR_A;
8206 }
8207 if (!(env->cp15.scr_el3 & SCR_IRQ)) {
8208 mask |= CPSR_I;
8209 }
8210 if (!(env->cp15.scr_el3 & SCR_FIQ)) {
8211 mask |= CPSR_F;
8212 }
8213
8214 addr += env->cp15.hvbar;
8215
8216 take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr);
8217 }
8218
8219 static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
8220 {
8221 ARMCPU *cpu = ARM_CPU(cs);
8222 CPUARMState *env = &cpu->env;
8223 uint32_t addr;
8224 uint32_t mask;
8225 int new_mode;
8226 uint32_t offset;
8227 uint32_t moe;
8228
8229 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
8230 switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
8231 case EC_BREAKPOINT:
8232 case EC_BREAKPOINT_SAME_EL:
8233 moe = 1;
8234 break;
8235 case EC_WATCHPOINT:
8236 case EC_WATCHPOINT_SAME_EL:
8237 moe = 10;
8238 break;
8239 case EC_AA32_BKPT:
8240 moe = 3;
8241 break;
8242 case EC_VECTORCATCH:
8243 moe = 5;
8244 break;
8245 default:
8246 moe = 0;
8247 break;
8248 }
8249
8250 if (moe) {
8251 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
8252 }
8253
8254 if (env->exception.target_el == 2) {
8255 arm_cpu_do_interrupt_aarch32_hyp(cs);
8256 return;
8257 }
8258
8259 /* TODO: Vectored interrupt controller. */
8260 switch (cs->exception_index) {
8261 case EXCP_UDEF:
8262 new_mode = ARM_CPU_MODE_UND;
8263 addr = 0x04;
8264 mask = CPSR_I;
8265 if (env->thumb)
8266 offset = 2;
8267 else
8268 offset = 4;
8269 break;
8270 case EXCP_SWI:
8271 new_mode = ARM_CPU_MODE_SVC;
8272 addr = 0x08;
8273 mask = CPSR_I;
8274 /* The PC already points to the next instruction. */
8275 offset = 0;
8276 break;
8277 case EXCP_BKPT:
8278 /* Fall through to prefetch abort. */
8279 case EXCP_PREFETCH_ABORT:
8280 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
8281 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
8282 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
8283 env->exception.fsr, (uint32_t)env->exception.vaddress);
8284 new_mode = ARM_CPU_MODE_ABT;
8285 addr = 0x0c;
8286 mask = CPSR_A | CPSR_I;
8287 offset = 4;
8288 break;
8289 case EXCP_DATA_ABORT:
8290 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
8291 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
8292 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
8293 env->exception.fsr,
8294 (uint32_t)env->exception.vaddress);
8295 new_mode = ARM_CPU_MODE_ABT;
8296 addr = 0x10;
8297 mask = CPSR_A | CPSR_I;
8298 offset = 8;
8299 break;
8300 case EXCP_IRQ:
8301 new_mode = ARM_CPU_MODE_IRQ;
8302 addr = 0x18;
8303 /* Disable IRQ and imprecise data aborts. */
8304 mask = CPSR_A | CPSR_I;
8305 offset = 4;
8306 if (env->cp15.scr_el3 & SCR_IRQ) {
8307 /* IRQ routed to monitor mode */
8308 new_mode = ARM_CPU_MODE_MON;
8309 mask |= CPSR_F;
8310 }
8311 break;
8312 case EXCP_FIQ:
8313 new_mode = ARM_CPU_MODE_FIQ;
8314 addr = 0x1c;
8315 /* Disable FIQ, IRQ and imprecise data aborts. */
8316 mask = CPSR_A | CPSR_I | CPSR_F;
8317 if (env->cp15.scr_el3 & SCR_FIQ) {
8318 /* FIQ routed to monitor mode */
8319 new_mode = ARM_CPU_MODE_MON;
8320 }
8321 offset = 4;
8322 break;
8323 case EXCP_VIRQ:
8324 new_mode = ARM_CPU_MODE_IRQ;
8325 addr = 0x18;
8326 /* Disable IRQ and imprecise data aborts. */
8327 mask = CPSR_A | CPSR_I;
8328 offset = 4;
8329 break;
8330 case EXCP_VFIQ:
8331 new_mode = ARM_CPU_MODE_FIQ;
8332 addr = 0x1c;
8333 /* Disable FIQ, IRQ and imprecise data aborts. */
8334 mask = CPSR_A | CPSR_I | CPSR_F;
8335 offset = 4;
8336 break;
8337 case EXCP_SMC:
8338 new_mode = ARM_CPU_MODE_MON;
8339 addr = 0x08;
8340 mask = CPSR_A | CPSR_I | CPSR_F;
8341 offset = 0;
8342 break;
8343 default:
8344 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
8345 return; /* Never happens. Keep compiler happy. */
8346 }
8347
8348 if (new_mode == ARM_CPU_MODE_MON) {
8349 addr += env->cp15.mvbar;
8350 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
8351 /* High vectors. When enabled, base address cannot be remapped. */
8352 addr += 0xffff0000;
8353 } else {
8354 /* ARM v7 architectures provide a vector base address register to remap
8355 * the interrupt vector table.
8356 * This register is only followed in non-monitor mode, and is banked.
8357 * Note: only bits 31:5 are valid.
8358 */
8359 addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
8360 }
8361
8362 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
8363 env->cp15.scr_el3 &= ~SCR_NS;
8364 }
8365
8366 take_aarch32_exception(env, new_mode, mask, offset, addr);
8367 }
8368
8369 /* Handle exception entry to a target EL which is using AArch64 */
8370 static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
8371 {
8372 ARMCPU *cpu = ARM_CPU(cs);
8373 CPUARMState *env = &cpu->env;
8374 unsigned int new_el = env->exception.target_el;
8375 target_ulong addr = env->cp15.vbar_el[new_el];
8376 unsigned int new_mode = aarch64_pstate_mode(new_el, true);
8377 unsigned int cur_el = arm_current_el(env);
8378
8379 /*
8380 * Note that new_el can never be 0. If cur_el is 0, then
8381 * el0_a64 is is_a64(), else el0_a64 is ignored.
8382 */
8383 aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
8384
8385 if (cur_el < new_el) {
8386 /* Entry vector offset depends on whether the implemented EL
8387 * immediately lower than the target level is using AArch32 or AArch64
8388 */
8389 bool is_aa64;
8390
8391 switch (new_el) {
8392 case 3:
8393 is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
8394 break;
8395 case 2:
8396 is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
8397 break;
8398 case 1:
8399 is_aa64 = is_a64(env);
8400 break;
8401 default:
8402 g_assert_not_reached();
8403 }
8404
8405 if (is_aa64) {
8406 addr += 0x400;
8407 } else {
8408 addr += 0x600;
8409 }
8410 } else if (pstate_read(env) & PSTATE_SP) {
8411 addr += 0x200;
8412 }
8413
8414 switch (cs->exception_index) {
8415 case EXCP_PREFETCH_ABORT:
8416 case EXCP_DATA_ABORT:
8417 env->cp15.far_el[new_el] = env->exception.vaddress;
8418 qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
8419 env->cp15.far_el[new_el]);
8420 /* fall through */
8421 case EXCP_BKPT:
8422 case EXCP_UDEF:
8423 case EXCP_SWI:
8424 case EXCP_HVC:
8425 case EXCP_HYP_TRAP:
8426 case EXCP_SMC:
8427 env->cp15.esr_el[new_el] = env->exception.syndrome;
8428 break;
8429 case EXCP_IRQ:
8430 case EXCP_VIRQ:
8431 addr += 0x80;
8432 break;
8433 case EXCP_FIQ:
8434 case EXCP_VFIQ:
8435 addr += 0x100;
8436 break;
8437 case EXCP_SEMIHOST:
8438 qemu_log_mask(CPU_LOG_INT,
8439 "...handling as semihosting call 0x%" PRIx64 "\n",
8440 env->xregs[0]);
8441 env->xregs[0] = do_arm_semihosting(env);
8442 return;
8443 default:
8444 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
8445 }
8446
8447 if (is_a64(env)) {
8448 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
8449 aarch64_save_sp(env, arm_current_el(env));
8450 env->elr_el[new_el] = env->pc;
8451 } else {
8452 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
8453 env->elr_el[new_el] = env->regs[15];
8454
8455 aarch64_sync_32_to_64(env);
8456
8457 env->condexec_bits = 0;
8458 }
8459 qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
8460 env->elr_el[new_el]);
8461
8462 pstate_write(env, PSTATE_DAIF | new_mode);
8463 env->aarch64 = 1;
8464 aarch64_restore_sp(env, new_el);
8465
8466 env->pc = addr;
8467
8468 qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
8469 new_el, env->pc, pstate_read(env));
8470 }
8471
8472 static inline bool check_for_semihosting(CPUState *cs)
8473 {
8474 /* Check whether this exception is a semihosting call; if so
8475 * then handle it and return true; otherwise return false.
8476 */
8477 ARMCPU *cpu = ARM_CPU(cs);
8478 CPUARMState *env = &cpu->env;
8479
8480 if (is_a64(env)) {
8481 if (cs->exception_index == EXCP_SEMIHOST) {
8482 /* This is always the 64-bit semihosting exception.
8483 * The "is this usermode" and "is semihosting enabled"
8484 * checks have been done at translate time.
8485 */
8486 qemu_log_mask(CPU_LOG_INT,
8487 "...handling as semihosting call 0x%" PRIx64 "\n",
8488 env->xregs[0]);
8489 env->xregs[0] = do_arm_semihosting(env);
8490 return true;
8491 }
8492 return false;
8493 } else {
8494 uint32_t imm;
8495
8496 /* Only intercept calls from privileged modes, to provide some
8497 * semblance of security.
8498 */
8499 if (cs->exception_index != EXCP_SEMIHOST &&
8500 (!semihosting_enabled() ||
8501 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) {
8502 return false;
8503 }
8504
8505 switch (cs->exception_index) {
8506 case EXCP_SEMIHOST:
8507 /* This is always a semihosting call; the "is this usermode"
8508 * and "is semihosting enabled" checks have been done at
8509 * translate time.
8510 */
8511 break;
8512 case EXCP_SWI:
8513 /* Check for semihosting interrupt. */
8514 if (env->thumb) {
8515 imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env))
8516 & 0xff;
8517 if (imm == 0xab) {
8518 break;
8519 }
8520 } else {
8521 imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env))
8522 & 0xffffff;
8523 if (imm == 0x123456) {
8524 break;
8525 }
8526 }
8527 return false;
8528 case EXCP_BKPT:
8529 /* See if this is a semihosting syscall. */
8530 if (env->thumb) {
8531 imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env))
8532 & 0xff;
8533 if (imm == 0xab) {
8534 env->regs[15] += 2;
8535 break;
8536 }
8537 }
8538 return false;
8539 default:
8540 return false;
8541 }
8542
8543 qemu_log_mask(CPU_LOG_INT,
8544 "...handling as semihosting call 0x%x\n",
8545 env->regs[0]);
8546 env->regs[0] = do_arm_semihosting(env);
8547 return true;
8548 }
8549 }
8550
8551 /* Handle a CPU exception for A and R profile CPUs.
8552 * Do any appropriate logging, handle PSCI calls, and then hand off
8553 * to the AArch64-entry or AArch32-entry function depending on the
8554 * target exception level's register width.
8555 */
8556 void arm_cpu_do_interrupt(CPUState *cs)
8557 {
8558 ARMCPU *cpu = ARM_CPU(cs);
8559 CPUARMState *env = &cpu->env;
8560 unsigned int new_el = env->exception.target_el;
8561
8562 assert(!arm_feature(env, ARM_FEATURE_M));
8563
8564 arm_log_exception(cs->exception_index);
8565 qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
8566 new_el);
8567 if (qemu_loglevel_mask(CPU_LOG_INT)
8568 && !excp_is_internal(cs->exception_index)) {
8569 qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n",
8570 env->exception.syndrome >> ARM_EL_EC_SHIFT,
8571 env->exception.syndrome);
8572 }
8573
8574 if (arm_is_psci_call(cpu, cs->exception_index)) {
8575 arm_handle_psci_call(cpu);
8576 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
8577 return;
8578 }
8579
8580 /* Semihosting semantics depend on the register width of the
8581 * code that caused the exception, not the target exception level,
8582 * so must be handled here.
8583 */
8584 if (check_for_semihosting(cs)) {
8585 return;
8586 }
8587
8588 /* Hooks may change global state so BQL should be held, also the
8589 * BQL needs to be held for any modification of
8590 * cs->interrupt_request.
8591 */
8592 g_assert(qemu_mutex_iothread_locked());
8593
8594 arm_call_pre_el_change_hook(cpu);
8595
8596 assert(!excp_is_internal(cs->exception_index));
8597 if (arm_el_is_aa64(env, new_el)) {
8598 arm_cpu_do_interrupt_aarch64(cs);
8599 } else {
8600 arm_cpu_do_interrupt_aarch32(cs);
8601 }
8602
8603 arm_call_el_change_hook(cpu);
8604
8605 if (!kvm_enabled()) {
8606 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
8607 }
8608 }
8609
8610 /* Return the exception level which controls this address translation regime */
8611 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
8612 {
8613 switch (mmu_idx) {
8614 case ARMMMUIdx_S2NS:
8615 case ARMMMUIdx_S1E2:
8616 return 2;
8617 case ARMMMUIdx_S1E3:
8618 return 3;
8619 case ARMMMUIdx_S1SE0:
8620 return arm_el_is_aa64(env, 3) ? 1 : 3;
8621 case ARMMMUIdx_S1SE1:
8622 case ARMMMUIdx_S1NSE0:
8623 case ARMMMUIdx_S1NSE1:
8624 case ARMMMUIdx_MPrivNegPri:
8625 case ARMMMUIdx_MUserNegPri:
8626 case ARMMMUIdx_MPriv:
8627 case ARMMMUIdx_MUser:
8628 case ARMMMUIdx_MSPrivNegPri:
8629 case ARMMMUIdx_MSUserNegPri:
8630 case ARMMMUIdx_MSPriv:
8631 case ARMMMUIdx_MSUser:
8632 return 1;
8633 default:
8634 g_assert_not_reached();
8635 }
8636 }
8637
8638 /* Return the SCTLR value which controls this address translation regime */
8639 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
8640 {
8641 return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
8642 }
8643
8644 /* Return true if the specified stage of address translation is disabled */
8645 static inline bool regime_translation_disabled(CPUARMState *env,
8646 ARMMMUIdx mmu_idx)
8647 {
8648 if (arm_feature(env, ARM_FEATURE_M)) {
8649 switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
8650 (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
8651 case R_V7M_MPU_CTRL_ENABLE_MASK:
8652 /* Enabled, but not for HardFault and NMI */
8653 return mmu_idx & ARM_MMU_IDX_M_NEGPRI;
8654 case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK:
8655 /* Enabled for all cases */
8656 return false;
8657 case 0:
8658 default:
8659 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
8660 * we warned about that in armv7m_nvic.c when the guest set it.
8661 */
8662 return true;
8663 }
8664 }
8665
8666 if (mmu_idx == ARMMMUIdx_S2NS) {
8667 return (env->cp15.hcr_el2 & HCR_VM) == 0;
8668 }
8669
8670 if (env->cp15.hcr_el2 & HCR_TGE) {
8671 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
8672 if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) {
8673 return true;
8674 }
8675 }
8676
8677 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
8678 }
8679
8680 static inline bool regime_translation_big_endian(CPUARMState *env,
8681 ARMMMUIdx mmu_idx)
8682 {
8683 return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
8684 }
8685
8686 /* Return the TCR controlling this translation regime */
8687 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
8688 {
8689 if (mmu_idx == ARMMMUIdx_S2NS) {
8690 return &env->cp15.vtcr_el2;
8691 }
8692 return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
8693 }
8694
8695 /* Convert a possible stage1+2 MMU index into the appropriate
8696 * stage 1 MMU index
8697 */
8698 static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
8699 {
8700 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
8701 mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0);
8702 }
8703 return mmu_idx;
8704 }
8705
8706 /* Returns TBI0 value for current regime el */
8707 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
8708 {
8709 TCR *tcr;
8710 uint32_t el;
8711
8712 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
8713 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
8714 */
8715 mmu_idx = stage_1_mmu_idx(mmu_idx);
8716
8717 tcr = regime_tcr(env, mmu_idx);
8718 el = regime_el(env, mmu_idx);
8719
8720 if (el > 1) {
8721 return extract64(tcr->raw_tcr, 20, 1);
8722 } else {
8723 return extract64(tcr->raw_tcr, 37, 1);
8724 }
8725 }
8726
8727 /* Returns TBI1 value for current regime el */
8728 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
8729 {
8730 TCR *tcr;
8731 uint32_t el;
8732
8733 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
8734 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
8735 */
8736 mmu_idx = stage_1_mmu_idx(mmu_idx);
8737
8738 tcr = regime_tcr(env, mmu_idx);
8739 el = regime_el(env, mmu_idx);
8740
8741 if (el > 1) {
8742 return 0;
8743 } else {
8744 return extract64(tcr->raw_tcr, 38, 1);
8745 }
8746 }
8747
8748 /* Return the TTBR associated with this translation regime */
8749 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
8750 int ttbrn)
8751 {
8752 if (mmu_idx == ARMMMUIdx_S2NS) {
8753 return env->cp15.vttbr_el2;
8754 }
8755 if (ttbrn == 0) {
8756 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
8757 } else {
8758 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
8759 }
8760 }
8761
8762 /* Return true if the translation regime is using LPAE format page tables */
8763 static inline bool regime_using_lpae_format(CPUARMState *env,
8764 ARMMMUIdx mmu_idx)
8765 {
8766 int el = regime_el(env, mmu_idx);
8767 if (el == 2 || arm_el_is_aa64(env, el)) {
8768 return true;
8769 }
8770 if (arm_feature(env, ARM_FEATURE_LPAE)
8771 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
8772 return true;
8773 }
8774 return false;
8775 }
8776
8777 /* Returns true if the stage 1 translation regime is using LPAE format page
8778 * tables. Used when raising alignment exceptions, whose FSR changes depending
8779 * on whether the long or short descriptor format is in use. */
8780 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
8781 {
8782 mmu_idx = stage_1_mmu_idx(mmu_idx);
8783
8784 return regime_using_lpae_format(env, mmu_idx);
8785 }
8786
8787 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
8788 {
8789 switch (mmu_idx) {
8790 case ARMMMUIdx_S1SE0:
8791 case ARMMMUIdx_S1NSE0:
8792 case ARMMMUIdx_MUser:
8793 case ARMMMUIdx_MSUser:
8794 case ARMMMUIdx_MUserNegPri:
8795 case ARMMMUIdx_MSUserNegPri:
8796 return true;
8797 default:
8798 return false;
8799 case ARMMMUIdx_S12NSE0:
8800 case ARMMMUIdx_S12NSE1:
8801 g_assert_not_reached();
8802 }
8803 }
8804
8805 /* Translate section/page access permissions to page
8806 * R/W protection flags
8807 *
8808 * @env: CPUARMState
8809 * @mmu_idx: MMU index indicating required translation regime
8810 * @ap: The 3-bit access permissions (AP[2:0])
8811 * @domain_prot: The 2-bit domain access permissions
8812 */
8813 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
8814 int ap, int domain_prot)
8815 {
8816 bool is_user = regime_is_user(env, mmu_idx);
8817
8818 if (domain_prot == 3) {
8819 return PAGE_READ | PAGE_WRITE;
8820 }
8821
8822 switch (ap) {
8823 case 0:
8824 if (arm_feature(env, ARM_FEATURE_V7)) {
8825 return 0;
8826 }
8827 switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
8828 case SCTLR_S:
8829 return is_user ? 0 : PAGE_READ;
8830 case SCTLR_R:
8831 return PAGE_READ;
8832 default:
8833 return 0;
8834 }
8835 case 1:
8836 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
8837 case 2:
8838 if (is_user) {
8839 return PAGE_READ;
8840 } else {
8841 return PAGE_READ | PAGE_WRITE;
8842 }
8843 case 3:
8844 return PAGE_READ | PAGE_WRITE;
8845 case 4: /* Reserved. */
8846 return 0;
8847 case 5:
8848 return is_user ? 0 : PAGE_READ;
8849 case 6:
8850 return PAGE_READ;
8851 case 7:
8852 if (!arm_feature(env, ARM_FEATURE_V6K)) {
8853 return 0;
8854 }
8855 return PAGE_READ;
8856 default:
8857 g_assert_not_reached();
8858 }
8859 }
8860
8861 /* Translate section/page access permissions to page
8862 * R/W protection flags.
8863 *
8864 * @ap: The 2-bit simple AP (AP[2:1])
8865 * @is_user: TRUE if accessing from PL0
8866 */
8867 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
8868 {
8869 switch (ap) {
8870 case 0:
8871 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
8872 case 1:
8873 return PAGE_READ | PAGE_WRITE;
8874 case 2:
8875 return is_user ? 0 : PAGE_READ;
8876 case 3:
8877 return PAGE_READ;
8878 default:
8879 g_assert_not_reached();
8880 }
8881 }
8882
8883 static inline int
8884 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
8885 {
8886 return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
8887 }
8888
8889 /* Translate S2 section/page access permissions to protection flags
8890 *
8891 * @env: CPUARMState
8892 * @s2ap: The 2-bit stage2 access permissions (S2AP)
8893 * @xn: XN (execute-never) bit
8894 */
8895 static int get_S2prot(CPUARMState *env, int s2ap, int xn)
8896 {
8897 int prot = 0;
8898
8899 if (s2ap & 1) {
8900 prot |= PAGE_READ;
8901 }
8902 if (s2ap & 2) {
8903 prot |= PAGE_WRITE;
8904 }
8905 if (!xn) {
8906 if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
8907 prot |= PAGE_EXEC;
8908 }
8909 }
8910 return prot;
8911 }
8912
8913 /* Translate section/page access permissions to protection flags
8914 *
8915 * @env: CPUARMState
8916 * @mmu_idx: MMU index indicating required translation regime
8917 * @is_aa64: TRUE if AArch64
8918 * @ap: The 2-bit simple AP (AP[2:1])
8919 * @ns: NS (non-secure) bit
8920 * @xn: XN (execute-never) bit
8921 * @pxn: PXN (privileged execute-never) bit
8922 */
8923 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
8924 int ap, int ns, int xn, int pxn)
8925 {
8926 bool is_user = regime_is_user(env, mmu_idx);
8927 int prot_rw, user_rw;
8928 bool have_wxn;
8929 int wxn = 0;
8930
8931 assert(mmu_idx != ARMMMUIdx_S2NS);
8932
8933 user_rw = simple_ap_to_rw_prot_is_user(ap, true);
8934 if (is_user) {
8935 prot_rw = user_rw;
8936 } else {
8937 prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
8938 }
8939
8940 if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
8941 return prot_rw;
8942 }
8943
8944 /* TODO have_wxn should be replaced with
8945 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
8946 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
8947 * compatible processors have EL2, which is required for [U]WXN.
8948 */
8949 have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
8950
8951 if (have_wxn) {
8952 wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
8953 }
8954
8955 if (is_aa64) {
8956 switch (regime_el(env, mmu_idx)) {
8957 case 1:
8958 if (!is_user) {
8959 xn = pxn || (user_rw & PAGE_WRITE);
8960 }
8961 break;
8962 case 2:
8963 case 3:
8964 break;
8965 }
8966 } else if (arm_feature(env, ARM_FEATURE_V7)) {
8967 switch (regime_el(env, mmu_idx)) {
8968 case 1:
8969 case 3:
8970 if (is_user) {
8971 xn = xn || !(user_rw & PAGE_READ);
8972 } else {
8973 int uwxn = 0;
8974 if (have_wxn) {
8975 uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
8976 }
8977 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
8978 (uwxn && (user_rw & PAGE_WRITE));
8979 }
8980 break;
8981 case 2:
8982 break;
8983 }
8984 } else {
8985 xn = wxn = 0;
8986 }
8987
8988 if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
8989 return prot_rw;
8990 }
8991 return prot_rw | PAGE_EXEC;
8992 }
8993
8994 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
8995 uint32_t *table, uint32_t address)
8996 {
8997 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
8998 TCR *tcr = regime_tcr(env, mmu_idx);
8999
9000 if (address & tcr->mask) {
9001 if (tcr->raw_tcr & TTBCR_PD1) {
9002 /* Translation table walk disabled for TTBR1 */
9003 return false;
9004 }
9005 *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
9006 } else {
9007 if (tcr->raw_tcr & TTBCR_PD0) {
9008 /* Translation table walk disabled for TTBR0 */
9009 return false;
9010 }
9011 *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
9012 }
9013 *table |= (address >> 18) & 0x3ffc;
9014 return true;
9015 }
9016
9017 /* Translate a S1 pagetable walk through S2 if needed. */
9018 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
9019 hwaddr addr, MemTxAttrs txattrs,
9020 ARMMMUFaultInfo *fi)
9021 {
9022 if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
9023 !regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
9024 target_ulong s2size;
9025 hwaddr s2pa;
9026 int s2prot;
9027 int ret;
9028
9029 ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
9030 &txattrs, &s2prot, &s2size, fi, NULL);
9031 if (ret) {
9032 assert(fi->type != ARMFault_None);
9033 fi->s2addr = addr;
9034 fi->stage2 = true;
9035 fi->s1ptw = true;
9036 return ~0;
9037 }
9038 addr = s2pa;
9039 }
9040 return addr;
9041 }
9042
9043 /* All loads done in the course of a page table walk go through here. */
9044 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
9045 ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
9046 {
9047 ARMCPU *cpu = ARM_CPU(cs);
9048 CPUARMState *env = &cpu->env;
9049 MemTxAttrs attrs = {};
9050 MemTxResult result = MEMTX_OK;
9051 AddressSpace *as;
9052 uint32_t data;
9053
9054 attrs.secure = is_secure;
9055 as = arm_addressspace(cs, attrs);
9056 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
9057 if (fi->s1ptw) {
9058 return 0;
9059 }
9060 if (regime_translation_big_endian(env, mmu_idx)) {
9061 data = address_space_ldl_be(as, addr, attrs, &result);
9062 } else {
9063 data = address_space_ldl_le(as, addr, attrs, &result);
9064 }
9065 if (result == MEMTX_OK) {
9066 return data;
9067 }
9068 fi->type = ARMFault_SyncExternalOnWalk;
9069 fi->ea = arm_extabort_type(result);
9070 return 0;
9071 }
9072
9073 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
9074 ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
9075 {
9076 ARMCPU *cpu = ARM_CPU(cs);
9077 CPUARMState *env = &cpu->env;
9078 MemTxAttrs attrs = {};
9079 MemTxResult result = MEMTX_OK;
9080 AddressSpace *as;
9081 uint64_t data;
9082
9083 attrs.secure = is_secure;
9084 as = arm_addressspace(cs, attrs);
9085 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
9086 if (fi->s1ptw) {
9087 return 0;
9088 }
9089 if (regime_translation_big_endian(env, mmu_idx)) {
9090 data = address_space_ldq_be(as, addr, attrs, &result);
9091 } else {
9092 data = address_space_ldq_le(as, addr, attrs, &result);
9093 }
9094 if (result == MEMTX_OK) {
9095 return data;
9096 }
9097 fi->type = ARMFault_SyncExternalOnWalk;
9098 fi->ea = arm_extabort_type(result);
9099 return 0;
9100 }
9101
9102 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
9103 MMUAccessType access_type, ARMMMUIdx mmu_idx,
9104 hwaddr *phys_ptr, int *prot,
9105 target_ulong *page_size,
9106 ARMMMUFaultInfo *fi)
9107 {
9108 CPUState *cs = CPU(arm_env_get_cpu(env));
9109 int level = 1;
9110 uint32_t table;
9111 uint32_t desc;
9112 int type;
9113 int ap;
9114 int domain = 0;
9115 int domain_prot;
9116 hwaddr phys_addr;
9117 uint32_t dacr;
9118
9119 /* Pagetable walk. */
9120 /* Lookup l1 descriptor. */
9121 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
9122 /* Section translation fault if page walk is disabled by PD0 or PD1 */
9123 fi->type = ARMFault_Translation;
9124 goto do_fault;
9125 }
9126 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
9127 mmu_idx, fi);
9128 if (fi->type != ARMFault_None) {
9129 goto do_fault;
9130 }
9131 type = (desc & 3);
9132 domain = (desc >> 5) & 0x0f;
9133 if (regime_el(env, mmu_idx) == 1) {
9134 dacr = env->cp15.dacr_ns;
9135 } else {
9136 dacr = env->cp15.dacr_s;
9137 }
9138 domain_prot = (dacr >> (domain * 2)) & 3;
9139 if (type == 0) {
9140 /* Section translation fault. */
9141 fi->type = ARMFault_Translation;
9142 goto do_fault;
9143 }
9144 if (type != 2) {
9145 level = 2;
9146 }
9147 if (domain_prot == 0 || domain_prot == 2) {
9148 fi->type = ARMFault_Domain;
9149 goto do_fault;
9150 }
9151 if (type == 2) {
9152 /* 1Mb section. */
9153 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
9154 ap = (desc >> 10) & 3;
9155 *page_size = 1024 * 1024;
9156 } else {
9157 /* Lookup l2 entry. */
9158 if (type == 1) {
9159 /* Coarse pagetable. */
9160 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
9161 } else {
9162 /* Fine pagetable. */
9163 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
9164 }
9165 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
9166 mmu_idx, fi);
9167 if (fi->type != ARMFault_None) {
9168 goto do_fault;
9169 }
9170 switch (desc & 3) {
9171 case 0: /* Page translation fault. */
9172 fi->type = ARMFault_Translation;
9173 goto do_fault;
9174 case 1: /* 64k page. */
9175 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
9176 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
9177 *page_size = 0x10000;
9178 break;
9179 case 2: /* 4k page. */
9180 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
9181 ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
9182 *page_size = 0x1000;
9183 break;
9184 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
9185 if (type == 1) {
9186 /* ARMv6/XScale extended small page format */
9187 if (arm_feature(env, ARM_FEATURE_XSCALE)
9188 || arm_feature(env, ARM_FEATURE_V6)) {
9189 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
9190 *page_size = 0x1000;
9191 } else {
9192 /* UNPREDICTABLE in ARMv5; we choose to take a
9193 * page translation fault.
9194 */
9195 fi->type = ARMFault_Translation;
9196 goto do_fault;
9197 }
9198 } else {
9199 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
9200 *page_size = 0x400;
9201 }
9202 ap = (desc >> 4) & 3;
9203 break;
9204 default:
9205 /* Never happens, but compiler isn't smart enough to tell. */
9206 abort();
9207 }
9208 }
9209 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
9210 *prot |= *prot ? PAGE_EXEC : 0;
9211 if (!(*prot & (1 << access_type))) {
9212 /* Access permission fault. */
9213 fi->type = ARMFault_Permission;
9214 goto do_fault;
9215 }
9216 *phys_ptr = phys_addr;
9217 return false;
9218 do_fault:
9219 fi->domain = domain;
9220 fi->level = level;
9221 return true;
9222 }
9223
9224 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
9225 MMUAccessType access_type, ARMMMUIdx mmu_idx,
9226 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
9227 target_ulong *page_size, ARMMMUFaultInfo *fi)
9228 {
9229 CPUState *cs = CPU(arm_env_get_cpu(env));
9230 int level = 1;
9231 uint32_t table;
9232 uint32_t desc;
9233 uint32_t xn;
9234 uint32_t pxn = 0;
9235 int type;
9236 int ap;
9237 int domain = 0;
9238 int domain_prot;
9239 hwaddr phys_addr;
9240 uint32_t dacr;
9241 bool ns;
9242
9243 /* Pagetable walk. */
9244 /* Lookup l1 descriptor. */
9245 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
9246 /* Section translation fault if page walk is disabled by PD0 or PD1 */
9247 fi->type = ARMFault_Translation;
9248 goto do_fault;
9249 }
9250 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
9251 mmu_idx, fi);
9252 if (fi->type != ARMFault_None) {
9253 goto do_fault;
9254 }
9255 type = (desc & 3);
9256 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
9257 /* Section translation fault, or attempt to use the encoding
9258 * which is Reserved on implementations without PXN.
9259 */
9260 fi->type = ARMFault_Translation;
9261 goto do_fault;
9262 }
9263 if ((type == 1) || !(desc & (1 << 18))) {
9264 /* Page or Section. */
9265 domain = (desc >> 5) & 0x0f;
9266 }
9267 if (regime_el(env, mmu_idx) == 1) {
9268 dacr = env->cp15.dacr_ns;
9269 } else {
9270 dacr = env->cp15.dacr_s;
9271 }
9272 if (type == 1) {
9273 level = 2;
9274 }
9275 domain_prot = (dacr >> (domain * 2)) & 3;
9276 if (domain_prot == 0 || domain_prot == 2) {
9277 /* Section or Page domain fault */
9278 fi->type = ARMFault_Domain;
9279 goto do_fault;
9280 }
9281 if (type != 1) {
9282 if (desc & (1 << 18)) {
9283 /* Supersection. */
9284 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
9285 phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
9286 phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
9287 *page_size = 0x1000000;
9288 } else {
9289 /* Section. */
9290 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
9291 *page_size = 0x100000;
9292 }
9293 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
9294 xn = desc & (1 << 4);
9295 pxn = desc & 1;
9296 ns = extract32(desc, 19, 1);
9297 } else {
9298 if (arm_feature(env, ARM_FEATURE_PXN)) {
9299 pxn = (desc >> 2) & 1;
9300 }
9301 ns = extract32(desc, 3, 1);
9302 /* Lookup l2 entry. */
9303 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
9304 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
9305 mmu_idx, fi);
9306 if (fi->type != ARMFault_None) {
9307 goto do_fault;
9308 }
9309 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
9310 switch (desc & 3) {
9311 case 0: /* Page translation fault. */
9312 fi->type = ARMFault_Translation;
9313 goto do_fault;
9314 case 1: /* 64k page. */
9315 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
9316 xn = desc & (1 << 15);
9317 *page_size = 0x10000;
9318 break;
9319 case 2: case 3: /* 4k page. */
9320 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
9321 xn = desc & 1;
9322 *page_size = 0x1000;
9323 break;
9324 default:
9325 /* Never happens, but compiler isn't smart enough to tell. */
9326 abort();
9327 }
9328 }
9329 if (domain_prot == 3) {
9330 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
9331 } else {
9332 if (pxn && !regime_is_user(env, mmu_idx)) {
9333 xn = 1;
9334 }
9335 if (xn && access_type == MMU_INST_FETCH) {
9336 fi->type = ARMFault_Permission;
9337 goto do_fault;
9338 }
9339
9340 if (arm_feature(env, ARM_FEATURE_V6K) &&
9341 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
9342 /* The simplified model uses AP[0] as an access control bit. */
9343 if ((ap & 1) == 0) {
9344 /* Access flag fault. */
9345 fi->type = ARMFault_AccessFlag;
9346 goto do_fault;
9347 }
9348 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
9349 } else {
9350 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
9351 }
9352 if (*prot && !xn) {
9353 *prot |= PAGE_EXEC;
9354 }
9355 if (!(*prot & (1 << access_type))) {
9356 /* Access permission fault. */
9357 fi->type = ARMFault_Permission;
9358 goto do_fault;
9359 }
9360 }
9361 if (ns) {
9362 /* The NS bit will (as required by the architecture) have no effect if
9363 * the CPU doesn't support TZ or this is a non-secure translation
9364 * regime, because the attribute will already be non-secure.
9365 */
9366 attrs->secure = false;
9367 }
9368 *phys_ptr = phys_addr;
9369 return false;
9370 do_fault:
9371 fi->domain = domain;
9372 fi->level = level;
9373 return true;
9374 }
9375
9376 /*
9377 * check_s2_mmu_setup
9378 * @cpu: ARMCPU
9379 * @is_aa64: True if the translation regime is in AArch64 state
9380 * @startlevel: Suggested starting level
9381 * @inputsize: Bitsize of IPAs
9382 * @stride: Page-table stride (See the ARM ARM)
9383 *
9384 * Returns true if the suggested S2 translation parameters are OK and
9385 * false otherwise.
9386 */
9387 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
9388 int inputsize, int stride)
9389 {
9390 const int grainsize = stride + 3;
9391 int startsizecheck;
9392
9393 /* Negative levels are never allowed. */
9394 if (level < 0) {
9395 return false;
9396 }
9397
9398 startsizecheck = inputsize - ((3 - level) * stride + grainsize);
9399 if (startsizecheck < 1 || startsizecheck > stride + 4) {
9400 return false;
9401 }
9402
9403 if (is_aa64) {
9404 CPUARMState *env = &cpu->env;
9405 unsigned int pamax = arm_pamax(cpu);
9406
9407 switch (stride) {
9408 case 13: /* 64KB Pages. */
9409 if (level == 0 || (level == 1 && pamax <= 42)) {
9410 return false;
9411 }
9412 break;
9413 case 11: /* 16KB Pages. */
9414 if (level == 0 || (level == 1 && pamax <= 40)) {
9415 return false;
9416 }
9417 break;
9418 case 9: /* 4KB Pages. */
9419 if (level == 0 && pamax <= 42) {
9420 return false;
9421 }
9422 break;
9423 default:
9424 g_assert_not_reached();
9425 }
9426
9427 /* Inputsize checks. */
9428 if (inputsize > pamax &&
9429 (arm_el_is_aa64(env, 1) || inputsize > 40)) {
9430 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
9431 return false;
9432 }
9433 } else {
9434 /* AArch32 only supports 4KB pages. Assert on that. */
9435 assert(stride == 9);
9436
9437 if (level == 0) {
9438 return false;
9439 }
9440 }
9441 return true;
9442 }
9443
9444 /* Translate from the 4-bit stage 2 representation of
9445 * memory attributes (without cache-allocation hints) to
9446 * the 8-bit representation of the stage 1 MAIR registers
9447 * (which includes allocation hints).
9448 *
9449 * ref: shared/translation/attrs/S2AttrDecode()
9450 * .../S2ConvertAttrsHints()
9451 */
9452 static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
9453 {
9454 uint8_t hiattr = extract32(s2attrs, 2, 2);
9455 uint8_t loattr = extract32(s2attrs, 0, 2);
9456 uint8_t hihint = 0, lohint = 0;
9457
9458 if (hiattr != 0) { /* normal memory */
9459 if ((env->cp15.hcr_el2 & HCR_CD) != 0) { /* cache disabled */
9460 hiattr = loattr = 1; /* non-cacheable */
9461 } else {
9462 if (hiattr != 1) { /* Write-through or write-back */
9463 hihint = 3; /* RW allocate */
9464 }
9465 if (loattr != 1) { /* Write-through or write-back */
9466 lohint = 3; /* RW allocate */
9467 }
9468 }
9469 }
9470
9471 return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
9472 }
9473
9474 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
9475 MMUAccessType access_type, ARMMMUIdx mmu_idx,
9476 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
9477 target_ulong *page_size_ptr,
9478 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
9479 {
9480 ARMCPU *cpu = arm_env_get_cpu(env);
9481 CPUState *cs = CPU(cpu);
9482 /* Read an LPAE long-descriptor translation table. */
9483 ARMFaultType fault_type = ARMFault_Translation;
9484 uint32_t level;
9485 uint32_t epd = 0;
9486 int32_t t0sz, t1sz;
9487 uint32_t tg;
9488 uint64_t ttbr;
9489 int ttbr_select;
9490 hwaddr descaddr, indexmask, indexmask_grainsize;
9491 uint32_t tableattrs;
9492 target_ulong page_size;
9493 uint32_t attrs;
9494 int32_t stride = 9;
9495 int32_t addrsize;
9496 int inputsize;
9497 int32_t tbi = 0;
9498 TCR *tcr = regime_tcr(env, mmu_idx);
9499 int ap, ns, xn, pxn;
9500 uint32_t el = regime_el(env, mmu_idx);
9501 bool ttbr1_valid = true;
9502 uint64_t descaddrmask;
9503 bool aarch64 = arm_el_is_aa64(env, el);
9504
9505 /* TODO:
9506 * This code does not handle the different format TCR for VTCR_EL2.
9507 * This code also does not support shareability levels.
9508 * Attribute and permission bit handling should also be checked when adding
9509 * support for those page table walks.
9510 */
9511 if (aarch64) {
9512 level = 0;
9513 addrsize = 64;
9514 if (el > 1) {
9515 if (mmu_idx != ARMMMUIdx_S2NS) {
9516 tbi = extract64(tcr->raw_tcr, 20, 1);
9517 }
9518 } else {
9519 if (extract64(address, 55, 1)) {
9520 tbi = extract64(tcr->raw_tcr, 38, 1);
9521 } else {
9522 tbi = extract64(tcr->raw_tcr, 37, 1);
9523 }
9524 }
9525 tbi *= 8;
9526
9527 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
9528 * invalid.
9529 */
9530 if (el > 1) {
9531 ttbr1_valid = false;
9532 }
9533 } else {
9534 level = 1;
9535 addrsize = 32;
9536 /* There is no TTBR1 for EL2 */
9537 if (el == 2) {
9538 ttbr1_valid = false;
9539 }
9540 }
9541
9542 /* Determine whether this address is in the region controlled by
9543 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
9544 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
9545 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
9546 */
9547 if (aarch64) {
9548 /* AArch64 translation. */
9549 t0sz = extract32(tcr->raw_tcr, 0, 6);
9550 t0sz = MIN(t0sz, 39);
9551 t0sz = MAX(t0sz, 16);
9552 } else if (mmu_idx != ARMMMUIdx_S2NS) {
9553 /* AArch32 stage 1 translation. */
9554 t0sz = extract32(tcr->raw_tcr, 0, 3);
9555 } else {
9556 /* AArch32 stage 2 translation. */
9557 bool sext = extract32(tcr->raw_tcr, 4, 1);
9558 bool sign = extract32(tcr->raw_tcr, 3, 1);
9559 /* Address size is 40-bit for a stage 2 translation,
9560 * and t0sz can be negative (from -8 to 7),
9561 * so we need to adjust it to use the TTBR selecting logic below.
9562 */
9563 addrsize = 40;
9564 t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8;
9565
9566 /* If the sign-extend bit is not the same as t0sz[3], the result
9567 * is unpredictable. Flag this as a guest error. */
9568 if (sign != sext) {
9569 qemu_log_mask(LOG_GUEST_ERROR,
9570 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
9571 }
9572 }
9573 t1sz = extract32(tcr->raw_tcr, 16, 6);
9574 if (aarch64) {
9575 t1sz = MIN(t1sz, 39);
9576 t1sz = MAX(t1sz, 16);
9577 }
9578 if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) {
9579 /* there is a ttbr0 region and we are in it (high bits all zero) */
9580 ttbr_select = 0;
9581 } else if (ttbr1_valid && t1sz &&
9582 !extract64(~address, addrsize - t1sz, t1sz - tbi)) {
9583 /* there is a ttbr1 region and we are in it (high bits all one) */
9584 ttbr_select = 1;
9585 } else if (!t0sz) {
9586 /* ttbr0 region is "everything not in the ttbr1 region" */
9587 ttbr_select = 0;
9588 } else if (!t1sz && ttbr1_valid) {
9589 /* ttbr1 region is "everything not in the ttbr0 region" */
9590 ttbr_select = 1;
9591 } else {
9592 /* in the gap between the two regions, this is a Translation fault */
9593 fault_type = ARMFault_Translation;
9594 goto do_fault;
9595 }
9596
9597 /* Note that QEMU ignores shareability and cacheability attributes,
9598 * so we don't need to do anything with the SH, ORGN, IRGN fields
9599 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
9600 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
9601 * implement any ASID-like capability so we can ignore it (instead
9602 * we will always flush the TLB any time the ASID is changed).
9603 */
9604 if (ttbr_select == 0) {
9605 ttbr = regime_ttbr(env, mmu_idx, 0);
9606 if (el < 2) {
9607 epd = extract32(tcr->raw_tcr, 7, 1);
9608 }
9609 inputsize = addrsize - t0sz;
9610
9611 tg = extract32(tcr->raw_tcr, 14, 2);
9612 if (tg == 1) { /* 64KB pages */
9613 stride = 13;
9614 }
9615 if (tg == 2) { /* 16KB pages */
9616 stride = 11;
9617 }
9618 } else {
9619 /* We should only be here if TTBR1 is valid */
9620 assert(ttbr1_valid);
9621
9622 ttbr = regime_ttbr(env, mmu_idx, 1);
9623 epd = extract32(tcr->raw_tcr, 23, 1);
9624 inputsize = addrsize - t1sz;
9625
9626 tg = extract32(tcr->raw_tcr, 30, 2);
9627 if (tg == 3) { /* 64KB pages */
9628 stride = 13;
9629 }
9630 if (tg == 1) { /* 16KB pages */
9631 stride = 11;
9632 }
9633 }
9634
9635 /* Here we should have set up all the parameters for the translation:
9636 * inputsize, ttbr, epd, stride, tbi
9637 */
9638
9639 if (epd) {
9640 /* Translation table walk disabled => Translation fault on TLB miss
9641 * Note: This is always 0 on 64-bit EL2 and EL3.
9642 */
9643 goto do_fault;
9644 }
9645
9646 if (mmu_idx != ARMMMUIdx_S2NS) {
9647 /* The starting level depends on the virtual address size (which can
9648 * be up to 48 bits) and the translation granule size. It indicates
9649 * the number of strides (stride bits at a time) needed to
9650 * consume the bits of the input address. In the pseudocode this is:
9651 * level = 4 - RoundUp((inputsize - grainsize) / stride)
9652 * where their 'inputsize' is our 'inputsize', 'grainsize' is
9653 * our 'stride + 3' and 'stride' is our 'stride'.
9654 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
9655 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
9656 * = 4 - (inputsize - 4) / stride;
9657 */
9658 level = 4 - (inputsize - 4) / stride;
9659 } else {
9660 /* For stage 2 translations the starting level is specified by the
9661 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
9662 */
9663 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
9664 uint32_t startlevel;
9665 bool ok;
9666
9667 if (!aarch64 || stride == 9) {
9668 /* AArch32 or 4KB pages */
9669 startlevel = 2 - sl0;
9670 } else {
9671 /* 16KB or 64KB pages */
9672 startlevel = 3 - sl0;
9673 }
9674
9675 /* Check that the starting level is valid. */
9676 ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
9677 inputsize, stride);
9678 if (!ok) {
9679 fault_type = ARMFault_Translation;
9680 goto do_fault;
9681 }
9682 level = startlevel;
9683 }
9684
9685 indexmask_grainsize = (1ULL << (stride + 3)) - 1;
9686 indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
9687
9688 /* Now we can extract the actual base address from the TTBR */
9689 descaddr = extract64(ttbr, 0, 48);
9690 descaddr &= ~indexmask;
9691
9692 /* The address field in the descriptor goes up to bit 39 for ARMv7
9693 * but up to bit 47 for ARMv8, but we use the descaddrmask
9694 * up to bit 39 for AArch32, because we don't need other bits in that case
9695 * to construct next descriptor address (anyway they should be all zeroes).
9696 */
9697 descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) &
9698 ~indexmask_grainsize;
9699
9700 /* Secure accesses start with the page table in secure memory and
9701 * can be downgraded to non-secure at any step. Non-secure accesses
9702 * remain non-secure. We implement this by just ORing in the NSTable/NS
9703 * bits at each step.
9704 */
9705 tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
9706 for (;;) {
9707 uint64_t descriptor;
9708 bool nstable;
9709
9710 descaddr |= (address >> (stride * (4 - level))) & indexmask;
9711 descaddr &= ~7ULL;
9712 nstable = extract32(tableattrs, 4, 1);
9713 descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi);
9714 if (fi->type != ARMFault_None) {
9715 goto do_fault;
9716 }
9717
9718 if (!(descriptor & 1) ||
9719 (!(descriptor & 2) && (level == 3))) {
9720 /* Invalid, or the Reserved level 3 encoding */
9721 goto do_fault;
9722 }
9723 descaddr = descriptor & descaddrmask;
9724
9725 if ((descriptor & 2) && (level < 3)) {
9726 /* Table entry. The top five bits are attributes which may
9727 * propagate down through lower levels of the table (and
9728 * which are all arranged so that 0 means "no effect", so
9729 * we can gather them up by ORing in the bits at each level).
9730 */
9731 tableattrs |= extract64(descriptor, 59, 5);
9732 level++;
9733 indexmask = indexmask_grainsize;
9734 continue;
9735 }
9736 /* Block entry at level 1 or 2, or page entry at level 3.
9737 * These are basically the same thing, although the number
9738 * of bits we pull in from the vaddr varies.
9739 */
9740 page_size = (1ULL << ((stride * (4 - level)) + 3));
9741 descaddr |= (address & (page_size - 1));
9742 /* Extract attributes from the descriptor */
9743 attrs = extract64(descriptor, 2, 10)
9744 | (extract64(descriptor, 52, 12) << 10);
9745
9746 if (mmu_idx == ARMMMUIdx_S2NS) {
9747 /* Stage 2 table descriptors do not include any attribute fields */
9748 break;
9749 }
9750 /* Merge in attributes from table descriptors */
9751 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
9752 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
9753 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
9754 * means "force PL1 access only", which means forcing AP[1] to 0.
9755 */
9756 if (extract32(tableattrs, 2, 1)) {
9757 attrs &= ~(1 << 4);
9758 }
9759 attrs |= nstable << 3; /* NS */
9760 break;
9761 }
9762 /* Here descaddr is the final physical address, and attributes
9763 * are all in attrs.
9764 */
9765 fault_type = ARMFault_AccessFlag;
9766 if ((attrs & (1 << 8)) == 0) {
9767 /* Access flag */
9768 goto do_fault;
9769 }
9770
9771 ap = extract32(attrs, 4, 2);
9772 xn = extract32(attrs, 12, 1);
9773
9774 if (mmu_idx == ARMMMUIdx_S2NS) {
9775 ns = true;
9776 *prot = get_S2prot(env, ap, xn);
9777 } else {
9778 ns = extract32(attrs, 3, 1);
9779 pxn = extract32(attrs, 11, 1);
9780 *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
9781 }
9782
9783 fault_type = ARMFault_Permission;
9784 if (!(*prot & (1 << access_type))) {
9785 goto do_fault;
9786 }
9787
9788 if (ns) {
9789 /* The NS bit will (as required by the architecture) have no effect if
9790 * the CPU doesn't support TZ or this is a non-secure translation
9791 * regime, because the attribute will already be non-secure.
9792 */
9793 txattrs->secure = false;
9794 }
9795
9796 if (cacheattrs != NULL) {
9797 if (mmu_idx == ARMMMUIdx_S2NS) {
9798 cacheattrs->attrs = convert_stage2_attrs(env,
9799 extract32(attrs, 0, 4));
9800 } else {
9801 /* Index into MAIR registers for cache attributes */
9802 uint8_t attrindx = extract32(attrs, 0, 3);
9803 uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
9804 assert(attrindx <= 7);
9805 cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
9806 }
9807 cacheattrs->shareability = extract32(attrs, 6, 2);
9808 }
9809
9810 *phys_ptr = descaddr;
9811 *page_size_ptr = page_size;
9812 return false;
9813
9814 do_fault:
9815 fi->type = fault_type;
9816 fi->level = level;
9817 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
9818 fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS);
9819 return true;
9820 }
9821
9822 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
9823 ARMMMUIdx mmu_idx,
9824 int32_t address, int *prot)
9825 {
9826 if (!arm_feature(env, ARM_FEATURE_M)) {
9827 *prot = PAGE_READ | PAGE_WRITE;
9828 switch (address) {
9829 case 0xF0000000 ... 0xFFFFFFFF:
9830 if (regime_sctlr(env, mmu_idx) & SCTLR_V) {
9831 /* hivecs execing is ok */
9832 *prot |= PAGE_EXEC;
9833 }
9834 break;
9835 case 0x00000000 ... 0x7FFFFFFF:
9836 *prot |= PAGE_EXEC;
9837 break;
9838 }
9839 } else {
9840 /* Default system address map for M profile cores.
9841 * The architecture specifies which regions are execute-never;
9842 * at the MPU level no other checks are defined.
9843 */
9844 switch (address) {
9845 case 0x00000000 ... 0x1fffffff: /* ROM */
9846 case 0x20000000 ... 0x3fffffff: /* SRAM */
9847 case 0x60000000 ... 0x7fffffff: /* RAM */
9848 case 0x80000000 ... 0x9fffffff: /* RAM */
9849 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
9850 break;
9851 case 0x40000000 ... 0x5fffffff: /* Peripheral */
9852 case 0xa0000000 ... 0xbfffffff: /* Device */
9853 case 0xc0000000 ... 0xdfffffff: /* Device */
9854 case 0xe0000000 ... 0xffffffff: /* System */
9855 *prot = PAGE_READ | PAGE_WRITE;
9856 break;
9857 default:
9858 g_assert_not_reached();
9859 }
9860 }
9861 }
9862
9863 static bool pmsav7_use_background_region(ARMCPU *cpu,
9864 ARMMMUIdx mmu_idx, bool is_user)
9865 {
9866 /* Return true if we should use the default memory map as a
9867 * "background" region if there are no hits against any MPU regions.
9868 */
9869 CPUARMState *env = &cpu->env;
9870
9871 if (is_user) {
9872 return false;
9873 }
9874
9875 if (arm_feature(env, ARM_FEATURE_M)) {
9876 return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
9877 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
9878 } else {
9879 return regime_sctlr(env, mmu_idx) & SCTLR_BR;
9880 }
9881 }
9882
9883 static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address)
9884 {
9885 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
9886 return arm_feature(env, ARM_FEATURE_M) &&
9887 extract32(address, 20, 12) == 0xe00;
9888 }
9889
9890 static inline bool m_is_system_region(CPUARMState *env, uint32_t address)
9891 {
9892 /* True if address is in the M profile system region
9893 * 0xe0000000 - 0xffffffff
9894 */
9895 return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7;
9896 }
9897
9898 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
9899 MMUAccessType access_type, ARMMMUIdx mmu_idx,
9900 hwaddr *phys_ptr, int *prot,
9901 target_ulong *page_size,
9902 ARMMMUFaultInfo *fi)
9903 {
9904 ARMCPU *cpu = arm_env_get_cpu(env);
9905 int n;
9906 bool is_user = regime_is_user(env, mmu_idx);
9907
9908 *phys_ptr = address;
9909 *page_size = TARGET_PAGE_SIZE;
9910 *prot = 0;
9911
9912 if (regime_translation_disabled(env, mmu_idx) ||
9913 m_is_ppb_region(env, address)) {
9914 /* MPU disabled or M profile PPB access: use default memory map.
9915 * The other case which uses the default memory map in the
9916 * v7M ARM ARM pseudocode is exception vector reads from the vector
9917 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
9918 * which always does a direct read using address_space_ldl(), rather
9919 * than going via this function, so we don't need to check that here.
9920 */
9921 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
9922 } else { /* MPU enabled */
9923 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
9924 /* region search */
9925 uint32_t base = env->pmsav7.drbar[n];
9926 uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
9927 uint32_t rmask;
9928 bool srdis = false;
9929
9930 if (!(env->pmsav7.drsr[n] & 0x1)) {
9931 continue;
9932 }
9933
9934 if (!rsize) {
9935 qemu_log_mask(LOG_GUEST_ERROR,
9936 "DRSR[%d]: Rsize field cannot be 0\n", n);
9937 continue;
9938 }
9939 rsize++;
9940 rmask = (1ull << rsize) - 1;
9941
9942 if (base & rmask) {
9943 qemu_log_mask(LOG_GUEST_ERROR,
9944 "DRBAR[%d]: 0x%" PRIx32 " misaligned "
9945 "to DRSR region size, mask = 0x%" PRIx32 "\n",
9946 n, base, rmask);
9947 continue;
9948 }
9949
9950 if (address < base || address > base + rmask) {
9951 /*
9952 * Address not in this region. We must check whether the
9953 * region covers addresses in the same page as our address.
9954 * In that case we must not report a size that covers the
9955 * whole page for a subsequent hit against a different MPU
9956 * region or the background region, because it would result in
9957 * incorrect TLB hits for subsequent accesses to addresses that
9958 * are in this MPU region.
9959 */
9960 if (ranges_overlap(base, rmask,
9961 address & TARGET_PAGE_MASK,
9962 TARGET_PAGE_SIZE)) {
9963 *page_size = 1;
9964 }
9965 continue;
9966 }
9967
9968 /* Region matched */
9969
9970 if (rsize >= 8) { /* no subregions for regions < 256 bytes */
9971 int i, snd;
9972 uint32_t srdis_mask;
9973
9974 rsize -= 3; /* sub region size (power of 2) */
9975 snd = ((address - base) >> rsize) & 0x7;
9976 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
9977
9978 srdis_mask = srdis ? 0x3 : 0x0;
9979 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
9980 /* This will check in groups of 2, 4 and then 8, whether
9981 * the subregion bits are consistent. rsize is incremented
9982 * back up to give the region size, considering consistent
9983 * adjacent subregions as one region. Stop testing if rsize
9984 * is already big enough for an entire QEMU page.
9985 */
9986 int snd_rounded = snd & ~(i - 1);
9987 uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
9988 snd_rounded + 8, i);
9989 if (srdis_mask ^ srdis_multi) {
9990 break;
9991 }
9992 srdis_mask = (srdis_mask << i) | srdis_mask;
9993 rsize++;
9994 }
9995 }
9996 if (srdis) {
9997 continue;
9998 }
9999 if (rsize < TARGET_PAGE_BITS) {
10000 *page_size = 1 << rsize;
10001 }
10002 break;
10003 }
10004
10005 if (n == -1) { /* no hits */
10006 if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
10007 /* background fault */
10008 fi->type = ARMFault_Background;
10009 return true;
10010 }
10011 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
10012 } else { /* a MPU hit! */
10013 uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
10014 uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
10015
10016 if (m_is_system_region(env, address)) {
10017 /* System space is always execute never */
10018 xn = 1;
10019 }
10020
10021 if (is_user) { /* User mode AP bit decoding */
10022 switch (ap) {
10023 case 0:
10024 case 1:
10025 case 5:
10026 break; /* no access */
10027 case 3:
10028 *prot |= PAGE_WRITE;
10029 /* fall through */
10030 case 2:
10031 case 6:
10032 *prot |= PAGE_READ | PAGE_EXEC;
10033 break;
10034 case 7:
10035 /* for v7M, same as 6; for R profile a reserved value */
10036 if (arm_feature(env, ARM_FEATURE_M)) {
10037 *prot |= PAGE_READ | PAGE_EXEC;
10038 break;
10039 }
10040 /* fall through */
10041 default:
10042 qemu_log_mask(LOG_GUEST_ERROR,
10043 "DRACR[%d]: Bad value for AP bits: 0x%"
10044 PRIx32 "\n", n, ap);
10045 }
10046 } else { /* Priv. mode AP bits decoding */
10047 switch (ap) {
10048 case 0:
10049 break; /* no access */
10050 case 1:
10051 case 2:
10052 case 3:
10053 *prot |= PAGE_WRITE;
10054 /* fall through */
10055 case 5:
10056 case 6:
10057 *prot |= PAGE_READ | PAGE_EXEC;
10058 break;
10059 case 7:
10060 /* for v7M, same as 6; for R profile a reserved value */
10061 if (arm_feature(env, ARM_FEATURE_M)) {
10062 *prot |= PAGE_READ | PAGE_EXEC;
10063 break;
10064 }
10065 /* fall through */
10066 default:
10067 qemu_log_mask(LOG_GUEST_ERROR,
10068 "DRACR[%d]: Bad value for AP bits: 0x%"
10069 PRIx32 "\n", n, ap);
10070 }
10071 }
10072
10073 /* execute never */
10074 if (xn) {
10075 *prot &= ~PAGE_EXEC;
10076 }
10077 }
10078 }
10079
10080 fi->type = ARMFault_Permission;
10081 fi->level = 1;
10082 return !(*prot & (1 << access_type));
10083 }
10084
10085 static bool v8m_is_sau_exempt(CPUARMState *env,
10086 uint32_t address, MMUAccessType access_type)
10087 {
10088 /* The architecture specifies that certain address ranges are
10089 * exempt from v8M SAU/IDAU checks.
10090 */
10091 return
10092 (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) ||
10093 (address >= 0xe0000000 && address <= 0xe0002fff) ||
10094 (address >= 0xe000e000 && address <= 0xe000efff) ||
10095 (address >= 0xe002e000 && address <= 0xe002efff) ||
10096 (address >= 0xe0040000 && address <= 0xe0041fff) ||
10097 (address >= 0xe00ff000 && address <= 0xe00fffff);
10098 }
10099
10100 static void v8m_security_lookup(CPUARMState *env, uint32_t address,
10101 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10102 V8M_SAttributes *sattrs)
10103 {
10104 /* Look up the security attributes for this address. Compare the
10105 * pseudocode SecurityCheck() function.
10106 * We assume the caller has zero-initialized *sattrs.
10107 */
10108 ARMCPU *cpu = arm_env_get_cpu(env);
10109 int r;
10110 bool idau_exempt = false, idau_ns = true, idau_nsc = true;
10111 int idau_region = IREGION_NOTVALID;
10112 uint32_t addr_page_base = address & TARGET_PAGE_MASK;
10113 uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
10114
10115 if (cpu->idau) {
10116 IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau);
10117 IDAUInterface *ii = IDAU_INTERFACE(cpu->idau);
10118
10119 iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns,
10120 &idau_nsc);
10121 }
10122
10123 if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) {
10124 /* 0xf0000000..0xffffffff is always S for insn fetches */
10125 return;
10126 }
10127
10128 if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) {
10129 sattrs->ns = !regime_is_secure(env, mmu_idx);
10130 return;
10131 }
10132
10133 if (idau_region != IREGION_NOTVALID) {
10134 sattrs->irvalid = true;
10135 sattrs->iregion = idau_region;
10136 }
10137
10138 switch (env->sau.ctrl & 3) {
10139 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
10140 break;
10141 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
10142 sattrs->ns = true;
10143 break;
10144 default: /* SAU.ENABLE == 1 */
10145 for (r = 0; r < cpu->sau_sregion; r++) {
10146 if (env->sau.rlar[r] & 1) {
10147 uint32_t base = env->sau.rbar[r] & ~0x1f;
10148 uint32_t limit = env->sau.rlar[r] | 0x1f;
10149
10150 if (base <= address && limit >= address) {
10151 if (base > addr_page_base || limit < addr_page_limit) {
10152 sattrs->subpage = true;
10153 }
10154 if (sattrs->srvalid) {
10155 /* If we hit in more than one region then we must report
10156 * as Secure, not NS-Callable, with no valid region
10157 * number info.
10158 */
10159 sattrs->ns = false;
10160 sattrs->nsc = false;
10161 sattrs->sregion = 0;
10162 sattrs->srvalid = false;
10163 break;
10164 } else {
10165 if (env->sau.rlar[r] & 2) {
10166 sattrs->nsc = true;
10167 } else {
10168 sattrs->ns = true;
10169 }
10170 sattrs->srvalid = true;
10171 sattrs->sregion = r;
10172 }
10173 } else {
10174 /*
10175 * Address not in this region. We must check whether the
10176 * region covers addresses in the same page as our address.
10177 * In that case we must not report a size that covers the
10178 * whole page for a subsequent hit against a different MPU
10179 * region or the background region, because it would result
10180 * in incorrect TLB hits for subsequent accesses to
10181 * addresses that are in this MPU region.
10182 */
10183 if (limit >= base &&
10184 ranges_overlap(base, limit - base + 1,
10185 addr_page_base,
10186 TARGET_PAGE_SIZE)) {
10187 sattrs->subpage = true;
10188 }
10189 }
10190 }
10191 }
10192
10193 /* The IDAU will override the SAU lookup results if it specifies
10194 * higher security than the SAU does.
10195 */
10196 if (!idau_ns) {
10197 if (sattrs->ns || (!idau_nsc && sattrs->nsc)) {
10198 sattrs->ns = false;
10199 sattrs->nsc = idau_nsc;
10200 }
10201 }
10202 break;
10203 }
10204 }
10205
10206 static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
10207 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10208 hwaddr *phys_ptr, MemTxAttrs *txattrs,
10209 int *prot, bool *is_subpage,
10210 ARMMMUFaultInfo *fi, uint32_t *mregion)
10211 {
10212 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
10213 * that a full phys-to-virt translation does).
10214 * mregion is (if not NULL) set to the region number which matched,
10215 * or -1 if no region number is returned (MPU off, address did not
10216 * hit a region, address hit in multiple regions).
10217 * We set is_subpage to true if the region hit doesn't cover the
10218 * entire TARGET_PAGE the address is within.
10219 */
10220 ARMCPU *cpu = arm_env_get_cpu(env);
10221 bool is_user = regime_is_user(env, mmu_idx);
10222 uint32_t secure = regime_is_secure(env, mmu_idx);
10223 int n;
10224 int matchregion = -1;
10225 bool hit = false;
10226 uint32_t addr_page_base = address & TARGET_PAGE_MASK;
10227 uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
10228
10229 *is_subpage = false;
10230 *phys_ptr = address;
10231 *prot = 0;
10232 if (mregion) {
10233 *mregion = -1;
10234 }
10235
10236 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
10237 * was an exception vector read from the vector table (which is always
10238 * done using the default system address map), because those accesses
10239 * are done in arm_v7m_load_vector(), which always does a direct
10240 * read using address_space_ldl(), rather than going via this function.
10241 */
10242 if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
10243 hit = true;
10244 } else if (m_is_ppb_region(env, address)) {
10245 hit = true;
10246 } else if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
10247 hit = true;
10248 } else {
10249 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
10250 /* region search */
10251 /* Note that the base address is bits [31:5] from the register
10252 * with bits [4:0] all zeroes, but the limit address is bits
10253 * [31:5] from the register with bits [4:0] all ones.
10254 */
10255 uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
10256 uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
10257
10258 if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
10259 /* Region disabled */
10260 continue;
10261 }
10262
10263 if (address < base || address > limit) {
10264 /*
10265 * Address not in this region. We must check whether the
10266 * region covers addresses in the same page as our address.
10267 * In that case we must not report a size that covers the
10268 * whole page for a subsequent hit against a different MPU
10269 * region or the background region, because it would result in
10270 * incorrect TLB hits for subsequent accesses to addresses that
10271 * are in this MPU region.
10272 */
10273 if (limit >= base &&
10274 ranges_overlap(base, limit - base + 1,
10275 addr_page_base,
10276 TARGET_PAGE_SIZE)) {
10277 *is_subpage = true;
10278 }
10279 continue;
10280 }
10281
10282 if (base > addr_page_base || limit < addr_page_limit) {
10283 *is_subpage = true;
10284 }
10285
10286 if (hit) {
10287 /* Multiple regions match -- always a failure (unlike
10288 * PMSAv7 where highest-numbered-region wins)
10289 */
10290 fi->type = ARMFault_Permission;
10291 fi->level = 1;
10292 return true;
10293 }
10294
10295 matchregion = n;
10296 hit = true;
10297 }
10298 }
10299
10300 if (!hit) {
10301 /* background fault */
10302 fi->type = ARMFault_Background;
10303 return true;
10304 }
10305
10306 if (matchregion == -1) {
10307 /* hit using the background region */
10308 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
10309 } else {
10310 uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
10311 uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
10312
10313 if (m_is_system_region(env, address)) {
10314 /* System space is always execute never */
10315 xn = 1;
10316 }
10317
10318 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
10319 if (*prot && !xn) {
10320 *prot |= PAGE_EXEC;
10321 }
10322 /* We don't need to look the attribute up in the MAIR0/MAIR1
10323 * registers because that only tells us about cacheability.
10324 */
10325 if (mregion) {
10326 *mregion = matchregion;
10327 }
10328 }
10329
10330 fi->type = ARMFault_Permission;
10331 fi->level = 1;
10332 return !(*prot & (1 << access_type));
10333 }
10334
10335
10336 static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
10337 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10338 hwaddr *phys_ptr, MemTxAttrs *txattrs,
10339 int *prot, target_ulong *page_size,
10340 ARMMMUFaultInfo *fi)
10341 {
10342 uint32_t secure = regime_is_secure(env, mmu_idx);
10343 V8M_SAttributes sattrs = {};
10344 bool ret;
10345 bool mpu_is_subpage;
10346
10347 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
10348 v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
10349 if (access_type == MMU_INST_FETCH) {
10350 /* Instruction fetches always use the MMU bank and the
10351 * transaction attribute determined by the fetch address,
10352 * regardless of CPU state. This is painful for QEMU
10353 * to handle, because it would mean we need to encode
10354 * into the mmu_idx not just the (user, negpri) information
10355 * for the current security state but also that for the
10356 * other security state, which would balloon the number
10357 * of mmu_idx values needed alarmingly.
10358 * Fortunately we can avoid this because it's not actually
10359 * possible to arbitrarily execute code from memory with
10360 * the wrong security attribute: it will always generate
10361 * an exception of some kind or another, apart from the
10362 * special case of an NS CPU executing an SG instruction
10363 * in S&NSC memory. So we always just fail the translation
10364 * here and sort things out in the exception handler
10365 * (including possibly emulating an SG instruction).
10366 */
10367 if (sattrs.ns != !secure) {
10368 if (sattrs.nsc) {
10369 fi->type = ARMFault_QEMU_NSCExec;
10370 } else {
10371 fi->type = ARMFault_QEMU_SFault;
10372 }
10373 *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
10374 *phys_ptr = address;
10375 *prot = 0;
10376 return true;
10377 }
10378 } else {
10379 /* For data accesses we always use the MMU bank indicated
10380 * by the current CPU state, but the security attributes
10381 * might downgrade a secure access to nonsecure.
10382 */
10383 if (sattrs.ns) {
10384 txattrs->secure = false;
10385 } else if (!secure) {
10386 /* NS access to S memory must fault.
10387 * Architecturally we should first check whether the
10388 * MPU information for this address indicates that we
10389 * are doing an unaligned access to Device memory, which
10390 * should generate a UsageFault instead. QEMU does not
10391 * currently check for that kind of unaligned access though.
10392 * If we added it we would need to do so as a special case
10393 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
10394 */
10395 fi->type = ARMFault_QEMU_SFault;
10396 *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
10397 *phys_ptr = address;
10398 *prot = 0;
10399 return true;
10400 }
10401 }
10402 }
10403
10404 ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr,
10405 txattrs, prot, &mpu_is_subpage, fi, NULL);
10406 /*
10407 * TODO: this is a temporary hack to ignore the fact that the SAU region
10408 * is smaller than a page if this is an executable region. We never
10409 * supported small MPU regions, but we did (accidentally) allow small
10410 * SAU regions, and if we now made small SAU regions not be executable
10411 * then this would break previously working guest code. We can't
10412 * remove this until/unless we implement support for execution from
10413 * small regions.
10414 */
10415 if (*prot & PAGE_EXEC) {
10416 sattrs.subpage = false;
10417 }
10418 *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
10419 return ret;
10420 }
10421
10422 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
10423 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10424 hwaddr *phys_ptr, int *prot,
10425 ARMMMUFaultInfo *fi)
10426 {
10427 int n;
10428 uint32_t mask;
10429 uint32_t base;
10430 bool is_user = regime_is_user(env, mmu_idx);
10431
10432 if (regime_translation_disabled(env, mmu_idx)) {
10433 /* MPU disabled. */
10434 *phys_ptr = address;
10435 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
10436 return false;
10437 }
10438
10439 *phys_ptr = address;
10440 for (n = 7; n >= 0; n--) {
10441 base = env->cp15.c6_region[n];
10442 if ((base & 1) == 0) {
10443 continue;
10444 }
10445 mask = 1 << ((base >> 1) & 0x1f);
10446 /* Keep this shift separate from the above to avoid an
10447 (undefined) << 32. */
10448 mask = (mask << 1) - 1;
10449 if (((base ^ address) & ~mask) == 0) {
10450 break;
10451 }
10452 }
10453 if (n < 0) {
10454 fi->type = ARMFault_Background;
10455 return true;
10456 }
10457
10458 if (access_type == MMU_INST_FETCH) {
10459 mask = env->cp15.pmsav5_insn_ap;
10460 } else {
10461 mask = env->cp15.pmsav5_data_ap;
10462 }
10463 mask = (mask >> (n * 4)) & 0xf;
10464 switch (mask) {
10465 case 0:
10466 fi->type = ARMFault_Permission;
10467 fi->level = 1;
10468 return true;
10469 case 1:
10470 if (is_user) {
10471 fi->type = ARMFault_Permission;
10472 fi->level = 1;
10473 return true;
10474 }
10475 *prot = PAGE_READ | PAGE_WRITE;
10476 break;
10477 case 2:
10478 *prot = PAGE_READ;
10479 if (!is_user) {
10480 *prot |= PAGE_WRITE;
10481 }
10482 break;
10483 case 3:
10484 *prot = PAGE_READ | PAGE_WRITE;
10485 break;
10486 case 5:
10487 if (is_user) {
10488 fi->type = ARMFault_Permission;
10489 fi->level = 1;
10490 return true;
10491 }
10492 *prot = PAGE_READ;
10493 break;
10494 case 6:
10495 *prot = PAGE_READ;
10496 break;
10497 default:
10498 /* Bad permission. */
10499 fi->type = ARMFault_Permission;
10500 fi->level = 1;
10501 return true;
10502 }
10503 *prot |= PAGE_EXEC;
10504 return false;
10505 }
10506
10507 /* Combine either inner or outer cacheability attributes for normal
10508 * memory, according to table D4-42 and pseudocode procedure
10509 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
10510 *
10511 * NB: only stage 1 includes allocation hints (RW bits), leading to
10512 * some asymmetry.
10513 */
10514 static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
10515 {
10516 if (s1 == 4 || s2 == 4) {
10517 /* non-cacheable has precedence */
10518 return 4;
10519 } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) {
10520 /* stage 1 write-through takes precedence */
10521 return s1;
10522 } else if (extract32(s2, 2, 2) == 2) {
10523 /* stage 2 write-through takes precedence, but the allocation hint
10524 * is still taken from stage 1
10525 */
10526 return (2 << 2) | extract32(s1, 0, 2);
10527 } else { /* write-back */
10528 return s1;
10529 }
10530 }
10531
10532 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
10533 * and CombineS1S2Desc()
10534 *
10535 * @s1: Attributes from stage 1 walk
10536 * @s2: Attributes from stage 2 walk
10537 */
10538 static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
10539 {
10540 uint8_t s1lo = extract32(s1.attrs, 0, 4), s2lo = extract32(s2.attrs, 0, 4);
10541 uint8_t s1hi = extract32(s1.attrs, 4, 4), s2hi = extract32(s2.attrs, 4, 4);
10542 ARMCacheAttrs ret;
10543
10544 /* Combine shareability attributes (table D4-43) */
10545 if (s1.shareability == 2 || s2.shareability == 2) {
10546 /* if either are outer-shareable, the result is outer-shareable */
10547 ret.shareability = 2;
10548 } else if (s1.shareability == 3 || s2.shareability == 3) {
10549 /* if either are inner-shareable, the result is inner-shareable */
10550 ret.shareability = 3;
10551 } else {
10552 /* both non-shareable */
10553 ret.shareability = 0;
10554 }
10555
10556 /* Combine memory type and cacheability attributes */
10557 if (s1hi == 0 || s2hi == 0) {
10558 /* Device has precedence over normal */
10559 if (s1lo == 0 || s2lo == 0) {
10560 /* nGnRnE has precedence over anything */
10561 ret.attrs = 0;
10562 } else if (s1lo == 4 || s2lo == 4) {
10563 /* non-Reordering has precedence over Reordering */
10564 ret.attrs = 4; /* nGnRE */
10565 } else if (s1lo == 8 || s2lo == 8) {
10566 /* non-Gathering has precedence over Gathering */
10567 ret.attrs = 8; /* nGRE */
10568 } else {
10569 ret.attrs = 0xc; /* GRE */
10570 }
10571
10572 /* Any location for which the resultant memory type is any
10573 * type of Device memory is always treated as Outer Shareable.
10574 */
10575 ret.shareability = 2;
10576 } else { /* Normal memory */
10577 /* Outer/inner cacheability combine independently */
10578 ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4
10579 | combine_cacheattr_nibble(s1lo, s2lo);
10580
10581 if (ret.attrs == 0x44) {
10582 /* Any location for which the resultant memory type is Normal
10583 * Inner Non-cacheable, Outer Non-cacheable is always treated
10584 * as Outer Shareable.
10585 */
10586 ret.shareability = 2;
10587 }
10588 }
10589
10590 return ret;
10591 }
10592
10593
10594 /* get_phys_addr - get the physical address for this virtual address
10595 *
10596 * Find the physical address corresponding to the given virtual address,
10597 * by doing a translation table walk on MMU based systems or using the
10598 * MPU state on MPU based systems.
10599 *
10600 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
10601 * prot and page_size may not be filled in, and the populated fsr value provides
10602 * information on why the translation aborted, in the format of a
10603 * DFSR/IFSR fault register, with the following caveats:
10604 * * we honour the short vs long DFSR format differences.
10605 * * the WnR bit is never set (the caller must do this).
10606 * * for PSMAv5 based systems we don't bother to return a full FSR format
10607 * value.
10608 *
10609 * @env: CPUARMState
10610 * @address: virtual address to get physical address for
10611 * @access_type: 0 for read, 1 for write, 2 for execute
10612 * @mmu_idx: MMU index indicating required translation regime
10613 * @phys_ptr: set to the physical address corresponding to the virtual address
10614 * @attrs: set to the memory transaction attributes to use
10615 * @prot: set to the permissions for the page containing phys_ptr
10616 * @page_size: set to the size of the page containing phys_ptr
10617 * @fi: set to fault info if the translation fails
10618 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
10619 */
10620 static bool get_phys_addr(CPUARMState *env, target_ulong address,
10621 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10622 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
10623 target_ulong *page_size,
10624 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
10625 {
10626 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
10627 /* Call ourselves recursively to do the stage 1 and then stage 2
10628 * translations.
10629 */
10630 if (arm_feature(env, ARM_FEATURE_EL2)) {
10631 hwaddr ipa;
10632 int s2_prot;
10633 int ret;
10634 ARMCacheAttrs cacheattrs2 = {};
10635
10636 ret = get_phys_addr(env, address, access_type,
10637 stage_1_mmu_idx(mmu_idx), &ipa, attrs,
10638 prot, page_size, fi, cacheattrs);
10639
10640 /* If S1 fails or S2 is disabled, return early. */
10641 if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
10642 *phys_ptr = ipa;
10643 return ret;
10644 }
10645
10646 /* S1 is done. Now do S2 translation. */
10647 ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS,
10648 phys_ptr, attrs, &s2_prot,
10649 page_size, fi,
10650 cacheattrs != NULL ? &cacheattrs2 : NULL);
10651 fi->s2addr = ipa;
10652 /* Combine the S1 and S2 perms. */
10653 *prot &= s2_prot;
10654
10655 /* Combine the S1 and S2 cache attributes, if needed */
10656 if (!ret && cacheattrs != NULL) {
10657 *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2);
10658 }
10659
10660 return ret;
10661 } else {
10662 /*
10663 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
10664 */
10665 mmu_idx = stage_1_mmu_idx(mmu_idx);
10666 }
10667 }
10668
10669 /* The page table entries may downgrade secure to non-secure, but
10670 * cannot upgrade an non-secure translation regime's attributes
10671 * to secure.
10672 */
10673 attrs->secure = regime_is_secure(env, mmu_idx);
10674 attrs->user = regime_is_user(env, mmu_idx);
10675
10676 /* Fast Context Switch Extension. This doesn't exist at all in v8.
10677 * In v7 and earlier it affects all stage 1 translations.
10678 */
10679 if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
10680 && !arm_feature(env, ARM_FEATURE_V8)) {
10681 if (regime_el(env, mmu_idx) == 3) {
10682 address += env->cp15.fcseidr_s;
10683 } else {
10684 address += env->cp15.fcseidr_ns;
10685 }
10686 }
10687
10688 if (arm_feature(env, ARM_FEATURE_PMSA)) {
10689 bool ret;
10690 *page_size = TARGET_PAGE_SIZE;
10691
10692 if (arm_feature(env, ARM_FEATURE_V8)) {
10693 /* PMSAv8 */
10694 ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
10695 phys_ptr, attrs, prot, page_size, fi);
10696 } else if (arm_feature(env, ARM_FEATURE_V7)) {
10697 /* PMSAv7 */
10698 ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
10699 phys_ptr, prot, page_size, fi);
10700 } else {
10701 /* Pre-v7 MPU */
10702 ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
10703 phys_ptr, prot, fi);
10704 }
10705 qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
10706 " mmu_idx %u -> %s (prot %c%c%c)\n",
10707 access_type == MMU_DATA_LOAD ? "reading" :
10708 (access_type == MMU_DATA_STORE ? "writing" : "execute"),
10709 (uint32_t)address, mmu_idx,
10710 ret ? "Miss" : "Hit",
10711 *prot & PAGE_READ ? 'r' : '-',
10712 *prot & PAGE_WRITE ? 'w' : '-',
10713 *prot & PAGE_EXEC ? 'x' : '-');
10714
10715 return ret;
10716 }
10717
10718 /* Definitely a real MMU, not an MPU */
10719
10720 if (regime_translation_disabled(env, mmu_idx)) {
10721 /* MMU disabled. */
10722 *phys_ptr = address;
10723 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
10724 *page_size = TARGET_PAGE_SIZE;
10725 return 0;
10726 }
10727
10728 if (regime_using_lpae_format(env, mmu_idx)) {
10729 return get_phys_addr_lpae(env, address, access_type, mmu_idx,
10730 phys_ptr, attrs, prot, page_size,
10731 fi, cacheattrs);
10732 } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
10733 return get_phys_addr_v6(env, address, access_type, mmu_idx,
10734 phys_ptr, attrs, prot, page_size, fi);
10735 } else {
10736 return get_phys_addr_v5(env, address, access_type, mmu_idx,
10737 phys_ptr, prot, page_size, fi);
10738 }
10739 }
10740
10741 /* Walk the page table and (if the mapping exists) add the page
10742 * to the TLB. Return false on success, or true on failure. Populate
10743 * fsr with ARM DFSR/IFSR fault register format value on failure.
10744 */
10745 bool arm_tlb_fill(CPUState *cs, vaddr address,
10746 MMUAccessType access_type, int mmu_idx,
10747 ARMMMUFaultInfo *fi)
10748 {
10749 ARMCPU *cpu = ARM_CPU(cs);
10750 CPUARMState *env = &cpu->env;
10751 hwaddr phys_addr;
10752 target_ulong page_size;
10753 int prot;
10754 int ret;
10755 MemTxAttrs attrs = {};
10756
10757 ret = get_phys_addr(env, address, access_type,
10758 core_to_arm_mmu_idx(env, mmu_idx), &phys_addr,
10759 &attrs, &prot, &page_size, fi, NULL);
10760 if (!ret) {
10761 /*
10762 * Map a single [sub]page. Regions smaller than our declared
10763 * target page size are handled specially, so for those we
10764 * pass in the exact addresses.
10765 */
10766 if (page_size >= TARGET_PAGE_SIZE) {
10767 phys_addr &= TARGET_PAGE_MASK;
10768 address &= TARGET_PAGE_MASK;
10769 }
10770 tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
10771 prot, mmu_idx, page_size);
10772 return 0;
10773 }
10774
10775 return ret;
10776 }
10777
10778 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
10779 MemTxAttrs *attrs)
10780 {
10781 ARMCPU *cpu = ARM_CPU(cs);
10782 CPUARMState *env = &cpu->env;
10783 hwaddr phys_addr;
10784 target_ulong page_size;
10785 int prot;
10786 bool ret;
10787 ARMMMUFaultInfo fi = {};
10788 ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
10789
10790 *attrs = (MemTxAttrs) {};
10791
10792 ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
10793 attrs, &prot, &page_size, &fi, NULL);
10794
10795 if (ret) {
10796 return -1;
10797 }
10798 return phys_addr;
10799 }
10800
10801 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
10802 {
10803 uint32_t mask;
10804 unsigned el = arm_current_el(env);
10805
10806 /* First handle registers which unprivileged can read */
10807
10808 switch (reg) {
10809 case 0 ... 7: /* xPSR sub-fields */
10810 mask = 0;
10811 if ((reg & 1) && el) {
10812 mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */
10813 }
10814 if (!(reg & 4)) {
10815 mask |= XPSR_NZCV | XPSR_Q; /* APSR */
10816 }
10817 /* EPSR reads as zero */
10818 return xpsr_read(env) & mask;
10819 break;
10820 case 20: /* CONTROL */
10821 return env->v7m.control[env->v7m.secure];
10822 case 0x94: /* CONTROL_NS */
10823 /* We have to handle this here because unprivileged Secure code
10824 * can read the NS CONTROL register.
10825 */
10826 if (!env->v7m.secure) {
10827 return 0;
10828 }
10829 return env->v7m.control[M_REG_NS];
10830 }
10831
10832 if (el == 0) {
10833 return 0; /* unprivileged reads others as zero */
10834 }
10835
10836 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
10837 switch (reg) {
10838 case 0x88: /* MSP_NS */
10839 if (!env->v7m.secure) {
10840 return 0;
10841 }
10842 return env->v7m.other_ss_msp;
10843 case 0x89: /* PSP_NS */
10844 if (!env->v7m.secure) {
10845 return 0;
10846 }
10847 return env->v7m.other_ss_psp;
10848 case 0x8a: /* MSPLIM_NS */
10849 if (!env->v7m.secure) {
10850 return 0;
10851 }
10852 return env->v7m.msplim[M_REG_NS];
10853 case 0x8b: /* PSPLIM_NS */
10854 if (!env->v7m.secure) {
10855 return 0;
10856 }
10857 return env->v7m.psplim[M_REG_NS];
10858 case 0x90: /* PRIMASK_NS */
10859 if (!env->v7m.secure) {
10860 return 0;
10861 }
10862 return env->v7m.primask[M_REG_NS];
10863 case 0x91: /* BASEPRI_NS */
10864 if (!env->v7m.secure) {
10865 return 0;
10866 }
10867 return env->v7m.basepri[M_REG_NS];
10868 case 0x93: /* FAULTMASK_NS */
10869 if (!env->v7m.secure) {
10870 return 0;
10871 }
10872 return env->v7m.faultmask[M_REG_NS];
10873 case 0x98: /* SP_NS */
10874 {
10875 /* This gives the non-secure SP selected based on whether we're
10876 * currently in handler mode or not, using the NS CONTROL.SPSEL.
10877 */
10878 bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
10879
10880 if (!env->v7m.secure) {
10881 return 0;
10882 }
10883 if (!arm_v7m_is_handler_mode(env) && spsel) {
10884 return env->v7m.other_ss_psp;
10885 } else {
10886 return env->v7m.other_ss_msp;
10887 }
10888 }
10889 default:
10890 break;
10891 }
10892 }
10893
10894 switch (reg) {
10895 case 8: /* MSP */
10896 return v7m_using_psp(env) ? env->v7m.other_sp : env->regs[13];
10897 case 9: /* PSP */
10898 return v7m_using_psp(env) ? env->regs[13] : env->v7m.other_sp;
10899 case 10: /* MSPLIM */
10900 if (!arm_feature(env, ARM_FEATURE_V8)) {
10901 goto bad_reg;
10902 }
10903 return env->v7m.msplim[env->v7m.secure];
10904 case 11: /* PSPLIM */
10905 if (!arm_feature(env, ARM_FEATURE_V8)) {
10906 goto bad_reg;
10907 }
10908 return env->v7m.psplim[env->v7m.secure];
10909 case 16: /* PRIMASK */
10910 return env->v7m.primask[env->v7m.secure];
10911 case 17: /* BASEPRI */
10912 case 18: /* BASEPRI_MAX */
10913 return env->v7m.basepri[env->v7m.secure];
10914 case 19: /* FAULTMASK */
10915 return env->v7m.faultmask[env->v7m.secure];
10916 default:
10917 bad_reg:
10918 qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special"
10919 " register %d\n", reg);
10920 return 0;
10921 }
10922 }
10923
10924 void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
10925 {
10926 /* We're passed bits [11..0] of the instruction; extract
10927 * SYSm and the mask bits.
10928 * Invalid combinations of SYSm and mask are UNPREDICTABLE;
10929 * we choose to treat them as if the mask bits were valid.
10930 * NB that the pseudocode 'mask' variable is bits [11..10],
10931 * whereas ours is [11..8].
10932 */
10933 uint32_t mask = extract32(maskreg, 8, 4);
10934 uint32_t reg = extract32(maskreg, 0, 8);
10935
10936 if (arm_current_el(env) == 0 && reg > 7) {
10937 /* only xPSR sub-fields may be written by unprivileged */
10938 return;
10939 }
10940
10941 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
10942 switch (reg) {
10943 case 0x88: /* MSP_NS */
10944 if (!env->v7m.secure) {
10945 return;
10946 }
10947 env->v7m.other_ss_msp = val;
10948 return;
10949 case 0x89: /* PSP_NS */
10950 if (!env->v7m.secure) {
10951 return;
10952 }
10953 env->v7m.other_ss_psp = val;
10954 return;
10955 case 0x8a: /* MSPLIM_NS */
10956 if (!env->v7m.secure) {
10957 return;
10958 }
10959 env->v7m.msplim[M_REG_NS] = val & ~7;
10960 return;
10961 case 0x8b: /* PSPLIM_NS */
10962 if (!env->v7m.secure) {
10963 return;
10964 }
10965 env->v7m.psplim[M_REG_NS] = val & ~7;
10966 return;
10967 case 0x90: /* PRIMASK_NS */
10968 if (!env->v7m.secure) {
10969 return;
10970 }
10971 env->v7m.primask[M_REG_NS] = val & 1;
10972 return;
10973 case 0x91: /* BASEPRI_NS */
10974 if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN)) {
10975 return;
10976 }
10977 env->v7m.basepri[M_REG_NS] = val & 0xff;
10978 return;
10979 case 0x93: /* FAULTMASK_NS */
10980 if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN)) {
10981 return;
10982 }
10983 env->v7m.faultmask[M_REG_NS] = val & 1;
10984 return;
10985 case 0x94: /* CONTROL_NS */
10986 if (!env->v7m.secure) {
10987 return;
10988 }
10989 write_v7m_control_spsel_for_secstate(env,
10990 val & R_V7M_CONTROL_SPSEL_MASK,
10991 M_REG_NS);
10992 if (arm_feature(env, ARM_FEATURE_M_MAIN)) {
10993 env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK;
10994 env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK;
10995 }
10996 return;
10997 case 0x98: /* SP_NS */
10998 {
10999 /* This gives the non-secure SP selected based on whether we're
11000 * currently in handler mode or not, using the NS CONTROL.SPSEL.
11001 */
11002 bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
11003 bool is_psp = !arm_v7m_is_handler_mode(env) && spsel;
11004 uint32_t limit;
11005
11006 if (!env->v7m.secure) {
11007 return;
11008 }
11009
11010 limit = is_psp ? env->v7m.psplim[false] : env->v7m.msplim[false];
11011
11012 if (val < limit) {
11013 CPUState *cs = CPU(arm_env_get_cpu(env));
11014
11015 cpu_restore_state(cs, GETPC(), true);
11016 raise_exception(env, EXCP_STKOF, 0, 1);
11017 }
11018
11019 if (is_psp) {
11020 env->v7m.other_ss_psp = val;
11021 } else {
11022 env->v7m.other_ss_msp = val;
11023 }
11024 return;
11025 }
11026 default:
11027 break;
11028 }
11029 }
11030
11031 switch (reg) {
11032 case 0 ... 7: /* xPSR sub-fields */
11033 /* only APSR is actually writable */
11034 if (!(reg & 4)) {
11035 uint32_t apsrmask = 0;
11036
11037 if (mask & 8) {
11038 apsrmask |= XPSR_NZCV | XPSR_Q;
11039 }
11040 if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
11041 apsrmask |= XPSR_GE;
11042 }
11043 xpsr_write(env, val, apsrmask);
11044 }
11045 break;
11046 case 8: /* MSP */
11047 if (v7m_using_psp(env)) {
11048 env->v7m.other_sp = val;
11049 } else {
11050 env->regs[13] = val;
11051 }
11052 break;
11053 case 9: /* PSP */
11054 if (v7m_using_psp(env)) {
11055 env->regs[13] = val;
11056 } else {
11057 env->v7m.other_sp = val;
11058 }
11059 break;
11060 case 10: /* MSPLIM */
11061 if (!arm_feature(env, ARM_FEATURE_V8)) {
11062 goto bad_reg;
11063 }
11064 env->v7m.msplim[env->v7m.secure] = val & ~7;
11065 break;
11066 case 11: /* PSPLIM */
11067 if (!arm_feature(env, ARM_FEATURE_V8)) {
11068 goto bad_reg;
11069 }
11070 env->v7m.psplim[env->v7m.secure] = val & ~7;
11071 break;
11072 case 16: /* PRIMASK */
11073 env->v7m.primask[env->v7m.secure] = val & 1;
11074 break;
11075 case 17: /* BASEPRI */
11076 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
11077 goto bad_reg;
11078 }
11079 env->v7m.basepri[env->v7m.secure] = val & 0xff;
11080 break;
11081 case 18: /* BASEPRI_MAX */
11082 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
11083 goto bad_reg;
11084 }
11085 val &= 0xff;
11086 if (val != 0 && (val < env->v7m.basepri[env->v7m.secure]
11087 || env->v7m.basepri[env->v7m.secure] == 0)) {
11088 env->v7m.basepri[env->v7m.secure] = val;
11089 }
11090 break;
11091 case 19: /* FAULTMASK */
11092 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
11093 goto bad_reg;
11094 }
11095 env->v7m.faultmask[env->v7m.secure] = val & 1;
11096 break;
11097 case 20: /* CONTROL */
11098 /* Writing to the SPSEL bit only has an effect if we are in
11099 * thread mode; other bits can be updated by any privileged code.
11100 * write_v7m_control_spsel() deals with updating the SPSEL bit in
11101 * env->v7m.control, so we only need update the others.
11102 * For v7M, we must just ignore explicit writes to SPSEL in handler
11103 * mode; for v8M the write is permitted but will have no effect.
11104 */
11105 if (arm_feature(env, ARM_FEATURE_V8) ||
11106 !arm_v7m_is_handler_mode(env)) {
11107 write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
11108 }
11109 if (arm_feature(env, ARM_FEATURE_M_MAIN)) {
11110 env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
11111 env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
11112 }
11113 break;
11114 default:
11115 bad_reg:
11116 qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special"
11117 " register %d\n", reg);
11118 return;
11119 }
11120 }
11121
11122 uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
11123 {
11124 /* Implement the TT instruction. op is bits [7:6] of the insn. */
11125 bool forceunpriv = op & 1;
11126 bool alt = op & 2;
11127 V8M_SAttributes sattrs = {};
11128 uint32_t tt_resp;
11129 bool r, rw, nsr, nsrw, mrvalid;
11130 int prot;
11131 ARMMMUFaultInfo fi = {};
11132 MemTxAttrs attrs = {};
11133 hwaddr phys_addr;
11134 ARMMMUIdx mmu_idx;
11135 uint32_t mregion;
11136 bool targetpriv;
11137 bool targetsec = env->v7m.secure;
11138 bool is_subpage;
11139
11140 /* Work out what the security state and privilege level we're
11141 * interested in is...
11142 */
11143 if (alt) {
11144 targetsec = !targetsec;
11145 }
11146
11147 if (forceunpriv) {
11148 targetpriv = false;
11149 } else {
11150 targetpriv = arm_v7m_is_handler_mode(env) ||
11151 !(env->v7m.control[targetsec] & R_V7M_CONTROL_NPRIV_MASK);
11152 }
11153
11154 /* ...and then figure out which MMU index this is */
11155 mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targetsec, targetpriv);
11156
11157 /* We know that the MPU and SAU don't care about the access type
11158 * for our purposes beyond that we don't want to claim to be
11159 * an insn fetch, so we arbitrarily call this a read.
11160 */
11161
11162 /* MPU region info only available for privileged or if
11163 * inspecting the other MPU state.
11164 */
11165 if (arm_current_el(env) != 0 || alt) {
11166 /* We can ignore the return value as prot is always set */
11167 pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
11168 &phys_addr, &attrs, &prot, &is_subpage,
11169 &fi, &mregion);
11170 if (mregion == -1) {
11171 mrvalid = false;
11172 mregion = 0;
11173 } else {
11174 mrvalid = true;
11175 }
11176 r = prot & PAGE_READ;
11177 rw = prot & PAGE_WRITE;
11178 } else {
11179 r = false;
11180 rw = false;
11181 mrvalid = false;
11182 mregion = 0;
11183 }
11184
11185 if (env->v7m.secure) {
11186 v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
11187 nsr = sattrs.ns && r;
11188 nsrw = sattrs.ns && rw;
11189 } else {
11190 sattrs.ns = true;
11191 nsr = false;
11192 nsrw = false;
11193 }
11194
11195 tt_resp = (sattrs.iregion << 24) |
11196 (sattrs.irvalid << 23) |
11197 ((!sattrs.ns) << 22) |
11198 (nsrw << 21) |
11199 (nsr << 20) |
11200 (rw << 19) |
11201 (r << 18) |
11202 (sattrs.srvalid << 17) |
11203 (mrvalid << 16) |
11204 (sattrs.sregion << 8) |
11205 mregion;
11206
11207 return tt_resp;
11208 }
11209
11210 #endif
11211
11212 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
11213 {
11214 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
11215 * Note that we do not implement the (architecturally mandated)
11216 * alignment fault for attempts to use this on Device memory
11217 * (which matches the usual QEMU behaviour of not implementing either
11218 * alignment faults or any memory attribute handling).
11219 */
11220
11221 ARMCPU *cpu = arm_env_get_cpu(env);
11222 uint64_t blocklen = 4 << cpu->dcz_blocksize;
11223 uint64_t vaddr = vaddr_in & ~(blocklen - 1);
11224
11225 #ifndef CONFIG_USER_ONLY
11226 {
11227 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
11228 * the block size so we might have to do more than one TLB lookup.
11229 * We know that in fact for any v8 CPU the page size is at least 4K
11230 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
11231 * 1K as an artefact of legacy v5 subpage support being present in the
11232 * same QEMU executable.
11233 */
11234 int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
11235 void *hostaddr[maxidx];
11236 int try, i;
11237 unsigned mmu_idx = cpu_mmu_index(env, false);
11238 TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
11239
11240 for (try = 0; try < 2; try++) {
11241
11242 for (i = 0; i < maxidx; i++) {
11243 hostaddr[i] = tlb_vaddr_to_host(env,
11244 vaddr + TARGET_PAGE_SIZE * i,
11245 1, mmu_idx);
11246 if (!hostaddr[i]) {
11247 break;
11248 }
11249 }
11250 if (i == maxidx) {
11251 /* If it's all in the TLB it's fair game for just writing to;
11252 * we know we don't need to update dirty status, etc.
11253 */
11254 for (i = 0; i < maxidx - 1; i++) {
11255 memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
11256 }
11257 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
11258 return;
11259 }
11260 /* OK, try a store and see if we can populate the tlb. This
11261 * might cause an exception if the memory isn't writable,
11262 * in which case we will longjmp out of here. We must for
11263 * this purpose use the actual register value passed to us
11264 * so that we get the fault address right.
11265 */
11266 helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC());
11267 /* Now we can populate the other TLB entries, if any */
11268 for (i = 0; i < maxidx; i++) {
11269 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
11270 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
11271 helper_ret_stb_mmu(env, va, 0, oi, GETPC());
11272 }
11273 }
11274 }
11275
11276 /* Slow path (probably attempt to do this to an I/O device or
11277 * similar, or clearing of a block of code we have translations
11278 * cached for). Just do a series of byte writes as the architecture
11279 * demands. It's not worth trying to use a cpu_physical_memory_map(),
11280 * memset(), unmap() sequence here because:
11281 * + we'd need to account for the blocksize being larger than a page
11282 * + the direct-RAM access case is almost always going to be dealt
11283 * with in the fastpath code above, so there's no speed benefit
11284 * + we would have to deal with the map returning NULL because the
11285 * bounce buffer was in use
11286 */
11287 for (i = 0; i < blocklen; i++) {
11288 helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC());
11289 }
11290 }
11291 #else
11292 memset(g2h(vaddr), 0, blocklen);
11293 #endif
11294 }
11295
11296 /* Note that signed overflow is undefined in C. The following routines are
11297 careful to use unsigned types where modulo arithmetic is required.
11298 Failure to do so _will_ break on newer gcc. */
11299
11300 /* Signed saturating arithmetic. */
11301
11302 /* Perform 16-bit signed saturating addition. */
11303 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
11304 {
11305 uint16_t res;
11306
11307 res = a + b;
11308 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
11309 if (a & 0x8000)
11310 res = 0x8000;
11311 else
11312 res = 0x7fff;
11313 }
11314 return res;
11315 }
11316
11317 /* Perform 8-bit signed saturating addition. */
11318 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
11319 {
11320 uint8_t res;
11321
11322 res = a + b;
11323 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
11324 if (a & 0x80)
11325 res = 0x80;
11326 else
11327 res = 0x7f;
11328 }
11329 return res;
11330 }
11331
11332 /* Perform 16-bit signed saturating subtraction. */
11333 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
11334 {
11335 uint16_t res;
11336
11337 res = a - b;
11338 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
11339 if (a & 0x8000)
11340 res = 0x8000;
11341 else
11342 res = 0x7fff;
11343 }
11344 return res;
11345 }
11346
11347 /* Perform 8-bit signed saturating subtraction. */
11348 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
11349 {
11350 uint8_t res;
11351
11352 res = a - b;
11353 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
11354 if (a & 0x80)
11355 res = 0x80;
11356 else
11357 res = 0x7f;
11358 }
11359 return res;
11360 }
11361
11362 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11363 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11364 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11365 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11366 #define PFX q
11367
11368 #include "op_addsub.h"
11369
11370 /* Unsigned saturating arithmetic. */
11371 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
11372 {
11373 uint16_t res;
11374 res = a + b;
11375 if (res < a)
11376 res = 0xffff;
11377 return res;
11378 }
11379
11380 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
11381 {
11382 if (a > b)
11383 return a - b;
11384 else
11385 return 0;
11386 }
11387
11388 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
11389 {
11390 uint8_t res;
11391 res = a + b;
11392 if (res < a)
11393 res = 0xff;
11394 return res;
11395 }
11396
11397 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
11398 {
11399 if (a > b)
11400 return a - b;
11401 else
11402 return 0;
11403 }
11404
11405 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11406 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11407 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11408 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11409 #define PFX uq
11410
11411 #include "op_addsub.h"
11412
11413 /* Signed modulo arithmetic. */
11414 #define SARITH16(a, b, n, op) do { \
11415 int32_t sum; \
11416 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11417 RESULT(sum, n, 16); \
11418 if (sum >= 0) \
11419 ge |= 3 << (n * 2); \
11420 } while(0)
11421
11422 #define SARITH8(a, b, n, op) do { \
11423 int32_t sum; \
11424 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11425 RESULT(sum, n, 8); \
11426 if (sum >= 0) \
11427 ge |= 1 << n; \
11428 } while(0)
11429
11430
11431 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11432 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11433 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11434 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11435 #define PFX s
11436 #define ARITH_GE
11437
11438 #include "op_addsub.h"
11439
11440 /* Unsigned modulo arithmetic. */
11441 #define ADD16(a, b, n) do { \
11442 uint32_t sum; \
11443 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11444 RESULT(sum, n, 16); \
11445 if ((sum >> 16) == 1) \
11446 ge |= 3 << (n * 2); \
11447 } while(0)
11448
11449 #define ADD8(a, b, n) do { \
11450 uint32_t sum; \
11451 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11452 RESULT(sum, n, 8); \
11453 if ((sum >> 8) == 1) \
11454 ge |= 1 << n; \
11455 } while(0)
11456
11457 #define SUB16(a, b, n) do { \
11458 uint32_t sum; \
11459 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11460 RESULT(sum, n, 16); \
11461 if ((sum >> 16) == 0) \
11462 ge |= 3 << (n * 2); \
11463 } while(0)
11464
11465 #define SUB8(a, b, n) do { \
11466 uint32_t sum; \
11467 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11468 RESULT(sum, n, 8); \
11469 if ((sum >> 8) == 0) \
11470 ge |= 1 << n; \
11471 } while(0)
11472
11473 #define PFX u
11474 #define ARITH_GE
11475
11476 #include "op_addsub.h"
11477
11478 /* Halved signed arithmetic. */
11479 #define ADD16(a, b, n) \
11480 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11481 #define SUB16(a, b, n) \
11482 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11483 #define ADD8(a, b, n) \
11484 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11485 #define SUB8(a, b, n) \
11486 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11487 #define PFX sh
11488
11489 #include "op_addsub.h"
11490
11491 /* Halved unsigned arithmetic. */
11492 #define ADD16(a, b, n) \
11493 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11494 #define SUB16(a, b, n) \
11495 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11496 #define ADD8(a, b, n) \
11497 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11498 #define SUB8(a, b, n) \
11499 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11500 #define PFX uh
11501
11502 #include "op_addsub.h"
11503
11504 static inline uint8_t do_usad(uint8_t a, uint8_t b)
11505 {
11506 if (a > b)
11507 return a - b;
11508 else
11509 return b - a;
11510 }
11511
11512 /* Unsigned sum of absolute byte differences. */
11513 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
11514 {
11515 uint32_t sum;
11516 sum = do_usad(a, b);
11517 sum += do_usad(a >> 8, b >> 8);
11518 sum += do_usad(a >> 16, b >>16);
11519 sum += do_usad(a >> 24, b >> 24);
11520 return sum;
11521 }
11522
11523 /* For ARMv6 SEL instruction. */
11524 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
11525 {
11526 uint32_t mask;
11527
11528 mask = 0;
11529 if (flags & 1)
11530 mask |= 0xff;
11531 if (flags & 2)
11532 mask |= 0xff00;
11533 if (flags & 4)
11534 mask |= 0xff0000;
11535 if (flags & 8)
11536 mask |= 0xff000000;
11537 return (a & mask) | (b & ~mask);
11538 }
11539
11540 /* VFP support. We follow the convention used for VFP instructions:
11541 Single precision routines have a "s" suffix, double precision a
11542 "d" suffix. */
11543
11544 /* Convert host exception flags to vfp form. */
11545 static inline int vfp_exceptbits_from_host(int host_bits)
11546 {
11547 int target_bits = 0;
11548
11549 if (host_bits & float_flag_invalid)
11550 target_bits |= 1;
11551 if (host_bits & float_flag_divbyzero)
11552 target_bits |= 2;
11553 if (host_bits & float_flag_overflow)
11554 target_bits |= 4;
11555 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
11556 target_bits |= 8;
11557 if (host_bits & float_flag_inexact)
11558 target_bits |= 0x10;
11559 if (host_bits & float_flag_input_denormal)
11560 target_bits |= 0x80;
11561 return target_bits;
11562 }
11563
11564 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
11565 {
11566 int i;
11567 uint32_t fpscr;
11568
11569 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
11570 | (env->vfp.vec_len << 16)
11571 | (env->vfp.vec_stride << 20);
11572
11573 i = get_float_exception_flags(&env->vfp.fp_status);
11574 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
11575 /* FZ16 does not generate an input denormal exception. */
11576 i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
11577 & ~float_flag_input_denormal);
11578
11579 fpscr |= vfp_exceptbits_from_host(i);
11580 return fpscr;
11581 }
11582
11583 uint32_t vfp_get_fpscr(CPUARMState *env)
11584 {
11585 return HELPER(vfp_get_fpscr)(env);
11586 }
11587
11588 /* Convert vfp exception flags to target form. */
11589 static inline int vfp_exceptbits_to_host(int target_bits)
11590 {
11591 int host_bits = 0;
11592
11593 if (target_bits & 1)
11594 host_bits |= float_flag_invalid;
11595 if (target_bits & 2)
11596 host_bits |= float_flag_divbyzero;
11597 if (target_bits & 4)
11598 host_bits |= float_flag_overflow;
11599 if (target_bits & 8)
11600 host_bits |= float_flag_underflow;
11601 if (target_bits & 0x10)
11602 host_bits |= float_flag_inexact;
11603 if (target_bits & 0x80)
11604 host_bits |= float_flag_input_denormal;
11605 return host_bits;
11606 }
11607
11608 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
11609 {
11610 int i;
11611 uint32_t changed;
11612
11613 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
11614 if (!arm_feature(env, ARM_FEATURE_V8_FP16)) {
11615 val &= ~FPCR_FZ16;
11616 }
11617
11618 changed = env->vfp.xregs[ARM_VFP_FPSCR];
11619 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
11620 env->vfp.vec_len = (val >> 16) & 7;
11621 env->vfp.vec_stride = (val >> 20) & 3;
11622
11623 changed ^= val;
11624 if (changed & (3 << 22)) {
11625 i = (val >> 22) & 3;
11626 switch (i) {
11627 case FPROUNDING_TIEEVEN:
11628 i = float_round_nearest_even;
11629 break;
11630 case FPROUNDING_POSINF:
11631 i = float_round_up;
11632 break;
11633 case FPROUNDING_NEGINF:
11634 i = float_round_down;
11635 break;
11636 case FPROUNDING_ZERO:
11637 i = float_round_to_zero;
11638 break;
11639 }
11640 set_float_rounding_mode(i, &env->vfp.fp_status);
11641 set_float_rounding_mode(i, &env->vfp.fp_status_f16);
11642 }
11643 if (changed & FPCR_FZ16) {
11644 bool ftz_enabled = val & FPCR_FZ16;
11645 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
11646 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
11647 }
11648 if (changed & FPCR_FZ) {
11649 bool ftz_enabled = val & FPCR_FZ;
11650 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
11651 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
11652 }
11653 if (changed & FPCR_DN) {
11654 bool dnan_enabled = val & FPCR_DN;
11655 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
11656 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
11657 }
11658
11659 /* The exception flags are ORed together when we read fpscr so we
11660 * only need to preserve the current state in one of our
11661 * float_status values.
11662 */
11663 i = vfp_exceptbits_to_host(val);
11664 set_float_exception_flags(i, &env->vfp.fp_status);
11665 set_float_exception_flags(0, &env->vfp.fp_status_f16);
11666 set_float_exception_flags(0, &env->vfp.standard_fp_status);
11667 }
11668
11669 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
11670 {
11671 HELPER(vfp_set_fpscr)(env, val);
11672 }
11673
11674 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
11675
11676 #define VFP_BINOP(name) \
11677 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
11678 { \
11679 float_status *fpst = fpstp; \
11680 return float32_ ## name(a, b, fpst); \
11681 } \
11682 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
11683 { \
11684 float_status *fpst = fpstp; \
11685 return float64_ ## name(a, b, fpst); \
11686 }
11687 VFP_BINOP(add)
11688 VFP_BINOP(sub)
11689 VFP_BINOP(mul)
11690 VFP_BINOP(div)
11691 VFP_BINOP(min)
11692 VFP_BINOP(max)
11693 VFP_BINOP(minnum)
11694 VFP_BINOP(maxnum)
11695 #undef VFP_BINOP
11696
11697 float32 VFP_HELPER(neg, s)(float32 a)
11698 {
11699 return float32_chs(a);
11700 }
11701
11702 float64 VFP_HELPER(neg, d)(float64 a)
11703 {
11704 return float64_chs(a);
11705 }
11706
11707 float32 VFP_HELPER(abs, s)(float32 a)
11708 {
11709 return float32_abs(a);
11710 }
11711
11712 float64 VFP_HELPER(abs, d)(float64 a)
11713 {
11714 return float64_abs(a);
11715 }
11716
11717 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
11718 {
11719 return float32_sqrt(a, &env->vfp.fp_status);
11720 }
11721
11722 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
11723 {
11724 return float64_sqrt(a, &env->vfp.fp_status);
11725 }
11726
11727 /* XXX: check quiet/signaling case */
11728 #define DO_VFP_cmp(p, type) \
11729 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
11730 { \
11731 uint32_t flags; \
11732 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
11733 case 0: flags = 0x6; break; \
11734 case -1: flags = 0x8; break; \
11735 case 1: flags = 0x2; break; \
11736 default: case 2: flags = 0x3; break; \
11737 } \
11738 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
11739 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
11740 } \
11741 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
11742 { \
11743 uint32_t flags; \
11744 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
11745 case 0: flags = 0x6; break; \
11746 case -1: flags = 0x8; break; \
11747 case 1: flags = 0x2; break; \
11748 default: case 2: flags = 0x3; break; \
11749 } \
11750 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
11751 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
11752 }
11753 DO_VFP_cmp(s, float32)
11754 DO_VFP_cmp(d, float64)
11755 #undef DO_VFP_cmp
11756
11757 /* Integer to float and float to integer conversions */
11758
11759 #define CONV_ITOF(name, ftype, fsz, sign) \
11760 ftype HELPER(name)(uint32_t x, void *fpstp) \
11761 { \
11762 float_status *fpst = fpstp; \
11763 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
11764 }
11765
11766 #define CONV_FTOI(name, ftype, fsz, sign, round) \
11767 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
11768 { \
11769 float_status *fpst = fpstp; \
11770 if (float##fsz##_is_any_nan(x)) { \
11771 float_raise(float_flag_invalid, fpst); \
11772 return 0; \
11773 } \
11774 return float##fsz##_to_##sign##int32##round(x, fpst); \
11775 }
11776
11777 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
11778 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
11779 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
11780 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
11781
11782 FLOAT_CONVS(si, h, uint32_t, 16, )
11783 FLOAT_CONVS(si, s, float32, 32, )
11784 FLOAT_CONVS(si, d, float64, 64, )
11785 FLOAT_CONVS(ui, h, uint32_t, 16, u)
11786 FLOAT_CONVS(ui, s, float32, 32, u)
11787 FLOAT_CONVS(ui, d, float64, 64, u)
11788
11789 #undef CONV_ITOF
11790 #undef CONV_FTOI
11791 #undef FLOAT_CONVS
11792
11793 /* floating point conversion */
11794 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
11795 {
11796 return float32_to_float64(x, &env->vfp.fp_status);
11797 }
11798
11799 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
11800 {
11801 return float64_to_float32(x, &env->vfp.fp_status);
11802 }
11803
11804 /* VFP3 fixed point conversion. */
11805 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
11806 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
11807 void *fpstp) \
11808 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
11809
11810 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ROUND, suff) \
11811 uint##isz##_t HELPER(vfp_to##name##p##suff)(float##fsz x, uint32_t shift, \
11812 void *fpst) \
11813 { \
11814 if (unlikely(float##fsz##_is_any_nan(x))) { \
11815 float_raise(float_flag_invalid, fpst); \
11816 return 0; \
11817 } \
11818 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
11819 }
11820
11821 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
11822 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
11823 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
11824 float_round_to_zero, _round_to_zero) \
11825 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
11826 get_float_rounding_mode(fpst), )
11827
11828 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
11829 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
11830 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
11831 get_float_rounding_mode(fpst), )
11832
11833 VFP_CONV_FIX(sh, d, 64, 64, int16)
11834 VFP_CONV_FIX(sl, d, 64, 64, int32)
11835 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
11836 VFP_CONV_FIX(uh, d, 64, 64, uint16)
11837 VFP_CONV_FIX(ul, d, 64, 64, uint32)
11838 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
11839 VFP_CONV_FIX(sh, s, 32, 32, int16)
11840 VFP_CONV_FIX(sl, s, 32, 32, int32)
11841 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
11842 VFP_CONV_FIX(uh, s, 32, 32, uint16)
11843 VFP_CONV_FIX(ul, s, 32, 32, uint32)
11844 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
11845
11846 #undef VFP_CONV_FIX
11847 #undef VFP_CONV_FIX_FLOAT
11848 #undef VFP_CONV_FLOAT_FIX_ROUND
11849 #undef VFP_CONV_FIX_A64
11850
11851 uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
11852 {
11853 return int32_to_float16_scalbn(x, -shift, fpst);
11854 }
11855
11856 uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
11857 {
11858 return uint32_to_float16_scalbn(x, -shift, fpst);
11859 }
11860
11861 uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
11862 {
11863 return int64_to_float16_scalbn(x, -shift, fpst);
11864 }
11865
11866 uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
11867 {
11868 return uint64_to_float16_scalbn(x, -shift, fpst);
11869 }
11870
11871 uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
11872 {
11873 if (unlikely(float16_is_any_nan(x))) {
11874 float_raise(float_flag_invalid, fpst);
11875 return 0;
11876 }
11877 return float16_to_int16_scalbn(x, get_float_rounding_mode(fpst),
11878 shift, fpst);
11879 }
11880
11881 uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
11882 {
11883 if (unlikely(float16_is_any_nan(x))) {
11884 float_raise(float_flag_invalid, fpst);
11885 return 0;
11886 }
11887 return float16_to_uint16_scalbn(x, get_float_rounding_mode(fpst),
11888 shift, fpst);
11889 }
11890
11891 uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
11892 {
11893 if (unlikely(float16_is_any_nan(x))) {
11894 float_raise(float_flag_invalid, fpst);
11895 return 0;
11896 }
11897 return float16_to_int32_scalbn(x, get_float_rounding_mode(fpst),
11898 shift, fpst);
11899 }
11900
11901 uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
11902 {
11903 if (unlikely(float16_is_any_nan(x))) {
11904 float_raise(float_flag_invalid, fpst);
11905 return 0;
11906 }
11907 return float16_to_uint32_scalbn(x, get_float_rounding_mode(fpst),
11908 shift, fpst);
11909 }
11910
11911 uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
11912 {
11913 if (unlikely(float16_is_any_nan(x))) {
11914 float_raise(float_flag_invalid, fpst);
11915 return 0;
11916 }
11917 return float16_to_int64_scalbn(x, get_float_rounding_mode(fpst),
11918 shift, fpst);
11919 }
11920
11921 uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
11922 {
11923 if (unlikely(float16_is_any_nan(x))) {
11924 float_raise(float_flag_invalid, fpst);
11925 return 0;
11926 }
11927 return float16_to_uint64_scalbn(x, get_float_rounding_mode(fpst),
11928 shift, fpst);
11929 }
11930
11931 /* Set the current fp rounding mode and return the old one.
11932 * The argument is a softfloat float_round_ value.
11933 */
11934 uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
11935 {
11936 float_status *fp_status = fpstp;
11937
11938 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
11939 set_float_rounding_mode(rmode, fp_status);
11940
11941 return prev_rmode;
11942 }
11943
11944 /* Set the current fp rounding mode in the standard fp status and return
11945 * the old one. This is for NEON instructions that need to change the
11946 * rounding mode but wish to use the standard FPSCR values for everything
11947 * else. Always set the rounding mode back to the correct value after
11948 * modifying it.
11949 * The argument is a softfloat float_round_ value.
11950 */
11951 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
11952 {
11953 float_status *fp_status = &env->vfp.standard_fp_status;
11954
11955 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
11956 set_float_rounding_mode(rmode, fp_status);
11957
11958 return prev_rmode;
11959 }
11960
11961 /* Half precision conversions. */
11962 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
11963 {
11964 /* Squash FZ16 to 0 for the duration of conversion. In this case,
11965 * it would affect flushing input denormals.
11966 */
11967 float_status *fpst = fpstp;
11968 flag save = get_flush_inputs_to_zero(fpst);
11969 set_flush_inputs_to_zero(false, fpst);
11970 float32 r = float16_to_float32(a, !ahp_mode, fpst);
11971 set_flush_inputs_to_zero(save, fpst);
11972 return r;
11973 }
11974
11975 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
11976 {
11977 /* Squash FZ16 to 0 for the duration of conversion. In this case,
11978 * it would affect flushing output denormals.
11979 */
11980 float_status *fpst = fpstp;
11981 flag save = get_flush_to_zero(fpst);
11982 set_flush_to_zero(false, fpst);
11983 float16 r = float32_to_float16(a, !ahp_mode, fpst);
11984 set_flush_to_zero(save, fpst);
11985 return r;
11986 }
11987
11988 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
11989 {
11990 /* Squash FZ16 to 0 for the duration of conversion. In this case,
11991 * it would affect flushing input denormals.
11992 */
11993 float_status *fpst = fpstp;
11994 flag save = get_flush_inputs_to_zero(fpst);
11995 set_flush_inputs_to_zero(false, fpst);
11996 float64 r = float16_to_float64(a, !ahp_mode, fpst);
11997 set_flush_inputs_to_zero(save, fpst);
11998 return r;
11999 }
12000
12001 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
12002 {
12003 /* Squash FZ16 to 0 for the duration of conversion. In this case,
12004 * it would affect flushing output denormals.
12005 */
12006 float_status *fpst = fpstp;
12007 flag save = get_flush_to_zero(fpst);
12008 set_flush_to_zero(false, fpst);
12009 float16 r = float64_to_float16(a, !ahp_mode, fpst);
12010 set_flush_to_zero(save, fpst);
12011 return r;
12012 }
12013
12014 #define float32_two make_float32(0x40000000)
12015 #define float32_three make_float32(0x40400000)
12016 #define float32_one_point_five make_float32(0x3fc00000)
12017
12018 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
12019 {
12020 float_status *s = &env->vfp.standard_fp_status;
12021 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
12022 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
12023 if (!(float32_is_zero(a) || float32_is_zero(b))) {
12024 float_raise(float_flag_input_denormal, s);
12025 }
12026 return float32_two;
12027 }
12028 return float32_sub(float32_two, float32_mul(a, b, s), s);
12029 }
12030
12031 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
12032 {
12033 float_status *s = &env->vfp.standard_fp_status;
12034 float32 product;
12035 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
12036 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
12037 if (!(float32_is_zero(a) || float32_is_zero(b))) {
12038 float_raise(float_flag_input_denormal, s);
12039 }
12040 return float32_one_point_five;
12041 }
12042 product = float32_mul(a, b, s);
12043 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
12044 }
12045
12046 /* NEON helpers. */
12047
12048 /* Constants 256 and 512 are used in some helpers; we avoid relying on
12049 * int->float conversions at run-time. */
12050 #define float64_256 make_float64(0x4070000000000000LL)
12051 #define float64_512 make_float64(0x4080000000000000LL)
12052 #define float16_maxnorm make_float16(0x7bff)
12053 #define float32_maxnorm make_float32(0x7f7fffff)
12054 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
12055
12056 /* Reciprocal functions
12057 *
12058 * The algorithm that must be used to calculate the estimate
12059 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
12060 */
12061
12062 /* See RecipEstimate()
12063 *
12064 * input is a 9 bit fixed point number
12065 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
12066 * result range 256 .. 511 for a number from 1.0 to 511/256.
12067 */
12068
12069 static int recip_estimate(int input)
12070 {
12071 int a, b, r;
12072 assert(256 <= input && input < 512);
12073 a = (input * 2) + 1;
12074 b = (1 << 19) / a;
12075 r = (b + 1) >> 1;
12076 assert(256 <= r && r < 512);
12077 return r;
12078 }
12079
12080 /*
12081 * Common wrapper to call recip_estimate
12082 *
12083 * The parameters are exponent and 64 bit fraction (without implicit
12084 * bit) where the binary point is nominally at bit 52. Returns a
12085 * float64 which can then be rounded to the appropriate size by the
12086 * callee.
12087 */
12088
12089 static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
12090 {
12091 uint32_t scaled, estimate;
12092 uint64_t result_frac;
12093 int result_exp;
12094
12095 /* Handle sub-normals */
12096 if (*exp == 0) {
12097 if (extract64(frac, 51, 1) == 0) {
12098 *exp = -1;
12099 frac <<= 2;
12100 } else {
12101 frac <<= 1;
12102 }
12103 }
12104
12105 /* scaled = UInt('1':fraction<51:44>) */
12106 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
12107 estimate = recip_estimate(scaled);
12108
12109 result_exp = exp_off - *exp;
12110 result_frac = deposit64(0, 44, 8, estimate);
12111 if (result_exp == 0) {
12112 result_frac = deposit64(result_frac >> 1, 51, 1, 1);
12113 } else if (result_exp == -1) {
12114 result_frac = deposit64(result_frac >> 2, 50, 2, 1);
12115 result_exp = 0;
12116 }
12117
12118 *exp = result_exp;
12119
12120 return result_frac;
12121 }
12122
12123 static bool round_to_inf(float_status *fpst, bool sign_bit)
12124 {
12125 switch (fpst->float_rounding_mode) {
12126 case float_round_nearest_even: /* Round to Nearest */
12127 return true;
12128 case float_round_up: /* Round to +Inf */
12129 return !sign_bit;
12130 case float_round_down: /* Round to -Inf */
12131 return sign_bit;
12132 case float_round_to_zero: /* Round to Zero */
12133 return false;
12134 }
12135
12136 g_assert_not_reached();
12137 }
12138
12139 uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
12140 {
12141 float_status *fpst = fpstp;
12142 float16 f16 = float16_squash_input_denormal(input, fpst);
12143 uint32_t f16_val = float16_val(f16);
12144 uint32_t f16_sign = float16_is_neg(f16);
12145 int f16_exp = extract32(f16_val, 10, 5);
12146 uint32_t f16_frac = extract32(f16_val, 0, 10);
12147 uint64_t f64_frac;
12148
12149 if (float16_is_any_nan(f16)) {
12150 float16 nan = f16;
12151 if (float16_is_signaling_nan(f16, fpst)) {
12152 float_raise(float_flag_invalid, fpst);
12153 nan = float16_silence_nan(f16, fpst);
12154 }
12155 if (fpst->default_nan_mode) {
12156 nan = float16_default_nan(fpst);
12157 }
12158 return nan;
12159 } else if (float16_is_infinity(f16)) {
12160 return float16_set_sign(float16_zero, float16_is_neg(f16));
12161 } else if (float16_is_zero(f16)) {
12162 float_raise(float_flag_divbyzero, fpst);
12163 return float16_set_sign(float16_infinity, float16_is_neg(f16));
12164 } else if (float16_abs(f16) < (1 << 8)) {
12165 /* Abs(value) < 2.0^-16 */
12166 float_raise(float_flag_overflow | float_flag_inexact, fpst);
12167 if (round_to_inf(fpst, f16_sign)) {
12168 return float16_set_sign(float16_infinity, f16_sign);
12169 } else {
12170 return float16_set_sign(float16_maxnorm, f16_sign);
12171 }
12172 } else if (f16_exp >= 29 && fpst->flush_to_zero) {
12173 float_raise(float_flag_underflow, fpst);
12174 return float16_set_sign(float16_zero, float16_is_neg(f16));
12175 }
12176
12177 f64_frac = call_recip_estimate(&f16_exp, 29,
12178 ((uint64_t) f16_frac) << (52 - 10));
12179
12180 /* result = sign : result_exp<4:0> : fraction<51:42> */
12181 f16_val = deposit32(0, 15, 1, f16_sign);
12182 f16_val = deposit32(f16_val, 10, 5, f16_exp);
12183 f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
12184 return make_float16(f16_val);
12185 }
12186
12187 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
12188 {
12189 float_status *fpst = fpstp;
12190 float32 f32 = float32_squash_input_denormal(input, fpst);
12191 uint32_t f32_val = float32_val(f32);
12192 bool f32_sign = float32_is_neg(f32);
12193 int f32_exp = extract32(f32_val, 23, 8);
12194 uint32_t f32_frac = extract32(f32_val, 0, 23);
12195 uint64_t f64_frac;
12196
12197 if (float32_is_any_nan(f32)) {
12198 float32 nan = f32;
12199 if (float32_is_signaling_nan(f32, fpst)) {
12200 float_raise(float_flag_invalid, fpst);
12201 nan = float32_silence_nan(f32, fpst);
12202 }
12203 if (fpst->default_nan_mode) {
12204 nan = float32_default_nan(fpst);
12205 }
12206 return nan;
12207 } else if (float32_is_infinity(f32)) {
12208 return float32_set_sign(float32_zero, float32_is_neg(f32));
12209 } else if (float32_is_zero(f32)) {
12210 float_raise(float_flag_divbyzero, fpst);
12211 return float32_set_sign(float32_infinity, float32_is_neg(f32));
12212 } else if (float32_abs(f32) < (1ULL << 21)) {
12213 /* Abs(value) < 2.0^-128 */
12214 float_raise(float_flag_overflow | float_flag_inexact, fpst);
12215 if (round_to_inf(fpst, f32_sign)) {
12216 return float32_set_sign(float32_infinity, f32_sign);
12217 } else {
12218 return float32_set_sign(float32_maxnorm, f32_sign);
12219 }
12220 } else if (f32_exp >= 253 && fpst->flush_to_zero) {
12221 float_raise(float_flag_underflow, fpst);
12222 return float32_set_sign(float32_zero, float32_is_neg(f32));
12223 }
12224
12225 f64_frac = call_recip_estimate(&f32_exp, 253,
12226 ((uint64_t) f32_frac) << (52 - 23));
12227
12228 /* result = sign : result_exp<7:0> : fraction<51:29> */
12229 f32_val = deposit32(0, 31, 1, f32_sign);
12230 f32_val = deposit32(f32_val, 23, 8, f32_exp);
12231 f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
12232 return make_float32(f32_val);
12233 }
12234
12235 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
12236 {
12237 float_status *fpst = fpstp;
12238 float64 f64 = float64_squash_input_denormal(input, fpst);
12239 uint64_t f64_val = float64_val(f64);
12240 bool f64_sign = float64_is_neg(f64);
12241 int f64_exp = extract64(f64_val, 52, 11);
12242 uint64_t f64_frac = extract64(f64_val, 0, 52);
12243
12244 /* Deal with any special cases */
12245 if (float64_is_any_nan(f64)) {
12246 float64 nan = f64;
12247 if (float64_is_signaling_nan(f64, fpst)) {
12248 float_raise(float_flag_invalid, fpst);
12249 nan = float64_silence_nan(f64, fpst);
12250 }
12251 if (fpst->default_nan_mode) {
12252 nan = float64_default_nan(fpst);
12253 }
12254 return nan;
12255 } else if (float64_is_infinity(f64)) {
12256 return float64_set_sign(float64_zero, float64_is_neg(f64));
12257 } else if (float64_is_zero(f64)) {
12258 float_raise(float_flag_divbyzero, fpst);
12259 return float64_set_sign(float64_infinity, float64_is_neg(f64));
12260 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
12261 /* Abs(value) < 2.0^-1024 */
12262 float_raise(float_flag_overflow | float_flag_inexact, fpst);
12263 if (round_to_inf(fpst, f64_sign)) {
12264 return float64_set_sign(float64_infinity, f64_sign);
12265 } else {
12266 return float64_set_sign(float64_maxnorm, f64_sign);
12267 }
12268 } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
12269 float_raise(float_flag_underflow, fpst);
12270 return float64_set_sign(float64_zero, float64_is_neg(f64));
12271 }
12272
12273 f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
12274
12275 /* result = sign : result_exp<10:0> : fraction<51:0>; */
12276 f64_val = deposit64(0, 63, 1, f64_sign);
12277 f64_val = deposit64(f64_val, 52, 11, f64_exp);
12278 f64_val = deposit64(f64_val, 0, 52, f64_frac);
12279 return make_float64(f64_val);
12280 }
12281
12282 /* The algorithm that must be used to calculate the estimate
12283 * is specified by the ARM ARM.
12284 */
12285
12286 static int do_recip_sqrt_estimate(int a)
12287 {
12288 int b, estimate;
12289
12290 assert(128 <= a && a < 512);
12291 if (a < 256) {
12292 a = a * 2 + 1;
12293 } else {
12294 a = (a >> 1) << 1;
12295 a = (a + 1) * 2;
12296 }
12297 b = 512;
12298 while (a * (b + 1) * (b + 1) < (1 << 28)) {
12299 b += 1;
12300 }
12301 estimate = (b + 1) / 2;
12302 assert(256 <= estimate && estimate < 512);
12303
12304 return estimate;
12305 }
12306
12307
12308 static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
12309 {
12310 int estimate;
12311 uint32_t scaled;
12312
12313 if (*exp == 0) {
12314 while (extract64(frac, 51, 1) == 0) {
12315 frac = frac << 1;
12316 *exp -= 1;
12317 }
12318 frac = extract64(frac, 0, 51) << 1;
12319 }
12320
12321 if (*exp & 1) {
12322 /* scaled = UInt('01':fraction<51:45>) */
12323 scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
12324 } else {
12325 /* scaled = UInt('1':fraction<51:44>) */
12326 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
12327 }
12328 estimate = do_recip_sqrt_estimate(scaled);
12329
12330 *exp = (exp_off - *exp) / 2;
12331 return extract64(estimate, 0, 8) << 44;
12332 }
12333
12334 uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
12335 {
12336 float_status *s = fpstp;
12337 float16 f16 = float16_squash_input_denormal(input, s);
12338 uint16_t val = float16_val(f16);
12339 bool f16_sign = float16_is_neg(f16);
12340 int f16_exp = extract32(val, 10, 5);
12341 uint16_t f16_frac = extract32(val, 0, 10);
12342 uint64_t f64_frac;
12343
12344 if (float16_is_any_nan(f16)) {
12345 float16 nan = f16;
12346 if (float16_is_signaling_nan(f16, s)) {
12347 float_raise(float_flag_invalid, s);
12348 nan = float16_silence_nan(f16, s);
12349 }
12350 if (s->default_nan_mode) {
12351 nan = float16_default_nan(s);
12352 }
12353 return nan;
12354 } else if (float16_is_zero(f16)) {
12355 float_raise(float_flag_divbyzero, s);
12356 return float16_set_sign(float16_infinity, f16_sign);
12357 } else if (f16_sign) {
12358 float_raise(float_flag_invalid, s);
12359 return float16_default_nan(s);
12360 } else if (float16_is_infinity(f16)) {
12361 return float16_zero;
12362 }
12363
12364 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
12365 * preserving the parity of the exponent. */
12366
12367 f64_frac = ((uint64_t) f16_frac) << (52 - 10);
12368
12369 f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
12370
12371 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
12372 val = deposit32(0, 15, 1, f16_sign);
12373 val = deposit32(val, 10, 5, f16_exp);
12374 val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
12375 return make_float16(val);
12376 }
12377
12378 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
12379 {
12380 float_status *s = fpstp;
12381 float32 f32 = float32_squash_input_denormal(input, s);
12382 uint32_t val = float32_val(f32);
12383 uint32_t f32_sign = float32_is_neg(f32);
12384 int f32_exp = extract32(val, 23, 8);
12385 uint32_t f32_frac = extract32(val, 0, 23);
12386 uint64_t f64_frac;
12387
12388 if (float32_is_any_nan(f32)) {
12389 float32 nan = f32;
12390 if (float32_is_signaling_nan(f32, s)) {
12391 float_raise(float_flag_invalid, s);
12392 nan = float32_silence_nan(f32, s);
12393 }
12394 if (s->default_nan_mode) {
12395 nan = float32_default_nan(s);
12396 }
12397 return nan;
12398 } else if (float32_is_zero(f32)) {
12399 float_raise(float_flag_divbyzero, s);
12400 return float32_set_sign(float32_infinity, float32_is_neg(f32));
12401 } else if (float32_is_neg(f32)) {
12402 float_raise(float_flag_invalid, s);
12403 return float32_default_nan(s);
12404 } else if (float32_is_infinity(f32)) {
12405 return float32_zero;
12406 }
12407
12408 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
12409 * preserving the parity of the exponent. */
12410
12411 f64_frac = ((uint64_t) f32_frac) << 29;
12412
12413 f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
12414
12415 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
12416 val = deposit32(0, 31, 1, f32_sign);
12417 val = deposit32(val, 23, 8, f32_exp);
12418 val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
12419 return make_float32(val);
12420 }
12421
12422 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
12423 {
12424 float_status *s = fpstp;
12425 float64 f64 = float64_squash_input_denormal(input, s);
12426 uint64_t val = float64_val(f64);
12427 bool f64_sign = float64_is_neg(f64);
12428 int f64_exp = extract64(val, 52, 11);
12429 uint64_t f64_frac = extract64(val, 0, 52);
12430
12431 if (float64_is_any_nan(f64)) {
12432 float64 nan = f64;
12433 if (float64_is_signaling_nan(f64, s)) {
12434 float_raise(float_flag_invalid, s);
12435 nan = float64_silence_nan(f64, s);
12436 }
12437 if (s->default_nan_mode) {
12438 nan = float64_default_nan(s);
12439 }
12440 return nan;
12441 } else if (float64_is_zero(f64)) {
12442 float_raise(float_flag_divbyzero, s);
12443 return float64_set_sign(float64_infinity, float64_is_neg(f64));
12444 } else if (float64_is_neg(f64)) {
12445 float_raise(float_flag_invalid, s);
12446 return float64_default_nan(s);
12447 } else if (float64_is_infinity(f64)) {
12448 return float64_zero;
12449 }
12450
12451 f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
12452
12453 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
12454 val = deposit64(0, 61, 1, f64_sign);
12455 val = deposit64(val, 52, 11, f64_exp);
12456 val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
12457 return make_float64(val);
12458 }
12459
12460 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
12461 {
12462 /* float_status *s = fpstp; */
12463 int input, estimate;
12464
12465 if ((a & 0x80000000) == 0) {
12466 return 0xffffffff;
12467 }
12468
12469 input = extract32(a, 23, 9);
12470 estimate = recip_estimate(input);
12471
12472 return deposit32(0, (32 - 9), 9, estimate);
12473 }
12474
12475 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
12476 {
12477 int estimate;
12478
12479 if ((a & 0xc0000000) == 0) {
12480 return 0xffffffff;
12481 }
12482
12483 estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
12484
12485 return deposit32(0, 23, 9, estimate);
12486 }
12487
12488 /* VFPv4 fused multiply-accumulate */
12489 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
12490 {
12491 float_status *fpst = fpstp;
12492 return float32_muladd(a, b, c, 0, fpst);
12493 }
12494
12495 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
12496 {
12497 float_status *fpst = fpstp;
12498 return float64_muladd(a, b, c, 0, fpst);
12499 }
12500
12501 /* ARMv8 round to integral */
12502 float32 HELPER(rints_exact)(float32 x, void *fp_status)
12503 {
12504 return float32_round_to_int(x, fp_status);
12505 }
12506
12507 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
12508 {
12509 return float64_round_to_int(x, fp_status);
12510 }
12511
12512 float32 HELPER(rints)(float32 x, void *fp_status)
12513 {
12514 int old_flags = get_float_exception_flags(fp_status), new_flags;
12515 float32 ret;
12516
12517 ret = float32_round_to_int(x, fp_status);
12518
12519 /* Suppress any inexact exceptions the conversion produced */
12520 if (!(old_flags & float_flag_inexact)) {
12521 new_flags = get_float_exception_flags(fp_status);
12522 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
12523 }
12524
12525 return ret;
12526 }
12527
12528 float64 HELPER(rintd)(float64 x, void *fp_status)
12529 {
12530 int old_flags = get_float_exception_flags(fp_status), new_flags;
12531 float64 ret;
12532
12533 ret = float64_round_to_int(x, fp_status);
12534
12535 new_flags = get_float_exception_flags(fp_status);
12536
12537 /* Suppress any inexact exceptions the conversion produced */
12538 if (!(old_flags & float_flag_inexact)) {
12539 new_flags = get_float_exception_flags(fp_status);
12540 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
12541 }
12542
12543 return ret;
12544 }
12545
12546 /* Convert ARM rounding mode to softfloat */
12547 int arm_rmode_to_sf(int rmode)
12548 {
12549 switch (rmode) {
12550 case FPROUNDING_TIEAWAY:
12551 rmode = float_round_ties_away;
12552 break;
12553 case FPROUNDING_ODD:
12554 /* FIXME: add support for TIEAWAY and ODD */
12555 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
12556 rmode);
12557 /* fall through for now */
12558 case FPROUNDING_TIEEVEN:
12559 default:
12560 rmode = float_round_nearest_even;
12561 break;
12562 case FPROUNDING_POSINF:
12563 rmode = float_round_up;
12564 break;
12565 case FPROUNDING_NEGINF:
12566 rmode = float_round_down;
12567 break;
12568 case FPROUNDING_ZERO:
12569 rmode = float_round_to_zero;
12570 break;
12571 }
12572 return rmode;
12573 }
12574
12575 /* CRC helpers.
12576 * The upper bytes of val (above the number specified by 'bytes') must have
12577 * been zeroed out by the caller.
12578 */
12579 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
12580 {
12581 uint8_t buf[4];
12582
12583 stl_le_p(buf, val);
12584
12585 /* zlib crc32 converts the accumulator and output to one's complement. */
12586 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
12587 }
12588
12589 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
12590 {
12591 uint8_t buf[4];
12592
12593 stl_le_p(buf, val);
12594
12595 /* Linux crc32c converts the output to one's complement. */
12596 return crc32c(acc, buf, bytes) ^ 0xffffffff;
12597 }
12598
12599 /* Return the exception level to which FP-disabled exceptions should
12600 * be taken, or 0 if FP is enabled.
12601 */
12602 int fp_exception_el(CPUARMState *env, int cur_el)
12603 {
12604 #ifndef CONFIG_USER_ONLY
12605 int fpen;
12606
12607 /* CPACR and the CPTR registers don't exist before v6, so FP is
12608 * always accessible
12609 */
12610 if (!arm_feature(env, ARM_FEATURE_V6)) {
12611 return 0;
12612 }
12613
12614 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12615 * 0, 2 : trap EL0 and EL1/PL1 accesses
12616 * 1 : trap only EL0 accesses
12617 * 3 : trap no accesses
12618 */
12619 fpen = extract32(env->cp15.cpacr_el1, 20, 2);
12620 switch (fpen) {
12621 case 0:
12622 case 2:
12623 if (cur_el == 0 || cur_el == 1) {
12624 /* Trap to PL1, which might be EL1 or EL3 */
12625 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
12626 return 3;
12627 }
12628 return 1;
12629 }
12630 if (cur_el == 3 && !is_a64(env)) {
12631 /* Secure PL1 running at EL3 */
12632 return 3;
12633 }
12634 break;
12635 case 1:
12636 if (cur_el == 0) {
12637 return 1;
12638 }
12639 break;
12640 case 3:
12641 break;
12642 }
12643
12644 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
12645 * check because zero bits in the registers mean "don't trap".
12646 */
12647
12648 /* CPTR_EL2 : present in v7VE or v8 */
12649 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
12650 && !arm_is_secure_below_el3(env)) {
12651 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
12652 return 2;
12653 }
12654
12655 /* CPTR_EL3 : present in v8 */
12656 if (extract32(env->cp15.cptr_el[3], 10, 1)) {
12657 /* Trap all FP ops to EL3 */
12658 return 3;
12659 }
12660 #endif
12661 return 0;
12662 }
12663
12664 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
12665 target_ulong *cs_base, uint32_t *pflags)
12666 {
12667 ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
12668 int current_el = arm_current_el(env);
12669 int fp_el = fp_exception_el(env, current_el);
12670 uint32_t flags;
12671
12672 if (is_a64(env)) {
12673 *pc = env->pc;
12674 flags = ARM_TBFLAG_AARCH64_STATE_MASK;
12675 /* Get control bits for tagged addresses */
12676 flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT);
12677 flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT);
12678
12679 if (arm_feature(env, ARM_FEATURE_SVE)) {
12680 int sve_el = sve_exception_el(env, current_el);
12681 uint32_t zcr_len;
12682
12683 /* If SVE is disabled, but FP is enabled,
12684 * then the effective len is 0.
12685 */
12686 if (sve_el != 0 && fp_el == 0) {
12687 zcr_len = 0;
12688 } else {
12689 zcr_len = sve_zcr_len_for_el(env, current_el);
12690 }
12691 flags |= sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT;
12692 flags |= zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT;
12693 }
12694 } else {
12695 *pc = env->regs[15];
12696 flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
12697 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
12698 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
12699 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
12700 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT);
12701 if (!(access_secure_reg(env))) {
12702 flags |= ARM_TBFLAG_NS_MASK;
12703 }
12704 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
12705 || arm_el_is_aa64(env, 1)) {
12706 flags |= ARM_TBFLAG_VFPEN_MASK;
12707 }
12708 flags |= (extract32(env->cp15.c15_cpar, 0, 2)
12709 << ARM_TBFLAG_XSCALE_CPAR_SHIFT);
12710 }
12711
12712 flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT);
12713
12714 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12715 * states defined in the ARM ARM for software singlestep:
12716 * SS_ACTIVE PSTATE.SS State
12717 * 0 x Inactive (the TB flag for SS is always 0)
12718 * 1 0 Active-pending
12719 * 1 1 Active-not-pending
12720 */
12721 if (arm_singlestep_active(env)) {
12722 flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
12723 if (is_a64(env)) {
12724 if (env->pstate & PSTATE_SS) {
12725 flags |= ARM_TBFLAG_PSTATE_SS_MASK;
12726 }
12727 } else {
12728 if (env->uncached_cpsr & PSTATE_SS) {
12729 flags |= ARM_TBFLAG_PSTATE_SS_MASK;
12730 }
12731 }
12732 }
12733 if (arm_cpu_data_is_big_endian(env)) {
12734 flags |= ARM_TBFLAG_BE_DATA_MASK;
12735 }
12736 flags |= fp_el << ARM_TBFLAG_FPEXC_EL_SHIFT;
12737
12738 if (arm_v7m_is_handler_mode(env)) {
12739 flags |= ARM_TBFLAG_HANDLER_MASK;
12740 }
12741
12742 /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is
12743 * suppressing them because the requested execution priority is less than 0.
12744 */
12745 if (arm_feature(env, ARM_FEATURE_V8) &&
12746 arm_feature(env, ARM_FEATURE_M) &&
12747 !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
12748 (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
12749 flags |= ARM_TBFLAG_STACKCHECK_MASK;
12750 }
12751
12752 *pflags = flags;
12753 *cs_base = 0;
12754 }
12755
12756 #ifdef TARGET_AARCH64
12757 /*
12758 * The manual says that when SVE is enabled and VQ is widened the
12759 * implementation is allowed to zero the previously inaccessible
12760 * portion of the registers. The corollary to that is that when
12761 * SVE is enabled and VQ is narrowed we are also allowed to zero
12762 * the now inaccessible portion of the registers.
12763 *
12764 * The intent of this is that no predicate bit beyond VQ is ever set.
12765 * Which means that some operations on predicate registers themselves
12766 * may operate on full uint64_t or even unrolled across the maximum
12767 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12768 * may well be cheaper than conditionals to restrict the operation
12769 * to the relevant portion of a uint16_t[16].
12770 */
12771 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
12772 {
12773 int i, j;
12774 uint64_t pmask;
12775
12776 assert(vq >= 1 && vq <= ARM_MAX_VQ);
12777 assert(vq <= arm_env_get_cpu(env)->sve_max_vq);
12778
12779 /* Zap the high bits of the zregs. */
12780 for (i = 0; i < 32; i++) {
12781 memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq));
12782 }
12783
12784 /* Zap the high bits of the pregs and ffr. */
12785 pmask = 0;
12786 if (vq & 3) {
12787 pmask = ~(-1ULL << (16 * (vq & 3)));
12788 }
12789 for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) {
12790 for (i = 0; i < 17; ++i) {
12791 env->vfp.pregs[i].p[j] &= pmask;
12792 }
12793 pmask = 0;
12794 }
12795 }
12796
12797 /*
12798 * Notice a change in SVE vector size when changing EL.
12799 */
12800 void aarch64_sve_change_el(CPUARMState *env, int old_el,
12801 int new_el, bool el0_a64)
12802 {
12803 int old_len, new_len;
12804 bool old_a64, new_a64;
12805
12806 /* Nothing to do if no SVE. */
12807 if (!arm_feature(env, ARM_FEATURE_SVE)) {
12808 return;
12809 }
12810
12811 /* Nothing to do if FP is disabled in either EL. */
12812 if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) {
12813 return;
12814 }
12815
12816 /*
12817 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12818 * at ELx, or not available because the EL is in AArch32 state, then
12819 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12820 * has an effective value of 0".
12821 *
12822 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12823 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12824 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12825 * we already have the correct register contents when encountering the
12826 * vq0->vq0 transition between EL0->EL1.
12827 */
12828 old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
12829 old_len = (old_a64 && !sve_exception_el(env, old_el)
12830 ? sve_zcr_len_for_el(env, old_el) : 0);
12831 new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
12832 new_len = (new_a64 && !sve_exception_el(env, new_el)
12833 ? sve_zcr_len_for_el(env, new_el) : 0);
12834
12835 /* When changing vector length, clear inaccessible state. */
12836 if (new_len < old_len) {
12837 aarch64_sve_narrow_vq(env, new_len + 1);
12838 }
12839 }
12840 #endif
AR7 emulation for QEMU