slirp: Generalizing and neutralizing ARP code
[qemu/ar7.git] / target-openrisc / cpu.c
blobcafc07f7889787ae5f425ef8e6d80bba1eef3c09
1 /*
2 * QEMU OpenRISC CPU
4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "qemu-common.h"
24 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
26 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
28 cpu->env.pc = value;
31 static bool openrisc_cpu_has_work(CPUState *cs)
33 return cs->interrupt_request & (CPU_INTERRUPT_HARD |
34 CPU_INTERRUPT_TIMER);
37 /* CPUClass::reset() */
38 static void openrisc_cpu_reset(CPUState *s)
40 OpenRISCCPU *cpu = OPENRISC_CPU(s);
41 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
43 occ->parent_reset(s);
45 #ifndef CONFIG_USER_ONLY
46 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, tlb));
47 #else
48 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq));
49 #endif
51 tlb_flush(s, 1);
52 /*tb_flush(&cpu->env); FIXME: Do we need it? */
54 cpu->env.pc = 0x100;
55 cpu->env.sr = SR_FO | SR_SM;
56 s->exception_index = -1;
58 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
59 cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
60 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
61 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
63 #ifndef CONFIG_USER_ONLY
64 cpu->env.picmr = 0x00000000;
65 cpu->env.picsr = 0x00000000;
67 cpu->env.ttmr = 0x00000000;
68 cpu->env.ttcr = 0x00000000;
69 #endif
72 static inline void set_feature(OpenRISCCPU *cpu, int feature)
74 cpu->feature |= feature;
75 cpu->env.cpucfgr = cpu->feature;
78 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
80 CPUState *cs = CPU(dev);
81 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
83 qemu_init_vcpu(cs);
84 cpu_reset(cs);
86 occ->parent_realize(dev, errp);
89 static void openrisc_cpu_initfn(Object *obj)
91 CPUState *cs = CPU(obj);
92 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
93 static int inited;
95 cs->env_ptr = &cpu->env;
96 cpu_exec_init(cs, &error_abort);
98 #ifndef CONFIG_USER_ONLY
99 cpu_openrisc_mmu_init(cpu);
100 #endif
102 if (tcg_enabled() && !inited) {
103 inited = 1;
104 openrisc_translate_init();
108 /* CPU models */
110 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
112 ObjectClass *oc;
113 char *typename;
115 if (cpu_model == NULL) {
116 return NULL;
119 typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model);
120 oc = object_class_by_name(typename);
121 g_free(typename);
122 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
123 object_class_is_abstract(oc))) {
124 return NULL;
126 return oc;
129 static void or1200_initfn(Object *obj)
131 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
133 set_feature(cpu, OPENRISC_FEATURE_OB32S);
134 set_feature(cpu, OPENRISC_FEATURE_OF32S);
137 static void openrisc_any_initfn(Object *obj)
139 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
141 set_feature(cpu, OPENRISC_FEATURE_OB32S);
144 typedef struct OpenRISCCPUInfo {
145 const char *name;
146 void (*initfn)(Object *obj);
147 } OpenRISCCPUInfo;
149 static const OpenRISCCPUInfo openrisc_cpus[] = {
150 { .name = "or1200", .initfn = or1200_initfn },
151 { .name = "any", .initfn = openrisc_any_initfn },
154 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
156 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
157 CPUClass *cc = CPU_CLASS(occ);
158 DeviceClass *dc = DEVICE_CLASS(oc);
160 occ->parent_realize = dc->realize;
161 dc->realize = openrisc_cpu_realizefn;
163 occ->parent_reset = cc->reset;
164 cc->reset = openrisc_cpu_reset;
166 cc->class_by_name = openrisc_cpu_class_by_name;
167 cc->has_work = openrisc_cpu_has_work;
168 cc->do_interrupt = openrisc_cpu_do_interrupt;
169 cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
170 cc->dump_state = openrisc_cpu_dump_state;
171 cc->set_pc = openrisc_cpu_set_pc;
172 cc->gdb_read_register = openrisc_cpu_gdb_read_register;
173 cc->gdb_write_register = openrisc_cpu_gdb_write_register;
174 #ifdef CONFIG_USER_ONLY
175 cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault;
176 #else
177 cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
178 dc->vmsd = &vmstate_openrisc_cpu;
179 #endif
180 cc->gdb_num_core_regs = 32 + 3;
183 * Reason: openrisc_cpu_initfn() calls cpu_exec_init(), which saves
184 * the object in cpus -> dangling pointer after final
185 * object_unref().
187 dc->cannot_destroy_with_object_finalize_yet = true;
190 static void cpu_register(const OpenRISCCPUInfo *info)
192 TypeInfo type_info = {
193 .parent = TYPE_OPENRISC_CPU,
194 .instance_size = sizeof(OpenRISCCPU),
195 .instance_init = info->initfn,
196 .class_size = sizeof(OpenRISCCPUClass),
199 type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
200 type_register(&type_info);
201 g_free((void *)type_info.name);
204 static const TypeInfo openrisc_cpu_type_info = {
205 .name = TYPE_OPENRISC_CPU,
206 .parent = TYPE_CPU,
207 .instance_size = sizeof(OpenRISCCPU),
208 .instance_init = openrisc_cpu_initfn,
209 .abstract = true,
210 .class_size = sizeof(OpenRISCCPUClass),
211 .class_init = openrisc_cpu_class_init,
214 static void openrisc_cpu_register_types(void)
216 int i;
218 type_register_static(&openrisc_cpu_type_info);
219 for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
220 cpu_register(&openrisc_cpus[i]);
224 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
226 return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model));
229 /* Sort alphabetically by type name, except for "any". */
230 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
232 ObjectClass *class_a = (ObjectClass *)a;
233 ObjectClass *class_b = (ObjectClass *)b;
234 const char *name_a, *name_b;
236 name_a = object_class_get_name(class_a);
237 name_b = object_class_get_name(class_b);
238 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
239 return 1;
240 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
241 return -1;
242 } else {
243 return strcmp(name_a, name_b);
247 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
249 ObjectClass *oc = data;
250 CPUListState *s = user_data;
251 const char *typename;
252 char *name;
254 typename = object_class_get_name(oc);
255 name = g_strndup(typename,
256 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
257 (*s->cpu_fprintf)(s->file, " %s\n",
258 name);
259 g_free(name);
262 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
264 CPUListState s = {
265 .file = f,
266 .cpu_fprintf = cpu_fprintf,
268 GSList *list;
270 list = object_class_get_list(TYPE_OPENRISC_CPU, false);
271 list = g_slist_sort(list, openrisc_cpu_list_compare);
272 (*cpu_fprintf)(f, "Available CPUs:\n");
273 g_slist_foreach(list, openrisc_cpu_list_entry, &s);
274 g_slist_free(list);
277 type_init(openrisc_cpu_register_types)