2 * I/O instructions for S/390
4 * Copyright 2012, 2015 IBM Corp.
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
8 * your option) any later version. See the COPYING file in the top-level
12 #include "qemu/osdep.h"
16 #include "hw/s390x/ioinst.h"
18 #include "hw/s390x/s390-pci-bus.h"
20 int ioinst_disassemble_sch_ident(uint32_t value
, int *m
, int *cssid
, int *ssid
,
23 if (!IOINST_SCHID_ONE(value
)) {
26 if (!IOINST_SCHID_M(value
)) {
27 if (IOINST_SCHID_CSSID(value
)) {
33 *cssid
= IOINST_SCHID_CSSID(value
);
36 *ssid
= IOINST_SCHID_SSID(value
);
37 *schid
= IOINST_SCHID_NR(value
);
41 void ioinst_handle_xsch(S390CPU
*cpu
, uint64_t reg1
)
43 int cssid
, ssid
, schid
, m
;
46 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
47 program_interrupt(&cpu
->env
, PGM_OPERAND
, 4);
50 trace_ioinst_sch_id("xsch", cssid
, ssid
, schid
);
51 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
52 if (!sch
|| !css_subch_visible(sch
)) {
56 setcc(cpu
, css_do_xsch(sch
));
59 void ioinst_handle_csch(S390CPU
*cpu
, uint64_t reg1
)
61 int cssid
, ssid
, schid
, m
;
64 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
65 program_interrupt(&cpu
->env
, PGM_OPERAND
, 4);
68 trace_ioinst_sch_id("csch", cssid
, ssid
, schid
);
69 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
70 if (!sch
|| !css_subch_visible(sch
)) {
74 setcc(cpu
, css_do_csch(sch
));
77 void ioinst_handle_hsch(S390CPU
*cpu
, uint64_t reg1
)
79 int cssid
, ssid
, schid
, m
;
82 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
83 program_interrupt(&cpu
->env
, PGM_OPERAND
, 4);
86 trace_ioinst_sch_id("hsch", cssid
, ssid
, schid
);
87 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
88 if (!sch
|| !css_subch_visible(sch
)) {
92 setcc(cpu
, css_do_hsch(sch
));
95 static int ioinst_schib_valid(SCHIB
*schib
)
97 if ((be16_to_cpu(schib
->pmcw
.flags
) & PMCW_FLAGS_MASK_INVALID
) ||
98 (be32_to_cpu(schib
->pmcw
.chars
) & PMCW_CHARS_MASK_INVALID
)) {
101 /* Disallow extended measurements for now. */
102 if (be32_to_cpu(schib
->pmcw
.chars
) & PMCW_CHARS_MASK_XMWME
) {
108 void ioinst_handle_msch(S390CPU
*cpu
, uint64_t reg1
, uint32_t ipb
)
110 int cssid
, ssid
, schid
, m
;
114 CPUS390XState
*env
= &cpu
->env
;
117 addr
= decode_basedisp_s(env
, ipb
, &ar
);
119 program_interrupt(env
, PGM_SPECIFICATION
, 4);
122 if (s390_cpu_virt_mem_read(cpu
, addr
, ar
, &schib
, sizeof(schib
))) {
125 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
) ||
126 !ioinst_schib_valid(&schib
)) {
127 program_interrupt(env
, PGM_OPERAND
, 4);
130 trace_ioinst_sch_id("msch", cssid
, ssid
, schid
);
131 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
132 if (!sch
|| !css_subch_visible(sch
)) {
136 setcc(cpu
, css_do_msch(sch
, &schib
));
139 static void copy_orb_from_guest(ORB
*dest
, const ORB
*src
)
141 dest
->intparm
= be32_to_cpu(src
->intparm
);
142 dest
->ctrl0
= be16_to_cpu(src
->ctrl0
);
143 dest
->lpm
= src
->lpm
;
144 dest
->ctrl1
= src
->ctrl1
;
145 dest
->cpa
= be32_to_cpu(src
->cpa
);
148 static int ioinst_orb_valid(ORB
*orb
)
150 if ((orb
->ctrl0
& ORB_CTRL0_MASK_INVALID
) ||
151 (orb
->ctrl1
& ORB_CTRL1_MASK_INVALID
)) {
154 /* We don't support MIDA. */
155 if (orb
->ctrl1
& ORB_CTRL1_MASK_MIDAW
) {
158 if ((orb
->cpa
& HIGH_ORDER_BIT
) != 0) {
164 void ioinst_handle_ssch(S390CPU
*cpu
, uint64_t reg1
, uint32_t ipb
)
166 int cssid
, ssid
, schid
, m
;
170 CPUS390XState
*env
= &cpu
->env
;
173 addr
= decode_basedisp_s(env
, ipb
, &ar
);
175 program_interrupt(env
, PGM_SPECIFICATION
, 4);
178 if (s390_cpu_virt_mem_read(cpu
, addr
, ar
, &orig_orb
, sizeof(orb
))) {
181 copy_orb_from_guest(&orb
, &orig_orb
);
182 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
) ||
183 !ioinst_orb_valid(&orb
)) {
184 program_interrupt(env
, PGM_OPERAND
, 4);
187 trace_ioinst_sch_id("ssch", cssid
, ssid
, schid
);
188 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
189 if (!sch
|| !css_subch_visible(sch
)) {
193 setcc(cpu
, css_do_ssch(sch
, &orb
));
196 void ioinst_handle_stcrw(S390CPU
*cpu
, uint32_t ipb
)
201 CPUS390XState
*env
= &cpu
->env
;
204 addr
= decode_basedisp_s(env
, ipb
, &ar
);
206 program_interrupt(env
, PGM_SPECIFICATION
, 4);
210 cc
= css_do_stcrw(&crw
);
211 /* 0 - crw stored, 1 - zeroes stored */
213 if (s390_cpu_virt_mem_write(cpu
, addr
, ar
, &crw
, sizeof(crw
)) == 0) {
215 } else if (cc
== 0) {
216 /* Write failed: requeue CRW since STCRW is a suppressing instruction */
217 css_undo_stcrw(&crw
);
221 void ioinst_handle_stsch(S390CPU
*cpu
, uint64_t reg1
, uint32_t ipb
)
223 int cssid
, ssid
, schid
, m
;
228 CPUS390XState
*env
= &cpu
->env
;
231 addr
= decode_basedisp_s(env
, ipb
, &ar
);
233 program_interrupt(env
, PGM_SPECIFICATION
, 4);
237 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
239 * As operand exceptions have a lower priority than access exceptions,
240 * we check whether the memory area is writeable (injecting the
241 * access execption if it is not) first.
243 if (!s390_cpu_virt_mem_check_write(cpu
, addr
, ar
, sizeof(schib
))) {
244 program_interrupt(env
, PGM_OPERAND
, 4);
248 trace_ioinst_sch_id("stsch", cssid
, ssid
, schid
);
249 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
251 if (css_subch_visible(sch
)) {
252 css_do_stsch(sch
, &schib
);
255 /* Indicate no more subchannels in this css/ss */
259 if (css_schid_final(m
, cssid
, ssid
, schid
)) {
260 cc
= 3; /* No more subchannels in this css/ss */
262 /* Store an empty schib. */
263 memset(&schib
, 0, sizeof(schib
));
268 if (s390_cpu_virt_mem_write(cpu
, addr
, ar
, &schib
,
269 sizeof(schib
)) != 0) {
273 /* Access exceptions have a higher priority than cc3 */
274 if (s390_cpu_virt_mem_check_write(cpu
, addr
, ar
, sizeof(schib
)) != 0) {
281 int ioinst_handle_tsch(S390CPU
*cpu
, uint64_t reg1
, uint32_t ipb
)
283 CPUS390XState
*env
= &cpu
->env
;
284 int cssid
, ssid
, schid
, m
;
291 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
292 program_interrupt(env
, PGM_OPERAND
, 4);
295 trace_ioinst_sch_id("tsch", cssid
, ssid
, schid
);
296 addr
= decode_basedisp_s(env
, ipb
, &ar
);
298 program_interrupt(env
, PGM_SPECIFICATION
, 4);
302 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
303 if (sch
&& css_subch_visible(sch
)) {
304 cc
= css_do_tsch_get_irb(sch
, &irb
, &irb_len
);
308 /* 0 - status pending, 1 - not status pending, 3 - not operational */
310 if (s390_cpu_virt_mem_write(cpu
, addr
, ar
, &irb
, irb_len
) != 0) {
313 css_do_tsch_update_subch(sch
);
315 irb_len
= sizeof(irb
) - sizeof(irb
.emw
);
316 /* Access exceptions have a higher priority than cc3 */
317 if (s390_cpu_virt_mem_check_write(cpu
, addr
, ar
, irb_len
) != 0) {
326 typedef struct ChscReq
{
332 } QEMU_PACKED ChscReq
;
334 typedef struct ChscResp
{
339 } QEMU_PACKED ChscResp
;
341 #define CHSC_MIN_RESP_LEN 0x0008
343 #define CHSC_SCPD 0x0002
344 #define CHSC_SCSC 0x0010
345 #define CHSC_SDA 0x0031
346 #define CHSC_SEI 0x000e
348 #define CHSC_SCPD_0_M 0x20000000
349 #define CHSC_SCPD_0_C 0x10000000
350 #define CHSC_SCPD_0_FMT 0x0f000000
351 #define CHSC_SCPD_0_CSSID 0x00ff0000
352 #define CHSC_SCPD_0_RFMT 0x00000f00
353 #define CHSC_SCPD_0_RES 0xc000f000
354 #define CHSC_SCPD_1_RES 0xffffff00
355 #define CHSC_SCPD_01_CHPID 0x000000ff
356 static void ioinst_handle_chsc_scpd(ChscReq
*req
, ChscResp
*res
)
358 uint16_t len
= be16_to_cpu(req
->len
);
359 uint32_t param0
= be32_to_cpu(req
->param0
);
360 uint32_t param1
= be32_to_cpu(req
->param1
);
364 uint8_t f_chpid
, l_chpid
;
368 rfmt
= (param0
& CHSC_SCPD_0_RFMT
) >> 8;
369 if ((rfmt
== 0) || (rfmt
== 1)) {
370 rfmt
= !!(param0
& CHSC_SCPD_0_C
);
372 if ((len
!= 0x0010) || (param0
& CHSC_SCPD_0_RES
) ||
373 (param1
& CHSC_SCPD_1_RES
) || req
->param2
) {
377 if (param0
& CHSC_SCPD_0_FMT
) {
381 cssid
= (param0
& CHSC_SCPD_0_CSSID
) >> 16;
382 m
= param0
& CHSC_SCPD_0_M
;
384 if (!m
|| !css_present(cssid
)) {
389 f_chpid
= param0
& CHSC_SCPD_01_CHPID
;
390 l_chpid
= param1
& CHSC_SCPD_01_CHPID
;
391 if (l_chpid
< f_chpid
) {
395 /* css_collect_chp_desc() is endian-aware */
396 desc_size
= css_collect_chp_desc(m
, cssid
, f_chpid
, l_chpid
, rfmt
,
398 res
->code
= cpu_to_be16(0x0001);
399 res
->len
= cpu_to_be16(8 + desc_size
);
400 res
->param
= cpu_to_be32(rfmt
);
404 res
->code
= cpu_to_be16(resp_code
);
405 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
406 res
->param
= cpu_to_be32(rfmt
);
409 #define CHSC_SCSC_0_M 0x20000000
410 #define CHSC_SCSC_0_FMT 0x000f0000
411 #define CHSC_SCSC_0_CSSID 0x0000ff00
412 #define CHSC_SCSC_0_RES 0xdff000ff
413 static void ioinst_handle_chsc_scsc(ChscReq
*req
, ChscResp
*res
)
415 uint16_t len
= be16_to_cpu(req
->len
);
416 uint32_t param0
= be32_to_cpu(req
->param0
);
419 uint32_t general_chars
[510];
420 uint32_t chsc_chars
[508];
427 if (param0
& CHSC_SCSC_0_FMT
) {
431 cssid
= (param0
& CHSC_SCSC_0_CSSID
) >> 8;
433 if (!(param0
& CHSC_SCSC_0_M
) || !css_present(cssid
)) {
438 if ((param0
& CHSC_SCSC_0_RES
) || req
->param1
|| req
->param2
) {
442 res
->code
= cpu_to_be16(0x0001);
443 res
->len
= cpu_to_be16(4080);
446 memset(general_chars
, 0, sizeof(general_chars
));
447 memset(chsc_chars
, 0, sizeof(chsc_chars
));
449 general_chars
[0] = cpu_to_be32(0x03000000);
450 general_chars
[1] = cpu_to_be32(0x00079000);
451 general_chars
[3] = cpu_to_be32(0x00080000);
453 chsc_chars
[0] = cpu_to_be32(0x40000000);
454 chsc_chars
[3] = cpu_to_be32(0x00040000);
456 memcpy(res
->data
, general_chars
, sizeof(general_chars
));
457 memcpy(res
->data
+ sizeof(general_chars
), chsc_chars
, sizeof(chsc_chars
));
461 res
->code
= cpu_to_be16(resp_code
);
462 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
466 #define CHSC_SDA_0_FMT 0x0f000000
467 #define CHSC_SDA_0_OC 0x0000ffff
468 #define CHSC_SDA_0_RES 0xf0ff0000
469 #define CHSC_SDA_OC_MCSSE 0x0
470 #define CHSC_SDA_OC_MSS 0x2
471 static void ioinst_handle_chsc_sda(ChscReq
*req
, ChscResp
*res
)
473 uint16_t resp_code
= 0x0001;
474 uint16_t len
= be16_to_cpu(req
->len
);
475 uint32_t param0
= be32_to_cpu(req
->param0
);
479 if ((len
!= 0x0400) || (param0
& CHSC_SDA_0_RES
)) {
484 if (param0
& CHSC_SDA_0_FMT
) {
489 oc
= param0
& CHSC_SDA_0_OC
;
491 case CHSC_SDA_OC_MCSSE
:
492 ret
= css_enable_mcsse();
493 if (ret
== -EINVAL
) {
498 case CHSC_SDA_OC_MSS
:
499 ret
= css_enable_mss();
500 if (ret
== -EINVAL
) {
511 res
->code
= cpu_to_be16(resp_code
);
512 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
516 static int chsc_sei_nt0_get_event(void *res
)
522 static int chsc_sei_nt0_have_event(void)
528 static int chsc_sei_nt2_get_event(void *res
)
530 if (s390_has_feat(S390_FEAT_ZPCI
)) {
531 return pci_chsc_sei_nt2_get_event(res
);
536 static int chsc_sei_nt2_have_event(void)
538 if (s390_has_feat(S390_FEAT_ZPCI
)) {
539 return pci_chsc_sei_nt2_have_event();
544 #define CHSC_SEI_NT0 (1ULL << 63)
545 #define CHSC_SEI_NT2 (1ULL << 61)
546 static void ioinst_handle_chsc_sei(ChscReq
*req
, ChscResp
*res
)
548 uint64_t selection_mask
= ldq_p(&req
->param1
);
549 uint8_t *res_flags
= (uint8_t *)res
->data
;
553 /* regarding architecture nt0 can not be masked */
554 have_event
= !chsc_sei_nt0_get_event(res
);
555 have_more
= chsc_sei_nt0_have_event();
557 if (selection_mask
& CHSC_SEI_NT2
) {
559 have_event
= !chsc_sei_nt2_get_event(res
);
563 have_more
= chsc_sei_nt2_have_event();
568 res
->code
= cpu_to_be16(0x0001);
570 (*res_flags
) |= 0x80;
572 (*res_flags
) &= ~0x80;
573 css_clear_sei_pending();
576 res
->code
= cpu_to_be16(0x0005);
577 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
581 static void ioinst_handle_chsc_unimplemented(ChscResp
*res
)
583 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
584 res
->code
= cpu_to_be16(0x0004);
588 void ioinst_handle_chsc(S390CPU
*cpu
, uint32_t ipb
)
596 CPUS390XState
*env
= &cpu
->env
;
597 uint8_t buf
[TARGET_PAGE_SIZE
];
599 trace_ioinst("chsc");
600 reg
= (ipb
>> 20) & 0x00f;
601 addr
= env
->regs
[reg
];
604 program_interrupt(env
, PGM_SPECIFICATION
, 4);
608 * Reading sizeof(ChscReq) bytes is currently enough for all of our
609 * present CHSC sub-handlers ... if we ever need more, we should take
610 * care of req->len here first.
612 if (s390_cpu_virt_mem_read(cpu
, addr
, reg
, buf
, sizeof(ChscReq
))) {
615 req
= (ChscReq
*)buf
;
616 len
= be16_to_cpu(req
->len
);
617 /* Length field valid? */
618 if ((len
< 16) || (len
> 4088) || (len
& 7)) {
619 program_interrupt(env
, PGM_OPERAND
, 4);
622 memset((char *)req
+ len
, 0, TARGET_PAGE_SIZE
- len
);
623 res
= (void *)((char *)req
+ len
);
624 command
= be16_to_cpu(req
->command
);
625 trace_ioinst_chsc_cmd(command
, len
);
628 ioinst_handle_chsc_scsc(req
, res
);
631 ioinst_handle_chsc_scpd(req
, res
);
634 ioinst_handle_chsc_sda(req
, res
);
637 ioinst_handle_chsc_sei(req
, res
);
640 ioinst_handle_chsc_unimplemented(res
);
644 if (!s390_cpu_virt_mem_write(cpu
, addr
+ len
, reg
, res
,
645 be16_to_cpu(res
->len
))) {
646 setcc(cpu
, 0); /* Command execution complete */
650 #define SCHM_REG1_RES(_reg) (_reg & 0x000000000ffffffc)
651 #define SCHM_REG1_MBK(_reg) ((_reg & 0x00000000f0000000) >> 28)
652 #define SCHM_REG1_UPD(_reg) ((_reg & 0x0000000000000002) >> 1)
653 #define SCHM_REG1_DCT(_reg) (_reg & 0x0000000000000001)
655 void ioinst_handle_schm(S390CPU
*cpu
, uint64_t reg1
, uint64_t reg2
,
661 CPUS390XState
*env
= &cpu
->env
;
663 trace_ioinst("schm");
665 if (SCHM_REG1_RES(reg1
)) {
666 program_interrupt(env
, PGM_OPERAND
, 4);
670 mbk
= SCHM_REG1_MBK(reg1
);
671 update
= SCHM_REG1_UPD(reg1
);
672 dct
= SCHM_REG1_DCT(reg1
);
674 if (update
&& (reg2
& 0x000000000000001f)) {
675 program_interrupt(env
, PGM_OPERAND
, 4);
679 css_do_schm(mbk
, update
, dct
, update
? reg2
: 0);
682 void ioinst_handle_rsch(S390CPU
*cpu
, uint64_t reg1
)
684 int cssid
, ssid
, schid
, m
;
687 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
688 program_interrupt(&cpu
->env
, PGM_OPERAND
, 4);
691 trace_ioinst_sch_id("rsch", cssid
, ssid
, schid
);
692 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
693 if (!sch
|| !css_subch_visible(sch
)) {
697 setcc(cpu
, css_do_rsch(sch
));
700 #define RCHP_REG1_RES(_reg) (_reg & 0x00000000ff00ff00)
701 #define RCHP_REG1_CSSID(_reg) ((_reg & 0x0000000000ff0000) >> 16)
702 #define RCHP_REG1_CHPID(_reg) (_reg & 0x00000000000000ff)
703 void ioinst_handle_rchp(S390CPU
*cpu
, uint64_t reg1
)
709 CPUS390XState
*env
= &cpu
->env
;
711 if (RCHP_REG1_RES(reg1
)) {
712 program_interrupt(env
, PGM_OPERAND
, 4);
716 cssid
= RCHP_REG1_CSSID(reg1
);
717 chpid
= RCHP_REG1_CHPID(reg1
);
719 trace_ioinst_chp_id("rchp", cssid
, chpid
);
721 ret
= css_do_rchp(cssid
, chpid
);
734 /* Invalid channel subsystem. */
735 program_interrupt(env
, PGM_OPERAND
, 4);
741 #define SAL_REG1_INVALID(_reg) (_reg & 0x0000000080000000)
742 void ioinst_handle_sal(S390CPU
*cpu
, uint64_t reg1
)
744 /* We do not provide address limit checking, so let's suppress it. */
745 if (SAL_REG1_INVALID(reg1
) || reg1
& 0x000000000000ffff) {
746 program_interrupt(&cpu
->env
, PGM_OPERAND
, 4);