hw/intc/ibex_plic.c

   1 /*
   2  * QEMU RISC-V lowRISC Ibex PLIC
   3  *
   4  * Copyright (c) 2020 Western Digital
   5  *
   6  * Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/log.h"
  23 #include "hw/qdev-properties.h"
  24 #include "hw/core/cpu.h"
  25 #include "hw/boards.h"
  26 #include "hw/pci/msi.h"
  27 #include "target/riscv/cpu_bits.h"
  28 #include "target/riscv/cpu.h"
  29 #include "hw/intc/ibex_plic.h"
  30
  31 static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
  32 {
  33     uint32_t end = base + (num * 0x04);
  34
  35     if (addr >= base && addr < end) {
  36         return true;
  37     }
  38
  39     return false;
  40 }
  41
  42 static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
  43 {
  44     int pending_num = irq / 32;
  45
  46     if (s->claimed[pending_num] & 1 << (irq % 32)) {
  47         /*
  48          * The interrupt has been claimed, but not completed.
  49          * The pending bit can't be set.
  50          */
  51         s->hidden_pending[pending_num] |= level << (irq % 32);
  52         return;
  53     }
  54
  55     s->pending[pending_num] |= level << (irq % 32);
  56 }
  57
  58 static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
  59 {
  60     int i;
  61     uint32_t max_irq = 0;
  62     uint32_t max_prio = s->threshold;
  63
  64     for (i = 0; i < s->pending_num; i++) {
  65         uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
  66
  67         if (!(s->pending[i] & s->enable[i])) {
  68             /* No pending and enabled IRQ */
  69             continue;
  70         }
  71
  72         if (s->priority[irq_num] > max_prio) {
  73             max_irq = irq_num;
  74             max_prio = s->priority[irq_num];
  75         }
  76     }
  77
  78     if (max_irq) {
  79         s->claim = max_irq;
  80         return true;
  81     }
  82
  83     return false;
  84 }
  85
  86 static void ibex_plic_update(IbexPlicState *s)
  87 {
  88     CPUState *cpu;
  89     int level, i;
  90
  91     for (i = 0; i < s->num_cpus; i++) {
  92         cpu = qemu_get_cpu(i);
  93
  94         if (!cpu) {
  95             continue;
  96         }
  97
  98         level = ibex_plic_irqs_pending(s, 0);
  99
 100         riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
 101     }
 102 }
 103
 104 static void ibex_plic_reset(DeviceState *dev)
 105 {
 106     IbexPlicState *s = IBEX_PLIC(dev);
 107
 108     s->threshold = 0x00000000;
 109     s->claim = 0x00000000;
 110 }
 111
 112 static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
 113                                unsigned int size)
 114 {
 115     IbexPlicState *s = opaque;
 116     int offset;
 117     uint32_t ret = 0;
 118
 119     if (addr_between(addr, s->pending_base, s->pending_num)) {
 120         offset = (addr - s->pending_base) / 4;
 121         ret = s->pending[offset];
 122     } else if (addr_between(addr, s->source_base, s->source_num)) {
 123         qemu_log_mask(LOG_UNIMP,
 124                       "%s: Interrupt source mode not supported\n", __func__);
 125     } else if (addr_between(addr, s->priority_base, s->priority_num)) {
 126         offset = (addr - s->priority_base) / 4;
 127         ret = s->priority[offset];
 128     } else if (addr_between(addr, s->enable_base, s->enable_num)) {
 129         offset = (addr - s->enable_base) / 4;
 130         ret = s->enable[offset];
 131     } else if (addr_between(addr, s->threshold_base, 1)) {
 132         ret = s->threshold;
 133     } else if (addr_between(addr, s->claim_base, 1)) {
 134         int pending_num = s->claim / 32;
 135         s->pending[pending_num] &= ~(1 << (s->claim % 32));
 136
 137         /* Set the interrupt as claimed, but not completed */
 138         s->claimed[pending_num] |= 1 << (s->claim % 32);
 139
 140         /* Return the current claimed interrupt */
 141         ret = s->claim;
 142
 143         /* Clear the claimed interrupt */
 144         s->claim = 0x00000000;
 145
 146         /* Update the interrupt status after the claim */
 147         ibex_plic_update(s);
 148     }
 149
 150     return ret;
 151 }
 152
 153 static void ibex_plic_write(void *opaque, hwaddr addr,
 154                             uint64_t value, unsigned int size)
 155 {
 156     IbexPlicState *s = opaque;
 157
 158     if (addr_between(addr, s->pending_base, s->pending_num)) {
 159         qemu_log_mask(LOG_GUEST_ERROR,
 160                       "%s: Pending registers are read only\n", __func__);
 161     } else if (addr_between(addr, s->source_base, s->source_num)) {
 162         qemu_log_mask(LOG_UNIMP,
 163                       "%s: Interrupt source mode not supported\n", __func__);
 164     } else if (addr_between(addr, s->priority_base, s->priority_num)) {
 165         uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
 166         s->priority[irq] = value & 7;
 167         ibex_plic_update(s);
 168     } else if (addr_between(addr, s->enable_base, s->enable_num)) {
 169         uint32_t enable_reg = (addr - s->enable_base) / 4;
 170
 171         s->enable[enable_reg] = value;
 172     } else if (addr_between(addr, s->threshold_base, 1)) {
 173         s->threshold = value & 3;
 174     } else if (addr_between(addr, s->claim_base, 1)) {
 175         if (s->claim == value) {
 176             /* Interrupt was completed */
 177             s->claim = 0;
 178         }
 179         if (s->claimed[value / 32] & 1 << (value % 32)) {
 180             int pending_num = value / 32;
 181
 182             /* This value was already claimed, clear it. */
 183             s->claimed[pending_num] &= ~(1 << (value % 32));
 184
 185             if (s->hidden_pending[pending_num] & (1 << (value % 32))) {
 186                 /*
 187                  * If the bit in hidden_pending is set then that means we
 188                  * received an interrupt between claiming and completing
 189                  * the interrupt that hasn't since been de-asserted.
 190                  * On hardware this would trigger an interrupt, so let's
 191                  * trigger one here as well.
 192                  */
 193                 s->pending[pending_num] |= 1 << (value % 32);
 194             }
 195         }
 196     }
 197
 198     ibex_plic_update(s);
 199 }
 200
 201 static const MemoryRegionOps ibex_plic_ops = {
 202     .read = ibex_plic_read,
 203     .write = ibex_plic_write,
 204     .endianness = DEVICE_NATIVE_ENDIAN,
 205     .valid = {
 206         .min_access_size = 4,
 207         .max_access_size = 4
 208     }
 209 };
 210
 211 static void ibex_plic_irq_request(void *opaque, int irq, int level)
 212 {
 213     IbexPlicState *s = opaque;
 214
 215     ibex_plic_irqs_set_pending(s, irq, level > 0);
 216     ibex_plic_update(s);
 217 }
 218
 219 static Property ibex_plic_properties[] = {
 220     DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
 221     DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
 222
 223     DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
 224     DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
 225
 226     DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
 227     DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
 228
 229     DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
 230     DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
 231
 232     DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
 233     DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
 234
 235     DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
 236
 237     DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
 238     DEFINE_PROP_END_OF_LIST(),
 239 };
 240
 241 static void ibex_plic_init(Object *obj)
 242 {
 243     IbexPlicState *s = IBEX_PLIC(obj);
 244
 245     memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s,
 246                           TYPE_IBEX_PLIC, 0x400);
 247     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 248 }
 249
 250 static void ibex_plic_realize(DeviceState *dev, Error **errp)
 251 {
 252     IbexPlicState *s = IBEX_PLIC(dev);
 253     int i;
 254
 255     s->pending = g_new0(uint32_t, s->pending_num);
 256     s->hidden_pending = g_new0(uint32_t, s->pending_num);
 257     s->claimed = g_new0(uint32_t, s->pending_num);
 258     s->source = g_new0(uint32_t, s->source_num);
 259     s->priority = g_new0(uint32_t, s->priority_num);
 260     s->enable = g_new0(uint32_t, s->enable_num);
 261
 262     qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources);
 263
 264     /*
 265      * We can't allow the supervisor to control SEIP as this would allow the
 266      * supervisor to clear a pending external interrupt which will result in
 267      * a lost interrupt in the case a PLIC is attached. The SEIP bit must be
 268      * hardware controlled when a PLIC is attached.
 269      */
 270     MachineState *ms = MACHINE(qdev_get_machine());
 271     unsigned int smp_cpus = ms->smp.cpus;
 272     for (i = 0; i < smp_cpus; i++) {
 273         RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
 274         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
 275             error_report("SEIP already claimed");
 276             exit(1);
 277         }
 278     }
 279
 280     msi_nonbroken = true;
 281 }
 282
 283 static void ibex_plic_class_init(ObjectClass *klass, void *data)
 284 {
 285     DeviceClass *dc = DEVICE_CLASS(klass);
 286
 287     dc->reset = ibex_plic_reset;
 288     device_class_set_props(dc, ibex_plic_properties);
 289     dc->realize = ibex_plic_realize;
 290 }
 291
 292 static const TypeInfo ibex_plic_info = {
 293     .name          = TYPE_IBEX_PLIC,
 294     .parent        = TYPE_SYS_BUS_DEVICE,
 295     .instance_size = sizeof(IbexPlicState),
 296     .instance_init = ibex_plic_init,
 297     .class_init    = ibex_plic_class_init,
 298 };
 299
 300 static void ibex_plic_register_types(void)
 301 {
 302     type_register_static(&ibex_plic_info);
 303 }
 304
 305 type_init(ibex_plic_register_types)