2 * Moxie emulation for qemu: main translation routines.
4 * Copyright (c) 2009, 2013 Anthony Green
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public License
8 * as published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 /* For information on the Moxie architecture, see
21 * http://moxielogic.org/wiki
24 #include "qemu/osdep.h"
27 #include "exec/exec-all.h"
28 #include "disas/disas.h"
30 #include "exec/cpu_ldst.h"
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
35 /* This is the state at translation time. */
36 typedef struct DisasContext
{
37 struct TranslationBlock
*tb
;
38 target_ulong pc
, saved_pc
;
41 /* Routine used to access memory */
45 int singlestep_enabled
;
49 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
50 * exception condition */
51 BS_STOP
= 1, /* We want to stop translation for any reason */
52 BS_BRANCH
= 2, /* We reached a branch condition */
53 BS_EXCP
= 3, /* We reached an exception condition */
57 static TCGv cpu_gregs
[16];
58 static TCGv_ptr cpu_env
;
59 static TCGv cc_a
, cc_b
;
61 #include "exec/gen-icount.h"
63 #define REG(x) (cpu_gregs[x])
65 /* Extract the signed 10-bit offset from a 16-bit branch
67 static int extract_branch_offset(int opcode
)
69 return (((signed short)((opcode
& ((1 << 10) - 1)) << 6)) >> 6) << 1;
72 void moxie_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
75 MoxieCPU
*cpu
= MOXIE_CPU(cs
);
76 CPUMoxieState
*env
= &cpu
->env
;
78 cpu_fprintf(f
, "pc=0x%08x\n", env
->pc
);
79 cpu_fprintf(f
, "$fp=0x%08x $sp=0x%08x $r0=0x%08x $r1=0x%08x\n",
80 env
->gregs
[0], env
->gregs
[1], env
->gregs
[2], env
->gregs
[3]);
81 for (i
= 4; i
< 16; i
+= 4) {
82 cpu_fprintf(f
, "$r%d=0x%08x $r%d=0x%08x $r%d=0x%08x $r%d=0x%08x\n",
83 i
-2, env
->gregs
[i
], i
-1, env
->gregs
[i
+ 1],
84 i
, env
->gregs
[i
+ 2], i
+1, env
->gregs
[i
+ 3]);
86 for (i
= 4; i
< 16; i
+= 4) {
87 cpu_fprintf(f
, "sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x\n",
88 i
-2, env
->sregs
[i
], i
-1, env
->sregs
[i
+ 1],
89 i
, env
->sregs
[i
+ 2], i
+1, env
->sregs
[i
+ 3]);
93 void moxie_translate_init(void)
97 static const char * const gregnames
[16] = {
98 "$fp", "$sp", "$r0", "$r1",
99 "$r2", "$r3", "$r4", "$r5",
100 "$r6", "$r7", "$r8", "$r9",
101 "$r10", "$r11", "$r12", "$r13"
107 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
108 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
109 offsetof(CPUMoxieState
, pc
), "$pc");
110 for (i
= 0; i
< 16; i
++)
111 cpu_gregs
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
112 offsetof(CPUMoxieState
, gregs
[i
]),
115 cc_a
= tcg_global_mem_new_i32(TCG_AREG0
,
116 offsetof(CPUMoxieState
, cc_a
), "cc_a");
117 cc_b
= tcg_global_mem_new_i32(TCG_AREG0
,
118 offsetof(CPUMoxieState
, cc_b
), "cc_b");
123 static inline void gen_goto_tb(CPUMoxieState
*env
, DisasContext
*ctx
,
124 int n
, target_ulong dest
)
126 TranslationBlock
*tb
;
129 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
130 !ctx
->singlestep_enabled
) {
132 tcg_gen_movi_i32(cpu_pc
, dest
);
133 tcg_gen_exit_tb((uintptr_t)tb
+ n
);
135 tcg_gen_movi_i32(cpu_pc
, dest
);
136 if (ctx
->singlestep_enabled
) {
137 gen_helper_debug(cpu_env
);
143 static int decode_opc(MoxieCPU
*cpu
, DisasContext
*ctx
)
145 CPUMoxieState
*env
= &cpu
->env
;
147 /* Local cache for the instruction opcode. */
149 /* Set the default instruction length. */
152 /* Examine the 16-bit opcode. */
153 opcode
= ctx
->opcode
;
155 /* Decode instruction. */
156 if (opcode
& (1 << 15)) {
157 if (opcode
& (1 << 14)) {
158 /* This is a Form 3 instruction. */
159 int inst
= (opcode
>> 10 & 0xf);
161 #define BRANCH(cond) \
163 TCGLabel *l1 = gen_new_label(); \
164 tcg_gen_brcond_i32(cond, cc_a, cc_b, l1); \
165 gen_goto_tb(env, ctx, 1, ctx->pc+2); \
167 gen_goto_tb(env, ctx, 0, extract_branch_offset(opcode) + ctx->pc+2); \
168 ctx->bstate = BS_BRANCH; \
184 case 0x04: /* bltu */
185 BRANCH(TCG_COND_LTU
);
187 case 0x05: /* bgtu */
188 BRANCH(TCG_COND_GTU
);
196 case 0x08: /* bgeu */
197 BRANCH(TCG_COND_GEU
);
199 case 0x09: /* bleu */
200 BRANCH(TCG_COND_LEU
);
204 TCGv temp
= tcg_temp_new_i32();
205 tcg_gen_movi_i32(cpu_pc
, ctx
->pc
);
206 tcg_gen_movi_i32(temp
, MOXIE_EX_BAD
);
207 gen_helper_raise_exception(cpu_env
, temp
);
208 tcg_temp_free_i32(temp
);
213 /* This is a Form 2 instruction. */
214 int inst
= (opcode
>> 12 & 0x3);
218 int a
= (opcode
>> 8) & 0xf;
219 unsigned int v
= (opcode
& 0xff);
220 tcg_gen_addi_i32(REG(a
), REG(a
), v
);
225 int a
= (opcode
>> 8) & 0xf;
226 unsigned int v
= (opcode
& 0xff);
227 tcg_gen_subi_i32(REG(a
), REG(a
), v
);
232 int a
= (opcode
>> 8) & 0xf;
233 unsigned v
= (opcode
& 0xff);
234 tcg_gen_ld_i32(REG(a
), cpu_env
,
235 offsetof(CPUMoxieState
, sregs
[v
]));
240 int a
= (opcode
>> 8) & 0xf;
241 unsigned v
= (opcode
& 0xff);
242 tcg_gen_st_i32(REG(a
), cpu_env
,
243 offsetof(CPUMoxieState
, sregs
[v
]));
248 TCGv temp
= tcg_temp_new_i32();
249 tcg_gen_movi_i32(cpu_pc
, ctx
->pc
);
250 tcg_gen_movi_i32(temp
, MOXIE_EX_BAD
);
251 gen_helper_raise_exception(cpu_env
, temp
);
252 tcg_temp_free_i32(temp
);
258 /* This is a Form 1 instruction. */
259 int inst
= opcode
>> 8;
263 case 0x01: /* ldi.l (immediate) */
265 int reg
= (opcode
>> 4) & 0xf;
266 int val
= cpu_ldl_code(env
, ctx
->pc
+2);
267 tcg_gen_movi_i32(REG(reg
), val
);
271 case 0x02: /* mov (register-to-register) */
273 int dest
= (opcode
>> 4) & 0xf;
274 int src
= opcode
& 0xf;
275 tcg_gen_mov_i32(REG(dest
), REG(src
));
278 case 0x03: /* jsra */
280 TCGv t1
= tcg_temp_new_i32();
281 TCGv t2
= tcg_temp_new_i32();
283 tcg_gen_movi_i32(t1
, ctx
->pc
+ 6);
285 /* Make space for the static chain and return address. */
286 tcg_gen_subi_i32(t2
, REG(1), 8);
287 tcg_gen_mov_i32(REG(1), t2
);
288 tcg_gen_qemu_st32(t1
, REG(1), ctx
->memidx
);
290 /* Push the current frame pointer. */
291 tcg_gen_subi_i32(t2
, REG(1), 4);
292 tcg_gen_mov_i32(REG(1), t2
);
293 tcg_gen_qemu_st32(REG(0), REG(1), ctx
->memidx
);
295 /* Set the pc and $fp. */
296 tcg_gen_mov_i32(REG(0), REG(1));
298 gen_goto_tb(env
, ctx
, 0, cpu_ldl_code(env
, ctx
->pc
+2));
300 tcg_temp_free_i32(t1
);
301 tcg_temp_free_i32(t2
);
303 ctx
->bstate
= BS_BRANCH
;
309 TCGv t1
= tcg_temp_new_i32();
311 /* The new $sp is the old $fp. */
312 tcg_gen_mov_i32(REG(1), REG(0));
314 /* Pop the frame pointer. */
315 tcg_gen_qemu_ld32u(REG(0), REG(1), ctx
->memidx
);
316 tcg_gen_addi_i32(t1
, REG(1), 4);
317 tcg_gen_mov_i32(REG(1), t1
);
320 /* Pop the return address and skip over the static chain
322 tcg_gen_qemu_ld32u(cpu_pc
, REG(1), ctx
->memidx
);
323 tcg_gen_addi_i32(t1
, REG(1), 8);
324 tcg_gen_mov_i32(REG(1), t1
);
326 tcg_temp_free_i32(t1
);
331 ctx
->bstate
= BS_BRANCH
;
334 case 0x05: /* add.l */
336 int a
= (opcode
>> 4) & 0xf;
337 int b
= opcode
& 0xf;
339 tcg_gen_add_i32(REG(a
), REG(a
), REG(b
));
342 case 0x06: /* push */
344 int a
= (opcode
>> 4) & 0xf;
345 int b
= opcode
& 0xf;
347 TCGv t1
= tcg_temp_new_i32();
348 tcg_gen_subi_i32(t1
, REG(a
), 4);
349 tcg_gen_mov_i32(REG(a
), t1
);
350 tcg_gen_qemu_st32(REG(b
), REG(a
), ctx
->memidx
);
351 tcg_temp_free_i32(t1
);
356 int a
= (opcode
>> 4) & 0xf;
357 int b
= opcode
& 0xf;
358 TCGv t1
= tcg_temp_new_i32();
360 tcg_gen_qemu_ld32u(REG(b
), REG(a
), ctx
->memidx
);
361 tcg_gen_addi_i32(t1
, REG(a
), 4);
362 tcg_gen_mov_i32(REG(a
), t1
);
363 tcg_temp_free_i32(t1
);
366 case 0x08: /* lda.l */
368 int reg
= (opcode
>> 4) & 0xf;
370 TCGv ptr
= tcg_temp_new_i32();
371 tcg_gen_movi_i32(ptr
, cpu_ldl_code(env
, ctx
->pc
+2));
372 tcg_gen_qemu_ld32u(REG(reg
), ptr
, ctx
->memidx
);
373 tcg_temp_free_i32(ptr
);
378 case 0x09: /* sta.l */
380 int val
= (opcode
>> 4) & 0xf;
382 TCGv ptr
= tcg_temp_new_i32();
383 tcg_gen_movi_i32(ptr
, cpu_ldl_code(env
, ctx
->pc
+2));
384 tcg_gen_qemu_st32(REG(val
), ptr
, ctx
->memidx
);
385 tcg_temp_free_i32(ptr
);
390 case 0x0a: /* ld.l (register indirect) */
392 int src
= opcode
& 0xf;
393 int dest
= (opcode
>> 4) & 0xf;
395 tcg_gen_qemu_ld32u(REG(dest
), REG(src
), ctx
->memidx
);
398 case 0x0b: /* st.l */
400 int dest
= (opcode
>> 4) & 0xf;
401 int val
= opcode
& 0xf;
403 tcg_gen_qemu_st32(REG(val
), REG(dest
), ctx
->memidx
);
406 case 0x0c: /* ldo.l */
408 int a
= (opcode
>> 4) & 0xf;
409 int b
= opcode
& 0xf;
411 TCGv t1
= tcg_temp_new_i32();
412 TCGv t2
= tcg_temp_new_i32();
413 tcg_gen_addi_i32(t1
, REG(b
), cpu_ldl_code(env
, ctx
->pc
+2));
414 tcg_gen_qemu_ld32u(t2
, t1
, ctx
->memidx
);
415 tcg_gen_mov_i32(REG(a
), t2
);
417 tcg_temp_free_i32(t1
);
418 tcg_temp_free_i32(t2
);
423 case 0x0d: /* sto.l */
425 int a
= (opcode
>> 4) & 0xf;
426 int b
= opcode
& 0xf;
428 TCGv t1
= tcg_temp_new_i32();
429 TCGv t2
= tcg_temp_new_i32();
430 tcg_gen_addi_i32(t1
, REG(a
), cpu_ldl_code(env
, ctx
->pc
+2));
431 tcg_gen_qemu_st32(REG(b
), t1
, ctx
->memidx
);
433 tcg_temp_free_i32(t1
);
434 tcg_temp_free_i32(t2
);
441 int a
= (opcode
>> 4) & 0xf;
442 int b
= opcode
& 0xf;
444 tcg_gen_mov_i32(cc_a
, REG(a
));
445 tcg_gen_mov_i32(cc_b
, REG(b
));
450 int fnreg
= (opcode
>> 4) & 0xf;
452 /* Load the stack pointer into T0. */
453 TCGv t1
= tcg_temp_new_i32();
454 TCGv t2
= tcg_temp_new_i32();
456 tcg_gen_movi_i32(t1
, ctx
->pc
+2);
458 /* Make space for the static chain and return address. */
459 tcg_gen_subi_i32(t2
, REG(1), 8);
460 tcg_gen_mov_i32(REG(1), t2
);
461 tcg_gen_qemu_st32(t1
, REG(1), ctx
->memidx
);
463 /* Push the current frame pointer. */
464 tcg_gen_subi_i32(t2
, REG(1), 4);
465 tcg_gen_mov_i32(REG(1), t2
);
466 tcg_gen_qemu_st32(REG(0), REG(1), ctx
->memidx
);
468 /* Set the pc and $fp. */
469 tcg_gen_mov_i32(REG(0), REG(1));
470 tcg_gen_mov_i32(cpu_pc
, REG(fnreg
));
471 tcg_temp_free_i32(t1
);
472 tcg_temp_free_i32(t2
);
474 ctx
->bstate
= BS_BRANCH
;
477 case 0x1a: /* jmpa */
479 tcg_gen_movi_i32(cpu_pc
, cpu_ldl_code(env
, ctx
->pc
+2));
481 ctx
->bstate
= BS_BRANCH
;
485 case 0x1b: /* ldi.b (immediate) */
487 int reg
= (opcode
>> 4) & 0xf;
488 int val
= cpu_ldl_code(env
, ctx
->pc
+2);
489 tcg_gen_movi_i32(REG(reg
), val
);
493 case 0x1c: /* ld.b (register indirect) */
495 int src
= opcode
& 0xf;
496 int dest
= (opcode
>> 4) & 0xf;
498 tcg_gen_qemu_ld8u(REG(dest
), REG(src
), ctx
->memidx
);
501 case 0x1d: /* lda.b */
503 int reg
= (opcode
>> 4) & 0xf;
505 TCGv ptr
= tcg_temp_new_i32();
506 tcg_gen_movi_i32(ptr
, cpu_ldl_code(env
, ctx
->pc
+2));
507 tcg_gen_qemu_ld8u(REG(reg
), ptr
, ctx
->memidx
);
508 tcg_temp_free_i32(ptr
);
513 case 0x1e: /* st.b */
515 int dest
= (opcode
>> 4) & 0xf;
516 int val
= opcode
& 0xf;
518 tcg_gen_qemu_st8(REG(val
), REG(dest
), ctx
->memidx
);
521 case 0x1f: /* sta.b */
523 int val
= (opcode
>> 4) & 0xf;
525 TCGv ptr
= tcg_temp_new_i32();
526 tcg_gen_movi_i32(ptr
, cpu_ldl_code(env
, ctx
->pc
+2));
527 tcg_gen_qemu_st8(REG(val
), ptr
, ctx
->memidx
);
528 tcg_temp_free_i32(ptr
);
533 case 0x20: /* ldi.s (immediate) */
535 int reg
= (opcode
>> 4) & 0xf;
536 int val
= cpu_ldl_code(env
, ctx
->pc
+2);
537 tcg_gen_movi_i32(REG(reg
), val
);
541 case 0x21: /* ld.s (register indirect) */
543 int src
= opcode
& 0xf;
544 int dest
= (opcode
>> 4) & 0xf;
546 tcg_gen_qemu_ld16u(REG(dest
), REG(src
), ctx
->memidx
);
549 case 0x22: /* lda.s */
551 int reg
= (opcode
>> 4) & 0xf;
553 TCGv ptr
= tcg_temp_new_i32();
554 tcg_gen_movi_i32(ptr
, cpu_ldl_code(env
, ctx
->pc
+2));
555 tcg_gen_qemu_ld16u(REG(reg
), ptr
, ctx
->memidx
);
556 tcg_temp_free_i32(ptr
);
561 case 0x23: /* st.s */
563 int dest
= (opcode
>> 4) & 0xf;
564 int val
= opcode
& 0xf;
566 tcg_gen_qemu_st16(REG(val
), REG(dest
), ctx
->memidx
);
569 case 0x24: /* sta.s */
571 int val
= (opcode
>> 4) & 0xf;
573 TCGv ptr
= tcg_temp_new_i32();
574 tcg_gen_movi_i32(ptr
, cpu_ldl_code(env
, ctx
->pc
+2));
575 tcg_gen_qemu_st16(REG(val
), ptr
, ctx
->memidx
);
576 tcg_temp_free_i32(ptr
);
583 int reg
= (opcode
>> 4) & 0xf;
584 tcg_gen_mov_i32(cpu_pc
, REG(reg
));
586 ctx
->bstate
= BS_BRANCH
;
591 int a
= (opcode
>> 4) & 0xf;
592 int b
= opcode
& 0xf;
594 tcg_gen_and_i32(REG(a
), REG(a
), REG(b
));
597 case 0x27: /* lshr */
599 int a
= (opcode
>> 4) & 0xf;
600 int b
= opcode
& 0xf;
602 TCGv sv
= tcg_temp_new_i32();
603 tcg_gen_andi_i32(sv
, REG(b
), 0x1f);
604 tcg_gen_shr_i32(REG(a
), REG(a
), sv
);
605 tcg_temp_free_i32(sv
);
608 case 0x28: /* ashl */
610 int a
= (opcode
>> 4) & 0xf;
611 int b
= opcode
& 0xf;
613 TCGv sv
= tcg_temp_new_i32();
614 tcg_gen_andi_i32(sv
, REG(b
), 0x1f);
615 tcg_gen_shl_i32(REG(a
), REG(a
), sv
);
616 tcg_temp_free_i32(sv
);
619 case 0x29: /* sub.l */
621 int a
= (opcode
>> 4) & 0xf;
622 int b
= opcode
& 0xf;
624 tcg_gen_sub_i32(REG(a
), REG(a
), REG(b
));
629 int a
= (opcode
>> 4) & 0xf;
630 int b
= opcode
& 0xf;
632 tcg_gen_neg_i32(REG(a
), REG(b
));
637 int a
= (opcode
>> 4) & 0xf;
638 int b
= opcode
& 0xf;
640 tcg_gen_or_i32(REG(a
), REG(a
), REG(b
));
645 int a
= (opcode
>> 4) & 0xf;
646 int b
= opcode
& 0xf;
648 tcg_gen_not_i32(REG(a
), REG(b
));
651 case 0x2d: /* ashr */
653 int a
= (opcode
>> 4) & 0xf;
654 int b
= opcode
& 0xf;
656 TCGv sv
= tcg_temp_new_i32();
657 tcg_gen_andi_i32(sv
, REG(b
), 0x1f);
658 tcg_gen_sar_i32(REG(a
), REG(a
), sv
);
659 tcg_temp_free_i32(sv
);
664 int a
= (opcode
>> 4) & 0xf;
665 int b
= opcode
& 0xf;
667 tcg_gen_xor_i32(REG(a
), REG(a
), REG(b
));
670 case 0x2f: /* mul.l */
672 int a
= (opcode
>> 4) & 0xf;
673 int b
= opcode
& 0xf;
675 tcg_gen_mul_i32(REG(a
), REG(a
), REG(b
));
680 int val
= cpu_ldl_code(env
, ctx
->pc
+2);
682 TCGv temp
= tcg_temp_new_i32();
683 tcg_gen_movi_i32(temp
, val
);
684 tcg_gen_st_i32(temp
, cpu_env
,
685 offsetof(CPUMoxieState
, sregs
[3]));
686 tcg_gen_movi_i32(cpu_pc
, ctx
->pc
);
687 tcg_gen_movi_i32(temp
, MOXIE_EX_SWI
);
688 gen_helper_raise_exception(cpu_env
, temp
);
689 tcg_temp_free_i32(temp
);
694 case 0x31: /* div.l */
696 int a
= (opcode
>> 4) & 0xf;
697 int b
= opcode
& 0xf;
698 tcg_gen_movi_i32(cpu_pc
, ctx
->pc
);
699 gen_helper_div(REG(a
), cpu_env
, REG(a
), REG(b
));
702 case 0x32: /* udiv.l */
704 int a
= (opcode
>> 4) & 0xf;
705 int b
= opcode
& 0xf;
706 tcg_gen_movi_i32(cpu_pc
, ctx
->pc
);
707 gen_helper_udiv(REG(a
), cpu_env
, REG(a
), REG(b
));
710 case 0x33: /* mod.l */
712 int a
= (opcode
>> 4) & 0xf;
713 int b
= opcode
& 0xf;
714 tcg_gen_rem_i32(REG(a
), REG(a
), REG(b
));
717 case 0x34: /* umod.l */
719 int a
= (opcode
>> 4) & 0xf;
720 int b
= opcode
& 0xf;
721 tcg_gen_remu_i32(REG(a
), REG(a
), REG(b
));
726 TCGv temp
= tcg_temp_new_i32();
727 tcg_gen_movi_i32(cpu_pc
, ctx
->pc
);
728 tcg_gen_movi_i32(temp
, MOXIE_EX_BREAK
);
729 gen_helper_raise_exception(cpu_env
, temp
);
730 tcg_temp_free_i32(temp
);
733 case 0x36: /* ldo.b */
735 int a
= (opcode
>> 4) & 0xf;
736 int b
= opcode
& 0xf;
738 TCGv t1
= tcg_temp_new_i32();
739 TCGv t2
= tcg_temp_new_i32();
740 tcg_gen_addi_i32(t1
, REG(b
), cpu_ldl_code(env
, ctx
->pc
+2));
741 tcg_gen_qemu_ld8u(t2
, t1
, ctx
->memidx
);
742 tcg_gen_mov_i32(REG(a
), t2
);
744 tcg_temp_free_i32(t1
);
745 tcg_temp_free_i32(t2
);
750 case 0x37: /* sto.b */
752 int a
= (opcode
>> 4) & 0xf;
753 int b
= opcode
& 0xf;
755 TCGv t1
= tcg_temp_new_i32();
756 TCGv t2
= tcg_temp_new_i32();
757 tcg_gen_addi_i32(t1
, REG(a
), cpu_ldl_code(env
, ctx
->pc
+2));
758 tcg_gen_qemu_st8(REG(b
), t1
, ctx
->memidx
);
760 tcg_temp_free_i32(t1
);
761 tcg_temp_free_i32(t2
);
766 case 0x38: /* ldo.s */
768 int a
= (opcode
>> 4) & 0xf;
769 int b
= opcode
& 0xf;
771 TCGv t1
= tcg_temp_new_i32();
772 TCGv t2
= tcg_temp_new_i32();
773 tcg_gen_addi_i32(t1
, REG(b
), cpu_ldl_code(env
, ctx
->pc
+2));
774 tcg_gen_qemu_ld16u(t2
, t1
, ctx
->memidx
);
775 tcg_gen_mov_i32(REG(a
), t2
);
777 tcg_temp_free_i32(t1
);
778 tcg_temp_free_i32(t2
);
783 case 0x39: /* sto.s */
785 int a
= (opcode
>> 4) & 0xf;
786 int b
= opcode
& 0xf;
788 TCGv t1
= tcg_temp_new_i32();
789 TCGv t2
= tcg_temp_new_i32();
790 tcg_gen_addi_i32(t1
, REG(a
), cpu_ldl_code(env
, ctx
->pc
+2));
791 tcg_gen_qemu_st16(REG(b
), t1
, ctx
->memidx
);
792 tcg_temp_free_i32(t1
);
793 tcg_temp_free_i32(t2
);
800 TCGv temp
= tcg_temp_new_i32();
801 tcg_gen_movi_i32(cpu_pc
, ctx
->pc
);
802 tcg_gen_movi_i32(temp
, MOXIE_EX_BAD
);
803 gen_helper_raise_exception(cpu_env
, temp
);
804 tcg_temp_free_i32(temp
);
813 /* generate intermediate code for basic block 'tb'. */
814 void gen_intermediate_code(CPUMoxieState
*env
, struct TranslationBlock
*tb
)
816 MoxieCPU
*cpu
= moxie_env_get_cpu(env
);
817 CPUState
*cs
= CPU(cpu
);
819 target_ulong pc_start
;
820 int num_insns
, max_insns
;
827 ctx
.singlestep_enabled
= 0;
828 ctx
.bstate
= BS_NONE
;
830 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
831 if (max_insns
== 0) {
832 max_insns
= CF_COUNT_MASK
;
834 if (max_insns
> TCG_MAX_INSNS
) {
835 max_insns
= TCG_MAX_INSNS
;
840 tcg_gen_insn_start(ctx
.pc
);
843 if (unlikely(cpu_breakpoint_test(cs
, ctx
.pc
, BP_ANY
))) {
844 tcg_gen_movi_i32(cpu_pc
, ctx
.pc
);
845 gen_helper_debug(cpu_env
);
846 ctx
.bstate
= BS_EXCP
;
847 /* The address covered by the breakpoint must be included in
848 [tb->pc, tb->pc + tb->size) in order to for it to be
849 properly cleared -- thus we increment the PC here so that
850 the logic setting tb->size below does the right thing. */
852 goto done_generating
;
855 ctx
.opcode
= cpu_lduw_code(env
, ctx
.pc
);
856 ctx
.pc
+= decode_opc(cpu
, &ctx
);
858 if (num_insns
>= max_insns
) {
861 if (cs
->singlestep_enabled
) {
864 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0) {
867 } while (ctx
.bstate
== BS_NONE
&& !tcg_op_buf_full());
869 if (cs
->singlestep_enabled
) {
870 tcg_gen_movi_tl(cpu_pc
, ctx
.pc
);
871 gen_helper_debug(cpu_env
);
873 switch (ctx
.bstate
) {
876 gen_goto_tb(env
, &ctx
, 0, ctx
.pc
);
887 gen_tb_end(tb
, num_insns
);
889 tb
->size
= ctx
.pc
- pc_start
;
890 tb
->icount
= num_insns
;
893 void restore_state_to_opc(CPUMoxieState
*env
, TranslationBlock
*tb
,