hw/pci-host/prep.c

   1 /*
   2  * QEMU PREP PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2011-2013 Andreas Färber
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qemu-common.h"
  28 #include "qemu/datadir.h"
  29 #include "qemu/units.h"
  30 #include "qapi/error.h"
  31 #include "hw/pci/pci.h"
  32 #include "hw/pci/pci_bus.h"
  33 #include "hw/pci/pci_host.h"
  34 #include "hw/qdev-properties.h"
  35 #include "migration/vmstate.h"
  36 #include "hw/intc/i8259.h"
  37 #include "hw/irq.h"
  38 #include "hw/loader.h"
  39 #include "hw/or-irq.h"
  40 #include "exec/address-spaces.h"
  41 #include "elf.h"
  42 #include "qom/object.h"
  43
  44 #define TYPE_RAVEN_PCI_DEVICE "raven"
  45 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
  46
  47 OBJECT_DECLARE_SIMPLE_TYPE(RavenPCIState, RAVEN_PCI_DEVICE)
  48
  49 struct RavenPCIState {
  50     PCIDevice dev;
  51
  52     uint32_t elf_machine;
  53     char *bios_name;
  54     MemoryRegion bios;
  55 };
  56
  57 typedef struct PRePPCIState PREPPCIState;
  58 DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE,
  59                          TYPE_RAVEN_PCI_HOST_BRIDGE)
  60
  61 struct PRePPCIState {
  62     PCIHostState parent_obj;
  63
  64     qemu_or_irq *or_irq;
  65     qemu_irq pci_irqs[PCI_NUM_PINS];
  66     PCIBus pci_bus;
  67     AddressSpace pci_io_as;
  68     MemoryRegion pci_io;
  69     MemoryRegion pci_io_non_contiguous;
  70     MemoryRegion pci_memory;
  71     MemoryRegion pci_intack;
  72     MemoryRegion bm;
  73     MemoryRegion bm_ram_alias;
  74     MemoryRegion bm_pci_memory_alias;
  75     AddressSpace bm_as;
  76     RavenPCIState pci_dev;
  77
  78     int contiguous_map;
  79     bool is_legacy_prep;
  80 };
  81
  82 #define BIOS_SIZE (1 * MiB)
  83
  84 static inline uint32_t raven_pci_io_config(hwaddr addr)
  85 {
  86     int i;
  87
  88     for (i = 0; i < 11; i++) {
  89         if ((addr & (1 << (11 + i))) != 0) {
  90             break;
  91         }
  92     }
  93     return (addr & 0x7ff) |  (i << 11);
  94 }
  95
  96 static void raven_pci_io_write(void *opaque, hwaddr addr,
  97                                uint64_t val, unsigned int size)
  98 {
  99     PREPPCIState *s = opaque;
 100     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 101     pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
 102 }
 103
 104 static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
 105                                   unsigned int size)
 106 {
 107     PREPPCIState *s = opaque;
 108     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 109     return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
 110 }
 111
 112 static const MemoryRegionOps raven_pci_io_ops = {
 113     .read = raven_pci_io_read,
 114     .write = raven_pci_io_write,
 115     .endianness = DEVICE_LITTLE_ENDIAN,
 116 };
 117
 118 static uint64_t raven_intack_read(void *opaque, hwaddr addr,
 119                                   unsigned int size)
 120 {
 121     return pic_read_irq(isa_pic);
 122 }
 123
 124 static const MemoryRegionOps raven_intack_ops = {
 125     .read = raven_intack_read,
 126     .valid = {
 127         .max_access_size = 1,
 128     },
 129 };
 130
 131 static inline hwaddr raven_io_address(PREPPCIState *s,
 132                                       hwaddr addr)
 133 {
 134     if (s->contiguous_map == 0) {
 135         /* 64 KB contiguous space for IOs */
 136         addr &= 0xFFFF;
 137     } else {
 138         /* 8 MB non-contiguous space for IOs */
 139         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 140     }
 141
 142     /* FIXME: handle endianness switch */
 143
 144     return addr;
 145 }
 146
 147 static uint64_t raven_io_read(void *opaque, hwaddr addr,
 148                               unsigned int size)
 149 {
 150     PREPPCIState *s = opaque;
 151     uint8_t buf[4];
 152
 153     addr = raven_io_address(s, addr);
 154     address_space_read(&s->pci_io_as, addr + 0x80000000,
 155                        MEMTXATTRS_UNSPECIFIED, buf, size);
 156
 157     if (size == 1) {
 158         return buf[0];
 159     } else if (size == 2) {
 160         return lduw_le_p(buf);
 161     } else if (size == 4) {
 162         return ldl_le_p(buf);
 163     } else {
 164         g_assert_not_reached();
 165     }
 166 }
 167
 168 static void raven_io_write(void *opaque, hwaddr addr,
 169                            uint64_t val, unsigned int size)
 170 {
 171     PREPPCIState *s = opaque;
 172     uint8_t buf[4];
 173
 174     addr = raven_io_address(s, addr);
 175
 176     if (size == 1) {
 177         buf[0] = val;
 178     } else if (size == 2) {
 179         stw_le_p(buf, val);
 180     } else if (size == 4) {
 181         stl_le_p(buf, val);
 182     } else {
 183         g_assert_not_reached();
 184     }
 185
 186     address_space_write(&s->pci_io_as, addr + 0x80000000,
 187                         MEMTXATTRS_UNSPECIFIED, buf, size);
 188 }
 189
 190 static const MemoryRegionOps raven_io_ops = {
 191     .read = raven_io_read,
 192     .write = raven_io_write,
 193     .endianness = DEVICE_LITTLE_ENDIAN,
 194     .impl.max_access_size = 4,
 195     .valid.unaligned = true,
 196 };
 197
 198 static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
 199 {
 200     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 201 }
 202
 203 static void raven_set_irq(void *opaque, int irq_num, int level)
 204 {
 205     PREPPCIState *s = opaque;
 206
 207     qemu_set_irq(s->pci_irqs[irq_num], level);
 208 }
 209
 210 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
 211                                              int devfn)
 212 {
 213     PREPPCIState *s = opaque;
 214
 215     return &s->bm_as;
 216 }
 217
 218 static void raven_change_gpio(void *opaque, int n, int level)
 219 {
 220     PREPPCIState *s = opaque;
 221
 222     s->contiguous_map = level;
 223 }
 224
 225 static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
 226 {
 227     SysBusDevice *dev = SYS_BUS_DEVICE(d);
 228     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 229     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
 230     MemoryRegion *address_space_mem = get_system_memory();
 231     int i;
 232
 233     if (s->is_legacy_prep) {
 234         for (i = 0; i < PCI_NUM_PINS; i++) {
 235             sysbus_init_irq(dev, &s->pci_irqs[i]);
 236         }
 237     } else {
 238         /* According to PReP specification section 6.1.6 "System Interrupt
 239          * Assignments", all PCI interrupts are routed via IRQ 15 */
 240         s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
 241         object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS,
 242                                 &error_fatal);
 243         qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal);
 244         sysbus_init_irq(dev, &s->or_irq->out_irq);
 245
 246         for (i = 0; i < PCI_NUM_PINS; i++) {
 247             s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
 248         }
 249     }
 250
 251     qdev_init_gpio_in(d, raven_change_gpio, 1);
 252
 253     pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS);
 254
 255     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
 256                           "pci-conf-idx", 4);
 257     memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
 258
 259     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
 260                           "pci-conf-data", 4);
 261     memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
 262
 263     memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
 264                           "pciio", 0x00400000);
 265     memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
 266
 267     memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
 268                           "pci-intack", 1);
 269     memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
 270
 271     /* TODO Remove once realize propagates to child devices. */
 272     qdev_realize(DEVICE(&s->pci_dev), BUS(&s->pci_bus), errp);
 273 }
 274
 275 static void raven_pcihost_initfn(Object *obj)
 276 {
 277     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 278     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
 279     MemoryRegion *address_space_mem = get_system_memory();
 280     DeviceState *pci_dev;
 281
 282     memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
 283     memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
 284                           "pci-io-non-contiguous", 0x00800000);
 285     memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
 286     address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
 287
 288     /* CPU address space */
 289     memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
 290     memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
 291                                         &s->pci_io_non_contiguous, 1);
 292     memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
 293     pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
 294                              &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
 295
 296     /* Bus master address space */
 297     memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB);
 298     memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
 299                              &s->pci_memory, 0,
 300                              memory_region_size(&s->pci_memory));
 301     memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
 302                              get_system_memory(), 0, 0x80000000);
 303     memory_region_add_subregion(&s->bm, 0         , &s->bm_pci_memory_alias);
 304     memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
 305     address_space_init(&s->bm_as, &s->bm, "raven-bm");
 306     pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
 307
 308     h->bus = &s->pci_bus;
 309
 310     object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
 311     pci_dev = DEVICE(&s->pci_dev);
 312     object_property_set_int(OBJECT(&s->pci_dev), "addr", PCI_DEVFN(0, 0),
 313                             NULL);
 314     qdev_prop_set_bit(pci_dev, "multifunction", false);
 315 }
 316
 317 static void raven_realize(PCIDevice *d, Error **errp)
 318 {
 319     RavenPCIState *s = RAVEN_PCI_DEVICE(d);
 320     char *filename;
 321     int bios_size = -1;
 322
 323     d->config[0x0C] = 0x08; // cache_line_size
 324     d->config[0x0D] = 0x10; // latency_timer
 325     d->config[0x34] = 0x00; // capabilities_pointer
 326
 327     memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
 328                                      &error_fatal);
 329     memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
 330                                 &s->bios);
 331     if (s->bios_name) {
 332         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
 333         if (filename) {
 334             if (s->elf_machine != EM_NONE) {
 335                 bios_size = load_elf(filename, NULL, NULL, NULL, NULL,
 336                                      NULL, NULL, NULL, 1, s->elf_machine,
 337                                      0, 0);
 338             }
 339             if (bios_size < 0) {
 340                 bios_size = get_image_size(filename);
 341                 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 342                     hwaddr bios_addr;
 343                     bios_size = (bios_size + 0xfff) & ~0xfff;
 344                     bios_addr = (uint32_t)(-BIOS_SIZE);
 345                     bios_size = load_image_targphys(filename, bios_addr,
 346                                                     bios_size);
 347                 }
 348             }
 349         }
 350         g_free(filename);
 351         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 352             memory_region_del_subregion(get_system_memory(), &s->bios);
 353             error_setg(errp, "Could not load bios image '%s'", s->bios_name);
 354             return;
 355         }
 356     }
 357
 358     vmstate_register_ram_global(&s->bios);
 359 }
 360
 361 static const VMStateDescription vmstate_raven = {
 362     .name = "raven",
 363     .version_id = 0,
 364     .minimum_version_id = 0,
 365     .fields = (VMStateField[]) {
 366         VMSTATE_PCI_DEVICE(dev, RavenPCIState),
 367         VMSTATE_END_OF_LIST()
 368     },
 369 };
 370
 371 static void raven_class_init(ObjectClass *klass, void *data)
 372 {
 373     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 374     DeviceClass *dc = DEVICE_CLASS(klass);
 375
 376     k->realize = raven_realize;
 377     k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
 378     k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
 379     k->revision = 0x00;
 380     k->class_id = PCI_CLASS_BRIDGE_HOST;
 381     dc->desc = "PReP Host Bridge - Motorola Raven";
 382     dc->vmsd = &vmstate_raven;
 383     /*
 384      * Reason: PCI-facing part of the host bridge, not usable without
 385      * the host-facing part, which can't be device_add'ed, yet.
 386      */
 387     dc->user_creatable = false;
 388 }
 389
 390 static const TypeInfo raven_info = {
 391     .name = TYPE_RAVEN_PCI_DEVICE,
 392     .parent = TYPE_PCI_DEVICE,
 393     .instance_size = sizeof(RavenPCIState),
 394     .class_init = raven_class_init,
 395     .interfaces = (InterfaceInfo[]) {
 396         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 397         { },
 398     },
 399 };
 400
 401 static Property raven_pcihost_properties[] = {
 402     DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
 403                        EM_NONE),
 404     DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
 405     /* Temporary workaround until legacy prep machine is removed */
 406     DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
 407                      false),
 408     DEFINE_PROP_END_OF_LIST()
 409 };
 410
 411 static void raven_pcihost_class_init(ObjectClass *klass, void *data)
 412 {
 413     DeviceClass *dc = DEVICE_CLASS(klass);
 414
 415     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 416     dc->realize = raven_pcihost_realizefn;
 417     device_class_set_props(dc, raven_pcihost_properties);
 418     dc->fw_name = "pci";
 419 }
 420
 421 static const TypeInfo raven_pcihost_info = {
 422     .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
 423     .parent = TYPE_PCI_HOST_BRIDGE,
 424     .instance_size = sizeof(PREPPCIState),
 425     .instance_init = raven_pcihost_initfn,
 426     .class_init = raven_pcihost_class_init,
 427 };
 428
 429 static void raven_register_types(void)
 430 {
 431     type_register_static(&raven_pcihost_info);
 432     type_register_static(&raven_info);
 433 }
 434
 435 type_init(raven_register_types)