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xen/pt/msi: Add the register value when printing logging and error messages
[qemu/ar7.git] / hw / xen / xen_pt_config_init.c
blob56c84e115fa80c0e2c70b118656e7e2e8936764c
1 /*
2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 * This work is licensed under the terms of the GNU GPL, version 2. See
6 * the COPYING file in the top-level directory.
7 *
8 * Alex Novik <alex@neocleus.com>
9 * Allen Kay <allen.m.kay@intel.com>
10 * Guy Zana <guy@neocleus.com>
11 *
12 * This file implements direct PCI assignment to a HVM guest
13 */
14
15 #include "qemu/timer.h"
16 #include "hw/xen/xen_backend.h"
17 #include "xen_pt.h"
18
19 #define XEN_PT_MERGE_VALUE(value, data, val_mask) \
20 (((value) & (val_mask)) | ((data) & ~(val_mask)))
21
22 #define XEN_PT_INVALID_REG 0xFFFFFFFF /* invalid register value */
23
24 /* prototype */
25
26 static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
27 uint32_t real_offset, uint32_t *data);
28
29
30 /* helper */
31
32 /* A return value of 1 means the capability should NOT be exposed to guest. */
33 static int xen_pt_hide_dev_cap(const XenHostPCIDevice *d, uint8_t grp_id)
34 {
35 switch (grp_id) {
36 case PCI_CAP_ID_EXP:
37 /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE
38 * Controller looks trivial, e.g., the PCI Express Capabilities
39 * Register is 0. We should not try to expose it to guest.
40 *
41 * The datasheet is available at
42 * http://download.intel.com/design/network/datashts/82599_datasheet.pdf
43 *
44 * See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the
45 * PCI Express Capability Structure of the VF of Intel 82599 10GbE
46 * Controller looks trivial, e.g., the PCI Express Capabilities
47 * Register is 0, so the Capability Version is 0 and
48 * xen_pt_pcie_size_init() would fail.
49 */
50 if (d->vendor_id == PCI_VENDOR_ID_INTEL &&
51 d->device_id == PCI_DEVICE_ID_INTEL_82599_SFP_VF) {
52 return 1;
53 }
54 break;
55 }
56 return 0;
57 }
58
59 /* find emulate register group entry */
60 XenPTRegGroup *xen_pt_find_reg_grp(XenPCIPassthroughState *s, uint32_t address)
61 {
62 XenPTRegGroup *entry = NULL;
63
64 /* find register group entry */
65 QLIST_FOREACH(entry, &s->reg_grps, entries) {
66 /* check address */
67 if ((entry->base_offset <= address)
68 && ((entry->base_offset + entry->size) > address)) {
69 return entry;
70 }
71 }
72
73 /* group entry not found */
74 return NULL;
75 }
76
77 /* find emulate register entry */
78 XenPTReg *xen_pt_find_reg(XenPTRegGroup *reg_grp, uint32_t address)
79 {
80 XenPTReg *reg_entry = NULL;
81 XenPTRegInfo *reg = NULL;
82 uint32_t real_offset = 0;
83
84 /* find register entry */
85 QLIST_FOREACH(reg_entry, &reg_grp->reg_tbl_list, entries) {
86 reg = reg_entry->reg;
87 real_offset = reg_grp->base_offset + reg->offset;
88 /* check address */
89 if ((real_offset <= address)
90 && ((real_offset + reg->size) > address)) {
91 return reg_entry;
92 }
93 }
94
95 return NULL;
96 }
97
98 static uint32_t get_throughable_mask(const XenPCIPassthroughState *s,
99 XenPTRegInfo *reg, uint32_t valid_mask)
100 {
101 uint32_t throughable_mask = ~(reg->emu_mask | reg->ro_mask);
102
103 if (!s->permissive) {
104 throughable_mask &= ~reg->res_mask;
105 }
106
107 return throughable_mask & valid_mask;
108 }
109
110 /****************
111 * general register functions
112 */
113
114 /* register initialization function */
115
116 static int xen_pt_common_reg_init(XenPCIPassthroughState *s,
117 XenPTRegInfo *reg, uint32_t real_offset,
118 uint32_t *data)
119 {
120 *data = reg->init_val;
121 return 0;
122 }
123
124 /* Read register functions */
125
126 static int xen_pt_byte_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
127 uint8_t *value, uint8_t valid_mask)
128 {
129 XenPTRegInfo *reg = cfg_entry->reg;
130 uint8_t valid_emu_mask = 0;
131
132 /* emulate byte register */
133 valid_emu_mask = reg->emu_mask & valid_mask;
134 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
135
136 return 0;
137 }
138 static int xen_pt_word_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
139 uint16_t *value, uint16_t valid_mask)
140 {
141 XenPTRegInfo *reg = cfg_entry->reg;
142 uint16_t valid_emu_mask = 0;
143
144 /* emulate word register */
145 valid_emu_mask = reg->emu_mask & valid_mask;
146 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
147
148 return 0;
149 }
150 static int xen_pt_long_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
151 uint32_t *value, uint32_t valid_mask)
152 {
153 XenPTRegInfo *reg = cfg_entry->reg;
154 uint32_t valid_emu_mask = 0;
155
156 /* emulate long register */
157 valid_emu_mask = reg->emu_mask & valid_mask;
158 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
159
160 return 0;
161 }
162
163 /* Write register functions */
164
165 static int xen_pt_byte_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
166 uint8_t *val, uint8_t dev_value,
167 uint8_t valid_mask)
168 {
169 XenPTRegInfo *reg = cfg_entry->reg;
170 uint8_t writable_mask = 0;
171 uint8_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
172
173 /* modify emulate register */
174 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
175 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
176
177 /* create value for writing to I/O device register */
178 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
179
180 return 0;
181 }
182 static int xen_pt_word_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
183 uint16_t *val, uint16_t dev_value,
184 uint16_t valid_mask)
185 {
186 XenPTRegInfo *reg = cfg_entry->reg;
187 uint16_t writable_mask = 0;
188 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
189
190 /* modify emulate register */
191 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
192 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
193
194 /* create value for writing to I/O device register */
195 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
196
197 return 0;
198 }
199 static int xen_pt_long_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
200 uint32_t *val, uint32_t dev_value,
201 uint32_t valid_mask)
202 {
203 XenPTRegInfo *reg = cfg_entry->reg;
204 uint32_t writable_mask = 0;
205 uint32_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
206
207 /* modify emulate register */
208 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
209 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
210
211 /* create value for writing to I/O device register */
212 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
213
214 return 0;
215 }
216
217
218 /* XenPTRegInfo declaration
219 * - only for emulated register (either a part or whole bit).
220 * - for passthrough register that need special behavior (like interacting with
221 * other component), set emu_mask to all 0 and specify r/w func properly.
222 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
223 */
224
225 /********************
226 * Header Type0
227 */
228
229 static int xen_pt_vendor_reg_init(XenPCIPassthroughState *s,
230 XenPTRegInfo *reg, uint32_t real_offset,
231 uint32_t *data)
232 {
233 *data = s->real_device.vendor_id;
234 return 0;
235 }
236 static int xen_pt_device_reg_init(XenPCIPassthroughState *s,
237 XenPTRegInfo *reg, uint32_t real_offset,
238 uint32_t *data)
239 {
240 *data = s->real_device.device_id;
241 return 0;
242 }
243 static int xen_pt_status_reg_init(XenPCIPassthroughState *s,
244 XenPTRegInfo *reg, uint32_t real_offset,
245 uint32_t *data)
246 {
247 XenPTRegGroup *reg_grp_entry = NULL;
248 XenPTReg *reg_entry = NULL;
249 uint32_t reg_field = 0;
250
251 /* find Header register group */
252 reg_grp_entry = xen_pt_find_reg_grp(s, PCI_CAPABILITY_LIST);
253 if (reg_grp_entry) {
254 /* find Capabilities Pointer register */
255 reg_entry = xen_pt_find_reg(reg_grp_entry, PCI_CAPABILITY_LIST);
256 if (reg_entry) {
257 /* check Capabilities Pointer register */
258 if (reg_entry->data) {
259 reg_field |= PCI_STATUS_CAP_LIST;
260 } else {
261 reg_field &= ~PCI_STATUS_CAP_LIST;
262 }
263 } else {
264 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTReg*"
265 " for Capabilities Pointer register."
266 " (%s)\n", __func__);
267 return -1;
268 }
269 } else {
270 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTRegGroup"
271 " for Header. (%s)\n", __func__);
272 return -1;
273 }
274
275 *data = reg_field;
276 return 0;
277 }
278 static int xen_pt_header_type_reg_init(XenPCIPassthroughState *s,
279 XenPTRegInfo *reg, uint32_t real_offset,
280 uint32_t *data)
281 {
282 /* read PCI_HEADER_TYPE */
283 *data = reg->init_val | 0x80;
284 return 0;
285 }
286
287 /* initialize Interrupt Pin register */
288 static int xen_pt_irqpin_reg_init(XenPCIPassthroughState *s,
289 XenPTRegInfo *reg, uint32_t real_offset,
290 uint32_t *data)
291 {
292 *data = xen_pt_pci_read_intx(s);
293 return 0;
294 }
295
296 /* Command register */
297 static int xen_pt_cmd_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
298 uint16_t *val, uint16_t dev_value,
299 uint16_t valid_mask)
300 {
301 XenPTRegInfo *reg = cfg_entry->reg;
302 uint16_t writable_mask = 0;
303 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
304
305 /* modify emulate register */
306 writable_mask = ~reg->ro_mask & valid_mask;
307 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
308
309 /* create value for writing to I/O device register */
310 if (*val & PCI_COMMAND_INTX_DISABLE) {
311 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
312 } else {
313 if (s->machine_irq) {
314 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
315 }
316 }
317
318 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
319
320 return 0;
321 }
322
323 /* BAR */
324 #define XEN_PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */
325 #define XEN_PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */
326 #define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
327 #define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
328
329 static bool is_64bit_bar(PCIIORegion *r)
330 {
331 return !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
332 }
333
334 static uint64_t xen_pt_get_bar_size(PCIIORegion *r)
335 {
336 if (is_64bit_bar(r)) {
337 uint64_t size64;
338 size64 = (r + 1)->size;
339 size64 <<= 32;
340 size64 += r->size;
341 return size64;
342 }
343 return r->size;
344 }
345
346 static XenPTBarFlag xen_pt_bar_reg_parse(XenPCIPassthroughState *s,
347 int index)
348 {
349 PCIDevice *d = &s->dev;
350 XenPTRegion *region = NULL;
351 PCIIORegion *r;
352
353 /* check 64bit BAR */
354 if ((0 < index) && (index < PCI_ROM_SLOT)) {
355 int type = s->real_device.io_regions[index - 1].type;
356
357 if ((type & XEN_HOST_PCI_REGION_TYPE_MEM)
358 && (type & XEN_HOST_PCI_REGION_TYPE_MEM_64)) {
359 region = &s->bases[index - 1];
360 if (region->bar_flag != XEN_PT_BAR_FLAG_UPPER) {
361 return XEN_PT_BAR_FLAG_UPPER;
362 }
363 }
364 }
365
366 /* check unused BAR */
367 r = &d->io_regions[index];
368 if (!xen_pt_get_bar_size(r)) {
369 return XEN_PT_BAR_FLAG_UNUSED;
370 }
371
372 /* for ExpROM BAR */
373 if (index == PCI_ROM_SLOT) {
374 return XEN_PT_BAR_FLAG_MEM;
375 }
376
377 /* check BAR I/O indicator */
378 if (s->real_device.io_regions[index].type & XEN_HOST_PCI_REGION_TYPE_IO) {
379 return XEN_PT_BAR_FLAG_IO;
380 } else {
381 return XEN_PT_BAR_FLAG_MEM;
382 }
383 }
384
385 static inline uint32_t base_address_with_flags(XenHostPCIIORegion *hr)
386 {
387 if (hr->type & XEN_HOST_PCI_REGION_TYPE_IO) {
388 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_IO_MASK);
389 } else {
390 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_MEM_MASK);
391 }
392 }
393
394 static int xen_pt_bar_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
395 uint32_t real_offset, uint32_t *data)
396 {
397 uint32_t reg_field = 0;
398 int index;
399
400 index = xen_pt_bar_offset_to_index(reg->offset);
401 if (index < 0 || index >= PCI_NUM_REGIONS) {
402 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
403 return -1;
404 }
405
406 /* set BAR flag */
407 s->bases[index].bar_flag = xen_pt_bar_reg_parse(s, index);
408 if (s->bases[index].bar_flag == XEN_PT_BAR_FLAG_UNUSED) {
409 reg_field = XEN_PT_INVALID_REG;
410 }
411
412 *data = reg_field;
413 return 0;
414 }
415 static int xen_pt_bar_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
416 uint32_t *value, uint32_t valid_mask)
417 {
418 XenPTRegInfo *reg = cfg_entry->reg;
419 uint32_t valid_emu_mask = 0;
420 uint32_t bar_emu_mask = 0;
421 int index;
422
423 /* get BAR index */
424 index = xen_pt_bar_offset_to_index(reg->offset);
425 if (index < 0 || index >= PCI_NUM_REGIONS - 1) {
426 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
427 return -1;
428 }
429
430 /* use fixed-up value from kernel sysfs */
431 *value = base_address_with_flags(&s->real_device.io_regions[index]);
432
433 /* set emulate mask depend on BAR flag */
434 switch (s->bases[index].bar_flag) {
435 case XEN_PT_BAR_FLAG_MEM:
436 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
437 break;
438 case XEN_PT_BAR_FLAG_IO:
439 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
440 break;
441 case XEN_PT_BAR_FLAG_UPPER:
442 bar_emu_mask = XEN_PT_BAR_ALLF;
443 break;
444 default:
445 break;
446 }
447
448 /* emulate BAR */
449 valid_emu_mask = bar_emu_mask & valid_mask;
450 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
451
452 return 0;
453 }
454 static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
455 uint32_t *val, uint32_t dev_value,
456 uint32_t valid_mask)
457 {
458 XenPTRegInfo *reg = cfg_entry->reg;
459 XenPTRegion *base = NULL;
460 PCIDevice *d = &s->dev;
461 const PCIIORegion *r;
462 uint32_t writable_mask = 0;
463 uint32_t bar_emu_mask = 0;
464 uint32_t bar_ro_mask = 0;
465 uint32_t r_size = 0;
466 int index = 0;
467
468 index = xen_pt_bar_offset_to_index(reg->offset);
469 if (index < 0 || index >= PCI_NUM_REGIONS) {
470 XEN_PT_ERR(d, "Internal error: Invalid BAR index [%d].\n", index);
471 return -1;
472 }
473
474 r = &d->io_regions[index];
475 base = &s->bases[index];
476 r_size = xen_pt_get_emul_size(base->bar_flag, r->size);
477
478 /* set emulate mask and read-only mask values depend on the BAR flag */
479 switch (s->bases[index].bar_flag) {
480 case XEN_PT_BAR_FLAG_MEM:
481 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
482 if (!r_size) {
483 /* low 32 bits mask for 64 bit bars */
484 bar_ro_mask = XEN_PT_BAR_ALLF;
485 } else {
486 bar_ro_mask = XEN_PT_BAR_MEM_RO_MASK | (r_size - 1);
487 }
488 break;
489 case XEN_PT_BAR_FLAG_IO:
490 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
491 bar_ro_mask = XEN_PT_BAR_IO_RO_MASK | (r_size - 1);
492 break;
493 case XEN_PT_BAR_FLAG_UPPER:
494 bar_emu_mask = XEN_PT_BAR_ALLF;
495 bar_ro_mask = r_size ? r_size - 1 : 0;
496 break;
497 default:
498 break;
499 }
500
501 /* modify emulate register */
502 writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
503 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
504
505 /* check whether we need to update the virtual region address or not */
506 switch (s->bases[index].bar_flag) {
507 case XEN_PT_BAR_FLAG_UPPER:
508 case XEN_PT_BAR_FLAG_MEM:
509 /* nothing to do */
510 break;
511 case XEN_PT_BAR_FLAG_IO:
512 /* nothing to do */
513 break;
514 default:
515 break;
516 }
517
518 /* create value for writing to I/O device register */
519 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
520
521 return 0;
522 }
523
524 /* write Exp ROM BAR */
525 static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState *s,
526 XenPTReg *cfg_entry, uint32_t *val,
527 uint32_t dev_value, uint32_t valid_mask)
528 {
529 XenPTRegInfo *reg = cfg_entry->reg;
530 XenPTRegion *base = NULL;
531 PCIDevice *d = (PCIDevice *)&s->dev;
532 uint32_t writable_mask = 0;
533 uint32_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
534 pcibus_t r_size = 0;
535 uint32_t bar_ro_mask = 0;
536
537 r_size = d->io_regions[PCI_ROM_SLOT].size;
538 base = &s->bases[PCI_ROM_SLOT];
539 /* align memory type resource size */
540 r_size = xen_pt_get_emul_size(base->bar_flag, r_size);
541
542 /* set emulate mask and read-only mask */
543 bar_ro_mask = (reg->ro_mask | (r_size - 1)) & ~PCI_ROM_ADDRESS_ENABLE;
544
545 /* modify emulate register */
546 writable_mask = ~bar_ro_mask & valid_mask;
547 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
548
549 /* create value for writing to I/O device register */
550 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
551
552 return 0;
553 }
554
555 static int xen_pt_intel_opregion_read(XenPCIPassthroughState *s,
556 XenPTReg *cfg_entry,
557 uint32_t *value, uint32_t valid_mask)
558 {
559 *value = igd_read_opregion(s);
560 return 0;
561 }
562
563 static int xen_pt_intel_opregion_write(XenPCIPassthroughState *s,
564 XenPTReg *cfg_entry, uint32_t *value,
565 uint32_t dev_value, uint32_t valid_mask)
566 {
567 igd_write_opregion(s, *value);
568 return 0;
569 }
570
571 /* Header Type0 reg static information table */
572 static XenPTRegInfo xen_pt_emu_reg_header0[] = {
573 /* Vendor ID reg */
574 {
575 .offset = PCI_VENDOR_ID,
576 .size = 2,
577 .init_val = 0x0000,
578 .ro_mask = 0xFFFF,
579 .emu_mask = 0xFFFF,
580 .init = xen_pt_vendor_reg_init,
581 .u.w.read = xen_pt_word_reg_read,
582 .u.w.write = xen_pt_word_reg_write,
583 },
584 /* Device ID reg */
585 {
586 .offset = PCI_DEVICE_ID,
587 .size = 2,
588 .init_val = 0x0000,
589 .ro_mask = 0xFFFF,
590 .emu_mask = 0xFFFF,
591 .init = xen_pt_device_reg_init,
592 .u.w.read = xen_pt_word_reg_read,
593 .u.w.write = xen_pt_word_reg_write,
594 },
595 /* Command reg */
596 {
597 .offset = PCI_COMMAND,
598 .size = 2,
599 .init_val = 0x0000,
600 .res_mask = 0xF880,
601 .emu_mask = 0x0743,
602 .init = xen_pt_common_reg_init,
603 .u.w.read = xen_pt_word_reg_read,
604 .u.w.write = xen_pt_cmd_reg_write,
605 },
606 /* Capabilities Pointer reg */
607 {
608 .offset = PCI_CAPABILITY_LIST,
609 .size = 1,
610 .init_val = 0x00,
611 .ro_mask = 0xFF,
612 .emu_mask = 0xFF,
613 .init = xen_pt_ptr_reg_init,
614 .u.b.read = xen_pt_byte_reg_read,
615 .u.b.write = xen_pt_byte_reg_write,
616 },
617 /* Status reg */
618 /* use emulated Cap Ptr value to initialize,
619 * so need to be declared after Cap Ptr reg
620 */
621 {
622 .offset = PCI_STATUS,
623 .size = 2,
624 .init_val = 0x0000,
625 .res_mask = 0x0007,
626 .ro_mask = 0x06F8,
627 .emu_mask = 0x0010,
628 .init = xen_pt_status_reg_init,
629 .u.w.read = xen_pt_word_reg_read,
630 .u.w.write = xen_pt_word_reg_write,
631 },
632 /* Cache Line Size reg */
633 {
634 .offset = PCI_CACHE_LINE_SIZE,
635 .size = 1,
636 .init_val = 0x00,
637 .ro_mask = 0x00,
638 .emu_mask = 0xFF,
639 .init = xen_pt_common_reg_init,
640 .u.b.read = xen_pt_byte_reg_read,
641 .u.b.write = xen_pt_byte_reg_write,
642 },
643 /* Latency Timer reg */
644 {
645 .offset = PCI_LATENCY_TIMER,
646 .size = 1,
647 .init_val = 0x00,
648 .ro_mask = 0x00,
649 .emu_mask = 0xFF,
650 .init = xen_pt_common_reg_init,
651 .u.b.read = xen_pt_byte_reg_read,
652 .u.b.write = xen_pt_byte_reg_write,
653 },
654 /* Header Type reg */
655 {
656 .offset = PCI_HEADER_TYPE,
657 .size = 1,
658 .init_val = 0x00,
659 .ro_mask = 0xFF,
660 .emu_mask = 0x00,
661 .init = xen_pt_header_type_reg_init,
662 .u.b.read = xen_pt_byte_reg_read,
663 .u.b.write = xen_pt_byte_reg_write,
664 },
665 /* Interrupt Line reg */
666 {
667 .offset = PCI_INTERRUPT_LINE,
668 .size = 1,
669 .init_val = 0x00,
670 .ro_mask = 0x00,
671 .emu_mask = 0xFF,
672 .init = xen_pt_common_reg_init,
673 .u.b.read = xen_pt_byte_reg_read,
674 .u.b.write = xen_pt_byte_reg_write,
675 },
676 /* Interrupt Pin reg */
677 {
678 .offset = PCI_INTERRUPT_PIN,
679 .size = 1,
680 .init_val = 0x00,
681 .ro_mask = 0xFF,
682 .emu_mask = 0xFF,
683 .init = xen_pt_irqpin_reg_init,
684 .u.b.read = xen_pt_byte_reg_read,
685 .u.b.write = xen_pt_byte_reg_write,
686 },
687 /* BAR 0 reg */
688 /* mask of BAR need to be decided later, depends on IO/MEM type */
689 {
690 .offset = PCI_BASE_ADDRESS_0,
691 .size = 4,
692 .init_val = 0x00000000,
693 .init = xen_pt_bar_reg_init,
694 .u.dw.read = xen_pt_bar_reg_read,
695 .u.dw.write = xen_pt_bar_reg_write,
696 },
697 /* BAR 1 reg */
698 {
699 .offset = PCI_BASE_ADDRESS_1,
700 .size = 4,
701 .init_val = 0x00000000,
702 .init = xen_pt_bar_reg_init,
703 .u.dw.read = xen_pt_bar_reg_read,
704 .u.dw.write = xen_pt_bar_reg_write,
705 },
706 /* BAR 2 reg */
707 {
708 .offset = PCI_BASE_ADDRESS_2,
709 .size = 4,
710 .init_val = 0x00000000,
711 .init = xen_pt_bar_reg_init,
712 .u.dw.read = xen_pt_bar_reg_read,
713 .u.dw.write = xen_pt_bar_reg_write,
714 },
715 /* BAR 3 reg */
716 {
717 .offset = PCI_BASE_ADDRESS_3,
718 .size = 4,
719 .init_val = 0x00000000,
720 .init = xen_pt_bar_reg_init,
721 .u.dw.read = xen_pt_bar_reg_read,
722 .u.dw.write = xen_pt_bar_reg_write,
723 },
724 /* BAR 4 reg */
725 {
726 .offset = PCI_BASE_ADDRESS_4,
727 .size = 4,
728 .init_val = 0x00000000,
729 .init = xen_pt_bar_reg_init,
730 .u.dw.read = xen_pt_bar_reg_read,
731 .u.dw.write = xen_pt_bar_reg_write,
732 },
733 /* BAR 5 reg */
734 {
735 .offset = PCI_BASE_ADDRESS_5,
736 .size = 4,
737 .init_val = 0x00000000,
738 .init = xen_pt_bar_reg_init,
739 .u.dw.read = xen_pt_bar_reg_read,
740 .u.dw.write = xen_pt_bar_reg_write,
741 },
742 /* Expansion ROM BAR reg */
743 {
744 .offset = PCI_ROM_ADDRESS,
745 .size = 4,
746 .init_val = 0x00000000,
747 .ro_mask = ~PCI_ROM_ADDRESS_MASK & ~PCI_ROM_ADDRESS_ENABLE,
748 .emu_mask = (uint32_t)PCI_ROM_ADDRESS_MASK,
749 .init = xen_pt_bar_reg_init,
750 .u.dw.read = xen_pt_long_reg_read,
751 .u.dw.write = xen_pt_exp_rom_bar_reg_write,
752 },
753 {
754 .size = 0,
755 },
756 };
757
758
759 /*********************************
760 * Vital Product Data Capability
761 */
762
763 /* Vital Product Data Capability Structure reg static information table */
764 static XenPTRegInfo xen_pt_emu_reg_vpd[] = {
765 {
766 .offset = PCI_CAP_LIST_NEXT,
767 .size = 1,
768 .init_val = 0x00,
769 .ro_mask = 0xFF,
770 .emu_mask = 0xFF,
771 .init = xen_pt_ptr_reg_init,
772 .u.b.read = xen_pt_byte_reg_read,
773 .u.b.write = xen_pt_byte_reg_write,
774 },
775 {
776 .offset = PCI_VPD_ADDR,
777 .size = 2,
778 .ro_mask = 0x0003,
779 .emu_mask = 0x0003,
780 .init = xen_pt_common_reg_init,
781 .u.w.read = xen_pt_word_reg_read,
782 .u.w.write = xen_pt_word_reg_write,
783 },
784 {
785 .size = 0,
786 },
787 };
788
789
790 /**************************************
791 * Vendor Specific Capability
792 */
793
794 /* Vendor Specific Capability Structure reg static information table */
795 static XenPTRegInfo xen_pt_emu_reg_vendor[] = {
796 {
797 .offset = PCI_CAP_LIST_NEXT,
798 .size = 1,
799 .init_val = 0x00,
800 .ro_mask = 0xFF,
801 .emu_mask = 0xFF,
802 .init = xen_pt_ptr_reg_init,
803 .u.b.read = xen_pt_byte_reg_read,
804 .u.b.write = xen_pt_byte_reg_write,
805 },
806 {
807 .size = 0,
808 },
809 };
810
811
812 /*****************************
813 * PCI Express Capability
814 */
815
816 static inline uint8_t get_capability_version(XenPCIPassthroughState *s,
817 uint32_t offset)
818 {
819 uint8_t flags = pci_get_byte(s->dev.config + offset + PCI_EXP_FLAGS);
820 return flags & PCI_EXP_FLAGS_VERS;
821 }
822
823 static inline uint8_t get_device_type(XenPCIPassthroughState *s,
824 uint32_t offset)
825 {
826 uint8_t flags = pci_get_byte(s->dev.config + offset + PCI_EXP_FLAGS);
827 return (flags & PCI_EXP_FLAGS_TYPE) >> 4;
828 }
829
830 /* initialize Link Control register */
831 static int xen_pt_linkctrl_reg_init(XenPCIPassthroughState *s,
832 XenPTRegInfo *reg, uint32_t real_offset,
833 uint32_t *data)
834 {
835 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
836 uint8_t dev_type = get_device_type(s, real_offset - reg->offset);
837
838 /* no need to initialize in case of Root Complex Integrated Endpoint
839 * with cap_ver 1.x
840 */
841 if ((dev_type == PCI_EXP_TYPE_RC_END) && (cap_ver == 1)) {
842 *data = XEN_PT_INVALID_REG;
843 }
844
845 *data = reg->init_val;
846 return 0;
847 }
848 /* initialize Device Control 2 register */
849 static int xen_pt_devctrl2_reg_init(XenPCIPassthroughState *s,
850 XenPTRegInfo *reg, uint32_t real_offset,
851 uint32_t *data)
852 {
853 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
854
855 /* no need to initialize in case of cap_ver 1.x */
856 if (cap_ver == 1) {
857 *data = XEN_PT_INVALID_REG;
858 }
859
860 *data = reg->init_val;
861 return 0;
862 }
863 /* initialize Link Control 2 register */
864 static int xen_pt_linkctrl2_reg_init(XenPCIPassthroughState *s,
865 XenPTRegInfo *reg, uint32_t real_offset,
866 uint32_t *data)
867 {
868 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
869 uint32_t reg_field = 0;
870
871 /* no need to initialize in case of cap_ver 1.x */
872 if (cap_ver == 1) {
873 reg_field = XEN_PT_INVALID_REG;
874 } else {
875 /* set Supported Link Speed */
876 uint8_t lnkcap = pci_get_byte(s->dev.config + real_offset - reg->offset
877 + PCI_EXP_LNKCAP);
878 reg_field |= PCI_EXP_LNKCAP_SLS & lnkcap;
879 }
880
881 *data = reg_field;
882 return 0;
883 }
884
885 /* PCI Express Capability Structure reg static information table */
886 static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
887 /* Next Pointer reg */
888 {
889 .offset = PCI_CAP_LIST_NEXT,
890 .size = 1,
891 .init_val = 0x00,
892 .ro_mask = 0xFF,
893 .emu_mask = 0xFF,
894 .init = xen_pt_ptr_reg_init,
895 .u.b.read = xen_pt_byte_reg_read,
896 .u.b.write = xen_pt_byte_reg_write,
897 },
898 /* Device Capabilities reg */
899 {
900 .offset = PCI_EXP_DEVCAP,
901 .size = 4,
902 .init_val = 0x00000000,
903 .ro_mask = 0xFFFFFFFF,
904 .emu_mask = 0x10000000,
905 .init = xen_pt_common_reg_init,
906 .u.dw.read = xen_pt_long_reg_read,
907 .u.dw.write = xen_pt_long_reg_write,
908 },
909 /* Device Control reg */
910 {
911 .offset = PCI_EXP_DEVCTL,
912 .size = 2,
913 .init_val = 0x2810,
914 .ro_mask = 0x8400,
915 .emu_mask = 0xFFFF,
916 .init = xen_pt_common_reg_init,
917 .u.w.read = xen_pt_word_reg_read,
918 .u.w.write = xen_pt_word_reg_write,
919 },
920 /* Device Status reg */
921 {
922 .offset = PCI_EXP_DEVSTA,
923 .size = 2,
924 .res_mask = 0xFFC0,
925 .ro_mask = 0x0030,
926 .init = xen_pt_common_reg_init,
927 .u.w.read = xen_pt_word_reg_read,
928 .u.w.write = xen_pt_word_reg_write,
929 },
930 /* Link Control reg */
931 {
932 .offset = PCI_EXP_LNKCTL,
933 .size = 2,
934 .init_val = 0x0000,
935 .ro_mask = 0xFC34,
936 .emu_mask = 0xFFFF,
937 .init = xen_pt_linkctrl_reg_init,
938 .u.w.read = xen_pt_word_reg_read,
939 .u.w.write = xen_pt_word_reg_write,
940 },
941 /* Link Status reg */
942 {
943 .offset = PCI_EXP_LNKSTA,
944 .size = 2,
945 .ro_mask = 0x3FFF,
946 .init = xen_pt_common_reg_init,
947 .u.w.read = xen_pt_word_reg_read,
948 .u.w.write = xen_pt_word_reg_write,
949 },
950 /* Device Control 2 reg */
951 {
952 .offset = 0x28,
953 .size = 2,
954 .init_val = 0x0000,
955 .ro_mask = 0xFFE0,
956 .emu_mask = 0xFFFF,
957 .init = xen_pt_devctrl2_reg_init,
958 .u.w.read = xen_pt_word_reg_read,
959 .u.w.write = xen_pt_word_reg_write,
960 },
961 /* Link Control 2 reg */
962 {
963 .offset = 0x30,
964 .size = 2,
965 .init_val = 0x0000,
966 .ro_mask = 0xE040,
967 .emu_mask = 0xFFFF,
968 .init = xen_pt_linkctrl2_reg_init,
969 .u.w.read = xen_pt_word_reg_read,
970 .u.w.write = xen_pt_word_reg_write,
971 },
972 {
973 .size = 0,
974 },
975 };
976
977
978 /*********************************
979 * Power Management Capability
980 */
981
982 /* write Power Management Control/Status register */
983 static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s,
984 XenPTReg *cfg_entry, uint16_t *val,
985 uint16_t dev_value, uint16_t valid_mask)
986 {
987 XenPTRegInfo *reg = cfg_entry->reg;
988 uint16_t writable_mask = 0;
989 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
990
991 /* modify emulate register */
992 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
993 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
994
995 /* create value for writing to I/O device register */
996 *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~PCI_PM_CTRL_PME_STATUS,
997 throughable_mask);
998
999 return 0;
1000 }
1001
1002 /* Power Management Capability reg static information table */
1003 static XenPTRegInfo xen_pt_emu_reg_pm[] = {
1004 /* Next Pointer reg */
1005 {
1006 .offset = PCI_CAP_LIST_NEXT,
1007 .size = 1,
1008 .init_val = 0x00,
1009 .ro_mask = 0xFF,
1010 .emu_mask = 0xFF,
1011 .init = xen_pt_ptr_reg_init,
1012 .u.b.read = xen_pt_byte_reg_read,
1013 .u.b.write = xen_pt_byte_reg_write,
1014 },
1015 /* Power Management Capabilities reg */
1016 {
1017 .offset = PCI_CAP_FLAGS,
1018 .size = 2,
1019 .init_val = 0x0000,
1020 .ro_mask = 0xFFFF,
1021 .emu_mask = 0xF9C8,
1022 .init = xen_pt_common_reg_init,
1023 .u.w.read = xen_pt_word_reg_read,
1024 .u.w.write = xen_pt_word_reg_write,
1025 },
1026 /* PCI Power Management Control/Status reg */
1027 {
1028 .offset = PCI_PM_CTRL,
1029 .size = 2,
1030 .init_val = 0x0008,
1031 .res_mask = 0x00F0,
1032 .ro_mask = 0xE10C,
1033 .emu_mask = 0x810B,
1034 .init = xen_pt_common_reg_init,
1035 .u.w.read = xen_pt_word_reg_read,
1036 .u.w.write = xen_pt_pmcsr_reg_write,
1037 },
1038 {
1039 .size = 0,
1040 },
1041 };
1042
1043
1044 /********************************
1045 * MSI Capability
1046 */
1047
1048 /* Helper */
1049 #define xen_pt_msi_check_type(offset, flags, what) \
1050 ((offset) == ((flags) & PCI_MSI_FLAGS_64BIT ? \
1051 PCI_MSI_##what##_64 : PCI_MSI_##what##_32))
1052
1053 /* Message Control register */
1054 static int xen_pt_msgctrl_reg_init(XenPCIPassthroughState *s,
1055 XenPTRegInfo *reg, uint32_t real_offset,
1056 uint32_t *data)
1057 {
1058 PCIDevice *d = &s->dev;
1059 XenPTMSI *msi = s->msi;
1060 uint16_t reg_field = 0;
1061
1062 /* use I/O device register's value as initial value */
1063 reg_field = pci_get_word(d->config + real_offset);
1064
1065 if (reg_field & PCI_MSI_FLAGS_ENABLE) {
1066 XEN_PT_LOG(&s->dev, "MSI already enabled, disabling it first\n");
1067 xen_host_pci_set_word(&s->real_device, real_offset,
1068 reg_field & ~PCI_MSI_FLAGS_ENABLE);
1069 }
1070 msi->flags |= reg_field;
1071 msi->ctrl_offset = real_offset;
1072 msi->initialized = false;
1073 msi->mapped = false;
1074
1075 *data = reg->init_val;
1076 return 0;
1077 }
1078 static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState *s,
1079 XenPTReg *cfg_entry, uint16_t *val,
1080 uint16_t dev_value, uint16_t valid_mask)
1081 {
1082 XenPTRegInfo *reg = cfg_entry->reg;
1083 XenPTMSI *msi = s->msi;
1084 uint16_t writable_mask = 0;
1085 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
1086
1087 /* Currently no support for multi-vector */
1088 if (*val & PCI_MSI_FLAGS_QSIZE) {
1089 XEN_PT_WARN(&s->dev, "Tries to set more than 1 vector ctrl %x\n", *val);
1090 }
1091
1092 /* modify emulate register */
1093 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1094 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1095 msi->flags |= cfg_entry->data & ~PCI_MSI_FLAGS_ENABLE;
1096
1097 /* create value for writing to I/O device register */
1098 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1099
1100 /* update MSI */
1101 if (*val & PCI_MSI_FLAGS_ENABLE) {
1102 /* setup MSI pirq for the first time */
1103 if (!msi->initialized) {
1104 /* Init physical one */
1105 XEN_PT_LOG(&s->dev, "setup MSI (register: %x).\n", *val);
1106 if (xen_pt_msi_setup(s)) {
1107 /* We do not broadcast the error to the framework code, so
1108 * that MSI errors are contained in MSI emulation code and
1109 * QEMU can go on running.
1110 * Guest MSI would be actually not working.
1111 */
1112 *val &= ~PCI_MSI_FLAGS_ENABLE;
1113 XEN_PT_WARN(&s->dev, "Can not map MSI (register: %x)!\n", *val);
1114 return 0;
1115 }
1116 if (xen_pt_msi_update(s)) {
1117 *val &= ~PCI_MSI_FLAGS_ENABLE;
1118 XEN_PT_WARN(&s->dev, "Can not bind MSI (register: %x)!\n", *val);
1119 return 0;
1120 }
1121 msi->initialized = true;
1122 msi->mapped = true;
1123 }
1124 msi->flags |= PCI_MSI_FLAGS_ENABLE;
1125 } else if (msi->mapped) {
1126 xen_pt_msi_disable(s);
1127 }
1128
1129 return 0;
1130 }
1131
1132 /* initialize Message Upper Address register */
1133 static int xen_pt_msgaddr64_reg_init(XenPCIPassthroughState *s,
1134 XenPTRegInfo *reg, uint32_t real_offset,
1135 uint32_t *data)
1136 {
1137 /* no need to initialize in case of 32 bit type */
1138 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1139 *data = XEN_PT_INVALID_REG;
1140 } else {
1141 *data = reg->init_val;
1142 }
1143
1144 return 0;
1145 }
1146 /* this function will be called twice (for 32 bit and 64 bit type) */
1147 /* initialize Message Data register */
1148 static int xen_pt_msgdata_reg_init(XenPCIPassthroughState *s,
1149 XenPTRegInfo *reg, uint32_t real_offset,
1150 uint32_t *data)
1151 {
1152 uint32_t flags = s->msi->flags;
1153 uint32_t offset = reg->offset;
1154
1155 /* check the offset whether matches the type or not */
1156 if (xen_pt_msi_check_type(offset, flags, DATA)) {
1157 *data = reg->init_val;
1158 } else {
1159 *data = XEN_PT_INVALID_REG;
1160 }
1161 return 0;
1162 }
1163
1164 /* this function will be called twice (for 32 bit and 64 bit type) */
1165 /* initialize Mask register */
1166 static int xen_pt_mask_reg_init(XenPCIPassthroughState *s,
1167 XenPTRegInfo *reg, uint32_t real_offset,
1168 uint32_t *data)
1169 {
1170 uint32_t flags = s->msi->flags;
1171
1172 /* check the offset whether matches the type or not */
1173 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
1174 *data = XEN_PT_INVALID_REG;
1175 } else if (xen_pt_msi_check_type(reg->offset, flags, MASK)) {
1176 *data = reg->init_val;
1177 } else {
1178 *data = XEN_PT_INVALID_REG;
1179 }
1180 return 0;
1181 }
1182
1183 /* this function will be called twice (for 32 bit and 64 bit type) */
1184 /* initialize Pending register */
1185 static int xen_pt_pending_reg_init(XenPCIPassthroughState *s,
1186 XenPTRegInfo *reg, uint32_t real_offset,
1187 uint32_t *data)
1188 {
1189 uint32_t flags = s->msi->flags;
1190
1191 /* check the offset whether matches the type or not */
1192 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
1193 *data = XEN_PT_INVALID_REG;
1194 } else if (xen_pt_msi_check_type(reg->offset, flags, PENDING)) {
1195 *data = reg->init_val;
1196 } else {
1197 *data = XEN_PT_INVALID_REG;
1198 }
1199 return 0;
1200 }
1201
1202 /* write Message Address register */
1203 static int xen_pt_msgaddr32_reg_write(XenPCIPassthroughState *s,
1204 XenPTReg *cfg_entry, uint32_t *val,
1205 uint32_t dev_value, uint32_t valid_mask)
1206 {
1207 XenPTRegInfo *reg = cfg_entry->reg;
1208 uint32_t writable_mask = 0;
1209 uint32_t old_addr = cfg_entry->data;
1210
1211 /* modify emulate register */
1212 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1213 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1214 s->msi->addr_lo = cfg_entry->data;
1215
1216 /* create value for writing to I/O device register */
1217 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
1218
1219 /* update MSI */
1220 if (cfg_entry->data != old_addr) {
1221 if (s->msi->mapped) {
1222 xen_pt_msi_update(s);
1223 }
1224 }
1225
1226 return 0;
1227 }
1228 /* write Message Upper Address register */
1229 static int xen_pt_msgaddr64_reg_write(XenPCIPassthroughState *s,
1230 XenPTReg *cfg_entry, uint32_t *val,
1231 uint32_t dev_value, uint32_t valid_mask)
1232 {
1233 XenPTRegInfo *reg = cfg_entry->reg;
1234 uint32_t writable_mask = 0;
1235 uint32_t old_addr = cfg_entry->data;
1236
1237 /* check whether the type is 64 bit or not */
1238 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1239 XEN_PT_ERR(&s->dev,
1240 "Can't write to the upper address without 64 bit support\n");
1241 return -1;
1242 }
1243
1244 /* modify emulate register */
1245 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1246 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1247 /* update the msi_info too */
1248 s->msi->addr_hi = cfg_entry->data;
1249
1250 /* create value for writing to I/O device register */
1251 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
1252
1253 /* update MSI */
1254 if (cfg_entry->data != old_addr) {
1255 if (s->msi->mapped) {
1256 xen_pt_msi_update(s);
1257 }
1258 }
1259
1260 return 0;
1261 }
1262
1263
1264 /* this function will be called twice (for 32 bit and 64 bit type) */
1265 /* write Message Data register */
1266 static int xen_pt_msgdata_reg_write(XenPCIPassthroughState *s,
1267 XenPTReg *cfg_entry, uint16_t *val,
1268 uint16_t dev_value, uint16_t valid_mask)
1269 {
1270 XenPTRegInfo *reg = cfg_entry->reg;
1271 XenPTMSI *msi = s->msi;
1272 uint16_t writable_mask = 0;
1273 uint16_t old_data = cfg_entry->data;
1274 uint32_t offset = reg->offset;
1275
1276 /* check the offset whether matches the type or not */
1277 if (!xen_pt_msi_check_type(offset, msi->flags, DATA)) {
1278 /* exit I/O emulator */
1279 XEN_PT_ERR(&s->dev, "the offset does not match the 32/64 bit type!\n");
1280 return -1;
1281 }
1282
1283 /* modify emulate register */
1284 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1285 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1286 /* update the msi_info too */
1287 msi->data = cfg_entry->data;
1288
1289 /* create value for writing to I/O device register */
1290 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
1291
1292 /* update MSI */
1293 if (cfg_entry->data != old_data) {
1294 if (msi->mapped) {
1295 xen_pt_msi_update(s);
1296 }
1297 }
1298
1299 return 0;
1300 }
1301
1302 /* MSI Capability Structure reg static information table */
1303 static XenPTRegInfo xen_pt_emu_reg_msi[] = {
1304 /* Next Pointer reg */
1305 {
1306 .offset = PCI_CAP_LIST_NEXT,
1307 .size = 1,
1308 .init_val = 0x00,
1309 .ro_mask = 0xFF,
1310 .emu_mask = 0xFF,
1311 .init = xen_pt_ptr_reg_init,
1312 .u.b.read = xen_pt_byte_reg_read,
1313 .u.b.write = xen_pt_byte_reg_write,
1314 },
1315 /* Message Control reg */
1316 {
1317 .offset = PCI_MSI_FLAGS,
1318 .size = 2,
1319 .init_val = 0x0000,
1320 .res_mask = 0xFE00,
1321 .ro_mask = 0x018E,
1322 .emu_mask = 0x017E,
1323 .init = xen_pt_msgctrl_reg_init,
1324 .u.w.read = xen_pt_word_reg_read,
1325 .u.w.write = xen_pt_msgctrl_reg_write,
1326 },
1327 /* Message Address reg */
1328 {
1329 .offset = PCI_MSI_ADDRESS_LO,
1330 .size = 4,
1331 .init_val = 0x00000000,
1332 .ro_mask = 0x00000003,
1333 .emu_mask = 0xFFFFFFFF,
1334 .init = xen_pt_common_reg_init,
1335 .u.dw.read = xen_pt_long_reg_read,
1336 .u.dw.write = xen_pt_msgaddr32_reg_write,
1337 },
1338 /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */
1339 {
1340 .offset = PCI_MSI_ADDRESS_HI,
1341 .size = 4,
1342 .init_val = 0x00000000,
1343 .ro_mask = 0x00000000,
1344 .emu_mask = 0xFFFFFFFF,
1345 .init = xen_pt_msgaddr64_reg_init,
1346 .u.dw.read = xen_pt_long_reg_read,
1347 .u.dw.write = xen_pt_msgaddr64_reg_write,
1348 },
1349 /* Message Data reg (16 bits of data for 32-bit devices) */
1350 {
1351 .offset = PCI_MSI_DATA_32,
1352 .size = 2,
1353 .init_val = 0x0000,
1354 .ro_mask = 0x0000,
1355 .emu_mask = 0xFFFF,
1356 .init = xen_pt_msgdata_reg_init,
1357 .u.w.read = xen_pt_word_reg_read,
1358 .u.w.write = xen_pt_msgdata_reg_write,
1359 },
1360 /* Message Data reg (16 bits of data for 64-bit devices) */
1361 {
1362 .offset = PCI_MSI_DATA_64,
1363 .size = 2,
1364 .init_val = 0x0000,
1365 .ro_mask = 0x0000,
1366 .emu_mask = 0xFFFF,
1367 .init = xen_pt_msgdata_reg_init,
1368 .u.w.read = xen_pt_word_reg_read,
1369 .u.w.write = xen_pt_msgdata_reg_write,
1370 },
1371 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1372 {
1373 .offset = PCI_MSI_MASK_32,
1374 .size = 4,
1375 .init_val = 0x00000000,
1376 .ro_mask = 0xFFFFFFFF,
1377 .emu_mask = 0xFFFFFFFF,
1378 .init = xen_pt_mask_reg_init,
1379 .u.dw.read = xen_pt_long_reg_read,
1380 .u.dw.write = xen_pt_long_reg_write,
1381 },
1382 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1383 {
1384 .offset = PCI_MSI_MASK_64,
1385 .size = 4,
1386 .init_val = 0x00000000,
1387 .ro_mask = 0xFFFFFFFF,
1388 .emu_mask = 0xFFFFFFFF,
1389 .init = xen_pt_mask_reg_init,
1390 .u.dw.read = xen_pt_long_reg_read,
1391 .u.dw.write = xen_pt_long_reg_write,
1392 },
1393 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1394 {
1395 .offset = PCI_MSI_MASK_32 + 4,
1396 .size = 4,
1397 .init_val = 0x00000000,
1398 .ro_mask = 0xFFFFFFFF,
1399 .emu_mask = 0x00000000,
1400 .init = xen_pt_pending_reg_init,
1401 .u.dw.read = xen_pt_long_reg_read,
1402 .u.dw.write = xen_pt_long_reg_write,
1403 },
1404 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1405 {
1406 .offset = PCI_MSI_MASK_64 + 4,
1407 .size = 4,
1408 .init_val = 0x00000000,
1409 .ro_mask = 0xFFFFFFFF,
1410 .emu_mask = 0x00000000,
1411 .init = xen_pt_pending_reg_init,
1412 .u.dw.read = xen_pt_long_reg_read,
1413 .u.dw.write = xen_pt_long_reg_write,
1414 },
1415 {
1416 .size = 0,
1417 },
1418 };
1419
1420
1421 /**************************************
1422 * MSI-X Capability
1423 */
1424
1425 /* Message Control register for MSI-X */
1426 static int xen_pt_msixctrl_reg_init(XenPCIPassthroughState *s,
1427 XenPTRegInfo *reg, uint32_t real_offset,
1428 uint32_t *data)
1429 {
1430 PCIDevice *d = &s->dev;
1431 uint16_t reg_field = 0;
1432
1433 /* use I/O device register's value as initial value */
1434 reg_field = pci_get_word(d->config + real_offset);
1435
1436 if (reg_field & PCI_MSIX_FLAGS_ENABLE) {
1437 XEN_PT_LOG(d, "MSIX already enabled, disabling it first\n");
1438 xen_host_pci_set_word(&s->real_device, real_offset,
1439 reg_field & ~PCI_MSIX_FLAGS_ENABLE);
1440 }
1441
1442 s->msix->ctrl_offset = real_offset;
1443
1444 *data = reg->init_val;
1445 return 0;
1446 }
1447 static int xen_pt_msixctrl_reg_write(XenPCIPassthroughState *s,
1448 XenPTReg *cfg_entry, uint16_t *val,
1449 uint16_t dev_value, uint16_t valid_mask)
1450 {
1451 XenPTRegInfo *reg = cfg_entry->reg;
1452 uint16_t writable_mask = 0;
1453 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
1454 int debug_msix_enabled_old;
1455
1456 /* modify emulate register */
1457 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1458 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1459
1460 /* create value for writing to I/O device register */
1461 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1462
1463 /* update MSI-X */
1464 if ((*val & PCI_MSIX_FLAGS_ENABLE)
1465 && !(*val & PCI_MSIX_FLAGS_MASKALL)) {
1466 xen_pt_msix_update(s);
1467 } else if (!(*val & PCI_MSIX_FLAGS_ENABLE) && s->msix->enabled) {
1468 xen_pt_msix_disable(s);
1469 }
1470
1471 debug_msix_enabled_old = s->msix->enabled;
1472 s->msix->enabled = !!(*val & PCI_MSIX_FLAGS_ENABLE);
1473 if (s->msix->enabled != debug_msix_enabled_old) {
1474 XEN_PT_LOG(&s->dev, "%s MSI-X\n",
1475 s->msix->enabled ? "enable" : "disable");
1476 }
1477
1478 return 0;
1479 }
1480
1481 /* MSI-X Capability Structure reg static information table */
1482 static XenPTRegInfo xen_pt_emu_reg_msix[] = {
1483 /* Next Pointer reg */
1484 {
1485 .offset = PCI_CAP_LIST_NEXT,
1486 .size = 1,
1487 .init_val = 0x00,
1488 .ro_mask = 0xFF,
1489 .emu_mask = 0xFF,
1490 .init = xen_pt_ptr_reg_init,
1491 .u.b.read = xen_pt_byte_reg_read,
1492 .u.b.write = xen_pt_byte_reg_write,
1493 },
1494 /* Message Control reg */
1495 {
1496 .offset = PCI_MSI_FLAGS,
1497 .size = 2,
1498 .init_val = 0x0000,
1499 .res_mask = 0x3800,
1500 .ro_mask = 0x07FF,
1501 .emu_mask = 0x0000,
1502 .init = xen_pt_msixctrl_reg_init,
1503 .u.w.read = xen_pt_word_reg_read,
1504 .u.w.write = xen_pt_msixctrl_reg_write,
1505 },
1506 {
1507 .size = 0,
1508 },
1509 };
1510
1511 static XenPTRegInfo xen_pt_emu_reg_igd_opregion[] = {
1512 /* Intel IGFX OpRegion reg */
1513 {
1514 .offset = 0x0,
1515 .size = 4,
1516 .init_val = 0,
1517 .u.dw.read = xen_pt_intel_opregion_read,
1518 .u.dw.write = xen_pt_intel_opregion_write,
1519 },
1520 {
1521 .size = 0,
1522 },
1523 };
1524
1525 /****************************
1526 * Capabilities
1527 */
1528
1529 /* capability structure register group size functions */
1530
1531 static int xen_pt_reg_grp_size_init(XenPCIPassthroughState *s,
1532 const XenPTRegGroupInfo *grp_reg,
1533 uint32_t base_offset, uint8_t *size)
1534 {
1535 *size = grp_reg->grp_size;
1536 return 0;
1537 }
1538 /* get Vendor Specific Capability Structure register group size */
1539 static int xen_pt_vendor_size_init(XenPCIPassthroughState *s,
1540 const XenPTRegGroupInfo *grp_reg,
1541 uint32_t base_offset, uint8_t *size)
1542 {
1543 *size = pci_get_byte(s->dev.config + base_offset + 0x02);
1544 return 0;
1545 }
1546 /* get PCI Express Capability Structure register group size */
1547 static int xen_pt_pcie_size_init(XenPCIPassthroughState *s,
1548 const XenPTRegGroupInfo *grp_reg,
1549 uint32_t base_offset, uint8_t *size)
1550 {
1551 PCIDevice *d = &s->dev;
1552 uint8_t version = get_capability_version(s, base_offset);
1553 uint8_t type = get_device_type(s, base_offset);
1554 uint8_t pcie_size = 0;
1555
1556
1557 /* calculate size depend on capability version and device/port type */
1558 /* in case of PCI Express Base Specification Rev 1.x */
1559 if (version == 1) {
1560 /* The PCI Express Capabilities, Device Capabilities, and Device
1561 * Status/Control registers are required for all PCI Express devices.
1562 * The Link Capabilities and Link Status/Control are required for all
1563 * Endpoints that are not Root Complex Integrated Endpoints. Endpoints
1564 * are not required to implement registers other than those listed
1565 * above and terminate the capability structure.
1566 */
1567 switch (type) {
1568 case PCI_EXP_TYPE_ENDPOINT:
1569 case PCI_EXP_TYPE_LEG_END:
1570 pcie_size = 0x14;
1571 break;
1572 case PCI_EXP_TYPE_RC_END:
1573 /* has no link */
1574 pcie_size = 0x0C;
1575 break;
1576 /* only EndPoint passthrough is supported */
1577 case PCI_EXP_TYPE_ROOT_PORT:
1578 case PCI_EXP_TYPE_UPSTREAM:
1579 case PCI_EXP_TYPE_DOWNSTREAM:
1580 case PCI_EXP_TYPE_PCI_BRIDGE:
1581 case PCI_EXP_TYPE_PCIE_BRIDGE:
1582 case PCI_EXP_TYPE_RC_EC:
1583 default:
1584 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1585 return -1;
1586 }
1587 }
1588 /* in case of PCI Express Base Specification Rev 2.0 */
1589 else if (version == 2) {
1590 switch (type) {
1591 case PCI_EXP_TYPE_ENDPOINT:
1592 case PCI_EXP_TYPE_LEG_END:
1593 case PCI_EXP_TYPE_RC_END:
1594 /* For Functions that do not implement the registers,
1595 * these spaces must be hardwired to 0b.
1596 */
1597 pcie_size = 0x3C;
1598 break;
1599 /* only EndPoint passthrough is supported */
1600 case PCI_EXP_TYPE_ROOT_PORT:
1601 case PCI_EXP_TYPE_UPSTREAM:
1602 case PCI_EXP_TYPE_DOWNSTREAM:
1603 case PCI_EXP_TYPE_PCI_BRIDGE:
1604 case PCI_EXP_TYPE_PCIE_BRIDGE:
1605 case PCI_EXP_TYPE_RC_EC:
1606 default:
1607 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1608 return -1;
1609 }
1610 } else {
1611 XEN_PT_ERR(d, "Unsupported capability version %#x.\n", version);
1612 return -1;
1613 }
1614
1615 *size = pcie_size;
1616 return 0;
1617 }
1618 /* get MSI Capability Structure register group size */
1619 static int xen_pt_msi_size_init(XenPCIPassthroughState *s,
1620 const XenPTRegGroupInfo *grp_reg,
1621 uint32_t base_offset, uint8_t *size)
1622 {
1623 PCIDevice *d = &s->dev;
1624 uint16_t msg_ctrl = 0;
1625 uint8_t msi_size = 0xa;
1626
1627 msg_ctrl = pci_get_word(d->config + (base_offset + PCI_MSI_FLAGS));
1628
1629 /* check if 64-bit address is capable of per-vector masking */
1630 if (msg_ctrl & PCI_MSI_FLAGS_64BIT) {
1631 msi_size += 4;
1632 }
1633 if (msg_ctrl & PCI_MSI_FLAGS_MASKBIT) {
1634 msi_size += 10;
1635 }
1636
1637 s->msi = g_new0(XenPTMSI, 1);
1638 s->msi->pirq = XEN_PT_UNASSIGNED_PIRQ;
1639
1640 *size = msi_size;
1641 return 0;
1642 }
1643 /* get MSI-X Capability Structure register group size */
1644 static int xen_pt_msix_size_init(XenPCIPassthroughState *s,
1645 const XenPTRegGroupInfo *grp_reg,
1646 uint32_t base_offset, uint8_t *size)
1647 {
1648 int rc = 0;
1649
1650 rc = xen_pt_msix_init(s, base_offset);
1651
1652 if (rc < 0) {
1653 XEN_PT_ERR(&s->dev, "Internal error: Invalid xen_pt_msix_init.\n");
1654 return rc;
1655 }
1656
1657 *size = grp_reg->grp_size;
1658 return 0;
1659 }
1660
1661
1662 static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = {
1663 /* Header Type0 reg group */
1664 {
1665 .grp_id = 0xFF,
1666 .grp_type = XEN_PT_GRP_TYPE_EMU,
1667 .grp_size = 0x40,
1668 .size_init = xen_pt_reg_grp_size_init,
1669 .emu_regs = xen_pt_emu_reg_header0,
1670 },
1671 /* PCI PowerManagement Capability reg group */
1672 {
1673 .grp_id = PCI_CAP_ID_PM,
1674 .grp_type = XEN_PT_GRP_TYPE_EMU,
1675 .grp_size = PCI_PM_SIZEOF,
1676 .size_init = xen_pt_reg_grp_size_init,
1677 .emu_regs = xen_pt_emu_reg_pm,
1678 },
1679 /* AGP Capability Structure reg group */
1680 {
1681 .grp_id = PCI_CAP_ID_AGP,
1682 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1683 .grp_size = 0x30,
1684 .size_init = xen_pt_reg_grp_size_init,
1685 },
1686 /* Vital Product Data Capability Structure reg group */
1687 {
1688 .grp_id = PCI_CAP_ID_VPD,
1689 .grp_type = XEN_PT_GRP_TYPE_EMU,
1690 .grp_size = 0x08,
1691 .size_init = xen_pt_reg_grp_size_init,
1692 .emu_regs = xen_pt_emu_reg_vpd,
1693 },
1694 /* Slot Identification reg group */
1695 {
1696 .grp_id = PCI_CAP_ID_SLOTID,
1697 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1698 .grp_size = 0x04,
1699 .size_init = xen_pt_reg_grp_size_init,
1700 },
1701 /* MSI Capability Structure reg group */
1702 {
1703 .grp_id = PCI_CAP_ID_MSI,
1704 .grp_type = XEN_PT_GRP_TYPE_EMU,
1705 .grp_size = 0xFF,
1706 .size_init = xen_pt_msi_size_init,
1707 .emu_regs = xen_pt_emu_reg_msi,
1708 },
1709 /* PCI-X Capabilities List Item reg group */
1710 {
1711 .grp_id = PCI_CAP_ID_PCIX,
1712 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1713 .grp_size = 0x18,
1714 .size_init = xen_pt_reg_grp_size_init,
1715 },
1716 /* Vendor Specific Capability Structure reg group */
1717 {
1718 .grp_id = PCI_CAP_ID_VNDR,
1719 .grp_type = XEN_PT_GRP_TYPE_EMU,
1720 .grp_size = 0xFF,
1721 .size_init = xen_pt_vendor_size_init,
1722 .emu_regs = xen_pt_emu_reg_vendor,
1723 },
1724 /* SHPC Capability List Item reg group */
1725 {
1726 .grp_id = PCI_CAP_ID_SHPC,
1727 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1728 .grp_size = 0x08,
1729 .size_init = xen_pt_reg_grp_size_init,
1730 },
1731 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
1732 {
1733 .grp_id = PCI_CAP_ID_SSVID,
1734 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1735 .grp_size = 0x08,
1736 .size_init = xen_pt_reg_grp_size_init,
1737 },
1738 /* AGP 8x Capability Structure reg group */
1739 {
1740 .grp_id = PCI_CAP_ID_AGP3,
1741 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1742 .grp_size = 0x30,
1743 .size_init = xen_pt_reg_grp_size_init,
1744 },
1745 /* PCI Express Capability Structure reg group */
1746 {
1747 .grp_id = PCI_CAP_ID_EXP,
1748 .grp_type = XEN_PT_GRP_TYPE_EMU,
1749 .grp_size = 0xFF,
1750 .size_init = xen_pt_pcie_size_init,
1751 .emu_regs = xen_pt_emu_reg_pcie,
1752 },
1753 /* MSI-X Capability Structure reg group */
1754 {
1755 .grp_id = PCI_CAP_ID_MSIX,
1756 .grp_type = XEN_PT_GRP_TYPE_EMU,
1757 .grp_size = 0x0C,
1758 .size_init = xen_pt_msix_size_init,
1759 .emu_regs = xen_pt_emu_reg_msix,
1760 },
1761 /* Intel IGD Opregion group */
1762 {
1763 .grp_id = XEN_PCI_INTEL_OPREGION,
1764 .grp_type = XEN_PT_GRP_TYPE_EMU,
1765 .grp_size = 0x4,
1766 .size_init = xen_pt_reg_grp_size_init,
1767 .emu_regs = xen_pt_emu_reg_igd_opregion,
1768 },
1769 {
1770 .grp_size = 0,
1771 },
1772 };
1773
1774 /* initialize Capabilities Pointer or Next Pointer register */
1775 static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s,
1776 XenPTRegInfo *reg, uint32_t real_offset,
1777 uint32_t *data)
1778 {
1779 int i;
1780 uint8_t *config = s->dev.config;
1781 uint32_t reg_field = pci_get_byte(config + real_offset);
1782 uint8_t cap_id = 0;
1783
1784 /* find capability offset */
1785 while (reg_field) {
1786 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
1787 if (xen_pt_hide_dev_cap(&s->real_device,
1788 xen_pt_emu_reg_grps[i].grp_id)) {
1789 continue;
1790 }
1791
1792 cap_id = pci_get_byte(config + reg_field + PCI_CAP_LIST_ID);
1793 if (xen_pt_emu_reg_grps[i].grp_id == cap_id) {
1794 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
1795 goto out;
1796 }
1797 /* ignore the 0 hardwired capability, find next one */
1798 break;
1799 }
1800 }
1801
1802 /* next capability */
1803 reg_field = pci_get_byte(config + reg_field + PCI_CAP_LIST_NEXT);
1804 }
1805
1806 out:
1807 *data = reg_field;
1808 return 0;
1809 }
1810
1811
1812 /*************
1813 * Main
1814 */
1815
1816 static uint8_t find_cap_offset(XenPCIPassthroughState *s, uint8_t cap)
1817 {
1818 uint8_t id;
1819 unsigned max_cap = XEN_PCI_CAP_MAX;
1820 uint8_t pos = PCI_CAPABILITY_LIST;
1821 uint8_t status = 0;
1822
1823 if (xen_host_pci_get_byte(&s->real_device, PCI_STATUS, &status)) {
1824 return 0;
1825 }
1826 if ((status & PCI_STATUS_CAP_LIST) == 0) {
1827 return 0;
1828 }
1829
1830 while (max_cap--) {
1831 if (xen_host_pci_get_byte(&s->real_device, pos, &pos)) {
1832 break;
1833 }
1834 if (pos < PCI_CONFIG_HEADER_SIZE) {
1835 break;
1836 }
1837
1838 pos &= ~3;
1839 if (xen_host_pci_get_byte(&s->real_device,
1840 pos + PCI_CAP_LIST_ID, &id)) {
1841 break;
1842 }
1843
1844 if (id == 0xff) {
1845 break;
1846 }
1847 if (id == cap) {
1848 return pos;
1849 }
1850
1851 pos += PCI_CAP_LIST_NEXT;
1852 }
1853 return 0;
1854 }
1855
1856 static int xen_pt_config_reg_init(XenPCIPassthroughState *s,
1857 XenPTRegGroup *reg_grp, XenPTRegInfo *reg)
1858 {
1859 XenPTReg *reg_entry;
1860 uint32_t data = 0;
1861 int rc = 0;
1862
1863 reg_entry = g_new0(XenPTReg, 1);
1864 reg_entry->reg = reg;
1865
1866 if (reg->init) {
1867 /* initialize emulate register */
1868 rc = reg->init(s, reg_entry->reg,
1869 reg_grp->base_offset + reg->offset, &data);
1870 if (rc < 0) {
1871 g_free(reg_entry);
1872 return rc;
1873 }
1874 if (data == XEN_PT_INVALID_REG) {
1875 /* free unused BAR register entry */
1876 g_free(reg_entry);
1877 return 0;
1878 }
1879 /* set register value */
1880 reg_entry->data = data;
1881 }
1882 /* list add register entry */
1883 QLIST_INSERT_HEAD(&reg_grp->reg_tbl_list, reg_entry, entries);
1884
1885 return 0;
1886 }
1887
1888 int xen_pt_config_init(XenPCIPassthroughState *s)
1889 {
1890 int i, rc;
1891
1892 QLIST_INIT(&s->reg_grps);
1893
1894 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
1895 uint32_t reg_grp_offset = 0;
1896 XenPTRegGroup *reg_grp_entry = NULL;
1897
1898 if (xen_pt_emu_reg_grps[i].grp_id != 0xFF
1899 && xen_pt_emu_reg_grps[i].grp_id != XEN_PCI_INTEL_OPREGION) {
1900 if (xen_pt_hide_dev_cap(&s->real_device,
1901 xen_pt_emu_reg_grps[i].grp_id)) {
1902 continue;
1903 }
1904
1905 reg_grp_offset = find_cap_offset(s, xen_pt_emu_reg_grps[i].grp_id);
1906
1907 if (!reg_grp_offset) {
1908 continue;
1909 }
1910 }
1911
1912 /*
1913 * By default we will trap up to 0x40 in the cfg space.
1914 * If an intel device is pass through we need to trap 0xfc,
1915 * therefore the size should be 0xff.
1916 */
1917 if (xen_pt_emu_reg_grps[i].grp_id == XEN_PCI_INTEL_OPREGION) {
1918 reg_grp_offset = XEN_PCI_INTEL_OPREGION;
1919 }
1920
1921 reg_grp_entry = g_new0(XenPTRegGroup, 1);
1922 QLIST_INIT(&reg_grp_entry->reg_tbl_list);
1923 QLIST_INSERT_HEAD(&s->reg_grps, reg_grp_entry, entries);
1924
1925 reg_grp_entry->base_offset = reg_grp_offset;
1926 reg_grp_entry->reg_grp = xen_pt_emu_reg_grps + i;
1927 if (xen_pt_emu_reg_grps[i].size_init) {
1928 /* get register group size */
1929 rc = xen_pt_emu_reg_grps[i].size_init(s, reg_grp_entry->reg_grp,
1930 reg_grp_offset,
1931 &reg_grp_entry->size);
1932 if (rc < 0) {
1933 xen_pt_config_delete(s);
1934 return rc;
1935 }
1936 }
1937
1938 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
1939 if (xen_pt_emu_reg_grps[i].emu_regs) {
1940 int j = 0;
1941 XenPTRegInfo *regs = xen_pt_emu_reg_grps[i].emu_regs;
1942 /* initialize capability register */
1943 for (j = 0; regs->size != 0; j++, regs++) {
1944 /* initialize capability register */
1945 rc = xen_pt_config_reg_init(s, reg_grp_entry, regs);
1946 if (rc < 0) {
1947 xen_pt_config_delete(s);
1948 return rc;
1949 }
1950 }
1951 }
1952 }
1953 }
1954
1955 return 0;
1956 }
1957
1958 /* delete all emulate register */
1959 void xen_pt_config_delete(XenPCIPassthroughState *s)
1960 {
1961 struct XenPTRegGroup *reg_group, *next_grp;
1962 struct XenPTReg *reg, *next_reg;
1963
1964 /* free MSI/MSI-X info table */
1965 if (s->msix) {
1966 xen_pt_msix_delete(s);
1967 }
1968 if (s->msi) {
1969 g_free(s->msi);
1970 }
1971
1972 /* free all register group entry */
1973 QLIST_FOREACH_SAFE(reg_group, &s->reg_grps, entries, next_grp) {
1974 /* free all register entry */
1975 QLIST_FOREACH_SAFE(reg, &reg_group->reg_tbl_list, entries, next_reg) {
1976 QLIST_REMOVE(reg, entries);
1977 g_free(reg);
1978 }
1979
1980 QLIST_REMOVE(reg_group, entries);
1981 g_free(reg_group);
1982 }
1983 }
AR7 emulation for QEMU