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target/mips: Add CP0 PWField register
[qemu/ar7.git] / target / mips / op_helper.c
blob76be944f068916afd413849bcf6481acce45907c
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
21 #include "cpu.h"
22 #include "internal.h"
23 #include "qemu/host-utils.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "sysemu/kvm.h"
28
29 /*****************************************************************************/
30 /* Exceptions processing helpers */
31
32 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
33 int error_code)
34 {
35 do_raise_exception_err(env, exception, error_code, 0);
36 }
37
38 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
39 {
40 do_raise_exception(env, exception, GETPC());
41 }
42
43 void helper_raise_exception_debug(CPUMIPSState *env)
44 {
45 do_raise_exception(env, EXCP_DEBUG, 0);
46 }
47
48 static void raise_exception(CPUMIPSState *env, uint32_t exception)
49 {
50 do_raise_exception(env, exception, 0);
51 }
52
53 #if defined(CONFIG_USER_ONLY)
54 #define HELPER_LD(name, insn, type) \
55 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
56 int mem_idx, uintptr_t retaddr) \
57 { \
58 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
59 }
60 #else
61 #define HELPER_LD(name, insn, type) \
62 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
63 int mem_idx, uintptr_t retaddr) \
64 { \
65 switch (mem_idx) \
66 { \
67 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
68 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
69 default: \
70 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
71 case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr); \
72 } \
73 }
74 #endif
75 HELPER_LD(lw, ldl, int32_t)
76 #if defined(TARGET_MIPS64)
77 HELPER_LD(ld, ldq, int64_t)
78 #endif
79 #undef HELPER_LD
80
81 #if defined(CONFIG_USER_ONLY)
82 #define HELPER_ST(name, insn, type) \
83 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
84 type val, int mem_idx, uintptr_t retaddr) \
85 { \
86 cpu_##insn##_data_ra(env, addr, val, retaddr); \
87 }
88 #else
89 #define HELPER_ST(name, insn, type) \
90 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
91 type val, int mem_idx, uintptr_t retaddr) \
92 { \
93 switch (mem_idx) \
94 { \
95 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
96 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
97 default: \
98 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
99 case 3: \
100 cpu_##insn##_error_ra(env, addr, val, retaddr); \
101 break; \
102 } \
103 }
104 #endif
105 HELPER_ST(sb, stb, uint8_t)
106 HELPER_ST(sw, stl, uint32_t)
107 #if defined(TARGET_MIPS64)
108 HELPER_ST(sd, stq, uint64_t)
109 #endif
110 #undef HELPER_ST
111
112 /* 64 bits arithmetic for 32 bits hosts */
113 static inline uint64_t get_HILO(CPUMIPSState *env)
114 {
115 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
116 }
117
118 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
119 {
120 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
121 return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
122 }
123
124 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
125 {
126 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
127 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
128 return tmp;
129 }
130
131 /* Multiplication variants of the vr54xx. */
132 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
133 target_ulong arg2)
134 {
135 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
136 (int64_t)(int32_t)arg2));
137 }
138
139 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
140 target_ulong arg2)
141 {
142 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
143 (uint64_t)(uint32_t)arg2);
144 }
145
146 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
147 target_ulong arg2)
148 {
149 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
150 (int64_t)(int32_t)arg2);
151 }
152
153 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
154 target_ulong arg2)
155 {
156 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
157 (int64_t)(int32_t)arg2);
158 }
159
160 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
161 target_ulong arg2)
162 {
163 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
164 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
165 }
166
167 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
168 target_ulong arg2)
169 {
170 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
171 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
172 }
173
174 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
175 target_ulong arg2)
176 {
177 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
178 (int64_t)(int32_t)arg2);
179 }
180
181 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
182 target_ulong arg2)
183 {
184 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
185 (int64_t)(int32_t)arg2);
186 }
187
188 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
189 target_ulong arg2)
190 {
191 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
192 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
193 }
194
195 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
196 target_ulong arg2)
197 {
198 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
199 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
200 }
201
202 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
203 target_ulong arg2)
204 {
205 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
206 }
207
208 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
209 target_ulong arg2)
210 {
211 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
212 (uint64_t)(uint32_t)arg2);
213 }
214
215 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
216 target_ulong arg2)
217 {
218 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
219 (int64_t)(int32_t)arg2);
220 }
221
222 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
223 target_ulong arg2)
224 {
225 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
226 (uint64_t)(uint32_t)arg2);
227 }
228
229 static inline target_ulong bitswap(target_ulong v)
230 {
231 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
232 ((v & (target_ulong)0x5555555555555555ULL) << 1);
233 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
234 ((v & (target_ulong)0x3333333333333333ULL) << 2);
235 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
236 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
237 return v;
238 }
239
240 #ifdef TARGET_MIPS64
241 target_ulong helper_dbitswap(target_ulong rt)
242 {
243 return bitswap(rt);
244 }
245 #endif
246
247 target_ulong helper_bitswap(target_ulong rt)
248 {
249 return (int32_t)bitswap(rt);
250 }
251
252 target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
253 uint32_t stripe)
254 {
255 int i;
256 uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff);
257 uint64_t tmp1 = tmp0;
258 for (i = 0; i <= 46; i++) {
259 int s;
260 if (i & 0x8) {
261 s = shift;
262 } else {
263 s = shiftx;
264 }
265
266 if (stripe != 0 && !(i & 0x4)) {
267 s = ~s;
268 }
269 if (s & 0x10) {
270 if (tmp0 & (1LL << (i + 16))) {
271 tmp1 |= 1LL << i;
272 } else {
273 tmp1 &= ~(1LL << i);
274 }
275 }
276 }
277
278 uint64_t tmp2 = tmp1;
279 for (i = 0; i <= 38; i++) {
280 int s;
281 if (i & 0x4) {
282 s = shift;
283 } else {
284 s = shiftx;
285 }
286
287 if (s & 0x8) {
288 if (tmp1 & (1LL << (i + 8))) {
289 tmp2 |= 1LL << i;
290 } else {
291 tmp2 &= ~(1LL << i);
292 }
293 }
294 }
295
296 uint64_t tmp3 = tmp2;
297 for (i = 0; i <= 34; i++) {
298 int s;
299 if (i & 0x2) {
300 s = shift;
301 } else {
302 s = shiftx;
303 }
304 if (s & 0x4) {
305 if (tmp2 & (1LL << (i + 4))) {
306 tmp3 |= 1LL << i;
307 } else {
308 tmp3 &= ~(1LL << i);
309 }
310 }
311 }
312
313 uint64_t tmp4 = tmp3;
314 for (i = 0; i <= 32; i++) {
315 int s;
316 if (i & 0x1) {
317 s = shift;
318 } else {
319 s = shiftx;
320 }
321 if (s & 0x2) {
322 if (tmp3 & (1LL << (i + 2))) {
323 tmp4 |= 1LL << i;
324 } else {
325 tmp4 &= ~(1LL << i);
326 }
327 }
328 }
329
330 uint64_t tmp5 = tmp4;
331 for (i = 0; i <= 31; i++) {
332 int s;
333 s = shift;
334 if (s & 0x1) {
335 if (tmp4 & (1LL << (i + 1))) {
336 tmp5 |= 1LL << i;
337 } else {
338 tmp5 &= ~(1LL << i);
339 }
340 }
341 }
342
343 return (int64_t)(int32_t)(uint32_t)tmp5;
344 }
345
346 #ifndef CONFIG_USER_ONLY
347
348 static inline hwaddr do_translate_address(CPUMIPSState *env,
349 target_ulong address,
350 int rw, uintptr_t retaddr)
351 {
352 hwaddr lladdr;
353 CPUState *cs = CPU(mips_env_get_cpu(env));
354
355 lladdr = cpu_mips_translate_address(env, address, rw);
356
357 if (lladdr == -1LL) {
358 cpu_loop_exit_restore(cs, retaddr);
359 } else {
360 return lladdr;
361 }
362 }
363
364 #define HELPER_LD_ATOMIC(name, insn, almask) \
365 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
366 { \
367 if (arg & almask) { \
368 if (!(env->hflags & MIPS_HFLAG_DM)) { \
369 env->CP0_BadVAddr = arg; \
370 } \
371 do_raise_exception(env, EXCP_AdEL, GETPC()); \
372 } \
373 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
374 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
375 return env->llval; \
376 }
377 HELPER_LD_ATOMIC(ll, lw, 0x3)
378 #ifdef TARGET_MIPS64
379 HELPER_LD_ATOMIC(lld, ld, 0x7)
380 #endif
381 #undef HELPER_LD_ATOMIC
382
383 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
384 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
385 target_ulong arg2, int mem_idx) \
386 { \
387 target_long tmp; \
388 \
389 if (arg2 & almask) { \
390 if (!(env->hflags & MIPS_HFLAG_DM)) { \
391 env->CP0_BadVAddr = arg2; \
392 } \
393 do_raise_exception(env, EXCP_AdES, GETPC()); \
394 } \
395 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
396 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
397 if (tmp == env->llval) { \
398 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
399 return 1; \
400 } \
401 } \
402 return 0; \
403 }
404 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
405 #ifdef TARGET_MIPS64
406 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
407 #endif
408 #undef HELPER_ST_ATOMIC
409 #endif
410
411 #ifdef TARGET_WORDS_BIGENDIAN
412 #define GET_LMASK(v) ((v) & 3)
413 #define GET_OFFSET(addr, offset) (addr + (offset))
414 #else
415 #define GET_LMASK(v) (((v) & 3) ^ 3)
416 #define GET_OFFSET(addr, offset) (addr - (offset))
417 #endif
418
419 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
420 int mem_idx)
421 {
422 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
423
424 if (GET_LMASK(arg2) <= 2) {
425 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
426 GETPC());
427 }
428
429 if (GET_LMASK(arg2) <= 1) {
430 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
431 GETPC());
432 }
433
434 if (GET_LMASK(arg2) == 0) {
435 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
436 GETPC());
437 }
438 }
439
440 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
441 int mem_idx)
442 {
443 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
444
445 if (GET_LMASK(arg2) >= 1) {
446 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
447 GETPC());
448 }
449
450 if (GET_LMASK(arg2) >= 2) {
451 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
452 GETPC());
453 }
454
455 if (GET_LMASK(arg2) == 3) {
456 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
457 GETPC());
458 }
459 }
460
461 #if defined(TARGET_MIPS64)
462 /* "half" load and stores. We must do the memory access inline,
463 or fault handling won't work. */
464
465 #ifdef TARGET_WORDS_BIGENDIAN
466 #define GET_LMASK64(v) ((v) & 7)
467 #else
468 #define GET_LMASK64(v) (((v) & 7) ^ 7)
469 #endif
470
471 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
472 int mem_idx)
473 {
474 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
475
476 if (GET_LMASK64(arg2) <= 6) {
477 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
478 GETPC());
479 }
480
481 if (GET_LMASK64(arg2) <= 5) {
482 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
483 GETPC());
484 }
485
486 if (GET_LMASK64(arg2) <= 4) {
487 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
488 GETPC());
489 }
490
491 if (GET_LMASK64(arg2) <= 3) {
492 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
493 GETPC());
494 }
495
496 if (GET_LMASK64(arg2) <= 2) {
497 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
498 GETPC());
499 }
500
501 if (GET_LMASK64(arg2) <= 1) {
502 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
503 GETPC());
504 }
505
506 if (GET_LMASK64(arg2) <= 0) {
507 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
508 GETPC());
509 }
510 }
511
512 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
513 int mem_idx)
514 {
515 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
516
517 if (GET_LMASK64(arg2) >= 1) {
518 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
519 GETPC());
520 }
521
522 if (GET_LMASK64(arg2) >= 2) {
523 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
524 GETPC());
525 }
526
527 if (GET_LMASK64(arg2) >= 3) {
528 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
529 GETPC());
530 }
531
532 if (GET_LMASK64(arg2) >= 4) {
533 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
534 GETPC());
535 }
536
537 if (GET_LMASK64(arg2) >= 5) {
538 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
539 GETPC());
540 }
541
542 if (GET_LMASK64(arg2) >= 6) {
543 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
544 GETPC());
545 }
546
547 if (GET_LMASK64(arg2) == 7) {
548 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
549 GETPC());
550 }
551 }
552 #endif /* TARGET_MIPS64 */
553
554 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
555
556 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
557 uint32_t mem_idx)
558 {
559 target_ulong base_reglist = reglist & 0xf;
560 target_ulong do_r31 = reglist & 0x10;
561
562 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
563 target_ulong i;
564
565 for (i = 0; i < base_reglist; i++) {
566 env->active_tc.gpr[multiple_regs[i]] =
567 (target_long)do_lw(env, addr, mem_idx, GETPC());
568 addr += 4;
569 }
570 }
571
572 if (do_r31) {
573 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
574 GETPC());
575 }
576 }
577
578 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
579 uint32_t mem_idx)
580 {
581 target_ulong base_reglist = reglist & 0xf;
582 target_ulong do_r31 = reglist & 0x10;
583
584 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
585 target_ulong i;
586
587 for (i = 0; i < base_reglist; i++) {
588 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
589 GETPC());
590 addr += 4;
591 }
592 }
593
594 if (do_r31) {
595 do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
596 }
597 }
598
599 #if defined(TARGET_MIPS64)
600 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
601 uint32_t mem_idx)
602 {
603 target_ulong base_reglist = reglist & 0xf;
604 target_ulong do_r31 = reglist & 0x10;
605
606 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
607 target_ulong i;
608
609 for (i = 0; i < base_reglist; i++) {
610 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
611 GETPC());
612 addr += 8;
613 }
614 }
615
616 if (do_r31) {
617 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
618 }
619 }
620
621 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
622 uint32_t mem_idx)
623 {
624 target_ulong base_reglist = reglist & 0xf;
625 target_ulong do_r31 = reglist & 0x10;
626
627 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
628 target_ulong i;
629
630 for (i = 0; i < base_reglist; i++) {
631 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
632 GETPC());
633 addr += 8;
634 }
635 }
636
637 if (do_r31) {
638 do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
639 }
640 }
641 #endif
642
643 #ifndef CONFIG_USER_ONLY
644 /* SMP helpers. */
645 static bool mips_vpe_is_wfi(MIPSCPU *c)
646 {
647 CPUState *cpu = CPU(c);
648 CPUMIPSState *env = &c->env;
649
650 /* If the VPE is halted but otherwise active, it means it's waiting for
651 an interrupt. */
652 return cpu->halted && mips_vpe_active(env);
653 }
654
655 static bool mips_vp_is_wfi(MIPSCPU *c)
656 {
657 CPUState *cpu = CPU(c);
658 CPUMIPSState *env = &c->env;
659
660 return cpu->halted && mips_vp_active(env);
661 }
662
663 static inline void mips_vpe_wake(MIPSCPU *c)
664 {
665 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
666 because there might be other conditions that state that c should
667 be sleeping. */
668 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
669 }
670
671 static inline void mips_vpe_sleep(MIPSCPU *cpu)
672 {
673 CPUState *cs = CPU(cpu);
674
675 /* The VPE was shut off, really go to bed.
676 Reset any old _WAKE requests. */
677 cs->halted = 1;
678 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
679 }
680
681 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
682 {
683 CPUMIPSState *c = &cpu->env;
684
685 /* FIXME: TC reschedule. */
686 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
687 mips_vpe_wake(cpu);
688 }
689 }
690
691 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
692 {
693 CPUMIPSState *c = &cpu->env;
694
695 /* FIXME: TC reschedule. */
696 if (!mips_vpe_active(c)) {
697 mips_vpe_sleep(cpu);
698 }
699 }
700
701 /**
702 * mips_cpu_map_tc:
703 * @env: CPU from which mapping is performed.
704 * @tc: Should point to an int with the value of the global TC index.
705 *
706 * This function will transform @tc into a local index within the
707 * returned #CPUMIPSState.
708 */
709 /* FIXME: This code assumes that all VPEs have the same number of TCs,
710 which depends on runtime setup. Can probably be fixed by
711 walking the list of CPUMIPSStates. */
712 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
713 {
714 MIPSCPU *cpu;
715 CPUState *cs;
716 CPUState *other_cs;
717 int vpe_idx;
718 int tc_idx = *tc;
719
720 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
721 /* Not allowed to address other CPUs. */
722 *tc = env->current_tc;
723 return env;
724 }
725
726 cs = CPU(mips_env_get_cpu(env));
727 vpe_idx = tc_idx / cs->nr_threads;
728 *tc = tc_idx % cs->nr_threads;
729 other_cs = qemu_get_cpu(vpe_idx);
730 if (other_cs == NULL) {
731 return env;
732 }
733 cpu = MIPS_CPU(other_cs);
734 return &cpu->env;
735 }
736
737 /* The per VPE CP0_Status register shares some fields with the per TC
738 CP0_TCStatus registers. These fields are wired to the same registers,
739 so changes to either of them should be reflected on both registers.
740
741 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
742
743 These helper call synchronizes the regs for a given cpu. */
744
745 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
746 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
747 int tc); */
748
749 /* Called for updates to CP0_TCStatus. */
750 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
751 target_ulong v)
752 {
753 uint32_t status;
754 uint32_t tcu, tmx, tasid, tksu;
755 uint32_t mask = ((1U << CP0St_CU3)
756 | (1 << CP0St_CU2)
757 | (1 << CP0St_CU1)
758 | (1 << CP0St_CU0)
759 | (1 << CP0St_MX)
760 | (3 << CP0St_KSU));
761
762 tcu = (v >> CP0TCSt_TCU0) & 0xf;
763 tmx = (v >> CP0TCSt_TMX) & 0x1;
764 tasid = v & cpu->CP0_EntryHi_ASID_mask;
765 tksu = (v >> CP0TCSt_TKSU) & 0x3;
766
767 status = tcu << CP0St_CU0;
768 status |= tmx << CP0St_MX;
769 status |= tksu << CP0St_KSU;
770
771 cpu->CP0_Status &= ~mask;
772 cpu->CP0_Status |= status;
773
774 /* Sync the TASID with EntryHi. */
775 cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
776 cpu->CP0_EntryHi |= tasid;
777
778 compute_hflags(cpu);
779 }
780
781 /* Called for updates to CP0_EntryHi. */
782 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
783 {
784 int32_t *tcst;
785 uint32_t asid, v = cpu->CP0_EntryHi;
786
787 asid = v & cpu->CP0_EntryHi_ASID_mask;
788
789 if (tc == cpu->current_tc) {
790 tcst = &cpu->active_tc.CP0_TCStatus;
791 } else {
792 tcst = &cpu->tcs[tc].CP0_TCStatus;
793 }
794
795 *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
796 *tcst |= asid;
797 }
798
799 /* CP0 helpers */
800 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
801 {
802 return env->mvp->CP0_MVPControl;
803 }
804
805 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
806 {
807 return env->mvp->CP0_MVPConf0;
808 }
809
810 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
811 {
812 return env->mvp->CP0_MVPConf1;
813 }
814
815 target_ulong helper_mfc0_random(CPUMIPSState *env)
816 {
817 return (int32_t)cpu_mips_get_random(env);
818 }
819
820 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
821 {
822 return env->active_tc.CP0_TCStatus;
823 }
824
825 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
826 {
827 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
828 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
829
830 if (other_tc == other->current_tc)
831 return other->active_tc.CP0_TCStatus;
832 else
833 return other->tcs[other_tc].CP0_TCStatus;
834 }
835
836 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
837 {
838 return env->active_tc.CP0_TCBind;
839 }
840
841 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
842 {
843 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
844 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
845
846 if (other_tc == other->current_tc)
847 return other->active_tc.CP0_TCBind;
848 else
849 return other->tcs[other_tc].CP0_TCBind;
850 }
851
852 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
853 {
854 return env->active_tc.PC;
855 }
856
857 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
858 {
859 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
860 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
861
862 if (other_tc == other->current_tc)
863 return other->active_tc.PC;
864 else
865 return other->tcs[other_tc].PC;
866 }
867
868 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
869 {
870 return env->active_tc.CP0_TCHalt;
871 }
872
873 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
874 {
875 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
876 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
877
878 if (other_tc == other->current_tc)
879 return other->active_tc.CP0_TCHalt;
880 else
881 return other->tcs[other_tc].CP0_TCHalt;
882 }
883
884 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
885 {
886 return env->active_tc.CP0_TCContext;
887 }
888
889 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
890 {
891 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
892 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
893
894 if (other_tc == other->current_tc)
895 return other->active_tc.CP0_TCContext;
896 else
897 return other->tcs[other_tc].CP0_TCContext;
898 }
899
900 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
901 {
902 return env->active_tc.CP0_TCSchedule;
903 }
904
905 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
906 {
907 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
908 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
909
910 if (other_tc == other->current_tc)
911 return other->active_tc.CP0_TCSchedule;
912 else
913 return other->tcs[other_tc].CP0_TCSchedule;
914 }
915
916 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
917 {
918 return env->active_tc.CP0_TCScheFBack;
919 }
920
921 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
922 {
923 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
924 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
925
926 if (other_tc == other->current_tc)
927 return other->active_tc.CP0_TCScheFBack;
928 else
929 return other->tcs[other_tc].CP0_TCScheFBack;
930 }
931
932 target_ulong helper_mfc0_count(CPUMIPSState *env)
933 {
934 int32_t count;
935 qemu_mutex_lock_iothread();
936 count = (int32_t) cpu_mips_get_count(env);
937 qemu_mutex_unlock_iothread();
938 return count;
939 }
940
941 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
942 {
943 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
944 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
945
946 return other->CP0_EntryHi;
947 }
948
949 target_ulong helper_mftc0_cause(CPUMIPSState *env)
950 {
951 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
952 int32_t tccause;
953 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
954
955 if (other_tc == other->current_tc) {
956 tccause = other->CP0_Cause;
957 } else {
958 tccause = other->CP0_Cause;
959 }
960
961 return tccause;
962 }
963
964 target_ulong helper_mftc0_status(CPUMIPSState *env)
965 {
966 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
967 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
968
969 return other->CP0_Status;
970 }
971
972 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
973 {
974 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
975 }
976
977 target_ulong helper_mfc0_maar(CPUMIPSState *env)
978 {
979 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
980 }
981
982 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
983 {
984 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
985 }
986
987 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
988 {
989 return (int32_t)env->CP0_WatchLo[sel];
990 }
991
992 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
993 {
994 return env->CP0_WatchHi[sel];
995 }
996
997 target_ulong helper_mfc0_debug(CPUMIPSState *env)
998 {
999 target_ulong t0 = env->CP0_Debug;
1000 if (env->hflags & MIPS_HFLAG_DM)
1001 t0 |= 1 << CP0DB_DM;
1002
1003 return t0;
1004 }
1005
1006 target_ulong helper_mftc0_debug(CPUMIPSState *env)
1007 {
1008 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1009 int32_t tcstatus;
1010 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1011
1012 if (other_tc == other->current_tc)
1013 tcstatus = other->active_tc.CP0_Debug_tcstatus;
1014 else
1015 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
1016
1017 /* XXX: Might be wrong, check with EJTAG spec. */
1018 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1019 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1020 }
1021
1022 #if defined(TARGET_MIPS64)
1023 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
1024 {
1025 return env->active_tc.PC;
1026 }
1027
1028 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
1029 {
1030 return env->active_tc.CP0_TCHalt;
1031 }
1032
1033 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
1034 {
1035 return env->active_tc.CP0_TCContext;
1036 }
1037
1038 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
1039 {
1040 return env->active_tc.CP0_TCSchedule;
1041 }
1042
1043 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
1044 {
1045 return env->active_tc.CP0_TCScheFBack;
1046 }
1047
1048 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
1049 {
1050 return env->lladdr >> env->CP0_LLAddr_shift;
1051 }
1052
1053 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
1054 {
1055 return env->CP0_MAAR[env->CP0_MAARI];
1056 }
1057
1058 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
1059 {
1060 return env->CP0_WatchLo[sel];
1061 }
1062 #endif /* TARGET_MIPS64 */
1063
1064 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
1065 {
1066 uint32_t index_p = env->CP0_Index & 0x80000000;
1067 uint32_t tlb_index = arg1 & 0x7fffffff;
1068 if (tlb_index < env->tlb->nb_tlb) {
1069 if (env->insn_flags & ISA_MIPS32R6) {
1070 index_p |= arg1 & 0x80000000;
1071 }
1072 env->CP0_Index = index_p | tlb_index;
1073 }
1074 }
1075
1076 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
1077 {
1078 uint32_t mask = 0;
1079 uint32_t newval;
1080
1081 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
1082 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
1083 (1 << CP0MVPCo_EVP);
1084 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1085 mask |= (1 << CP0MVPCo_STLB);
1086 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1087
1088 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1089
1090 env->mvp->CP0_MVPControl = newval;
1091 }
1092
1093 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1094 {
1095 uint32_t mask;
1096 uint32_t newval;
1097
1098 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1099 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1100 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1101
1102 /* Yield scheduler intercept not implemented. */
1103 /* Gating storage scheduler intercept not implemented. */
1104
1105 // TODO: Enable/disable TCs.
1106
1107 env->CP0_VPEControl = newval;
1108 }
1109
1110 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1111 {
1112 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1113 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1114 uint32_t mask;
1115 uint32_t newval;
1116
1117 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1118 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1119 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1120
1121 /* TODO: Enable/disable TCs. */
1122
1123 other->CP0_VPEControl = newval;
1124 }
1125
1126 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1127 {
1128 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1129 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1130 /* FIXME: Mask away return zero on read bits. */
1131 return other->CP0_VPEControl;
1132 }
1133
1134 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1135 {
1136 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1137 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1138
1139 return other->CP0_VPEConf0;
1140 }
1141
1142 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1143 {
1144 uint32_t mask = 0;
1145 uint32_t newval;
1146
1147 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1148 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1149 mask |= (0xff << CP0VPEC0_XTC);
1150 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1151 }
1152 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1153
1154 // TODO: TC exclusive handling due to ERL/EXL.
1155
1156 env->CP0_VPEConf0 = newval;
1157 }
1158
1159 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1160 {
1161 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1162 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1163 uint32_t mask = 0;
1164 uint32_t newval;
1165
1166 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1167 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1168
1169 /* TODO: TC exclusive handling due to ERL/EXL. */
1170 other->CP0_VPEConf0 = newval;
1171 }
1172
1173 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1174 {
1175 uint32_t mask = 0;
1176 uint32_t newval;
1177
1178 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1179 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1180 (0xff << CP0VPEC1_NCP1);
1181 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1182
1183 /* UDI not implemented. */
1184 /* CP2 not implemented. */
1185
1186 // TODO: Handle FPU (CP1) binding.
1187
1188 env->CP0_VPEConf1 = newval;
1189 }
1190
1191 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1192 {
1193 /* Yield qualifier inputs not implemented. */
1194 env->CP0_YQMask = 0x00000000;
1195 }
1196
1197 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1198 {
1199 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1200 }
1201
1202 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1203
1204 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1205 {
1206 /* 1k pages not implemented */
1207 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1208 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1209 | (rxi << (CP0EnLo_XI - 30));
1210 }
1211
1212 #if defined(TARGET_MIPS64)
1213 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1214
1215 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1216 {
1217 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1218 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1219 }
1220 #endif
1221
1222 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1223 {
1224 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1225 uint32_t newval;
1226
1227 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1228
1229 env->active_tc.CP0_TCStatus = newval;
1230 sync_c0_tcstatus(env, env->current_tc, newval);
1231 }
1232
1233 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1234 {
1235 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1236 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1237
1238 if (other_tc == other->current_tc)
1239 other->active_tc.CP0_TCStatus = arg1;
1240 else
1241 other->tcs[other_tc].CP0_TCStatus = arg1;
1242 sync_c0_tcstatus(other, other_tc, arg1);
1243 }
1244
1245 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1246 {
1247 uint32_t mask = (1 << CP0TCBd_TBE);
1248 uint32_t newval;
1249
1250 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1251 mask |= (1 << CP0TCBd_CurVPE);
1252 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1253 env->active_tc.CP0_TCBind = newval;
1254 }
1255
1256 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1257 {
1258 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1259 uint32_t mask = (1 << CP0TCBd_TBE);
1260 uint32_t newval;
1261 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1262
1263 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1264 mask |= (1 << CP0TCBd_CurVPE);
1265 if (other_tc == other->current_tc) {
1266 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1267 other->active_tc.CP0_TCBind = newval;
1268 } else {
1269 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1270 other->tcs[other_tc].CP0_TCBind = newval;
1271 }
1272 }
1273
1274 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1275 {
1276 env->active_tc.PC = arg1;
1277 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1278 env->lladdr = 0ULL;
1279 /* MIPS16 not implemented. */
1280 }
1281
1282 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1283 {
1284 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1285 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1286
1287 if (other_tc == other->current_tc) {
1288 other->active_tc.PC = arg1;
1289 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1290 other->lladdr = 0ULL;
1291 /* MIPS16 not implemented. */
1292 } else {
1293 other->tcs[other_tc].PC = arg1;
1294 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1295 other->lladdr = 0ULL;
1296 /* MIPS16 not implemented. */
1297 }
1298 }
1299
1300 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1301 {
1302 MIPSCPU *cpu = mips_env_get_cpu(env);
1303
1304 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1305
1306 // TODO: Halt TC / Restart (if allocated+active) TC.
1307 if (env->active_tc.CP0_TCHalt & 1) {
1308 mips_tc_sleep(cpu, env->current_tc);
1309 } else {
1310 mips_tc_wake(cpu, env->current_tc);
1311 }
1312 }
1313
1314 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1315 {
1316 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1317 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1318 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1319
1320 // TODO: Halt TC / Restart (if allocated+active) TC.
1321
1322 if (other_tc == other->current_tc)
1323 other->active_tc.CP0_TCHalt = arg1;
1324 else
1325 other->tcs[other_tc].CP0_TCHalt = arg1;
1326
1327 if (arg1 & 1) {
1328 mips_tc_sleep(other_cpu, other_tc);
1329 } else {
1330 mips_tc_wake(other_cpu, other_tc);
1331 }
1332 }
1333
1334 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1335 {
1336 env->active_tc.CP0_TCContext = arg1;
1337 }
1338
1339 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1340 {
1341 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1342 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1343
1344 if (other_tc == other->current_tc)
1345 other->active_tc.CP0_TCContext = arg1;
1346 else
1347 other->tcs[other_tc].CP0_TCContext = arg1;
1348 }
1349
1350 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1351 {
1352 env->active_tc.CP0_TCSchedule = arg1;
1353 }
1354
1355 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1356 {
1357 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1358 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1359
1360 if (other_tc == other->current_tc)
1361 other->active_tc.CP0_TCSchedule = arg1;
1362 else
1363 other->tcs[other_tc].CP0_TCSchedule = arg1;
1364 }
1365
1366 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1367 {
1368 env->active_tc.CP0_TCScheFBack = arg1;
1369 }
1370
1371 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1372 {
1373 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1374 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1375
1376 if (other_tc == other->current_tc)
1377 other->active_tc.CP0_TCScheFBack = arg1;
1378 else
1379 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1380 }
1381
1382 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1383 {
1384 /* 1k pages not implemented */
1385 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1386 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1387 | (rxi << (CP0EnLo_XI - 30));
1388 }
1389
1390 #if defined(TARGET_MIPS64)
1391 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1392 {
1393 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1394 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1395 }
1396 #endif
1397
1398 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1399 {
1400 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1401 }
1402
1403 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1404 {
1405 uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1406 if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1407 (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1408 mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1409 mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1410 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1411 }
1412 }
1413
1414 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1415 {
1416 /* SmartMIPS not implemented */
1417 /* 1k pages not implemented */
1418 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1419 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1420 compute_hflags(env);
1421 restore_pamask(env);
1422 }
1423
1424 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
1425 {
1426 CPUState *cs = CPU(mips_env_get_cpu(env));
1427
1428 env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
1429 tlb_flush(cs);
1430 }
1431
1432 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
1433 {
1434 CPUState *cs = CPU(mips_env_get_cpu(env));
1435
1436 env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
1437 tlb_flush(cs);
1438 }
1439
1440 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
1441 {
1442 CPUState *cs = CPU(mips_env_get_cpu(env));
1443
1444 env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
1445 tlb_flush(cs);
1446 }
1447
1448 void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
1449 {
1450 #if defined(TARGET_MIPS64)
1451 uint64_t mask = 0x3F3FFFFFFFULL;
1452 uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;
1453 uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;
1454
1455 if ((env->insn_flags & ISA_MIPS32R6)) {
1456 if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {
1457 mask &= ~(0x3FULL << CP0PF_BDI);
1458 }
1459 if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) {
1460 mask &= ~(0x3FULL << CP0PF_GDI);
1461 }
1462 if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) {
1463 mask &= ~(0x3FULL << CP0PF_UDI);
1464 }
1465 if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) {
1466 mask &= ~(0x3FULL << CP0PF_MDI);
1467 }
1468 if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) {
1469 mask &= ~(0x3FULL << CP0PF_PTI);
1470 }
1471 }
1472 env->CP0_PWField = arg1 & mask;
1473
1474 if ((new_ptei >= 32) ||
1475 ((env->insn_flags & ISA_MIPS32R6) &&
1476 (new_ptei == 0 || new_ptei == 1))) {
1477 env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |
1478 (old_ptei << CP0PF_PTEI);
1479 }
1480 #else
1481 uint32_t mask = 0x3FFFFFFF;
1482 uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
1483 uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;
1484
1485 if ((env->insn_flags & ISA_MIPS32R6)) {
1486 if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {
1487 mask &= ~(0x3F << CP0PF_GDW);
1488 }
1489 if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) {
1490 mask &= ~(0x3F << CP0PF_UDW);
1491 }
1492 if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) {
1493 mask &= ~(0x3F << CP0PF_MDW);
1494 }
1495 if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) {
1496 mask &= ~(0x3F << CP0PF_PTW);
1497 }
1498 }
1499 env->CP0_PWField = arg1 & mask;
1500
1501 if ((new_ptew >= 32) ||
1502 ((env->insn_flags & ISA_MIPS32R6) &&
1503 (new_ptew == 0 || new_ptew == 1))) {
1504 env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
1505 (old_ptew << CP0PF_PTEW);
1506 }
1507 #endif
1508 }
1509
1510 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1511 {
1512 if (env->insn_flags & ISA_MIPS32R6) {
1513 if (arg1 < env->tlb->nb_tlb) {
1514 env->CP0_Wired = arg1;
1515 }
1516 } else {
1517 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1518 }
1519 }
1520
1521 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1522 {
1523 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1524 }
1525
1526 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1527 {
1528 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1529 }
1530
1531 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1532 {
1533 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1534 }
1535
1536 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1537 {
1538 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1539 }
1540
1541 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1542 {
1543 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1544 }
1545
1546 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1547 {
1548 uint32_t mask = 0x0000000F;
1549
1550 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1551 (env->insn_flags & ISA_MIPS32R6)) {
1552 mask |= (1 << 4);
1553 }
1554 if (env->insn_flags & ISA_MIPS32R6) {
1555 mask |= (1 << 5);
1556 }
1557 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1558 mask |= (1 << 29);
1559
1560 if (arg1 & (1 << 29)) {
1561 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1562 } else {
1563 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1564 }
1565 }
1566
1567 env->CP0_HWREna = arg1 & mask;
1568 }
1569
1570 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1571 {
1572 qemu_mutex_lock_iothread();
1573 cpu_mips_store_count(env, arg1);
1574 qemu_mutex_unlock_iothread();
1575 }
1576
1577 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1578 {
1579 target_ulong old, val, mask;
1580 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1581 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1582 mask |= 1 << CP0EnHi_EHINV;
1583 }
1584
1585 /* 1k pages not implemented */
1586 #if defined(TARGET_MIPS64)
1587 if (env->insn_flags & ISA_MIPS32R6) {
1588 int entryhi_r = extract64(arg1, 62, 2);
1589 int config0_at = extract32(env->CP0_Config0, 13, 2);
1590 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1591 if ((entryhi_r == 2) ||
1592 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1593 /* skip EntryHi.R field if new value is reserved */
1594 mask &= ~(0x3ull << 62);
1595 }
1596 }
1597 mask &= env->SEGMask;
1598 #endif
1599 old = env->CP0_EntryHi;
1600 val = (arg1 & mask) | (old & ~mask);
1601 env->CP0_EntryHi = val;
1602 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1603 sync_c0_entryhi(env, env->current_tc);
1604 }
1605 /* If the ASID changes, flush qemu's TLB. */
1606 if ((old & env->CP0_EntryHi_ASID_mask) !=
1607 (val & env->CP0_EntryHi_ASID_mask)) {
1608 tlb_flush(CPU(mips_env_get_cpu(env)));
1609 }
1610 }
1611
1612 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1613 {
1614 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1615 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1616
1617 other->CP0_EntryHi = arg1;
1618 sync_c0_entryhi(other, other_tc);
1619 }
1620
1621 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1622 {
1623 qemu_mutex_lock_iothread();
1624 cpu_mips_store_compare(env, arg1);
1625 qemu_mutex_unlock_iothread();
1626 }
1627
1628 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1629 {
1630 MIPSCPU *cpu = mips_env_get_cpu(env);
1631 uint32_t val, old;
1632
1633 old = env->CP0_Status;
1634 cpu_mips_store_status(env, arg1);
1635 val = env->CP0_Status;
1636
1637 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1638 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1639 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1640 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1641 env->CP0_Cause);
1642 switch (cpu_mmu_index(env, false)) {
1643 case 3:
1644 qemu_log(", ERL\n");
1645 break;
1646 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1647 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1648 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1649 default:
1650 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1651 break;
1652 }
1653 }
1654 }
1655
1656 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1657 {
1658 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1659 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1660 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1661
1662 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1663 sync_c0_status(env, other, other_tc);
1664 }
1665
1666 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1667 {
1668 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1669 }
1670
1671 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1672 {
1673 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1674 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1675 }
1676
1677 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1678 {
1679 qemu_mutex_lock_iothread();
1680 cpu_mips_store_cause(env, arg1);
1681 qemu_mutex_unlock_iothread();
1682 }
1683
1684 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1685 {
1686 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1687 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1688
1689 cpu_mips_store_cause(other, arg1);
1690 }
1691
1692 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1693 {
1694 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1695 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1696
1697 return other->CP0_EPC;
1698 }
1699
1700 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1701 {
1702 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1703 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1704
1705 return other->CP0_EBase;
1706 }
1707
1708 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1709 {
1710 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1711 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1712 mask |= ~0x3FFFFFFF;
1713 }
1714 env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask);
1715 }
1716
1717 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1718 {
1719 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1720 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1721 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1722 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1723 mask |= ~0x3FFFFFFF;
1724 }
1725 other->CP0_EBase = (other->CP0_EBase & ~mask) | (arg1 & mask);
1726 }
1727
1728 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1729 {
1730 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1731 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1732
1733 switch (idx) {
1734 case 0: return other->CP0_Config0;
1735 case 1: return other->CP0_Config1;
1736 case 2: return other->CP0_Config2;
1737 case 3: return other->CP0_Config3;
1738 /* 4 and 5 are reserved. */
1739 case 6: return other->CP0_Config6;
1740 case 7: return other->CP0_Config7;
1741 default:
1742 break;
1743 }
1744 return 0;
1745 }
1746
1747 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1748 {
1749 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1750 }
1751
1752 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1753 {
1754 /* tertiary/secondary caches not implemented */
1755 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1756 }
1757
1758 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1759 {
1760 if (env->insn_flags & ASE_MICROMIPS) {
1761 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1762 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1763 }
1764 }
1765
1766 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1767 {
1768 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1769 (arg1 & env->CP0_Config4_rw_bitmask);
1770 }
1771
1772 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1773 {
1774 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1775 (arg1 & env->CP0_Config5_rw_bitmask);
1776 compute_hflags(env);
1777 }
1778
1779 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1780 {
1781 target_long mask = env->CP0_LLAddr_rw_bitmask;
1782 arg1 = arg1 << env->CP0_LLAddr_shift;
1783 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1784 }
1785
1786 #define MTC0_MAAR_MASK(env) \
1787 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1788
1789 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1790 {
1791 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1792 }
1793
1794 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1795 {
1796 env->CP0_MAAR[env->CP0_MAARI] =
1797 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1798 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1799 }
1800
1801 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1802 {
1803 int index = arg1 & 0x3f;
1804 if (index == 0x3f) {
1805 /* Software may write all ones to INDEX to determine the
1806 maximum value supported. */
1807 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1808 } else if (index < MIPS_MAAR_MAX) {
1809 env->CP0_MAARI = index;
1810 }
1811 /* Other than the all ones, if the
1812 value written is not supported, then INDEX is unchanged
1813 from its previous value. */
1814 }
1815
1816 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1817 {
1818 /* Watch exceptions for instructions, data loads, data stores
1819 not implemented. */
1820 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1821 }
1822
1823 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1824 {
1825 int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1826 env->CP0_WatchHi[sel] = arg1 & mask;
1827 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1828 }
1829
1830 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1831 {
1832 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1833 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1834 }
1835
1836 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1837 {
1838 env->CP0_Framemask = arg1; /* XXX */
1839 }
1840
1841 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1842 {
1843 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1844 if (arg1 & (1 << CP0DB_DM))
1845 env->hflags |= MIPS_HFLAG_DM;
1846 else
1847 env->hflags &= ~MIPS_HFLAG_DM;
1848 }
1849
1850 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1851 {
1852 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1853 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1854 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1855
1856 /* XXX: Might be wrong, check with EJTAG spec. */
1857 if (other_tc == other->current_tc)
1858 other->active_tc.CP0_Debug_tcstatus = val;
1859 else
1860 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1861 other->CP0_Debug = (other->CP0_Debug &
1862 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1863 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1864 }
1865
1866 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1867 {
1868 env->CP0_Performance0 = arg1 & 0x000007ff;
1869 }
1870
1871 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1872 {
1873 int32_t wst = arg1 & (1 << CP0EC_WST);
1874 int32_t spr = arg1 & (1 << CP0EC_SPR);
1875 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1876
1877 env->CP0_ErrCtl = wst | spr | itc;
1878
1879 if (itc && !wst && !spr) {
1880 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1881 } else {
1882 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1883 }
1884 }
1885
1886 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1887 {
1888 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1889 /* If CACHE instruction is configured for ITC tags then make all
1890 CP0.TagLo bits writable. The actual write to ITC Configuration
1891 Tag will take care of the read-only bits. */
1892 env->CP0_TagLo = arg1;
1893 } else {
1894 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1895 }
1896 }
1897
1898 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1899 {
1900 env->CP0_DataLo = arg1; /* XXX */
1901 }
1902
1903 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1904 {
1905 env->CP0_TagHi = arg1; /* XXX */
1906 }
1907
1908 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1909 {
1910 env->CP0_DataHi = arg1; /* XXX */
1911 }
1912
1913 /* MIPS MT functions */
1914 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1915 {
1916 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1917 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1918
1919 if (other_tc == other->current_tc)
1920 return other->active_tc.gpr[sel];
1921 else
1922 return other->tcs[other_tc].gpr[sel];
1923 }
1924
1925 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1926 {
1927 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1928 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1929
1930 if (other_tc == other->current_tc)
1931 return other->active_tc.LO[sel];
1932 else
1933 return other->tcs[other_tc].LO[sel];
1934 }
1935
1936 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1937 {
1938 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1939 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1940
1941 if (other_tc == other->current_tc)
1942 return other->active_tc.HI[sel];
1943 else
1944 return other->tcs[other_tc].HI[sel];
1945 }
1946
1947 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1948 {
1949 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1950 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1951
1952 if (other_tc == other->current_tc)
1953 return other->active_tc.ACX[sel];
1954 else
1955 return other->tcs[other_tc].ACX[sel];
1956 }
1957
1958 target_ulong helper_mftdsp(CPUMIPSState *env)
1959 {
1960 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1961 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1962
1963 if (other_tc == other->current_tc)
1964 return other->active_tc.DSPControl;
1965 else
1966 return other->tcs[other_tc].DSPControl;
1967 }
1968
1969 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1970 {
1971 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1972 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1973
1974 if (other_tc == other->current_tc)
1975 other->active_tc.gpr[sel] = arg1;
1976 else
1977 other->tcs[other_tc].gpr[sel] = arg1;
1978 }
1979
1980 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1981 {
1982 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1983 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1984
1985 if (other_tc == other->current_tc)
1986 other->active_tc.LO[sel] = arg1;
1987 else
1988 other->tcs[other_tc].LO[sel] = arg1;
1989 }
1990
1991 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1992 {
1993 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1994 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1995
1996 if (other_tc == other->current_tc)
1997 other->active_tc.HI[sel] = arg1;
1998 else
1999 other->tcs[other_tc].HI[sel] = arg1;
2000 }
2001
2002 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2003 {
2004 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2005 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2006
2007 if (other_tc == other->current_tc)
2008 other->active_tc.ACX[sel] = arg1;
2009 else
2010 other->tcs[other_tc].ACX[sel] = arg1;
2011 }
2012
2013 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
2014 {
2015 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2016 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2017
2018 if (other_tc == other->current_tc)
2019 other->active_tc.DSPControl = arg1;
2020 else
2021 other->tcs[other_tc].DSPControl = arg1;
2022 }
2023
2024 /* MIPS MT functions */
2025 target_ulong helper_dmt(void)
2026 {
2027 // TODO
2028 return 0;
2029 }
2030
2031 target_ulong helper_emt(void)
2032 {
2033 // TODO
2034 return 0;
2035 }
2036
2037 target_ulong helper_dvpe(CPUMIPSState *env)
2038 {
2039 CPUState *other_cs = first_cpu;
2040 target_ulong prev = env->mvp->CP0_MVPControl;
2041
2042 CPU_FOREACH(other_cs) {
2043 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2044 /* Turn off all VPEs except the one executing the dvpe. */
2045 if (&other_cpu->env != env) {
2046 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
2047 mips_vpe_sleep(other_cpu);
2048 }
2049 }
2050 return prev;
2051 }
2052
2053 target_ulong helper_evpe(CPUMIPSState *env)
2054 {
2055 CPUState *other_cs = first_cpu;
2056 target_ulong prev = env->mvp->CP0_MVPControl;
2057
2058 CPU_FOREACH(other_cs) {
2059 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2060
2061 if (&other_cpu->env != env
2062 /* If the VPE is WFI, don't disturb its sleep. */
2063 && !mips_vpe_is_wfi(other_cpu)) {
2064 /* Enable the VPE. */
2065 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
2066 mips_vpe_wake(other_cpu); /* And wake it up. */
2067 }
2068 }
2069 return prev;
2070 }
2071 #endif /* !CONFIG_USER_ONLY */
2072
2073 void helper_fork(target_ulong arg1, target_ulong arg2)
2074 {
2075 // arg1 = rt, arg2 = rs
2076 // TODO: store to TC register
2077 }
2078
2079 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
2080 {
2081 target_long arg1 = arg;
2082
2083 if (arg1 < 0) {
2084 /* No scheduling policy implemented. */
2085 if (arg1 != -2) {
2086 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
2087 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
2088 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2089 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
2090 do_raise_exception(env, EXCP_THREAD, GETPC());
2091 }
2092 }
2093 } else if (arg1 == 0) {
2094 if (0 /* TODO: TC underflow */) {
2095 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2096 do_raise_exception(env, EXCP_THREAD, GETPC());
2097 } else {
2098 // TODO: Deallocate TC
2099 }
2100 } else if (arg1 > 0) {
2101 /* Yield qualifier inputs not implemented. */
2102 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2103 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
2104 do_raise_exception(env, EXCP_THREAD, GETPC());
2105 }
2106 return env->CP0_YQMask;
2107 }
2108
2109 /* R6 Multi-threading */
2110 #ifndef CONFIG_USER_ONLY
2111 target_ulong helper_dvp(CPUMIPSState *env)
2112 {
2113 CPUState *other_cs = first_cpu;
2114 target_ulong prev = env->CP0_VPControl;
2115
2116 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
2117 CPU_FOREACH(other_cs) {
2118 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2119 /* Turn off all VPs except the one executing the dvp. */
2120 if (&other_cpu->env != env) {
2121 mips_vpe_sleep(other_cpu);
2122 }
2123 }
2124 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
2125 }
2126 return prev;
2127 }
2128
2129 target_ulong helper_evp(CPUMIPSState *env)
2130 {
2131 CPUState *other_cs = first_cpu;
2132 target_ulong prev = env->CP0_VPControl;
2133
2134 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
2135 CPU_FOREACH(other_cs) {
2136 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2137 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
2138 /* If the VP is WFI, don't disturb its sleep.
2139 * Otherwise, wake it up. */
2140 mips_vpe_wake(other_cpu);
2141 }
2142 }
2143 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
2144 }
2145 return prev;
2146 }
2147 #endif /* !CONFIG_USER_ONLY */
2148
2149 #ifndef CONFIG_USER_ONLY
2150 /* TLB management */
2151 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
2152 {
2153 /* Discard entries from env->tlb[first] onwards. */
2154 while (env->tlb->tlb_in_use > first) {
2155 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
2156 }
2157 }
2158
2159 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
2160 {
2161 #if defined(TARGET_MIPS64)
2162 return extract64(entrylo, 6, 54);
2163 #else
2164 return extract64(entrylo, 6, 24) | /* PFN */
2165 (extract64(entrylo, 32, 32) << 24); /* PFNX */
2166 #endif
2167 }
2168
2169 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
2170 {
2171 r4k_tlb_t *tlb;
2172 uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
2173
2174 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
2175 tlb = &env->tlb->mmu.r4k.tlb[idx];
2176 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
2177 tlb->EHINV = 1;
2178 return;
2179 }
2180 tlb->EHINV = 0;
2181 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2182 #if defined(TARGET_MIPS64)
2183 tlb->VPN &= env->SEGMask;
2184 #endif
2185 tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2186 tlb->PageMask = env->CP0_PageMask;
2187 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2188 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
2189 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
2190 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
2191 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
2192 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
2193 tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;
2194 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
2195 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
2196 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
2197 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
2198 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
2199 tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;
2200 }
2201
2202 void r4k_helper_tlbinv(CPUMIPSState *env)
2203 {
2204 int idx;
2205 r4k_tlb_t *tlb;
2206 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2207
2208 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2209 tlb = &env->tlb->mmu.r4k.tlb[idx];
2210 if (!tlb->G && tlb->ASID == ASID) {
2211 tlb->EHINV = 1;
2212 }
2213 }
2214 cpu_mips_tlb_flush(env);
2215 }
2216
2217 void r4k_helper_tlbinvf(CPUMIPSState *env)
2218 {
2219 int idx;
2220
2221 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2222 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
2223 }
2224 cpu_mips_tlb_flush(env);
2225 }
2226
2227 void r4k_helper_tlbwi(CPUMIPSState *env)
2228 {
2229 r4k_tlb_t *tlb;
2230 int idx;
2231 target_ulong VPN;
2232 uint16_t ASID;
2233 bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1;
2234
2235 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2236 tlb = &env->tlb->mmu.r4k.tlb[idx];
2237 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2238 #if defined(TARGET_MIPS64)
2239 VPN &= env->SEGMask;
2240 #endif
2241 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2242 EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0;
2243 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2244 V0 = (env->CP0_EntryLo0 & 2) != 0;
2245 D0 = (env->CP0_EntryLo0 & 4) != 0;
2246 XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1;
2247 RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1;
2248 V1 = (env->CP0_EntryLo1 & 2) != 0;
2249 D1 = (env->CP0_EntryLo1 & 4) != 0;
2250 XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1;
2251 RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1;
2252
2253 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2254 permissions on the current entry. */
2255 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
2256 (!tlb->EHINV && EHINV) ||
2257 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
2258 (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) ||
2259 (tlb->V1 && !V1) || (tlb->D1 && !D1) ||
2260 (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) {
2261 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2262 }
2263
2264 r4k_invalidate_tlb(env, idx, 0);
2265 r4k_fill_tlb(env, idx);
2266 }
2267
2268 void r4k_helper_tlbwr(CPUMIPSState *env)
2269 {
2270 int r = cpu_mips_get_random(env);
2271
2272 r4k_invalidate_tlb(env, r, 1);
2273 r4k_fill_tlb(env, r);
2274 }
2275
2276 void r4k_helper_tlbp(CPUMIPSState *env)
2277 {
2278 r4k_tlb_t *tlb;
2279 target_ulong mask;
2280 target_ulong tag;
2281 target_ulong VPN;
2282 uint16_t ASID;
2283 int i;
2284
2285 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2286 for (i = 0; i < env->tlb->nb_tlb; i++) {
2287 tlb = &env->tlb->mmu.r4k.tlb[i];
2288 /* 1k pages are not supported. */
2289 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2290 tag = env->CP0_EntryHi & ~mask;
2291 VPN = tlb->VPN & ~mask;
2292 #if defined(TARGET_MIPS64)
2293 tag &= env->SEGMask;
2294 #endif
2295 /* Check ASID, virtual page number & size */
2296 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2297 /* TLB match */
2298 env->CP0_Index = i;
2299 break;
2300 }
2301 }
2302 if (i == env->tlb->nb_tlb) {
2303 /* No match. Discard any shadow entries, if any of them match. */
2304 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2305 tlb = &env->tlb->mmu.r4k.tlb[i];
2306 /* 1k pages are not supported. */
2307 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2308 tag = env->CP0_EntryHi & ~mask;
2309 VPN = tlb->VPN & ~mask;
2310 #if defined(TARGET_MIPS64)
2311 tag &= env->SEGMask;
2312 #endif
2313 /* Check ASID, virtual page number & size */
2314 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2315 r4k_mips_tlb_flush_extra (env, i);
2316 break;
2317 }
2318 }
2319
2320 env->CP0_Index |= 0x80000000;
2321 }
2322 }
2323
2324 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2325 {
2326 #if defined(TARGET_MIPS64)
2327 return tlb_pfn << 6;
2328 #else
2329 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2330 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2331 #endif
2332 }
2333
2334 void r4k_helper_tlbr(CPUMIPSState *env)
2335 {
2336 r4k_tlb_t *tlb;
2337 uint16_t ASID;
2338 int idx;
2339
2340 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2341 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2342 tlb = &env->tlb->mmu.r4k.tlb[idx];
2343
2344 /* If this will change the current ASID, flush qemu's TLB. */
2345 if (ASID != tlb->ASID)
2346 cpu_mips_tlb_flush(env);
2347
2348 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2349
2350 if (tlb->EHINV) {
2351 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2352 env->CP0_PageMask = 0;
2353 env->CP0_EntryLo0 = 0;
2354 env->CP0_EntryLo1 = 0;
2355 } else {
2356 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2357 env->CP0_PageMask = tlb->PageMask;
2358 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2359 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2360 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2361 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2362 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2363 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2364 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2365 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2366 }
2367 }
2368
2369 void helper_tlbwi(CPUMIPSState *env)
2370 {
2371 env->tlb->helper_tlbwi(env);
2372 }
2373
2374 void helper_tlbwr(CPUMIPSState *env)
2375 {
2376 env->tlb->helper_tlbwr(env);
2377 }
2378
2379 void helper_tlbp(CPUMIPSState *env)
2380 {
2381 env->tlb->helper_tlbp(env);
2382 }
2383
2384 void helper_tlbr(CPUMIPSState *env)
2385 {
2386 env->tlb->helper_tlbr(env);
2387 }
2388
2389 void helper_tlbinv(CPUMIPSState *env)
2390 {
2391 env->tlb->helper_tlbinv(env);
2392 }
2393
2394 void helper_tlbinvf(CPUMIPSState *env)
2395 {
2396 env->tlb->helper_tlbinvf(env);
2397 }
2398
2399 /* Specials */
2400 target_ulong helper_di(CPUMIPSState *env)
2401 {
2402 target_ulong t0 = env->CP0_Status;
2403
2404 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2405 return t0;
2406 }
2407
2408 target_ulong helper_ei(CPUMIPSState *env)
2409 {
2410 target_ulong t0 = env->CP0_Status;
2411
2412 env->CP0_Status = t0 | (1 << CP0St_IE);
2413 return t0;
2414 }
2415
2416 static void debug_pre_eret(CPUMIPSState *env)
2417 {
2418 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2419 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2420 env->active_tc.PC, env->CP0_EPC);
2421 if (env->CP0_Status & (1 << CP0St_ERL))
2422 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2423 if (env->hflags & MIPS_HFLAG_DM)
2424 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2425 qemu_log("\n");
2426 }
2427 }
2428
2429 static void debug_post_eret(CPUMIPSState *env)
2430 {
2431 MIPSCPU *cpu = mips_env_get_cpu(env);
2432
2433 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2434 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2435 env->active_tc.PC, env->CP0_EPC);
2436 if (env->CP0_Status & (1 << CP0St_ERL))
2437 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2438 if (env->hflags & MIPS_HFLAG_DM)
2439 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2440 switch (cpu_mmu_index(env, false)) {
2441 case 3:
2442 qemu_log(", ERL\n");
2443 break;
2444 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2445 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2446 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2447 default:
2448 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2449 break;
2450 }
2451 }
2452 }
2453
2454 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2455 {
2456 env->active_tc.PC = error_pc & ~(target_ulong)1;
2457 if (error_pc & 1) {
2458 env->hflags |= MIPS_HFLAG_M16;
2459 } else {
2460 env->hflags &= ~(MIPS_HFLAG_M16);
2461 }
2462 }
2463
2464 static inline void exception_return(CPUMIPSState *env)
2465 {
2466 debug_pre_eret(env);
2467 if (env->CP0_Status & (1 << CP0St_ERL)) {
2468 set_pc(env, env->CP0_ErrorEPC);
2469 env->CP0_Status &= ~(1 << CP0St_ERL);
2470 } else {
2471 set_pc(env, env->CP0_EPC);
2472 env->CP0_Status &= ~(1 << CP0St_EXL);
2473 }
2474 compute_hflags(env);
2475 debug_post_eret(env);
2476 }
2477
2478 void helper_eret(CPUMIPSState *env)
2479 {
2480 exception_return(env);
2481 env->lladdr = 1;
2482 }
2483
2484 void helper_eretnc(CPUMIPSState *env)
2485 {
2486 exception_return(env);
2487 }
2488
2489 void helper_deret(CPUMIPSState *env)
2490 {
2491 debug_pre_eret(env);
2492
2493 env->hflags &= ~MIPS_HFLAG_DM;
2494 compute_hflags(env);
2495
2496 set_pc(env, env->CP0_DEPC);
2497
2498 debug_post_eret(env);
2499 }
2500 #endif /* !CONFIG_USER_ONLY */
2501
2502 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
2503 {
2504 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2505 return;
2506 }
2507 do_raise_exception(env, EXCP_RI, pc);
2508 }
2509
2510 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2511 {
2512 check_hwrena(env, 0, GETPC());
2513 return env->CP0_EBase & 0x3ff;
2514 }
2515
2516 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2517 {
2518 check_hwrena(env, 1, GETPC());
2519 return env->SYNCI_Step;
2520 }
2521
2522 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2523 {
2524 int32_t count;
2525 check_hwrena(env, 2, GETPC());
2526 #ifdef CONFIG_USER_ONLY
2527 count = env->CP0_Count;
2528 #else
2529 qemu_mutex_lock_iothread();
2530 count = (int32_t)cpu_mips_get_count(env);
2531 qemu_mutex_unlock_iothread();
2532 #endif
2533 return count;
2534 }
2535
2536 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2537 {
2538 check_hwrena(env, 3, GETPC());
2539 return env->CCRes;
2540 }
2541
2542 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2543 {
2544 check_hwrena(env, 4, GETPC());
2545 return env->CP0_Performance0;
2546 }
2547
2548 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2549 {
2550 check_hwrena(env, 5, GETPC());
2551 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2552 }
2553
2554 void helper_pmon(CPUMIPSState *env, int function)
2555 {
2556 function /= 2;
2557 switch (function) {
2558 case 2: /* TODO: char inbyte(int waitflag); */
2559 if (env->active_tc.gpr[4] == 0)
2560 env->active_tc.gpr[2] = -1;
2561 /* Fall through */
2562 case 11: /* TODO: char inbyte (void); */
2563 env->active_tc.gpr[2] = -1;
2564 break;
2565 case 3:
2566 case 12:
2567 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2568 break;
2569 case 17:
2570 break;
2571 case 158:
2572 {
2573 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2574 printf("%s", fmt);
2575 }
2576 break;
2577 }
2578 }
2579
2580 void helper_wait(CPUMIPSState *env)
2581 {
2582 CPUState *cs = CPU(mips_env_get_cpu(env));
2583
2584 cs->halted = 1;
2585 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2586 /* Last instruction in the block, PC was updated before
2587 - no need to recover PC and icount */
2588 raise_exception(env, EXCP_HLT);
2589 }
2590
2591 #if !defined(CONFIG_USER_ONLY)
2592
2593 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2594 MMUAccessType access_type,
2595 int mmu_idx, uintptr_t retaddr)
2596 {
2597 MIPSCPU *cpu = MIPS_CPU(cs);
2598 CPUMIPSState *env = &cpu->env;
2599 int error_code = 0;
2600 int excp;
2601
2602 if (!(env->hflags & MIPS_HFLAG_DM)) {
2603 env->CP0_BadVAddr = addr;
2604 }
2605
2606 if (access_type == MMU_DATA_STORE) {
2607 excp = EXCP_AdES;
2608 } else {
2609 excp = EXCP_AdEL;
2610 if (access_type == MMU_INST_FETCH) {
2611 error_code |= EXCP_INST_NOTAVAIL;
2612 }
2613 }
2614
2615 do_raise_exception_err(env, excp, error_code, retaddr);
2616 }
2617
2618 void tlb_fill(CPUState *cs, target_ulong addr, int size,
2619 MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
2620 {
2621 int ret;
2622
2623 ret = mips_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
2624 if (ret) {
2625 MIPSCPU *cpu = MIPS_CPU(cs);
2626 CPUMIPSState *env = &cpu->env;
2627
2628 do_raise_exception_err(env, cs->exception_index,
2629 env->error_code, retaddr);
2630 }
2631 }
2632
2633 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2634 bool is_write, bool is_exec, int unused,
2635 unsigned size)
2636 {
2637 MIPSCPU *cpu = MIPS_CPU(cs);
2638 CPUMIPSState *env = &cpu->env;
2639
2640 /*
2641 * Raising an exception with KVM enabled will crash because it won't be from
2642 * the main execution loop so the longjmp won't have a matching setjmp.
2643 * Until we can trigger a bus error exception through KVM lets just ignore
2644 * the access.
2645 */
2646 if (kvm_enabled()) {
2647 return;
2648 }
2649
2650 if (is_exec) {
2651 raise_exception(env, EXCP_IBE);
2652 } else {
2653 raise_exception(env, EXCP_DBE);
2654 }
2655 }
2656 #endif /* !CONFIG_USER_ONLY */
2657
2658 /* Complex FPU operations which may need stack space. */
2659
2660 #define FLOAT_TWO32 make_float32(1 << 30)
2661 #define FLOAT_TWO64 make_float64(1ULL << 62)
2662
2663 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2664 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2665
2666 /* convert MIPS rounding mode in FCR31 to IEEE library */
2667 unsigned int ieee_rm[] = {
2668 float_round_nearest_even,
2669 float_round_to_zero,
2670 float_round_up,
2671 float_round_down
2672 };
2673
2674 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2675 {
2676 target_ulong arg1 = 0;
2677
2678 switch (reg) {
2679 case 0:
2680 arg1 = (int32_t)env->active_fpu.fcr0;
2681 break;
2682 case 1:
2683 /* UFR Support - Read Status FR */
2684 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2685 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2686 arg1 = (int32_t)
2687 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2688 } else {
2689 do_raise_exception(env, EXCP_RI, GETPC());
2690 }
2691 }
2692 break;
2693 case 5:
2694 /* FRE Support - read Config5.FRE bit */
2695 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2696 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2697 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2698 } else {
2699 helper_raise_exception(env, EXCP_RI);
2700 }
2701 }
2702 break;
2703 case 25:
2704 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2705 break;
2706 case 26:
2707 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2708 break;
2709 case 28:
2710 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2711 break;
2712 default:
2713 arg1 = (int32_t)env->active_fpu.fcr31;
2714 break;
2715 }
2716
2717 return arg1;
2718 }
2719
2720 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2721 {
2722 switch (fs) {
2723 case 1:
2724 /* UFR Alias - Reset Status FR */
2725 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2726 return;
2727 }
2728 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2729 env->CP0_Status &= ~(1 << CP0St_FR);
2730 compute_hflags(env);
2731 } else {
2732 do_raise_exception(env, EXCP_RI, GETPC());
2733 }
2734 break;
2735 case 4:
2736 /* UNFR Alias - Set Status FR */
2737 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2738 return;
2739 }
2740 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2741 env->CP0_Status |= (1 << CP0St_FR);
2742 compute_hflags(env);
2743 } else {
2744 do_raise_exception(env, EXCP_RI, GETPC());
2745 }
2746 break;
2747 case 5:
2748 /* FRE Support - clear Config5.FRE bit */
2749 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2750 return;
2751 }
2752 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2753 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2754 compute_hflags(env);
2755 } else {
2756 helper_raise_exception(env, EXCP_RI);
2757 }
2758 break;
2759 case 6:
2760 /* FRE Support - set Config5.FRE bit */
2761 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2762 return;
2763 }
2764 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2765 env->CP0_Config5 |= (1 << CP0C5_FRE);
2766 compute_hflags(env);
2767 } else {
2768 helper_raise_exception(env, EXCP_RI);
2769 }
2770 break;
2771 case 25:
2772 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2773 return;
2774 }
2775 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2776 ((arg1 & 0x1) << 23);
2777 break;
2778 case 26:
2779 if (arg1 & 0x007c0000)
2780 return;
2781 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2782 break;
2783 case 28:
2784 if (arg1 & 0x007c0000)
2785 return;
2786 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2787 ((arg1 & 0x4) << 22);
2788 break;
2789 case 31:
2790 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
2791 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
2792 break;
2793 default:
2794 if (env->insn_flags & ISA_MIPS32R6) {
2795 do_raise_exception(env, EXCP_RI, GETPC());
2796 }
2797 return;
2798 }
2799 restore_fp_status(env);
2800 set_float_exception_flags(0, &env->active_fpu.fp_status);
2801 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2802 do_raise_exception(env, EXCP_FPE, GETPC());
2803 }
2804
2805 int ieee_ex_to_mips(int xcpt)
2806 {
2807 int ret = 0;
2808 if (xcpt) {
2809 if (xcpt & float_flag_invalid) {
2810 ret |= FP_INVALID;
2811 }
2812 if (xcpt & float_flag_overflow) {
2813 ret |= FP_OVERFLOW;
2814 }
2815 if (xcpt & float_flag_underflow) {
2816 ret |= FP_UNDERFLOW;
2817 }
2818 if (xcpt & float_flag_divbyzero) {
2819 ret |= FP_DIV0;
2820 }
2821 if (xcpt & float_flag_inexact) {
2822 ret |= FP_INEXACT;
2823 }
2824 }
2825 return ret;
2826 }
2827
2828 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2829 {
2830 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2831
2832 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2833
2834 if (tmp) {
2835 set_float_exception_flags(0, &env->active_fpu.fp_status);
2836
2837 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2838 do_raise_exception(env, EXCP_FPE, pc);
2839 } else {
2840 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2841 }
2842 }
2843 }
2844
2845 /* Float support.
2846 Single precition routines have a "s" suffix, double precision a
2847 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2848 paired single lower "pl", paired single upper "pu". */
2849
2850 /* unary operations, modifying fp status */
2851 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2852 {
2853 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2854 update_fcr31(env, GETPC());
2855 return fdt0;
2856 }
2857
2858 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2859 {
2860 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2861 update_fcr31(env, GETPC());
2862 return fst0;
2863 }
2864
2865 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2866 {
2867 uint64_t fdt2;
2868
2869 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2870 update_fcr31(env, GETPC());
2871 return fdt2;
2872 }
2873
2874 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2875 {
2876 uint64_t fdt2;
2877
2878 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2879 update_fcr31(env, GETPC());
2880 return fdt2;
2881 }
2882
2883 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2884 {
2885 uint64_t fdt2;
2886
2887 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2888 update_fcr31(env, GETPC());
2889 return fdt2;
2890 }
2891
2892 uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
2893 {
2894 uint64_t dt2;
2895
2896 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2897 if (get_float_exception_flags(&env->active_fpu.fp_status)
2898 & (float_flag_invalid | float_flag_overflow)) {
2899 dt2 = FP_TO_INT64_OVERFLOW;
2900 }
2901 update_fcr31(env, GETPC());
2902 return dt2;
2903 }
2904
2905 uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
2906 {
2907 uint64_t dt2;
2908
2909 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2910 if (get_float_exception_flags(&env->active_fpu.fp_status)
2911 & (float_flag_invalid | float_flag_overflow)) {
2912 dt2 = FP_TO_INT64_OVERFLOW;
2913 }
2914 update_fcr31(env, GETPC());
2915 return dt2;
2916 }
2917
2918 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2919 {
2920 uint32_t fst2;
2921 uint32_t fsth2;
2922
2923 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2924 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2925 update_fcr31(env, GETPC());
2926 return ((uint64_t)fsth2 << 32) | fst2;
2927 }
2928
2929 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2930 {
2931 uint32_t wt2;
2932 uint32_t wth2;
2933 int excp, excph;
2934
2935 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2936 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2937 if (excp & (float_flag_overflow | float_flag_invalid)) {
2938 wt2 = FP_TO_INT32_OVERFLOW;
2939 }
2940
2941 set_float_exception_flags(0, &env->active_fpu.fp_status);
2942 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2943 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2944 if (excph & (float_flag_overflow | float_flag_invalid)) {
2945 wth2 = FP_TO_INT32_OVERFLOW;
2946 }
2947
2948 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2949 update_fcr31(env, GETPC());
2950
2951 return ((uint64_t)wth2 << 32) | wt2;
2952 }
2953
2954 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2955 {
2956 uint32_t fst2;
2957
2958 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2959 update_fcr31(env, GETPC());
2960 return fst2;
2961 }
2962
2963 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2964 {
2965 uint32_t fst2;
2966
2967 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2968 update_fcr31(env, GETPC());
2969 return fst2;
2970 }
2971
2972 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2973 {
2974 uint32_t fst2;
2975
2976 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2977 update_fcr31(env, GETPC());
2978 return fst2;
2979 }
2980
2981 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2982 {
2983 uint32_t wt2;
2984
2985 wt2 = wt0;
2986 update_fcr31(env, GETPC());
2987 return wt2;
2988 }
2989
2990 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2991 {
2992 uint32_t wt2;
2993
2994 wt2 = wth0;
2995 update_fcr31(env, GETPC());
2996 return wt2;
2997 }
2998
2999 uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
3000 {
3001 uint32_t wt2;
3002
3003 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3004 if (get_float_exception_flags(&env->active_fpu.fp_status)
3005 & (float_flag_invalid | float_flag_overflow)) {
3006 wt2 = FP_TO_INT32_OVERFLOW;
3007 }
3008 update_fcr31(env, GETPC());
3009 return wt2;
3010 }
3011
3012 uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
3013 {
3014 uint32_t wt2;
3015
3016 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3017 if (get_float_exception_flags(&env->active_fpu.fp_status)
3018 & (float_flag_invalid | float_flag_overflow)) {
3019 wt2 = FP_TO_INT32_OVERFLOW;
3020 }
3021 update_fcr31(env, GETPC());
3022 return wt2;
3023 }
3024
3025 uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
3026 {
3027 uint64_t dt2;
3028
3029 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3030 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3031 restore_rounding_mode(env);
3032 if (get_float_exception_flags(&env->active_fpu.fp_status)
3033 & (float_flag_invalid | float_flag_overflow)) {
3034 dt2 = FP_TO_INT64_OVERFLOW;
3035 }
3036 update_fcr31(env, GETPC());
3037 return dt2;
3038 }
3039
3040 uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
3041 {
3042 uint64_t dt2;
3043
3044 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3045 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3046 restore_rounding_mode(env);
3047 if (get_float_exception_flags(&env->active_fpu.fp_status)
3048 & (float_flag_invalid | float_flag_overflow)) {
3049 dt2 = FP_TO_INT64_OVERFLOW;
3050 }
3051 update_fcr31(env, GETPC());
3052 return dt2;
3053 }
3054
3055 uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
3056 {
3057 uint32_t wt2;
3058
3059 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3060 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3061 restore_rounding_mode(env);
3062 if (get_float_exception_flags(&env->active_fpu.fp_status)
3063 & (float_flag_invalid | float_flag_overflow)) {
3064 wt2 = FP_TO_INT32_OVERFLOW;
3065 }
3066 update_fcr31(env, GETPC());
3067 return wt2;
3068 }
3069
3070 uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
3071 {
3072 uint32_t wt2;
3073
3074 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3075 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3076 restore_rounding_mode(env);
3077 if (get_float_exception_flags(&env->active_fpu.fp_status)
3078 & (float_flag_invalid | float_flag_overflow)) {
3079 wt2 = FP_TO_INT32_OVERFLOW;
3080 }
3081 update_fcr31(env, GETPC());
3082 return wt2;
3083 }
3084
3085 uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
3086 {
3087 uint64_t dt2;
3088
3089 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3090 if (get_float_exception_flags(&env->active_fpu.fp_status)
3091 & (float_flag_invalid | float_flag_overflow)) {
3092 dt2 = FP_TO_INT64_OVERFLOW;
3093 }
3094 update_fcr31(env, GETPC());
3095 return dt2;
3096 }
3097
3098 uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
3099 {
3100 uint64_t dt2;
3101
3102 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3103 if (get_float_exception_flags(&env->active_fpu.fp_status)
3104 & (float_flag_invalid | float_flag_overflow)) {
3105 dt2 = FP_TO_INT64_OVERFLOW;
3106 }
3107 update_fcr31(env, GETPC());
3108 return dt2;
3109 }
3110
3111 uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
3112 {
3113 uint32_t wt2;
3114
3115 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3116 if (get_float_exception_flags(&env->active_fpu.fp_status)
3117 & (float_flag_invalid | float_flag_overflow)) {
3118 wt2 = FP_TO_INT32_OVERFLOW;
3119 }
3120 update_fcr31(env, GETPC());
3121 return wt2;
3122 }
3123
3124 uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
3125 {
3126 uint32_t wt2;
3127
3128 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3129 if (get_float_exception_flags(&env->active_fpu.fp_status)
3130 & (float_flag_invalid | float_flag_overflow)) {
3131 wt2 = FP_TO_INT32_OVERFLOW;
3132 }
3133 update_fcr31(env, GETPC());
3134 return wt2;
3135 }
3136
3137 uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
3138 {
3139 uint64_t dt2;
3140
3141 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3142 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3143 restore_rounding_mode(env);
3144 if (get_float_exception_flags(&env->active_fpu.fp_status)
3145 & (float_flag_invalid | float_flag_overflow)) {
3146 dt2 = FP_TO_INT64_OVERFLOW;
3147 }
3148 update_fcr31(env, GETPC());
3149 return dt2;
3150 }
3151
3152 uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
3153 {
3154 uint64_t dt2;
3155
3156 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3157 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3158 restore_rounding_mode(env);
3159 if (get_float_exception_flags(&env->active_fpu.fp_status)
3160 & (float_flag_invalid | float_flag_overflow)) {
3161 dt2 = FP_TO_INT64_OVERFLOW;
3162 }
3163 update_fcr31(env, GETPC());
3164 return dt2;
3165 }
3166
3167 uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
3168 {
3169 uint32_t wt2;
3170
3171 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3172 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3173 restore_rounding_mode(env);
3174 if (get_float_exception_flags(&env->active_fpu.fp_status)
3175 & (float_flag_invalid | float_flag_overflow)) {
3176 wt2 = FP_TO_INT32_OVERFLOW;
3177 }
3178 update_fcr31(env, GETPC());
3179 return wt2;
3180 }
3181
3182 uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
3183 {
3184 uint32_t wt2;
3185
3186 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3187 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3188 restore_rounding_mode(env);
3189 if (get_float_exception_flags(&env->active_fpu.fp_status)
3190 & (float_flag_invalid | float_flag_overflow)) {
3191 wt2 = FP_TO_INT32_OVERFLOW;
3192 }
3193 update_fcr31(env, GETPC());
3194 return wt2;
3195 }
3196
3197 uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
3198 {
3199 uint64_t dt2;
3200
3201 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3202 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3203 restore_rounding_mode(env);
3204 if (get_float_exception_flags(&env->active_fpu.fp_status)
3205 & (float_flag_invalid | float_flag_overflow)) {
3206 dt2 = FP_TO_INT64_OVERFLOW;
3207 }
3208 update_fcr31(env, GETPC());
3209 return dt2;
3210 }
3211
3212 uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
3213 {
3214 uint64_t dt2;
3215
3216 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3217 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3218 restore_rounding_mode(env);
3219 if (get_float_exception_flags(&env->active_fpu.fp_status)
3220 & (float_flag_invalid | float_flag_overflow)) {
3221 dt2 = FP_TO_INT64_OVERFLOW;
3222 }
3223 update_fcr31(env, GETPC());
3224 return dt2;
3225 }
3226
3227 uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
3228 {
3229 uint32_t wt2;
3230
3231 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3232 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3233 restore_rounding_mode(env);
3234 if (get_float_exception_flags(&env->active_fpu.fp_status)
3235 & (float_flag_invalid | float_flag_overflow)) {
3236 wt2 = FP_TO_INT32_OVERFLOW;
3237 }
3238 update_fcr31(env, GETPC());
3239 return wt2;
3240 }
3241
3242 uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
3243 {
3244 uint32_t wt2;
3245
3246 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3247 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3248 restore_rounding_mode(env);
3249 if (get_float_exception_flags(&env->active_fpu.fp_status)
3250 & (float_flag_invalid | float_flag_overflow)) {
3251 wt2 = FP_TO_INT32_OVERFLOW;
3252 }
3253 update_fcr31(env, GETPC());
3254 return wt2;
3255 }
3256
3257 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3258 {
3259 uint64_t dt2;
3260
3261 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3262 if (get_float_exception_flags(&env->active_fpu.fp_status)
3263 & float_flag_invalid) {
3264 if (float64_is_any_nan(fdt0)) {
3265 dt2 = 0;
3266 }
3267 }
3268 update_fcr31(env, GETPC());
3269 return dt2;
3270 }
3271
3272 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3273 {
3274 uint64_t dt2;
3275
3276 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3277 if (get_float_exception_flags(&env->active_fpu.fp_status)
3278 & float_flag_invalid) {
3279 if (float32_is_any_nan(fst0)) {
3280 dt2 = 0;
3281 }
3282 }
3283 update_fcr31(env, GETPC());
3284 return dt2;
3285 }
3286
3287 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3288 {
3289 uint32_t wt2;
3290
3291 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3292 if (get_float_exception_flags(&env->active_fpu.fp_status)
3293 & float_flag_invalid) {
3294 if (float64_is_any_nan(fdt0)) {
3295 wt2 = 0;
3296 }
3297 }
3298 update_fcr31(env, GETPC());
3299 return wt2;
3300 }
3301
3302 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3303 {
3304 uint32_t wt2;
3305
3306 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3307 if (get_float_exception_flags(&env->active_fpu.fp_status)
3308 & float_flag_invalid) {
3309 if (float32_is_any_nan(fst0)) {
3310 wt2 = 0;
3311 }
3312 }
3313 update_fcr31(env, GETPC());
3314 return wt2;
3315 }
3316
3317 uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3318 {
3319 uint64_t dt2;
3320
3321 set_float_rounding_mode(float_round_nearest_even,
3322 &env->active_fpu.fp_status);
3323 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3324 restore_rounding_mode(env);
3325 if (get_float_exception_flags(&env->active_fpu.fp_status)
3326 & float_flag_invalid) {
3327 if (float64_is_any_nan(fdt0)) {
3328 dt2 = 0;
3329 }
3330 }
3331 update_fcr31(env, GETPC());
3332 return dt2;
3333 }
3334
3335 uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3336 {
3337 uint64_t dt2;
3338
3339 set_float_rounding_mode(float_round_nearest_even,
3340 &env->active_fpu.fp_status);
3341 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3342 restore_rounding_mode(env);
3343 if (get_float_exception_flags(&env->active_fpu.fp_status)
3344 & float_flag_invalid) {
3345 if (float32_is_any_nan(fst0)) {
3346 dt2 = 0;
3347 }
3348 }
3349 update_fcr31(env, GETPC());
3350 return dt2;
3351 }
3352
3353 uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3354 {
3355 uint32_t wt2;
3356
3357 set_float_rounding_mode(float_round_nearest_even,
3358 &env->active_fpu.fp_status);
3359 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3360 restore_rounding_mode(env);
3361 if (get_float_exception_flags(&env->active_fpu.fp_status)
3362 & float_flag_invalid) {
3363 if (float64_is_any_nan(fdt0)) {
3364 wt2 = 0;
3365 }
3366 }
3367 update_fcr31(env, GETPC());
3368 return wt2;
3369 }
3370
3371 uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3372 {
3373 uint32_t wt2;
3374
3375 set_float_rounding_mode(float_round_nearest_even,
3376 &env->active_fpu.fp_status);
3377 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3378 restore_rounding_mode(env);
3379 if (get_float_exception_flags(&env->active_fpu.fp_status)
3380 & float_flag_invalid) {
3381 if (float32_is_any_nan(fst0)) {
3382 wt2 = 0;
3383 }
3384 }
3385 update_fcr31(env, GETPC());
3386 return wt2;
3387 }
3388
3389 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3390 {
3391 uint64_t dt2;
3392
3393 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3394 if (get_float_exception_flags(&env->active_fpu.fp_status)
3395 & float_flag_invalid) {
3396 if (float64_is_any_nan(fdt0)) {
3397 dt2 = 0;
3398 }
3399 }
3400 update_fcr31(env, GETPC());
3401 return dt2;
3402 }
3403
3404 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3405 {
3406 uint64_t dt2;
3407
3408 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3409 if (get_float_exception_flags(&env->active_fpu.fp_status)
3410 & float_flag_invalid) {
3411 if (float32_is_any_nan(fst0)) {
3412 dt2 = 0;
3413 }
3414 }
3415 update_fcr31(env, GETPC());
3416 return dt2;
3417 }
3418
3419 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3420 {
3421 uint32_t wt2;
3422
3423 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3424 if (get_float_exception_flags(&env->active_fpu.fp_status)
3425 & float_flag_invalid) {
3426 if (float64_is_any_nan(fdt0)) {
3427 wt2 = 0;
3428 }
3429 }
3430 update_fcr31(env, GETPC());
3431 return wt2;
3432 }
3433
3434 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3435 {
3436 uint32_t wt2;
3437
3438 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3439 if (get_float_exception_flags(&env->active_fpu.fp_status)
3440 & float_flag_invalid) {
3441 if (float32_is_any_nan(fst0)) {
3442 wt2 = 0;
3443 }
3444 }
3445 update_fcr31(env, GETPC());
3446 return wt2;
3447 }
3448
3449 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3450 {
3451 uint64_t dt2;
3452
3453 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3454 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3455 restore_rounding_mode(env);
3456 if (get_float_exception_flags(&env->active_fpu.fp_status)
3457 & float_flag_invalid) {
3458 if (float64_is_any_nan(fdt0)) {
3459 dt2 = 0;
3460 }
3461 }
3462 update_fcr31(env, GETPC());
3463 return dt2;
3464 }
3465
3466 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3467 {
3468 uint64_t dt2;
3469
3470 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3471 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3472 restore_rounding_mode(env);
3473 if (get_float_exception_flags(&env->active_fpu.fp_status)
3474 & float_flag_invalid) {
3475 if (float32_is_any_nan(fst0)) {
3476 dt2 = 0;
3477 }
3478 }
3479 update_fcr31(env, GETPC());
3480 return dt2;
3481 }
3482
3483 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3484 {
3485 uint32_t wt2;
3486
3487 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3488 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3489 restore_rounding_mode(env);
3490 if (get_float_exception_flags(&env->active_fpu.fp_status)
3491 & float_flag_invalid) {
3492 if (float64_is_any_nan(fdt0)) {
3493 wt2 = 0;
3494 }
3495 }
3496 update_fcr31(env, GETPC());
3497 return wt2;
3498 }
3499
3500 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3501 {
3502 uint32_t wt2;
3503
3504 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3505 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3506 restore_rounding_mode(env);
3507 if (get_float_exception_flags(&env->active_fpu.fp_status)
3508 & float_flag_invalid) {
3509 if (float32_is_any_nan(fst0)) {
3510 wt2 = 0;
3511 }
3512 }
3513 update_fcr31(env, GETPC());
3514 return wt2;
3515 }
3516
3517 uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3518 {
3519 uint64_t dt2;
3520
3521 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3522 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3523 restore_rounding_mode(env);
3524 if (get_float_exception_flags(&env->active_fpu.fp_status)
3525 & float_flag_invalid) {
3526 if (float64_is_any_nan(fdt0)) {
3527 dt2 = 0;
3528 }
3529 }
3530 update_fcr31(env, GETPC());
3531 return dt2;
3532 }
3533
3534 uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3535 {
3536 uint64_t dt2;
3537
3538 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3539 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3540 restore_rounding_mode(env);
3541 if (get_float_exception_flags(&env->active_fpu.fp_status)
3542 & float_flag_invalid) {
3543 if (float32_is_any_nan(fst0)) {
3544 dt2 = 0;
3545 }
3546 }
3547 update_fcr31(env, GETPC());
3548 return dt2;
3549 }
3550
3551 uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3552 {
3553 uint32_t wt2;
3554
3555 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3556 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3557 restore_rounding_mode(env);
3558 if (get_float_exception_flags(&env->active_fpu.fp_status)
3559 & float_flag_invalid) {
3560 if (float64_is_any_nan(fdt0)) {
3561 wt2 = 0;
3562 }
3563 }
3564 update_fcr31(env, GETPC());
3565 return wt2;
3566 }
3567
3568 uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3569 {
3570 uint32_t wt2;
3571
3572 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3573 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3574 restore_rounding_mode(env);
3575 if (get_float_exception_flags(&env->active_fpu.fp_status)
3576 & float_flag_invalid) {
3577 if (float32_is_any_nan(fst0)) {
3578 wt2 = 0;
3579 }
3580 }
3581 update_fcr31(env, GETPC());
3582 return wt2;
3583 }
3584
3585 /* unary operations, not modifying fp status */
3586 #define FLOAT_UNOP(name) \
3587 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3588 { \
3589 return float64_ ## name(fdt0); \
3590 } \
3591 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3592 { \
3593 return float32_ ## name(fst0); \
3594 } \
3595 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3596 { \
3597 uint32_t wt0; \
3598 uint32_t wth0; \
3599 \
3600 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3601 wth0 = float32_ ## name(fdt0 >> 32); \
3602 return ((uint64_t)wth0 << 32) | wt0; \
3603 }
3604 FLOAT_UNOP(abs)
3605 FLOAT_UNOP(chs)
3606 #undef FLOAT_UNOP
3607
3608 /* MIPS specific unary operations */
3609 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3610 {
3611 uint64_t fdt2;
3612
3613 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3614 update_fcr31(env, GETPC());
3615 return fdt2;
3616 }
3617
3618 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3619 {
3620 uint32_t fst2;
3621
3622 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3623 update_fcr31(env, GETPC());
3624 return fst2;
3625 }
3626
3627 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3628 {
3629 uint64_t fdt2;
3630
3631 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3632 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3633 update_fcr31(env, GETPC());
3634 return fdt2;
3635 }
3636
3637 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3638 {
3639 uint32_t fst2;
3640
3641 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3642 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3643 update_fcr31(env, GETPC());
3644 return fst2;
3645 }
3646
3647 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3648 {
3649 uint64_t fdt2;
3650
3651 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3652 update_fcr31(env, GETPC());
3653 return fdt2;
3654 }
3655
3656 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3657 {
3658 uint32_t fst2;
3659
3660 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3661 update_fcr31(env, GETPC());
3662 return fst2;
3663 }
3664
3665 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3666 {
3667 uint32_t fst2;
3668 uint32_t fsth2;
3669
3670 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3671 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3672 update_fcr31(env, GETPC());
3673 return ((uint64_t)fsth2 << 32) | fst2;
3674 }
3675
3676 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3677 {
3678 uint64_t fdt2;
3679
3680 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3681 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3682 update_fcr31(env, GETPC());
3683 return fdt2;
3684 }
3685
3686 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3687 {
3688 uint32_t fst2;
3689
3690 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3691 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3692 update_fcr31(env, GETPC());
3693 return fst2;
3694 }
3695
3696 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3697 {
3698 uint32_t fst2;
3699 uint32_t fsth2;
3700
3701 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3702 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3703 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3704 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3705 update_fcr31(env, GETPC());
3706 return ((uint64_t)fsth2 << 32) | fst2;
3707 }
3708
3709 #define FLOAT_RINT(name, bits) \
3710 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3711 uint ## bits ## _t fs) \
3712 { \
3713 uint ## bits ## _t fdret; \
3714 \
3715 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3716 update_fcr31(env, GETPC()); \
3717 return fdret; \
3718 }
3719
3720 FLOAT_RINT(rint_s, 32)
3721 FLOAT_RINT(rint_d, 64)
3722 #undef FLOAT_RINT
3723
3724 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3725 #define FLOAT_CLASS_QUIET_NAN 0x002
3726 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3727 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3728 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3729 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3730 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3731 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3732 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3733 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3734
3735 #define FLOAT_CLASS(name, bits) \
3736 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3737 float_status *status) \
3738 { \
3739 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3740 return FLOAT_CLASS_SIGNALING_NAN; \
3741 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3742 return FLOAT_CLASS_QUIET_NAN; \
3743 } else if (float ## bits ## _is_neg(arg)) { \
3744 if (float ## bits ## _is_infinity(arg)) { \
3745 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3746 } else if (float ## bits ## _is_zero(arg)) { \
3747 return FLOAT_CLASS_NEGATIVE_ZERO; \
3748 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3749 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3750 } else { \
3751 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3752 } \
3753 } else { \
3754 if (float ## bits ## _is_infinity(arg)) { \
3755 return FLOAT_CLASS_POSITIVE_INFINITY; \
3756 } else if (float ## bits ## _is_zero(arg)) { \
3757 return FLOAT_CLASS_POSITIVE_ZERO; \
3758 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3759 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3760 } else { \
3761 return FLOAT_CLASS_POSITIVE_NORMAL; \
3762 } \
3763 } \
3764 } \
3765 \
3766 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3767 uint ## bits ## _t arg) \
3768 { \
3769 return float_ ## name(arg, &env->active_fpu.fp_status); \
3770 }
3771
3772 FLOAT_CLASS(class_s, 32)
3773 FLOAT_CLASS(class_d, 64)
3774 #undef FLOAT_CLASS
3775
3776 /* binary operations */
3777 #define FLOAT_BINOP(name) \
3778 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3779 uint64_t fdt0, uint64_t fdt1) \
3780 { \
3781 uint64_t dt2; \
3782 \
3783 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3784 update_fcr31(env, GETPC()); \
3785 return dt2; \
3786 } \
3787 \
3788 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3789 uint32_t fst0, uint32_t fst1) \
3790 { \
3791 uint32_t wt2; \
3792 \
3793 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3794 update_fcr31(env, GETPC()); \
3795 return wt2; \
3796 } \
3797 \
3798 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3799 uint64_t fdt0, \
3800 uint64_t fdt1) \
3801 { \
3802 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3803 uint32_t fsth0 = fdt0 >> 32; \
3804 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3805 uint32_t fsth1 = fdt1 >> 32; \
3806 uint32_t wt2; \
3807 uint32_t wth2; \
3808 \
3809 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3810 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3811 update_fcr31(env, GETPC()); \
3812 return ((uint64_t)wth2 << 32) | wt2; \
3813 }
3814
3815 FLOAT_BINOP(add)
3816 FLOAT_BINOP(sub)
3817 FLOAT_BINOP(mul)
3818 FLOAT_BINOP(div)
3819 #undef FLOAT_BINOP
3820
3821 /* MIPS specific binary operations */
3822 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3823 {
3824 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3825 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3826 update_fcr31(env, GETPC());
3827 return fdt2;
3828 }
3829
3830 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3831 {
3832 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3833 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3834 update_fcr31(env, GETPC());
3835 return fst2;
3836 }
3837
3838 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3839 {
3840 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3841 uint32_t fsth0 = fdt0 >> 32;
3842 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3843 uint32_t fsth2 = fdt2 >> 32;
3844
3845 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3846 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3847 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3848 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3849 update_fcr31(env, GETPC());
3850 return ((uint64_t)fsth2 << 32) | fst2;
3851 }
3852
3853 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3854 {
3855 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3856 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3857 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3858 update_fcr31(env, GETPC());
3859 return fdt2;
3860 }
3861
3862 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3863 {
3864 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3865 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3866 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3867 update_fcr31(env, GETPC());
3868 return fst2;
3869 }
3870
3871 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3872 {
3873 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3874 uint32_t fsth0 = fdt0 >> 32;
3875 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3876 uint32_t fsth2 = fdt2 >> 32;
3877
3878 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3879 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3880 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3881 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3882 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3883 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3884 update_fcr31(env, GETPC());
3885 return ((uint64_t)fsth2 << 32) | fst2;
3886 }
3887
3888 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3889 {
3890 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3891 uint32_t fsth0 = fdt0 >> 32;
3892 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3893 uint32_t fsth1 = fdt1 >> 32;
3894 uint32_t fst2;
3895 uint32_t fsth2;
3896
3897 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3898 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3899 update_fcr31(env, GETPC());
3900 return ((uint64_t)fsth2 << 32) | fst2;
3901 }
3902
3903 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3904 {
3905 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3906 uint32_t fsth0 = fdt0 >> 32;
3907 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3908 uint32_t fsth1 = fdt1 >> 32;
3909 uint32_t fst2;
3910 uint32_t fsth2;
3911
3912 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3913 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3914 update_fcr31(env, GETPC());
3915 return ((uint64_t)fsth2 << 32) | fst2;
3916 }
3917
3918 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3919 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3920 uint ## bits ## _t fs, \
3921 uint ## bits ## _t ft) \
3922 { \
3923 uint ## bits ## _t fdret; \
3924 \
3925 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3926 &env->active_fpu.fp_status); \
3927 update_fcr31(env, GETPC()); \
3928 return fdret; \
3929 }
3930
3931 FLOAT_MINMAX(max_s, 32, maxnum)
3932 FLOAT_MINMAX(max_d, 64, maxnum)
3933 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3934 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3935
3936 FLOAT_MINMAX(min_s, 32, minnum)
3937 FLOAT_MINMAX(min_d, 64, minnum)
3938 FLOAT_MINMAX(mina_s, 32, minnummag)
3939 FLOAT_MINMAX(mina_d, 64, minnummag)
3940 #undef FLOAT_MINMAX
3941
3942 /* ternary operations */
3943 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3944 { \
3945 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3946 if ((flags) & float_muladd_negate_c) { \
3947 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3948 } else { \
3949 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3950 } \
3951 if ((flags) & float_muladd_negate_result) { \
3952 a = prefix##_chs(a); \
3953 } \
3954 }
3955
3956 /* FMA based operations */
3957 #define FLOAT_FMA(name, type) \
3958 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3959 uint64_t fdt0, uint64_t fdt1, \
3960 uint64_t fdt2) \
3961 { \
3962 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3963 update_fcr31(env, GETPC()); \
3964 return fdt0; \
3965 } \
3966 \
3967 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3968 uint32_t fst0, uint32_t fst1, \
3969 uint32_t fst2) \
3970 { \
3971 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3972 update_fcr31(env, GETPC()); \
3973 return fst0; \
3974 } \
3975 \
3976 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3977 uint64_t fdt0, uint64_t fdt1, \
3978 uint64_t fdt2) \
3979 { \
3980 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3981 uint32_t fsth0 = fdt0 >> 32; \
3982 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3983 uint32_t fsth1 = fdt1 >> 32; \
3984 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3985 uint32_t fsth2 = fdt2 >> 32; \
3986 \
3987 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3988 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
3989 update_fcr31(env, GETPC()); \
3990 return ((uint64_t)fsth0 << 32) | fst0; \
3991 }
3992 FLOAT_FMA(madd, 0)
3993 FLOAT_FMA(msub, float_muladd_negate_c)
3994 FLOAT_FMA(nmadd, float_muladd_negate_result)
3995 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3996 #undef FLOAT_FMA
3997
3998 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
3999 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
4000 uint ## bits ## _t fs, \
4001 uint ## bits ## _t ft, \
4002 uint ## bits ## _t fd) \
4003 { \
4004 uint ## bits ## _t fdret; \
4005 \
4006 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
4007 &env->active_fpu.fp_status); \
4008 update_fcr31(env, GETPC()); \
4009 return fdret; \
4010 }
4011
4012 FLOAT_FMADDSUB(maddf_s, 32, 0)
4013 FLOAT_FMADDSUB(maddf_d, 64, 0)
4014 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
4015 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
4016 #undef FLOAT_FMADDSUB
4017
4018 /* compare operations */
4019 #define FOP_COND_D(op, cond) \
4020 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4021 uint64_t fdt1, int cc) \
4022 { \
4023 int c; \
4024 c = cond; \
4025 update_fcr31(env, GETPC()); \
4026 if (c) \
4027 SET_FP_COND(cc, env->active_fpu); \
4028 else \
4029 CLEAR_FP_COND(cc, env->active_fpu); \
4030 } \
4031 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4032 uint64_t fdt1, int cc) \
4033 { \
4034 int c; \
4035 fdt0 = float64_abs(fdt0); \
4036 fdt1 = float64_abs(fdt1); \
4037 c = cond; \
4038 update_fcr31(env, GETPC()); \
4039 if (c) \
4040 SET_FP_COND(cc, env->active_fpu); \
4041 else \
4042 CLEAR_FP_COND(cc, env->active_fpu); \
4043 }
4044
4045 /* NOTE: the comma operator will make "cond" to eval to false,
4046 * but float64_unordered_quiet() is still called. */
4047 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4048 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
4049 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4050 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4051 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4052 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4053 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4054 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4055 /* NOTE: the comma operator will make "cond" to eval to false,
4056 * but float64_unordered() is still called. */
4057 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4058 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
4059 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
4060 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
4061 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
4062 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
4063 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
4064 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
4065
4066 #define FOP_COND_S(op, cond) \
4067 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4068 uint32_t fst1, int cc) \
4069 { \
4070 int c; \
4071 c = cond; \
4072 update_fcr31(env, GETPC()); \
4073 if (c) \
4074 SET_FP_COND(cc, env->active_fpu); \
4075 else \
4076 CLEAR_FP_COND(cc, env->active_fpu); \
4077 } \
4078 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4079 uint32_t fst1, int cc) \
4080 { \
4081 int c; \
4082 fst0 = float32_abs(fst0); \
4083 fst1 = float32_abs(fst1); \
4084 c = cond; \
4085 update_fcr31(env, GETPC()); \
4086 if (c) \
4087 SET_FP_COND(cc, env->active_fpu); \
4088 else \
4089 CLEAR_FP_COND(cc, env->active_fpu); \
4090 }
4091
4092 /* NOTE: the comma operator will make "cond" to eval to false,
4093 * but float32_unordered_quiet() is still called. */
4094 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4095 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
4096 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
4097 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
4098 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
4099 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
4100 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
4101 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
4102 /* NOTE: the comma operator will make "cond" to eval to false,
4103 * but float32_unordered() is still called. */
4104 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4105 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
4106 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
4107 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
4108 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
4109 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
4110 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
4111 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
4112
4113 #define FOP_COND_PS(op, condl, condh) \
4114 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4115 uint64_t fdt1, int cc) \
4116 { \
4117 uint32_t fst0, fsth0, fst1, fsth1; \
4118 int ch, cl; \
4119 fst0 = fdt0 & 0XFFFFFFFF; \
4120 fsth0 = fdt0 >> 32; \
4121 fst1 = fdt1 & 0XFFFFFFFF; \
4122 fsth1 = fdt1 >> 32; \
4123 cl = condl; \
4124 ch = condh; \
4125 update_fcr31(env, GETPC()); \
4126 if (cl) \
4127 SET_FP_COND(cc, env->active_fpu); \
4128 else \
4129 CLEAR_FP_COND(cc, env->active_fpu); \
4130 if (ch) \
4131 SET_FP_COND(cc + 1, env->active_fpu); \
4132 else \
4133 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4134 } \
4135 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4136 uint64_t fdt1, int cc) \
4137 { \
4138 uint32_t fst0, fsth0, fst1, fsth1; \
4139 int ch, cl; \
4140 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
4141 fsth0 = float32_abs(fdt0 >> 32); \
4142 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
4143 fsth1 = float32_abs(fdt1 >> 32); \
4144 cl = condl; \
4145 ch = condh; \
4146 update_fcr31(env, GETPC()); \
4147 if (cl) \
4148 SET_FP_COND(cc, env->active_fpu); \
4149 else \
4150 CLEAR_FP_COND(cc, env->active_fpu); \
4151 if (ch) \
4152 SET_FP_COND(cc + 1, env->active_fpu); \
4153 else \
4154 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4155 }
4156
4157 /* NOTE: the comma operator will make "cond" to eval to false,
4158 * but float32_unordered_quiet() is still called. */
4159 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
4160 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
4161 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
4162 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
4163 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
4164 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4165 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
4166 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4167 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
4168 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4169 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
4170 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4171 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
4172 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4173 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
4174 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4175 /* NOTE: the comma operator will make "cond" to eval to false,
4176 * but float32_unordered() is still called. */
4177 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
4178 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
4179 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
4180 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
4181 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
4182 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
4183 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
4184 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
4185 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
4186 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
4187 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
4188 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
4189 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
4190 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
4191 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
4192 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
4193
4194 /* R6 compare operations */
4195 #define FOP_CONDN_D(op, cond) \
4196 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
4197 uint64_t fdt1) \
4198 { \
4199 uint64_t c; \
4200 c = cond; \
4201 update_fcr31(env, GETPC()); \
4202 if (c) { \
4203 return -1; \
4204 } else { \
4205 return 0; \
4206 } \
4207 }
4208
4209 /* NOTE: the comma operator will make "cond" to eval to false,
4210 * but float64_unordered_quiet() is still called. */
4211 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4212 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
4213 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4214 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4215 || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4216 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4217 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4218 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4219 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4220 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4221 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4222 /* NOTE: the comma operator will make "cond" to eval to false,
4223 * but float64_unordered() is still called. */
4224 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4225 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
4226 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4227 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4228 || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4229 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4230 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4231 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4232 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4233 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4234 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4235 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4236 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4237 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4238 || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4239 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4240 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4241 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4242 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
4243 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4244 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4245 || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4246 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4247 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4248 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4249
4250 #define FOP_CONDN_S(op, cond) \
4251 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4252 uint32_t fst1) \
4253 { \
4254 uint64_t c; \
4255 c = cond; \
4256 update_fcr31(env, GETPC()); \
4257 if (c) { \
4258 return -1; \
4259 } else { \
4260 return 0; \
4261 } \
4262 }
4263
4264 /* NOTE: the comma operator will make "cond" to eval to false,
4265 * but float32_unordered_quiet() is still called. */
4266 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4267 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
4268 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4269 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4270 || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4271 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4272 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4273 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4274 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4275 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4276 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4277 /* NOTE: the comma operator will make "cond" to eval to false,
4278 * but float32_unordered() is still called. */
4279 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4280 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
4281 FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4282 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4283 || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4284 FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4285 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4286 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4287 FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4288 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4289 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4290 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
4291 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4292 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4293 || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4294 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4295 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4296 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4297 FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status)
4298 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4299 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4300 || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4301 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4302 FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4303 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4304
4305 /* MSA */
4306 /* Data format min and max values */
4307 #define DF_BITS(df) (1 << ((df) + 3))
4308
4309 /* Element-by-element access macros */
4310 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4311
4312 #if !defined(CONFIG_USER_ONLY)
4313 #define MEMOP_IDX(DF) \
4314 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4315 cpu_mmu_index(env, false));
4316 #else
4317 #define MEMOP_IDX(DF)
4318 #endif
4319
4320 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
4321 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4322 target_ulong addr) \
4323 { \
4324 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4325 wr_t wx; \
4326 int i; \
4327 MEMOP_IDX(DF) \
4328 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4329 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
4330 } \
4331 memcpy(pwd, &wx, sizeof(wr_t)); \
4332 }
4333
4334 #if !defined(CONFIG_USER_ONLY)
4335 MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETPC())
4336 MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETPC())
4337 MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETPC())
4338 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETPC())
4339 #else
4340 MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
4341 MSA_LD_DF(DF_HALF, h, cpu_lduw_data)
4342 MSA_LD_DF(DF_WORD, w, cpu_ldl_data)
4343 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
4344 #endif
4345
4346 #define MSA_PAGESPAN(x) \
4347 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4348
4349 static inline void ensure_writable_pages(CPUMIPSState *env,
4350 target_ulong addr,
4351 int mmu_idx,
4352 uintptr_t retaddr)
4353 {
4354 #if !defined(CONFIG_USER_ONLY)
4355 target_ulong page_addr;
4356 if (unlikely(MSA_PAGESPAN(addr))) {
4357 /* first page */
4358 probe_write(env, addr, 0, mmu_idx, retaddr);
4359 /* second page */
4360 page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4361 probe_write(env, page_addr, 0, mmu_idx, retaddr);
4362 }
4363 #endif
4364 }
4365
4366 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
4367 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4368 target_ulong addr) \
4369 { \
4370 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4371 int mmu_idx = cpu_mmu_index(env, false); \
4372 int i; \
4373 MEMOP_IDX(DF) \
4374 ensure_writable_pages(env, addr, mmu_idx, GETPC()); \
4375 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4376 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
4377 } \
4378 }
4379
4380 #if !defined(CONFIG_USER_ONLY)
4381 MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETPC())
4382 MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETPC())
4383 MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETPC())
4384 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETPC())
4385 #else
4386 MSA_ST_DF(DF_BYTE, b, cpu_stb_data)
4387 MSA_ST_DF(DF_HALF, h, cpu_stw_data)
4388 MSA_ST_DF(DF_WORD, w, cpu_stl_data)
4389 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
4390 #endif
4391
4392 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
4393 {
4394 #ifndef CONFIG_USER_ONLY
4395 target_ulong index = addr & 0x1fffffff;
4396 if (op == 9) {
4397 /* Index Store Tag */
4398 memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
4399 8, MEMTXATTRS_UNSPECIFIED);
4400 } else if (op == 5) {
4401 /* Index Load Tag */
4402 memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
4403 8, MEMTXATTRS_UNSPECIFIED);
4404 }
4405 #endif
4406 }
AR7 emulation for QEMU