2 * ColdFire UART emulation.
4 * Copyright (c) 2007 CodeSourcery.
6 * This code is licensed under the GPL
8 #include "qemu/osdep.h"
10 #include "hw/m68k/mcf.h"
11 #include "sysemu/char.h"
12 #include "exec/address-spaces.h"
13 #include "qapi/error.h"
33 /* UART Status Register bits. */
34 #define MCF_UART_RxRDY 0x01
35 #define MCF_UART_FFULL 0x02
36 #define MCF_UART_TxRDY 0x04
37 #define MCF_UART_TxEMP 0x08
38 #define MCF_UART_OE 0x10
39 #define MCF_UART_PE 0x20
40 #define MCF_UART_FE 0x40
41 #define MCF_UART_RB 0x80
43 /* Interrupt flags. */
44 #define MCF_UART_TxINT 0x01
45 #define MCF_UART_RxINT 0x02
46 #define MCF_UART_DBINT 0x04
47 #define MCF_UART_COSINT 0x80
50 #define MCF_UART_BC0 0x01
51 #define MCF_UART_BC1 0x02
52 #define MCF_UART_PT 0x04
53 #define MCF_UART_PM0 0x08
54 #define MCF_UART_PM1 0x10
55 #define MCF_UART_ERR 0x20
56 #define MCF_UART_RxIRQ 0x40
57 #define MCF_UART_RxRTS 0x80
59 static void mcf_uart_update(mcf_uart_state
*s
)
61 s
->isr
&= ~(MCF_UART_TxINT
| MCF_UART_RxINT
);
62 if (s
->sr
& MCF_UART_TxRDY
)
63 s
->isr
|= MCF_UART_TxINT
;
64 if ((s
->sr
& ((s
->mr
[0] & MCF_UART_RxIRQ
)
65 ? MCF_UART_FFULL
: MCF_UART_RxRDY
)) != 0)
66 s
->isr
|= MCF_UART_RxINT
;
68 qemu_set_irq(s
->irq
, (s
->isr
& s
->imr
) != 0);
71 uint64_t mcf_uart_read(void *opaque
, hwaddr addr
,
74 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
75 switch (addr
& 0x3f) {
77 return s
->mr
[s
->current_mr
];
90 for (i
= 0; i
< s
->fifo_len
; i
++)
91 s
->fifo
[i
] = s
->fifo
[i
+ 1];
92 s
->sr
&= ~MCF_UART_FFULL
;
94 s
->sr
&= ~MCF_UART_RxRDY
;
96 qemu_chr_fe_accept_input(&s
->chr
);
100 /* TODO: Implement IPCR. */
113 /* Update TxRDY flag and set data if present and enabled. */
114 static void mcf_uart_do_tx(mcf_uart_state
*s
)
116 if (s
->tx_enabled
&& (s
->sr
& MCF_UART_TxEMP
) == 0) {
117 /* XXX this blocks entire thread. Rewrite to use
118 * qemu_chr_fe_write and background I/O callbacks */
119 qemu_chr_fe_write_all(&s
->chr
, (unsigned char *)&s
->tb
, 1);
120 s
->sr
|= MCF_UART_TxEMP
;
123 s
->sr
|= MCF_UART_TxRDY
;
125 s
->sr
&= ~MCF_UART_TxRDY
;
129 static void mcf_do_command(mcf_uart_state
*s
, uint8_t cmd
)
132 switch ((cmd
>> 4) & 7) {
135 case 1: /* Reset mode register pointer. */
138 case 2: /* Reset receiver. */
141 s
->sr
&= ~(MCF_UART_RxRDY
| MCF_UART_FFULL
);
143 case 3: /* Reset transmitter. */
145 s
->sr
|= MCF_UART_TxEMP
;
146 s
->sr
&= ~MCF_UART_TxRDY
;
148 case 4: /* Reset error status. */
150 case 5: /* Reset break-change interrupt. */
151 s
->isr
&= ~MCF_UART_DBINT
;
153 case 6: /* Start break. */
154 case 7: /* Stop break. */
158 /* Transmitter command. */
159 switch ((cmd
>> 2) & 3) {
162 case 1: /* Enable. */
166 case 2: /* Disable. */
170 case 3: /* Reserved. */
171 fprintf(stderr
, "mcf_uart: Bad TX command\n");
175 /* Receiver command. */
179 case 1: /* Enable. */
185 case 3: /* Reserved. */
186 fprintf(stderr
, "mcf_uart: Bad RX command\n");
191 void mcf_uart_write(void *opaque
, hwaddr addr
,
192 uint64_t val
, unsigned size
)
194 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
195 switch (addr
& 0x3f) {
197 s
->mr
[s
->current_mr
] = val
;
201 /* CSR is ignored. */
203 case 0x08: /* Command Register. */
204 mcf_do_command(s
, val
);
206 case 0x0c: /* Transmit Buffer. */
207 s
->sr
&= ~MCF_UART_TxEMP
;
212 /* ACR is ignored. */
223 static void mcf_uart_reset(mcf_uart_state
*s
)
228 s
->sr
= MCF_UART_TxEMP
;
235 static void mcf_uart_push_byte(mcf_uart_state
*s
, uint8_t data
)
237 /* Break events overwrite the last byte if the fifo is full. */
238 if (s
->fifo_len
== 4)
241 s
->fifo
[s
->fifo_len
] = data
;
243 s
->sr
|= MCF_UART_RxRDY
;
244 if (s
->fifo_len
== 4)
245 s
->sr
|= MCF_UART_FFULL
;
250 static void mcf_uart_event(void *opaque
, int event
)
252 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
255 case CHR_EVENT_BREAK
:
256 s
->isr
|= MCF_UART_DBINT
;
257 mcf_uart_push_byte(s
, 0);
264 static int mcf_uart_can_receive(void *opaque
)
266 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
268 return s
->rx_enabled
&& (s
->sr
& MCF_UART_FFULL
) == 0;
271 static void mcf_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
273 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
275 mcf_uart_push_byte(s
, buf
[0]);
278 void *mcf_uart_init(qemu_irq irq
, CharDriverState
*chr
)
282 s
= g_malloc0(sizeof(mcf_uart_state
));
285 qemu_chr_fe_init(&s
->chr
, chr
, &error_abort
);
286 qemu_chr_fe_set_handlers(&s
->chr
, mcf_uart_can_receive
,
287 mcf_uart_receive
, mcf_uart_event
, s
, NULL
);
293 static const MemoryRegionOps mcf_uart_ops
= {
294 .read
= mcf_uart_read
,
295 .write
= mcf_uart_write
,
296 .endianness
= DEVICE_NATIVE_ENDIAN
,
299 void mcf_uart_mm_init(MemoryRegion
*sysmem
,
302 CharDriverState
*chr
)
306 s
= mcf_uart_init(irq
, chr
);
307 memory_region_init_io(&s
->iomem
, NULL
, &mcf_uart_ops
, s
, "uart", 0x40);
308 memory_region_add_subregion(sysmem
, base
, &s
->iomem
);