hw/misc/lm32_sys.c

   1 /*
   2  *  QEMU model of the LatticeMico32 system control block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /*
  21  * This model is mainly intended for testing purposes and doesn't fit to any
  22  * real hardware. On the one hand it provides a control register (R_CTRL) on
  23  * the other hand it supports the lm32 tests.
  24  *
  25  * A write to the control register causes a system shutdown.
  26  * Tests first write the pointer to a test name to the test name register
  27  * (R_TESTNAME) and then write a zero to the pass/fail register (R_PASSFAIL) if
  28  * the test is passed or any non-zero value to it if the test is failed.
  29  */
  30
  31 #include "hw/hw.h"
  32 #include "hw/sysbus.h"
  33 #include "trace.h"
  34 #include "qemu/log.h"
  35 #include "qemu/error-report.h"
  36 #include "sysemu/sysemu.h"
  37
  38 enum {
  39     R_CTRL = 0,
  40     R_PASSFAIL,
  41     R_TESTNAME,
  42     R_MAX
  43 };
  44
  45 #define MAX_TESTNAME_LEN 16
  46
  47 #define TYPE_LM32_SYS "lm32-sys"
  48 #define LM32_SYS(obj) OBJECT_CHECK(LM32SysState, (obj), TYPE_LM32_SYS)
  49
  50 struct LM32SysState {
  51     SysBusDevice parent_obj;
  52
  53     MemoryRegion iomem;
  54     uint32_t base;
  55     uint32_t regs[R_MAX];
  56     uint8_t testname[MAX_TESTNAME_LEN];
  57 };
  58 typedef struct LM32SysState LM32SysState;
  59
  60 static void copy_testname(LM32SysState *s)
  61 {
  62     cpu_physical_memory_read(s->regs[R_TESTNAME], s->testname,
  63             MAX_TESTNAME_LEN);
  64     s->testname[MAX_TESTNAME_LEN - 1] = '\0';
  65 }
  66
  67 static void sys_write(void *opaque, hwaddr addr,
  68                       uint64_t value, unsigned size)
  69 {
  70     LM32SysState *s = opaque;
  71     char *testname;
  72
  73     trace_lm32_sys_memory_write(addr, value);
  74
  75     addr >>= 2;
  76     switch (addr) {
  77     case R_CTRL:
  78         qemu_system_shutdown_request();
  79         break;
  80     case R_PASSFAIL:
  81         s->regs[addr] = value;
  82         testname = (char *)s->testname;
  83         qemu_log("TC  %-16s %s\n", testname, (value) ? "FAILED" : "OK");
  84         break;
  85     case R_TESTNAME:
  86         s->regs[addr] = value;
  87         copy_testname(s);
  88         break;
  89
  90     default:
  91         error_report("lm32_sys: write access to unknown register 0x"
  92                 TARGET_FMT_plx, addr << 2);
  93         break;
  94     }
  95 }
  96
  97 static bool sys_ops_accepts(void *opaque, hwaddr addr,
  98                             unsigned size, bool is_write)
  99 {
 100     return is_write && size == 4;
 101 }
 102
 103 static const MemoryRegionOps sys_ops = {
 104     .write = sys_write,
 105     .valid.accepts = sys_ops_accepts,
 106     .endianness = DEVICE_NATIVE_ENDIAN,
 107 };
 108
 109 static void sys_reset(DeviceState *d)
 110 {
 111     LM32SysState *s = LM32_SYS(d);
 112     int i;
 113
 114     for (i = 0; i < R_MAX; i++) {
 115         s->regs[i] = 0;
 116     }
 117     memset(s->testname, 0, MAX_TESTNAME_LEN);
 118 }
 119
 120 static int lm32_sys_init(SysBusDevice *dev)
 121 {
 122     LM32SysState *s = LM32_SYS(dev);
 123
 124     memory_region_init_io(&s->iomem, OBJECT(dev), &sys_ops , s,
 125                           "sys", R_MAX * 4);
 126     sysbus_init_mmio(dev, &s->iomem);
 127
 128     /* Note: This device is not created in the board initialization,
 129      * instead it has to be added with the -device parameter. Therefore,
 130      * the device maps itself. */
 131     sysbus_mmio_map(dev, 0, s->base);
 132
 133     return 0;
 134 }
 135
 136 static const VMStateDescription vmstate_lm32_sys = {
 137     .name = "lm32-sys",
 138     .version_id = 1,
 139     .minimum_version_id = 1,
 140     .minimum_version_id_old = 1,
 141     .fields      = (VMStateField[]) {
 142         VMSTATE_UINT32_ARRAY(regs, LM32SysState, R_MAX),
 143         VMSTATE_BUFFER(testname, LM32SysState),
 144         VMSTATE_END_OF_LIST()
 145     }
 146 };
 147
 148 static Property lm32_sys_properties[] = {
 149     DEFINE_PROP_UINT32("base", LM32SysState, base, 0xffff0000),
 150     DEFINE_PROP_END_OF_LIST(),
 151 };
 152
 153 static void lm32_sys_class_init(ObjectClass *klass, void *data)
 154 {
 155     DeviceClass *dc = DEVICE_CLASS(klass);
 156     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 157
 158     k->init = lm32_sys_init;
 159     dc->reset = sys_reset;
 160     dc->vmsd = &vmstate_lm32_sys;
 161     dc->props = lm32_sys_properties;
 162 }
 163
 164 static const TypeInfo lm32_sys_info = {
 165     .name          = TYPE_LM32_SYS,
 166     .parent        = TYPE_SYS_BUS_DEVICE,
 167     .instance_size = sizeof(LM32SysState),
 168     .class_init    = lm32_sys_class_init,
 169 };
 170
 171 static void lm32_sys_register_types(void)
 172 {
 173     type_register_static(&lm32_sys_info);
 174 }
 175
 176 type_init(lm32_sys_register_types)