target/mips/mips-defs.h

   1 #ifndef QEMU_MIPS_DEFS_H
   2 #define QEMU_MIPS_DEFS_H
   3
   4 /* If we want to use host float regs... */
   5 //#define USE_HOST_FLOAT_REGS
   6
   7 /* Real pages are variable size... */
   8 #define TARGET_PAGE_BITS 12
   9 #define MIPS_TLB_MAX 128
  10
  11 #if defined(TARGET_MIPS64)
  12 #define TARGET_LONG_BITS 64
  13 #define TARGET_PHYS_ADDR_SPACE_BITS 48
  14 #define TARGET_VIRT_ADDR_SPACE_BITS 48
  15 #else
  16 #define TARGET_LONG_BITS 32
  17 #define TARGET_PHYS_ADDR_SPACE_BITS 40
  18 # ifdef CONFIG_USER_ONLY
  19 #  define TARGET_VIRT_ADDR_SPACE_BITS 31
  20 # else
  21 #  define TARGET_VIRT_ADDR_SPACE_BITS 32
  22 #endif
  23 #endif
  24
  25 /*
  26  * bit definitions for insn_flags (ISAs/ASEs flags)
  27  * ------------------------------------------------
  28  */
  29 /*
  30  *   bits 0-31: MIPS base instruction sets
  31  */
  32 #define ISA_MIPS1         0x0000000000000001ULL
  33 #define ISA_MIPS2         0x0000000000000002ULL
  34 #define ISA_MIPS3         0x0000000000000004ULL
  35 #define ISA_MIPS4         0x0000000000000008ULL
  36 #define ISA_MIPS5         0x0000000000000010ULL
  37 #define ISA_MIPS32        0x0000000000000020ULL
  38 #define ISA_MIPS32R2      0x0000000000000040ULL
  39 #define ISA_MIPS64        0x0000000000000080ULL
  40 #define ISA_MIPS64R2      0x0000000000000100ULL
  41 #define ISA_MIPS32R3      0x0000000000000200ULL
  42 #define ISA_MIPS64R3      0x0000000000000400ULL
  43 #define ISA_MIPS32R5      0x0000000000000800ULL
  44 #define ISA_MIPS64R5      0x0000000000001000ULL
  45 #define ISA_MIPS32R6      0x0000000000002000ULL
  46 #define ISA_MIPS64R6      0x0000000000004000ULL
  47 #define ISA_NANOMIPS32    0x0000000000008000ULL
  48 /*
  49  *   bits 32-47: MIPS ASEs
  50  */
  51 #define ASE_MIPS16        0x0000000100000000ULL
  52 #define ASE_MIPS3D        0x0000000200000000ULL
  53 #define ASE_MDMX          0x0000000400000000ULL
  54 #define ASE_DSP           0x0000000800000000ULL
  55 #define ASE_DSP_R2        0x0000001000000000ULL
  56 #define ASE_DSP_R3        0x0000002000000000ULL
  57 #define ASE_MT            0x0000004000000000ULL
  58 #define ASE_SMARTMIPS     0x0000008000000000ULL
  59 #define ASE_MICROMIPS     0x0000010000000000ULL
  60 #define ASE_MSA           0x0000020000000000ULL
  61 /*
  62  *   bits 48-55: vendor-specific base instruction sets
  63  */
  64 #define INSN_LOONGSON2E   0x0001000000000000ULL
  65 #define INSN_LOONGSON2F   0x0002000000000000ULL
  66 #define INSN_VR54XX       0x0004000000000000ULL
  67 #define INSN_R5900        0x0008000000000000ULL
  68 /*
  69  *   bits 56-63: vendor-specific ASEs
  70  */
  71 #define ASE_MMI           0x0100000000000000ULL
  72 #define ASE_MXU           0x0200000000000000ULL
  73
  74 /* MIPS CPU defines. */
  75 #define         CPU_MIPS1       (ISA_MIPS1)
  76 #define         CPU_MIPS2       (CPU_MIPS1 | ISA_MIPS2)
  77 #define         CPU_MIPS3       (CPU_MIPS2 | ISA_MIPS3)
  78 #define         CPU_MIPS4       (CPU_MIPS3 | ISA_MIPS4)
  79 #define         CPU_VR54XX      (CPU_MIPS4 | INSN_VR54XX)
  80 #define         CPU_R5900       (CPU_MIPS3 | INSN_R5900)
  81 #define         CPU_LOONGSON2E  (CPU_MIPS3 | INSN_LOONGSON2E)
  82 #define         CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F)
  83
  84 #define         CPU_MIPS5       (CPU_MIPS4 | ISA_MIPS5)
  85
  86 /* MIPS Technologies "Release 1" */
  87 #define         CPU_MIPS32      (CPU_MIPS2 | ISA_MIPS32)
  88 #define         CPU_MIPS64      (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
  89
  90 /* MIPS Technologies "Release 2" */
  91 #define         CPU_MIPS32R2    (CPU_MIPS32 | ISA_MIPS32R2)
  92 #define         CPU_MIPS64R2    (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
  93
  94 /* MIPS Technologies "Release 3" */
  95 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
  96 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
  97
  98 /* MIPS Technologies "Release 5" */
  99 #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
 100 #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
 101
 102 /* MIPS Technologies "Release 6" */
 103 #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
 104 #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
 105
 106 /* Wave Computing: "nanoMIPS" */
 107 #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
 108
 109 /* Strictly follow the architecture standard:
 110    - Disallow "special" instruction handling for PMON/SPIM.
 111    Note that we still maintain Count/Compare to match the host clock. */
 112 //#define MIPS_STRICT_STANDARD 1
 113
 114 #endif /* QEMU_MIPS_DEFS_H */