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spice: Convert core to QEMU thread API
[qemu/ar7.git] / target-sparc / op_helper.c
blobcb0bf2e2a6155e03b6d5529505973129e7b580fd
1 #include "cpu.h"
2 #include "dyngen-exec.h"
3 #include "helper.h"
4
5 #if !defined(CONFIG_USER_ONLY)
6 #include "softmmu_exec.h"
7 #endif
8
9 //#define DEBUG_MMU
10 //#define DEBUG_MXCC
11 //#define DEBUG_UNALIGNED
12 //#define DEBUG_UNASSIGNED
13 //#define DEBUG_ASI
14 //#define DEBUG_PSTATE
15 //#define DEBUG_CACHE_CONTROL
16
17 #ifdef DEBUG_MMU
18 #define DPRINTF_MMU(fmt, ...) \
19 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
20 #else
21 #define DPRINTF_MMU(fmt, ...) do {} while (0)
22 #endif
23
24 #ifdef DEBUG_MXCC
25 #define DPRINTF_MXCC(fmt, ...) \
26 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
27 #else
28 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
29 #endif
30
31 #ifdef DEBUG_ASI
32 #define DPRINTF_ASI(fmt, ...) \
33 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
34 #endif
35
36 #ifdef DEBUG_PSTATE
37 #define DPRINTF_PSTATE(fmt, ...) \
38 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
39 #else
40 #define DPRINTF_PSTATE(fmt, ...) do {} while (0)
41 #endif
42
43 #ifdef DEBUG_CACHE_CONTROL
44 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
45 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
46 #else
47 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
48 #endif
49
50 #ifdef TARGET_SPARC64
51 #ifndef TARGET_ABI32
52 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
53 #else
54 #define AM_CHECK(env1) (1)
55 #endif
56 #endif
57
58 #define DT0 (env->dt0)
59 #define DT1 (env->dt1)
60 #define QT0 (env->qt0)
61 #define QT1 (env->qt1)
62
63 /* Leon3 cache control */
64
65 /* Cache control: emulate the behavior of cache control registers but without
66 any effect on the emulated */
67
68 #define CACHE_STATE_MASK 0x3
69 #define CACHE_DISABLED 0x0
70 #define CACHE_FROZEN 0x1
71 #define CACHE_ENABLED 0x3
72
73 /* Cache Control register fields */
74
75 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */
76 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */
77 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */
78 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */
79 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */
80 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */
81 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */
82 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */
83
84 #if !defined(CONFIG_USER_ONLY)
85 static void do_unassigned_access(target_phys_addr_t addr, int is_write,
86 int is_exec, int is_asi, int size);
87 #else
88 #ifdef TARGET_SPARC64
89 static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
90 int is_asi, int size);
91 #endif
92 #endif
93
94 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
95 /* Calculates TSB pointer value for fault page size 8k or 64k */
96 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
97 uint64_t tag_access_register,
98 int page_size)
99 {
100 uint64_t tsb_base = tsb_register & ~0x1fffULL;
101 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
102 int tsb_size = tsb_register & 0xf;
103
104 /* discard lower 13 bits which hold tag access context */
105 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
106
107 /* now reorder bits */
108 uint64_t tsb_base_mask = ~0x1fffULL;
109 uint64_t va = tag_access_va;
110
111 /* move va bits to correct position */
112 if (page_size == 8*1024) {
113 va >>= 9;
114 } else if (page_size == 64*1024) {
115 va >>= 12;
116 }
117
118 if (tsb_size) {
119 tsb_base_mask <<= tsb_size;
120 }
121
122 /* calculate tsb_base mask and adjust va if split is in use */
123 if (tsb_split) {
124 if (page_size == 8*1024) {
125 va &= ~(1ULL << (13 + tsb_size));
126 } else if (page_size == 64*1024) {
127 va |= (1ULL << (13 + tsb_size));
128 }
129 tsb_base_mask <<= 1;
130 }
131
132 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
133 }
134
135 /* Calculates tag target register value by reordering bits
136 in tag access register */
137 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
138 {
139 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
140 }
141
142 static void replace_tlb_entry(SparcTLBEntry *tlb,
143 uint64_t tlb_tag, uint64_t tlb_tte,
144 CPUState *env1)
145 {
146 target_ulong mask, size, va, offset;
147
148 /* flush page range if translation is valid */
149 if (TTE_IS_VALID(tlb->tte)) {
150
151 mask = 0xffffffffffffe000ULL;
152 mask <<= 3 * ((tlb->tte >> 61) & 3);
153 size = ~mask + 1;
154
155 va = tlb->tag & mask;
156
157 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
158 tlb_flush_page(env1, va + offset);
159 }
160 }
161
162 tlb->tag = tlb_tag;
163 tlb->tte = tlb_tte;
164 }
165
166 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
167 const char *strmmu, CPUState *env1)
168 {
169 unsigned int i;
170 target_ulong mask;
171 uint64_t context;
172
173 int is_demap_context = (demap_addr >> 6) & 1;
174
175 /* demap context */
176 switch ((demap_addr >> 4) & 3) {
177 case 0: /* primary */
178 context = env1->dmmu.mmu_primary_context;
179 break;
180 case 1: /* secondary */
181 context = env1->dmmu.mmu_secondary_context;
182 break;
183 case 2: /* nucleus */
184 context = 0;
185 break;
186 case 3: /* reserved */
187 default:
188 return;
189 }
190
191 for (i = 0; i < 64; i++) {
192 if (TTE_IS_VALID(tlb[i].tte)) {
193
194 if (is_demap_context) {
195 /* will remove non-global entries matching context value */
196 if (TTE_IS_GLOBAL(tlb[i].tte) ||
197 !tlb_compare_context(&tlb[i], context)) {
198 continue;
199 }
200 } else {
201 /* demap page
202 will remove any entry matching VA */
203 mask = 0xffffffffffffe000ULL;
204 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
205
206 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
207 continue;
208 }
209
210 /* entry should be global or matching context value */
211 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
212 !tlb_compare_context(&tlb[i], context)) {
213 continue;
214 }
215 }
216
217 replace_tlb_entry(&tlb[i], 0, 0, env1);
218 #ifdef DEBUG_MMU
219 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
220 dump_mmu(stdout, fprintf, env1);
221 #endif
222 }
223 }
224 }
225
226 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
227 uint64_t tlb_tag, uint64_t tlb_tte,
228 const char *strmmu, CPUState *env1)
229 {
230 unsigned int i, replace_used;
231
232 /* Try replacing invalid entry */
233 for (i = 0; i < 64; i++) {
234 if (!TTE_IS_VALID(tlb[i].tte)) {
235 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
236 #ifdef DEBUG_MMU
237 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
238 dump_mmu(stdout, fprintf, env1);
239 #endif
240 return;
241 }
242 }
243
244 /* All entries are valid, try replacing unlocked entry */
245
246 for (replace_used = 0; replace_used < 2; ++replace_used) {
247
248 /* Used entries are not replaced on first pass */
249
250 for (i = 0; i < 64; i++) {
251 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
252
253 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
254 #ifdef DEBUG_MMU
255 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
256 strmmu, (replace_used ? "used" : "unused"), i);
257 dump_mmu(stdout, fprintf, env1);
258 #endif
259 return;
260 }
261 }
262
263 /* Now reset used bit and search for unused entries again */
264
265 for (i = 0; i < 64; i++) {
266 TTE_SET_UNUSED(tlb[i].tte);
267 }
268 }
269
270 #ifdef DEBUG_MMU
271 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
272 #endif
273 /* error state? */
274 }
275
276 #endif
277
278 static inline target_ulong address_mask(CPUState *env1, target_ulong addr)
279 {
280 #ifdef TARGET_SPARC64
281 if (AM_CHECK(env1)) {
282 addr &= 0xffffffffULL;
283 }
284 #endif
285 return addr;
286 }
287
288 /* returns true if access using this ASI is to have address translated by MMU
289 otherwise access is to raw physical address */
290 static inline int is_translating_asi(int asi)
291 {
292 #ifdef TARGET_SPARC64
293 /* Ultrasparc IIi translating asi
294 - note this list is defined by cpu implementation
295 */
296 switch (asi) {
297 case 0x04 ... 0x11:
298 case 0x16 ... 0x19:
299 case 0x1E ... 0x1F:
300 case 0x24 ... 0x2C:
301 case 0x70 ... 0x73:
302 case 0x78 ... 0x79:
303 case 0x80 ... 0xFF:
304 return 1;
305
306 default:
307 return 0;
308 }
309 #else
310 /* TODO: check sparc32 bits */
311 return 0;
312 #endif
313 }
314
315 static inline target_ulong asi_address_mask(CPUState *env1,
316 int asi, target_ulong addr)
317 {
318 if (is_translating_asi(asi)) {
319 return address_mask(env, addr);
320 } else {
321 return addr;
322 }
323 }
324
325 void helper_check_align(target_ulong addr, uint32_t align)
326 {
327 if (addr & align) {
328 #ifdef DEBUG_UNALIGNED
329 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
330 "\n", addr, env->pc);
331 #endif
332 helper_raise_exception(env, TT_UNALIGNED);
333 }
334 }
335
336 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
337 defined(DEBUG_MXCC)
338 static void dump_mxcc(CPUState *env)
339 {
340 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
341 "\n",
342 env->mxccdata[0], env->mxccdata[1],
343 env->mxccdata[2], env->mxccdata[3]);
344 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
345 "\n"
346 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
347 "\n",
348 env->mxccregs[0], env->mxccregs[1],
349 env->mxccregs[2], env->mxccregs[3],
350 env->mxccregs[4], env->mxccregs[5],
351 env->mxccregs[6], env->mxccregs[7]);
352 }
353 #endif
354
355 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
356 && defined(DEBUG_ASI)
357 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
358 uint64_t r1)
359 {
360 switch (size) {
361 case 1:
362 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
363 addr, asi, r1 & 0xff);
364 break;
365 case 2:
366 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
367 addr, asi, r1 & 0xffff);
368 break;
369 case 4:
370 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
371 addr, asi, r1 & 0xffffffff);
372 break;
373 case 8:
374 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
375 addr, asi, r1);
376 break;
377 }
378 }
379 #endif
380
381 #ifndef TARGET_SPARC64
382 #ifndef CONFIG_USER_ONLY
383
384
385 /* Leon3 cache control */
386
387 static void leon3_cache_control_int(void)
388 {
389 uint32_t state = 0;
390
391 if (env->cache_control & CACHE_CTRL_IF) {
392 /* Instruction cache state */
393 state = env->cache_control & CACHE_STATE_MASK;
394 if (state == CACHE_ENABLED) {
395 state = CACHE_FROZEN;
396 DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n");
397 }
398
399 env->cache_control &= ~CACHE_STATE_MASK;
400 env->cache_control |= state;
401 }
402
403 if (env->cache_control & CACHE_CTRL_DF) {
404 /* Data cache state */
405 state = (env->cache_control >> 2) & CACHE_STATE_MASK;
406 if (state == CACHE_ENABLED) {
407 state = CACHE_FROZEN;
408 DPRINTF_CACHE_CONTROL("Data cache: freeze\n");
409 }
410
411 env->cache_control &= ~(CACHE_STATE_MASK << 2);
412 env->cache_control |= (state << 2);
413 }
414 }
415
416 static void leon3_cache_control_st(target_ulong addr, uint64_t val, int size)
417 {
418 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
419 addr, val, size);
420
421 if (size != 4) {
422 DPRINTF_CACHE_CONTROL("32bits only\n");
423 return;
424 }
425
426 switch (addr) {
427 case 0x00: /* Cache control */
428
429 /* These values must always be read as zeros */
430 val &= ~CACHE_CTRL_FD;
431 val &= ~CACHE_CTRL_FI;
432 val &= ~CACHE_CTRL_IB;
433 val &= ~CACHE_CTRL_IP;
434 val &= ~CACHE_CTRL_DP;
435
436 env->cache_control = val;
437 break;
438 case 0x04: /* Instruction cache configuration */
439 case 0x08: /* Data cache configuration */
440 /* Read Only */
441 break;
442 default:
443 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
444 break;
445 };
446 }
447
448 static uint64_t leon3_cache_control_ld(target_ulong addr, int size)
449 {
450 uint64_t ret = 0;
451
452 if (size != 4) {
453 DPRINTF_CACHE_CONTROL("32bits only\n");
454 return 0;
455 }
456
457 switch (addr) {
458 case 0x00: /* Cache control */
459 ret = env->cache_control;
460 break;
461
462 /* Configuration registers are read and only always keep those
463 predefined values */
464
465 case 0x04: /* Instruction cache configuration */
466 ret = 0x10220000;
467 break;
468 case 0x08: /* Data cache configuration */
469 ret = 0x18220000;
470 break;
471 default:
472 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
473 break;
474 };
475 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
476 addr, ret, size);
477 return ret;
478 }
479
480 void leon3_irq_manager(void *irq_manager, int intno)
481 {
482 leon3_irq_ack(irq_manager, intno);
483 leon3_cache_control_int();
484 }
485
486 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
487 {
488 uint64_t ret = 0;
489 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
490 uint32_t last_addr = addr;
491 #endif
492
493 helper_check_align(addr, size - 1);
494 switch (asi) {
495 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
496 switch (addr) {
497 case 0x00: /* Leon3 Cache Control */
498 case 0x08: /* Leon3 Instruction Cache config */
499 case 0x0C: /* Leon3 Date Cache config */
500 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
501 ret = leon3_cache_control_ld(addr, size);
502 }
503 break;
504 case 0x01c00a00: /* MXCC control register */
505 if (size == 8) {
506 ret = env->mxccregs[3];
507 } else {
508 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
509 size);
510 }
511 break;
512 case 0x01c00a04: /* MXCC control register */
513 if (size == 4) {
514 ret = env->mxccregs[3];
515 } else {
516 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
517 size);
518 }
519 break;
520 case 0x01c00c00: /* Module reset register */
521 if (size == 8) {
522 ret = env->mxccregs[5];
523 /* should we do something here? */
524 } else {
525 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
526 size);
527 }
528 break;
529 case 0x01c00f00: /* MBus port address register */
530 if (size == 8) {
531 ret = env->mxccregs[7];
532 } else {
533 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
534 size);
535 }
536 break;
537 default:
538 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
539 size);
540 break;
541 }
542 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
543 "addr = %08x -> ret = %" PRIx64 ","
544 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
545 #ifdef DEBUG_MXCC
546 dump_mxcc(env);
547 #endif
548 break;
549 case 3: /* MMU probe */
550 {
551 int mmulev;
552
553 mmulev = (addr >> 8) & 15;
554 if (mmulev > 4) {
555 ret = 0;
556 } else {
557 ret = mmu_probe(env, addr, mmulev);
558 }
559 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
560 addr, mmulev, ret);
561 }
562 break;
563 case 4: /* read MMU regs */
564 {
565 int reg = (addr >> 8) & 0x1f;
566
567 ret = env->mmuregs[reg];
568 if (reg == 3) { /* Fault status cleared on read */
569 env->mmuregs[3] = 0;
570 } else if (reg == 0x13) { /* Fault status read */
571 ret = env->mmuregs[3];
572 } else if (reg == 0x14) { /* Fault address read */
573 ret = env->mmuregs[4];
574 }
575 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
576 }
577 break;
578 case 5: /* Turbosparc ITLB Diagnostic */
579 case 6: /* Turbosparc DTLB Diagnostic */
580 case 7: /* Turbosparc IOTLB Diagnostic */
581 break;
582 case 9: /* Supervisor code access */
583 switch (size) {
584 case 1:
585 ret = ldub_code(addr);
586 break;
587 case 2:
588 ret = lduw_code(addr);
589 break;
590 default:
591 case 4:
592 ret = ldl_code(addr);
593 break;
594 case 8:
595 ret = ldq_code(addr);
596 break;
597 }
598 break;
599 case 0xa: /* User data access */
600 switch (size) {
601 case 1:
602 ret = ldub_user(addr);
603 break;
604 case 2:
605 ret = lduw_user(addr);
606 break;
607 default:
608 case 4:
609 ret = ldl_user(addr);
610 break;
611 case 8:
612 ret = ldq_user(addr);
613 break;
614 }
615 break;
616 case 0xb: /* Supervisor data access */
617 switch (size) {
618 case 1:
619 ret = ldub_kernel(addr);
620 break;
621 case 2:
622 ret = lduw_kernel(addr);
623 break;
624 default:
625 case 4:
626 ret = ldl_kernel(addr);
627 break;
628 case 8:
629 ret = ldq_kernel(addr);
630 break;
631 }
632 break;
633 case 0xc: /* I-cache tag */
634 case 0xd: /* I-cache data */
635 case 0xe: /* D-cache tag */
636 case 0xf: /* D-cache data */
637 break;
638 case 0x20: /* MMU passthrough */
639 switch (size) {
640 case 1:
641 ret = ldub_phys(addr);
642 break;
643 case 2:
644 ret = lduw_phys(addr);
645 break;
646 default:
647 case 4:
648 ret = ldl_phys(addr);
649 break;
650 case 8:
651 ret = ldq_phys(addr);
652 break;
653 }
654 break;
655 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
656 switch (size) {
657 case 1:
658 ret = ldub_phys((target_phys_addr_t)addr
659 | ((target_phys_addr_t)(asi & 0xf) << 32));
660 break;
661 case 2:
662 ret = lduw_phys((target_phys_addr_t)addr
663 | ((target_phys_addr_t)(asi & 0xf) << 32));
664 break;
665 default:
666 case 4:
667 ret = ldl_phys((target_phys_addr_t)addr
668 | ((target_phys_addr_t)(asi & 0xf) << 32));
669 break;
670 case 8:
671 ret = ldq_phys((target_phys_addr_t)addr
672 | ((target_phys_addr_t)(asi & 0xf) << 32));
673 break;
674 }
675 break;
676 case 0x30: /* Turbosparc secondary cache diagnostic */
677 case 0x31: /* Turbosparc RAM snoop */
678 case 0x32: /* Turbosparc page table descriptor diagnostic */
679 case 0x39: /* data cache diagnostic register */
680 ret = 0;
681 break;
682 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
683 {
684 int reg = (addr >> 8) & 3;
685
686 switch (reg) {
687 case 0: /* Breakpoint Value (Addr) */
688 ret = env->mmubpregs[reg];
689 break;
690 case 1: /* Breakpoint Mask */
691 ret = env->mmubpregs[reg];
692 break;
693 case 2: /* Breakpoint Control */
694 ret = env->mmubpregs[reg];
695 break;
696 case 3: /* Breakpoint Status */
697 ret = env->mmubpregs[reg];
698 env->mmubpregs[reg] = 0ULL;
699 break;
700 }
701 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
702 ret);
703 }
704 break;
705 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
706 ret = env->mmubpctrv;
707 break;
708 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
709 ret = env->mmubpctrc;
710 break;
711 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
712 ret = env->mmubpctrs;
713 break;
714 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
715 ret = env->mmubpaction;
716 break;
717 case 8: /* User code access, XXX */
718 default:
719 do_unassigned_access(addr, 0, 0, asi, size);
720 ret = 0;
721 break;
722 }
723 if (sign) {
724 switch (size) {
725 case 1:
726 ret = (int8_t) ret;
727 break;
728 case 2:
729 ret = (int16_t) ret;
730 break;
731 case 4:
732 ret = (int32_t) ret;
733 break;
734 default:
735 break;
736 }
737 }
738 #ifdef DEBUG_ASI
739 dump_asi("read ", last_addr, asi, size, ret);
740 #endif
741 return ret;
742 }
743
744 void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
745 {
746 helper_check_align(addr, size - 1);
747 switch (asi) {
748 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
749 switch (addr) {
750 case 0x00: /* Leon3 Cache Control */
751 case 0x08: /* Leon3 Instruction Cache config */
752 case 0x0C: /* Leon3 Date Cache config */
753 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
754 leon3_cache_control_st(addr, val, size);
755 }
756 break;
757
758 case 0x01c00000: /* MXCC stream data register 0 */
759 if (size == 8) {
760 env->mxccdata[0] = val;
761 } else {
762 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
763 size);
764 }
765 break;
766 case 0x01c00008: /* MXCC stream data register 1 */
767 if (size == 8) {
768 env->mxccdata[1] = val;
769 } else {
770 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
771 size);
772 }
773 break;
774 case 0x01c00010: /* MXCC stream data register 2 */
775 if (size == 8) {
776 env->mxccdata[2] = val;
777 } else {
778 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
779 size);
780 }
781 break;
782 case 0x01c00018: /* MXCC stream data register 3 */
783 if (size == 8) {
784 env->mxccdata[3] = val;
785 } else {
786 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
787 size);
788 }
789 break;
790 case 0x01c00100: /* MXCC stream source */
791 if (size == 8) {
792 env->mxccregs[0] = val;
793 } else {
794 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
795 size);
796 }
797 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
798 0);
799 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
800 8);
801 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
802 16);
803 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
804 24);
805 break;
806 case 0x01c00200: /* MXCC stream destination */
807 if (size == 8) {
808 env->mxccregs[1] = val;
809 } else {
810 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
811 size);
812 }
813 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
814 env->mxccdata[0]);
815 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
816 env->mxccdata[1]);
817 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
818 env->mxccdata[2]);
819 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
820 env->mxccdata[3]);
821 break;
822 case 0x01c00a00: /* MXCC control register */
823 if (size == 8) {
824 env->mxccregs[3] = val;
825 } else {
826 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
827 size);
828 }
829 break;
830 case 0x01c00a04: /* MXCC control register */
831 if (size == 4) {
832 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
833 | val;
834 } else {
835 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
836 size);
837 }
838 break;
839 case 0x01c00e00: /* MXCC error register */
840 /* writing a 1 bit clears the error */
841 if (size == 8) {
842 env->mxccregs[6] &= ~val;
843 } else {
844 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
845 size);
846 }
847 break;
848 case 0x01c00f00: /* MBus port address register */
849 if (size == 8) {
850 env->mxccregs[7] = val;
851 } else {
852 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
853 size);
854 }
855 break;
856 default:
857 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
858 size);
859 break;
860 }
861 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
862 asi, size, addr, val);
863 #ifdef DEBUG_MXCC
864 dump_mxcc(env);
865 #endif
866 break;
867 case 3: /* MMU flush */
868 {
869 int mmulev;
870
871 mmulev = (addr >> 8) & 15;
872 DPRINTF_MMU("mmu flush level %d\n", mmulev);
873 switch (mmulev) {
874 case 0: /* flush page */
875 tlb_flush_page(env, addr & 0xfffff000);
876 break;
877 case 1: /* flush segment (256k) */
878 case 2: /* flush region (16M) */
879 case 3: /* flush context (4G) */
880 case 4: /* flush entire */
881 tlb_flush(env, 1);
882 break;
883 default:
884 break;
885 }
886 #ifdef DEBUG_MMU
887 dump_mmu(stdout, fprintf, env);
888 #endif
889 }
890 break;
891 case 4: /* write MMU regs */
892 {
893 int reg = (addr >> 8) & 0x1f;
894 uint32_t oldreg;
895
896 oldreg = env->mmuregs[reg];
897 switch (reg) {
898 case 0: /* Control Register */
899 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
900 (val & 0x00ffffff);
901 /* Mappings generated during no-fault mode or MMU
902 disabled mode are invalid in normal mode */
903 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
904 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
905 tlb_flush(env, 1);
906 }
907 break;
908 case 1: /* Context Table Pointer Register */
909 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
910 break;
911 case 2: /* Context Register */
912 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
913 if (oldreg != env->mmuregs[reg]) {
914 /* we flush when the MMU context changes because
915 QEMU has no MMU context support */
916 tlb_flush(env, 1);
917 }
918 break;
919 case 3: /* Synchronous Fault Status Register with Clear */
920 case 4: /* Synchronous Fault Address Register */
921 break;
922 case 0x10: /* TLB Replacement Control Register */
923 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
924 break;
925 case 0x13: /* Synchronous Fault Status Register with Read
926 and Clear */
927 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
928 break;
929 case 0x14: /* Synchronous Fault Address Register */
930 env->mmuregs[4] = val;
931 break;
932 default:
933 env->mmuregs[reg] = val;
934 break;
935 }
936 if (oldreg != env->mmuregs[reg]) {
937 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
938 reg, oldreg, env->mmuregs[reg]);
939 }
940 #ifdef DEBUG_MMU
941 dump_mmu(stdout, fprintf, env);
942 #endif
943 }
944 break;
945 case 5: /* Turbosparc ITLB Diagnostic */
946 case 6: /* Turbosparc DTLB Diagnostic */
947 case 7: /* Turbosparc IOTLB Diagnostic */
948 break;
949 case 0xa: /* User data access */
950 switch (size) {
951 case 1:
952 stb_user(addr, val);
953 break;
954 case 2:
955 stw_user(addr, val);
956 break;
957 default:
958 case 4:
959 stl_user(addr, val);
960 break;
961 case 8:
962 stq_user(addr, val);
963 break;
964 }
965 break;
966 case 0xb: /* Supervisor data access */
967 switch (size) {
968 case 1:
969 stb_kernel(addr, val);
970 break;
971 case 2:
972 stw_kernel(addr, val);
973 break;
974 default:
975 case 4:
976 stl_kernel(addr, val);
977 break;
978 case 8:
979 stq_kernel(addr, val);
980 break;
981 }
982 break;
983 case 0xc: /* I-cache tag */
984 case 0xd: /* I-cache data */
985 case 0xe: /* D-cache tag */
986 case 0xf: /* D-cache data */
987 case 0x10: /* I/D-cache flush page */
988 case 0x11: /* I/D-cache flush segment */
989 case 0x12: /* I/D-cache flush region */
990 case 0x13: /* I/D-cache flush context */
991 case 0x14: /* I/D-cache flush user */
992 break;
993 case 0x17: /* Block copy, sta access */
994 {
995 /* val = src
996 addr = dst
997 copy 32 bytes */
998 unsigned int i;
999 uint32_t src = val & ~3, dst = addr & ~3, temp;
1000
1001 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1002 temp = ldl_kernel(src);
1003 stl_kernel(dst, temp);
1004 }
1005 }
1006 break;
1007 case 0x1f: /* Block fill, stda access */
1008 {
1009 /* addr = dst
1010 fill 32 bytes with val */
1011 unsigned int i;
1012 uint32_t dst = addr & 7;
1013
1014 for (i = 0; i < 32; i += 8, dst += 8) {
1015 stq_kernel(dst, val);
1016 }
1017 }
1018 break;
1019 case 0x20: /* MMU passthrough */
1020 {
1021 switch (size) {
1022 case 1:
1023 stb_phys(addr, val);
1024 break;
1025 case 2:
1026 stw_phys(addr, val);
1027 break;
1028 case 4:
1029 default:
1030 stl_phys(addr, val);
1031 break;
1032 case 8:
1033 stq_phys(addr, val);
1034 break;
1035 }
1036 }
1037 break;
1038 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1039 {
1040 switch (size) {
1041 case 1:
1042 stb_phys((target_phys_addr_t)addr
1043 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1044 break;
1045 case 2:
1046 stw_phys((target_phys_addr_t)addr
1047 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1048 break;
1049 case 4:
1050 default:
1051 stl_phys((target_phys_addr_t)addr
1052 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1053 break;
1054 case 8:
1055 stq_phys((target_phys_addr_t)addr
1056 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1057 break;
1058 }
1059 }
1060 break;
1061 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1062 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1063 Turbosparc snoop RAM */
1064 case 0x32: /* store buffer control or Turbosparc page table
1065 descriptor diagnostic */
1066 case 0x36: /* I-cache flash clear */
1067 case 0x37: /* D-cache flash clear */
1068 break;
1069 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1070 {
1071 int reg = (addr >> 8) & 3;
1072
1073 switch (reg) {
1074 case 0: /* Breakpoint Value (Addr) */
1075 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1076 break;
1077 case 1: /* Breakpoint Mask */
1078 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1079 break;
1080 case 2: /* Breakpoint Control */
1081 env->mmubpregs[reg] = (val & 0x7fULL);
1082 break;
1083 case 3: /* Breakpoint Status */
1084 env->mmubpregs[reg] = (val & 0xfULL);
1085 break;
1086 }
1087 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1088 env->mmuregs[reg]);
1089 }
1090 break;
1091 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1092 env->mmubpctrv = val & 0xffffffff;
1093 break;
1094 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1095 env->mmubpctrc = val & 0x3;
1096 break;
1097 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1098 env->mmubpctrs = val & 0x3;
1099 break;
1100 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1101 env->mmubpaction = val & 0x1fff;
1102 break;
1103 case 8: /* User code access, XXX */
1104 case 9: /* Supervisor code access, XXX */
1105 default:
1106 do_unassigned_access(addr, 1, 0, asi, size);
1107 break;
1108 }
1109 #ifdef DEBUG_ASI
1110 dump_asi("write", addr, asi, size, val);
1111 #endif
1112 }
1113
1114 #endif /* CONFIG_USER_ONLY */
1115 #else /* TARGET_SPARC64 */
1116
1117 #ifdef CONFIG_USER_ONLY
1118 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1119 {
1120 uint64_t ret = 0;
1121 #if defined(DEBUG_ASI)
1122 target_ulong last_addr = addr;
1123 #endif
1124
1125 if (asi < 0x80) {
1126 helper_raise_exception(env, TT_PRIV_ACT);
1127 }
1128
1129 helper_check_align(addr, size - 1);
1130 addr = asi_address_mask(env, asi, addr);
1131
1132 switch (asi) {
1133 case 0x82: /* Primary no-fault */
1134 case 0x8a: /* Primary no-fault LE */
1135 if (page_check_range(addr, size, PAGE_READ) == -1) {
1136 #ifdef DEBUG_ASI
1137 dump_asi("read ", last_addr, asi, size, ret);
1138 #endif
1139 return 0;
1140 }
1141 /* Fall through */
1142 case 0x80: /* Primary */
1143 case 0x88: /* Primary LE */
1144 {
1145 switch (size) {
1146 case 1:
1147 ret = ldub_raw(addr);
1148 break;
1149 case 2:
1150 ret = lduw_raw(addr);
1151 break;
1152 case 4:
1153 ret = ldl_raw(addr);
1154 break;
1155 default:
1156 case 8:
1157 ret = ldq_raw(addr);
1158 break;
1159 }
1160 }
1161 break;
1162 case 0x83: /* Secondary no-fault */
1163 case 0x8b: /* Secondary no-fault LE */
1164 if (page_check_range(addr, size, PAGE_READ) == -1) {
1165 #ifdef DEBUG_ASI
1166 dump_asi("read ", last_addr, asi, size, ret);
1167 #endif
1168 return 0;
1169 }
1170 /* Fall through */
1171 case 0x81: /* Secondary */
1172 case 0x89: /* Secondary LE */
1173 /* XXX */
1174 break;
1175 default:
1176 break;
1177 }
1178
1179 /* Convert from little endian */
1180 switch (asi) {
1181 case 0x88: /* Primary LE */
1182 case 0x89: /* Secondary LE */
1183 case 0x8a: /* Primary no-fault LE */
1184 case 0x8b: /* Secondary no-fault LE */
1185 switch (size) {
1186 case 2:
1187 ret = bswap16(ret);
1188 break;
1189 case 4:
1190 ret = bswap32(ret);
1191 break;
1192 case 8:
1193 ret = bswap64(ret);
1194 break;
1195 default:
1196 break;
1197 }
1198 default:
1199 break;
1200 }
1201
1202 /* Convert to signed number */
1203 if (sign) {
1204 switch (size) {
1205 case 1:
1206 ret = (int8_t) ret;
1207 break;
1208 case 2:
1209 ret = (int16_t) ret;
1210 break;
1211 case 4:
1212 ret = (int32_t) ret;
1213 break;
1214 default:
1215 break;
1216 }
1217 }
1218 #ifdef DEBUG_ASI
1219 dump_asi("read ", last_addr, asi, size, ret);
1220 #endif
1221 return ret;
1222 }
1223
1224 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1225 {
1226 #ifdef DEBUG_ASI
1227 dump_asi("write", addr, asi, size, val);
1228 #endif
1229 if (asi < 0x80) {
1230 helper_raise_exception(env, TT_PRIV_ACT);
1231 }
1232
1233 helper_check_align(addr, size - 1);
1234 addr = asi_address_mask(env, asi, addr);
1235
1236 /* Convert to little endian */
1237 switch (asi) {
1238 case 0x88: /* Primary LE */
1239 case 0x89: /* Secondary LE */
1240 switch (size) {
1241 case 2:
1242 val = bswap16(val);
1243 break;
1244 case 4:
1245 val = bswap32(val);
1246 break;
1247 case 8:
1248 val = bswap64(val);
1249 break;
1250 default:
1251 break;
1252 }
1253 default:
1254 break;
1255 }
1256
1257 switch (asi) {
1258 case 0x80: /* Primary */
1259 case 0x88: /* Primary LE */
1260 {
1261 switch (size) {
1262 case 1:
1263 stb_raw(addr, val);
1264 break;
1265 case 2:
1266 stw_raw(addr, val);
1267 break;
1268 case 4:
1269 stl_raw(addr, val);
1270 break;
1271 case 8:
1272 default:
1273 stq_raw(addr, val);
1274 break;
1275 }
1276 }
1277 break;
1278 case 0x81: /* Secondary */
1279 case 0x89: /* Secondary LE */
1280 /* XXX */
1281 return;
1282
1283 case 0x82: /* Primary no-fault, RO */
1284 case 0x83: /* Secondary no-fault, RO */
1285 case 0x8a: /* Primary no-fault LE, RO */
1286 case 0x8b: /* Secondary no-fault LE, RO */
1287 default:
1288 do_unassigned_access(addr, 1, 0, 1, size);
1289 return;
1290 }
1291 }
1292
1293 #else /* CONFIG_USER_ONLY */
1294
1295 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1296 {
1297 uint64_t ret = 0;
1298 #if defined(DEBUG_ASI)
1299 target_ulong last_addr = addr;
1300 #endif
1301
1302 asi &= 0xff;
1303
1304 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1305 || (cpu_has_hypervisor(env)
1306 && asi >= 0x30 && asi < 0x80
1307 && !(env->hpstate & HS_PRIV))) {
1308 helper_raise_exception(env, TT_PRIV_ACT);
1309 }
1310
1311 helper_check_align(addr, size - 1);
1312 addr = asi_address_mask(env, asi, addr);
1313
1314 /* process nonfaulting loads first */
1315 if ((asi & 0xf6) == 0x82) {
1316 int mmu_idx;
1317
1318 /* secondary space access has lowest asi bit equal to 1 */
1319 if (env->pstate & PS_PRIV) {
1320 mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
1321 } else {
1322 mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
1323 }
1324
1325 if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
1326 #ifdef DEBUG_ASI
1327 dump_asi("read ", last_addr, asi, size, ret);
1328 #endif
1329 /* env->exception_index is set in get_physical_address_data(). */
1330 helper_raise_exception(env, env->exception_index);
1331 }
1332
1333 /* convert nonfaulting load ASIs to normal load ASIs */
1334 asi &= ~0x02;
1335 }
1336
1337 switch (asi) {
1338 case 0x10: /* As if user primary */
1339 case 0x11: /* As if user secondary */
1340 case 0x18: /* As if user primary LE */
1341 case 0x19: /* As if user secondary LE */
1342 case 0x80: /* Primary */
1343 case 0x81: /* Secondary */
1344 case 0x88: /* Primary LE */
1345 case 0x89: /* Secondary LE */
1346 case 0xe2: /* UA2007 Primary block init */
1347 case 0xe3: /* UA2007 Secondary block init */
1348 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1349 if (cpu_hypervisor_mode(env)) {
1350 switch (size) {
1351 case 1:
1352 ret = ldub_hypv(addr);
1353 break;
1354 case 2:
1355 ret = lduw_hypv(addr);
1356 break;
1357 case 4:
1358 ret = ldl_hypv(addr);
1359 break;
1360 default:
1361 case 8:
1362 ret = ldq_hypv(addr);
1363 break;
1364 }
1365 } else {
1366 /* secondary space access has lowest asi bit equal to 1 */
1367 if (asi & 1) {
1368 switch (size) {
1369 case 1:
1370 ret = ldub_kernel_secondary(addr);
1371 break;
1372 case 2:
1373 ret = lduw_kernel_secondary(addr);
1374 break;
1375 case 4:
1376 ret = ldl_kernel_secondary(addr);
1377 break;
1378 default:
1379 case 8:
1380 ret = ldq_kernel_secondary(addr);
1381 break;
1382 }
1383 } else {
1384 switch (size) {
1385 case 1:
1386 ret = ldub_kernel(addr);
1387 break;
1388 case 2:
1389 ret = lduw_kernel(addr);
1390 break;
1391 case 4:
1392 ret = ldl_kernel(addr);
1393 break;
1394 default:
1395 case 8:
1396 ret = ldq_kernel(addr);
1397 break;
1398 }
1399 }
1400 }
1401 } else {
1402 /* secondary space access has lowest asi bit equal to 1 */
1403 if (asi & 1) {
1404 switch (size) {
1405 case 1:
1406 ret = ldub_user_secondary(addr);
1407 break;
1408 case 2:
1409 ret = lduw_user_secondary(addr);
1410 break;
1411 case 4:
1412 ret = ldl_user_secondary(addr);
1413 break;
1414 default:
1415 case 8:
1416 ret = ldq_user_secondary(addr);
1417 break;
1418 }
1419 } else {
1420 switch (size) {
1421 case 1:
1422 ret = ldub_user(addr);
1423 break;
1424 case 2:
1425 ret = lduw_user(addr);
1426 break;
1427 case 4:
1428 ret = ldl_user(addr);
1429 break;
1430 default:
1431 case 8:
1432 ret = ldq_user(addr);
1433 break;
1434 }
1435 }
1436 }
1437 break;
1438 case 0x14: /* Bypass */
1439 case 0x15: /* Bypass, non-cacheable */
1440 case 0x1c: /* Bypass LE */
1441 case 0x1d: /* Bypass, non-cacheable LE */
1442 {
1443 switch (size) {
1444 case 1:
1445 ret = ldub_phys(addr);
1446 break;
1447 case 2:
1448 ret = lduw_phys(addr);
1449 break;
1450 case 4:
1451 ret = ldl_phys(addr);
1452 break;
1453 default:
1454 case 8:
1455 ret = ldq_phys(addr);
1456 break;
1457 }
1458 break;
1459 }
1460 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1461 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1462 Only ldda allowed */
1463 helper_raise_exception(env, TT_ILL_INSN);
1464 return 0;
1465 case 0x04: /* Nucleus */
1466 case 0x0c: /* Nucleus Little Endian (LE) */
1467 {
1468 switch (size) {
1469 case 1:
1470 ret = ldub_nucleus(addr);
1471 break;
1472 case 2:
1473 ret = lduw_nucleus(addr);
1474 break;
1475 case 4:
1476 ret = ldl_nucleus(addr);
1477 break;
1478 default:
1479 case 8:
1480 ret = ldq_nucleus(addr);
1481 break;
1482 }
1483 break;
1484 }
1485 case 0x4a: /* UPA config */
1486 /* XXX */
1487 break;
1488 case 0x45: /* LSU */
1489 ret = env->lsu;
1490 break;
1491 case 0x50: /* I-MMU regs */
1492 {
1493 int reg = (addr >> 3) & 0xf;
1494
1495 if (reg == 0) {
1496 /* I-TSB Tag Target register */
1497 ret = ultrasparc_tag_target(env->immu.tag_access);
1498 } else {
1499 ret = env->immuregs[reg];
1500 }
1501
1502 break;
1503 }
1504 case 0x51: /* I-MMU 8k TSB pointer */
1505 {
1506 /* env->immuregs[5] holds I-MMU TSB register value
1507 env->immuregs[6] holds I-MMU Tag Access register value */
1508 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1509 8*1024);
1510 break;
1511 }
1512 case 0x52: /* I-MMU 64k TSB pointer */
1513 {
1514 /* env->immuregs[5] holds I-MMU TSB register value
1515 env->immuregs[6] holds I-MMU Tag Access register value */
1516 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1517 64*1024);
1518 break;
1519 }
1520 case 0x55: /* I-MMU data access */
1521 {
1522 int reg = (addr >> 3) & 0x3f;
1523
1524 ret = env->itlb[reg].tte;
1525 break;
1526 }
1527 case 0x56: /* I-MMU tag read */
1528 {
1529 int reg = (addr >> 3) & 0x3f;
1530
1531 ret = env->itlb[reg].tag;
1532 break;
1533 }
1534 case 0x58: /* D-MMU regs */
1535 {
1536 int reg = (addr >> 3) & 0xf;
1537
1538 if (reg == 0) {
1539 /* D-TSB Tag Target register */
1540 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1541 } else {
1542 ret = env->dmmuregs[reg];
1543 }
1544 break;
1545 }
1546 case 0x59: /* D-MMU 8k TSB pointer */
1547 {
1548 /* env->dmmuregs[5] holds D-MMU TSB register value
1549 env->dmmuregs[6] holds D-MMU Tag Access register value */
1550 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1551 8*1024);
1552 break;
1553 }
1554 case 0x5a: /* D-MMU 64k TSB pointer */
1555 {
1556 /* env->dmmuregs[5] holds D-MMU TSB register value
1557 env->dmmuregs[6] holds D-MMU Tag Access register value */
1558 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1559 64*1024);
1560 break;
1561 }
1562 case 0x5d: /* D-MMU data access */
1563 {
1564 int reg = (addr >> 3) & 0x3f;
1565
1566 ret = env->dtlb[reg].tte;
1567 break;
1568 }
1569 case 0x5e: /* D-MMU tag read */
1570 {
1571 int reg = (addr >> 3) & 0x3f;
1572
1573 ret = env->dtlb[reg].tag;
1574 break;
1575 }
1576 case 0x46: /* D-cache data */
1577 case 0x47: /* D-cache tag access */
1578 case 0x4b: /* E-cache error enable */
1579 case 0x4c: /* E-cache asynchronous fault status */
1580 case 0x4d: /* E-cache asynchronous fault address */
1581 case 0x4e: /* E-cache tag data */
1582 case 0x66: /* I-cache instruction access */
1583 case 0x67: /* I-cache tag access */
1584 case 0x6e: /* I-cache predecode */
1585 case 0x6f: /* I-cache LRU etc. */
1586 case 0x76: /* E-cache tag */
1587 case 0x7e: /* E-cache tag */
1588 break;
1589 case 0x5b: /* D-MMU data pointer */
1590 case 0x48: /* Interrupt dispatch, RO */
1591 case 0x49: /* Interrupt data receive */
1592 case 0x7f: /* Incoming interrupt vector, RO */
1593 /* XXX */
1594 break;
1595 case 0x54: /* I-MMU data in, WO */
1596 case 0x57: /* I-MMU demap, WO */
1597 case 0x5c: /* D-MMU data in, WO */
1598 case 0x5f: /* D-MMU demap, WO */
1599 case 0x77: /* Interrupt vector, WO */
1600 default:
1601 do_unassigned_access(addr, 0, 0, 1, size);
1602 ret = 0;
1603 break;
1604 }
1605
1606 /* Convert from little endian */
1607 switch (asi) {
1608 case 0x0c: /* Nucleus Little Endian (LE) */
1609 case 0x18: /* As if user primary LE */
1610 case 0x19: /* As if user secondary LE */
1611 case 0x1c: /* Bypass LE */
1612 case 0x1d: /* Bypass, non-cacheable LE */
1613 case 0x88: /* Primary LE */
1614 case 0x89: /* Secondary LE */
1615 switch(size) {
1616 case 2:
1617 ret = bswap16(ret);
1618 break;
1619 case 4:
1620 ret = bswap32(ret);
1621 break;
1622 case 8:
1623 ret = bswap64(ret);
1624 break;
1625 default:
1626 break;
1627 }
1628 default:
1629 break;
1630 }
1631
1632 /* Convert to signed number */
1633 if (sign) {
1634 switch (size) {
1635 case 1:
1636 ret = (int8_t) ret;
1637 break;
1638 case 2:
1639 ret = (int16_t) ret;
1640 break;
1641 case 4:
1642 ret = (int32_t) ret;
1643 break;
1644 default:
1645 break;
1646 }
1647 }
1648 #ifdef DEBUG_ASI
1649 dump_asi("read ", last_addr, asi, size, ret);
1650 #endif
1651 return ret;
1652 }
1653
1654 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1655 {
1656 #ifdef DEBUG_ASI
1657 dump_asi("write", addr, asi, size, val);
1658 #endif
1659
1660 asi &= 0xff;
1661
1662 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1663 || (cpu_has_hypervisor(env)
1664 && asi >= 0x30 && asi < 0x80
1665 && !(env->hpstate & HS_PRIV))) {
1666 helper_raise_exception(env, TT_PRIV_ACT);
1667 }
1668
1669 helper_check_align(addr, size - 1);
1670 addr = asi_address_mask(env, asi, addr);
1671
1672 /* Convert to little endian */
1673 switch (asi) {
1674 case 0x0c: /* Nucleus Little Endian (LE) */
1675 case 0x18: /* As if user primary LE */
1676 case 0x19: /* As if user secondary LE */
1677 case 0x1c: /* Bypass LE */
1678 case 0x1d: /* Bypass, non-cacheable LE */
1679 case 0x88: /* Primary LE */
1680 case 0x89: /* Secondary LE */
1681 switch (size) {
1682 case 2:
1683 val = bswap16(val);
1684 break;
1685 case 4:
1686 val = bswap32(val);
1687 break;
1688 case 8:
1689 val = bswap64(val);
1690 break;
1691 default:
1692 break;
1693 }
1694 default:
1695 break;
1696 }
1697
1698 switch (asi) {
1699 case 0x10: /* As if user primary */
1700 case 0x11: /* As if user secondary */
1701 case 0x18: /* As if user primary LE */
1702 case 0x19: /* As if user secondary LE */
1703 case 0x80: /* Primary */
1704 case 0x81: /* Secondary */
1705 case 0x88: /* Primary LE */
1706 case 0x89: /* Secondary LE */
1707 case 0xe2: /* UA2007 Primary block init */
1708 case 0xe3: /* UA2007 Secondary block init */
1709 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1710 if (cpu_hypervisor_mode(env)) {
1711 switch (size) {
1712 case 1:
1713 stb_hypv(addr, val);
1714 break;
1715 case 2:
1716 stw_hypv(addr, val);
1717 break;
1718 case 4:
1719 stl_hypv(addr, val);
1720 break;
1721 case 8:
1722 default:
1723 stq_hypv(addr, val);
1724 break;
1725 }
1726 } else {
1727 /* secondary space access has lowest asi bit equal to 1 */
1728 if (asi & 1) {
1729 switch (size) {
1730 case 1:
1731 stb_kernel_secondary(addr, val);
1732 break;
1733 case 2:
1734 stw_kernel_secondary(addr, val);
1735 break;
1736 case 4:
1737 stl_kernel_secondary(addr, val);
1738 break;
1739 case 8:
1740 default:
1741 stq_kernel_secondary(addr, val);
1742 break;
1743 }
1744 } else {
1745 switch (size) {
1746 case 1:
1747 stb_kernel(addr, val);
1748 break;
1749 case 2:
1750 stw_kernel(addr, val);
1751 break;
1752 case 4:
1753 stl_kernel(addr, val);
1754 break;
1755 case 8:
1756 default:
1757 stq_kernel(addr, val);
1758 break;
1759 }
1760 }
1761 }
1762 } else {
1763 /* secondary space access has lowest asi bit equal to 1 */
1764 if (asi & 1) {
1765 switch (size) {
1766 case 1:
1767 stb_user_secondary(addr, val);
1768 break;
1769 case 2:
1770 stw_user_secondary(addr, val);
1771 break;
1772 case 4:
1773 stl_user_secondary(addr, val);
1774 break;
1775 case 8:
1776 default:
1777 stq_user_secondary(addr, val);
1778 break;
1779 }
1780 } else {
1781 switch (size) {
1782 case 1:
1783 stb_user(addr, val);
1784 break;
1785 case 2:
1786 stw_user(addr, val);
1787 break;
1788 case 4:
1789 stl_user(addr, val);
1790 break;
1791 case 8:
1792 default:
1793 stq_user(addr, val);
1794 break;
1795 }
1796 }
1797 }
1798 break;
1799 case 0x14: /* Bypass */
1800 case 0x15: /* Bypass, non-cacheable */
1801 case 0x1c: /* Bypass LE */
1802 case 0x1d: /* Bypass, non-cacheable LE */
1803 {
1804 switch (size) {
1805 case 1:
1806 stb_phys(addr, val);
1807 break;
1808 case 2:
1809 stw_phys(addr, val);
1810 break;
1811 case 4:
1812 stl_phys(addr, val);
1813 break;
1814 case 8:
1815 default:
1816 stq_phys(addr, val);
1817 break;
1818 }
1819 }
1820 return;
1821 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1822 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1823 Only ldda allowed */
1824 helper_raise_exception(env, TT_ILL_INSN);
1825 return;
1826 case 0x04: /* Nucleus */
1827 case 0x0c: /* Nucleus Little Endian (LE) */
1828 {
1829 switch (size) {
1830 case 1:
1831 stb_nucleus(addr, val);
1832 break;
1833 case 2:
1834 stw_nucleus(addr, val);
1835 break;
1836 case 4:
1837 stl_nucleus(addr, val);
1838 break;
1839 default:
1840 case 8:
1841 stq_nucleus(addr, val);
1842 break;
1843 }
1844 break;
1845 }
1846
1847 case 0x4a: /* UPA config */
1848 /* XXX */
1849 return;
1850 case 0x45: /* LSU */
1851 {
1852 uint64_t oldreg;
1853
1854 oldreg = env->lsu;
1855 env->lsu = val & (DMMU_E | IMMU_E);
1856 /* Mappings generated during D/I MMU disabled mode are
1857 invalid in normal mode */
1858 if (oldreg != env->lsu) {
1859 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1860 oldreg, env->lsu);
1861 #ifdef DEBUG_MMU
1862 dump_mmu(stdout, fprintf, env1);
1863 #endif
1864 tlb_flush(env, 1);
1865 }
1866 return;
1867 }
1868 case 0x50: /* I-MMU regs */
1869 {
1870 int reg = (addr >> 3) & 0xf;
1871 uint64_t oldreg;
1872
1873 oldreg = env->immuregs[reg];
1874 switch (reg) {
1875 case 0: /* RO */
1876 return;
1877 case 1: /* Not in I-MMU */
1878 case 2:
1879 return;
1880 case 3: /* SFSR */
1881 if ((val & 1) == 0) {
1882 val = 0; /* Clear SFSR */
1883 }
1884 env->immu.sfsr = val;
1885 break;
1886 case 4: /* RO */
1887 return;
1888 case 5: /* TSB access */
1889 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1890 PRIx64 "\n", env->immu.tsb, val);
1891 env->immu.tsb = val;
1892 break;
1893 case 6: /* Tag access */
1894 env->immu.tag_access = val;
1895 break;
1896 case 7:
1897 case 8:
1898 return;
1899 default:
1900 break;
1901 }
1902
1903 if (oldreg != env->immuregs[reg]) {
1904 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1905 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1906 }
1907 #ifdef DEBUG_MMU
1908 dump_mmu(stdout, fprintf, env);
1909 #endif
1910 return;
1911 }
1912 case 0x54: /* I-MMU data in */
1913 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1914 return;
1915 case 0x55: /* I-MMU data access */
1916 {
1917 /* TODO: auto demap */
1918
1919 unsigned int i = (addr >> 3) & 0x3f;
1920
1921 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1922
1923 #ifdef DEBUG_MMU
1924 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1925 dump_mmu(stdout, fprintf, env);
1926 #endif
1927 return;
1928 }
1929 case 0x57: /* I-MMU demap */
1930 demap_tlb(env->itlb, addr, "immu", env);
1931 return;
1932 case 0x58: /* D-MMU regs */
1933 {
1934 int reg = (addr >> 3) & 0xf;
1935 uint64_t oldreg;
1936
1937 oldreg = env->dmmuregs[reg];
1938 switch (reg) {
1939 case 0: /* RO */
1940 case 4:
1941 return;
1942 case 3: /* SFSR */
1943 if ((val & 1) == 0) {
1944 val = 0; /* Clear SFSR, Fault address */
1945 env->dmmu.sfar = 0;
1946 }
1947 env->dmmu.sfsr = val;
1948 break;
1949 case 1: /* Primary context */
1950 env->dmmu.mmu_primary_context = val;
1951 /* can be optimized to only flush MMU_USER_IDX
1952 and MMU_KERNEL_IDX entries */
1953 tlb_flush(env, 1);
1954 break;
1955 case 2: /* Secondary context */
1956 env->dmmu.mmu_secondary_context = val;
1957 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1958 and MMU_KERNEL_SECONDARY_IDX entries */
1959 tlb_flush(env, 1);
1960 break;
1961 case 5: /* TSB access */
1962 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1963 PRIx64 "\n", env->dmmu.tsb, val);
1964 env->dmmu.tsb = val;
1965 break;
1966 case 6: /* Tag access */
1967 env->dmmu.tag_access = val;
1968 break;
1969 case 7: /* Virtual Watchpoint */
1970 case 8: /* Physical Watchpoint */
1971 default:
1972 env->dmmuregs[reg] = val;
1973 break;
1974 }
1975
1976 if (oldreg != env->dmmuregs[reg]) {
1977 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1978 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1979 }
1980 #ifdef DEBUG_MMU
1981 dump_mmu(stdout, fprintf, env);
1982 #endif
1983 return;
1984 }
1985 case 0x5c: /* D-MMU data in */
1986 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
1987 return;
1988 case 0x5d: /* D-MMU data access */
1989 {
1990 unsigned int i = (addr >> 3) & 0x3f;
1991
1992 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
1993
1994 #ifdef DEBUG_MMU
1995 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1996 dump_mmu(stdout, fprintf, env);
1997 #endif
1998 return;
1999 }
2000 case 0x5f: /* D-MMU demap */
2001 demap_tlb(env->dtlb, addr, "dmmu", env);
2002 return;
2003 case 0x49: /* Interrupt data receive */
2004 /* XXX */
2005 return;
2006 case 0x46: /* D-cache data */
2007 case 0x47: /* D-cache tag access */
2008 case 0x4b: /* E-cache error enable */
2009 case 0x4c: /* E-cache asynchronous fault status */
2010 case 0x4d: /* E-cache asynchronous fault address */
2011 case 0x4e: /* E-cache tag data */
2012 case 0x66: /* I-cache instruction access */
2013 case 0x67: /* I-cache tag access */
2014 case 0x6e: /* I-cache predecode */
2015 case 0x6f: /* I-cache LRU etc. */
2016 case 0x76: /* E-cache tag */
2017 case 0x7e: /* E-cache tag */
2018 return;
2019 case 0x51: /* I-MMU 8k TSB pointer, RO */
2020 case 0x52: /* I-MMU 64k TSB pointer, RO */
2021 case 0x56: /* I-MMU tag read, RO */
2022 case 0x59: /* D-MMU 8k TSB pointer, RO */
2023 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2024 case 0x5b: /* D-MMU data pointer, RO */
2025 case 0x5e: /* D-MMU tag read, RO */
2026 case 0x48: /* Interrupt dispatch, RO */
2027 case 0x7f: /* Incoming interrupt vector, RO */
2028 case 0x82: /* Primary no-fault, RO */
2029 case 0x83: /* Secondary no-fault, RO */
2030 case 0x8a: /* Primary no-fault LE, RO */
2031 case 0x8b: /* Secondary no-fault LE, RO */
2032 default:
2033 do_unassigned_access(addr, 1, 0, 1, size);
2034 return;
2035 }
2036 }
2037 #endif /* CONFIG_USER_ONLY */
2038
2039 void helper_ldda_asi(target_ulong addr, int asi, int rd)
2040 {
2041 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2042 || (cpu_has_hypervisor(env)
2043 && asi >= 0x30 && asi < 0x80
2044 && !(env->hpstate & HS_PRIV))) {
2045 helper_raise_exception(env, TT_PRIV_ACT);
2046 }
2047
2048 addr = asi_address_mask(env, asi, addr);
2049
2050 switch (asi) {
2051 #if !defined(CONFIG_USER_ONLY)
2052 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2053 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2054 helper_check_align(addr, 0xf);
2055 if (rd == 0) {
2056 env->gregs[1] = ldq_nucleus(addr + 8);
2057 if (asi == 0x2c) {
2058 bswap64s(&env->gregs[1]);
2059 }
2060 } else if (rd < 8) {
2061 env->gregs[rd] = ldq_nucleus(addr);
2062 env->gregs[rd + 1] = ldq_nucleus(addr + 8);
2063 if (asi == 0x2c) {
2064 bswap64s(&env->gregs[rd]);
2065 bswap64s(&env->gregs[rd + 1]);
2066 }
2067 } else {
2068 env->regwptr[rd] = ldq_nucleus(addr);
2069 env->regwptr[rd + 1] = ldq_nucleus(addr + 8);
2070 if (asi == 0x2c) {
2071 bswap64s(&env->regwptr[rd]);
2072 bswap64s(&env->regwptr[rd + 1]);
2073 }
2074 }
2075 break;
2076 #endif
2077 default:
2078 helper_check_align(addr, 0x3);
2079 if (rd == 0) {
2080 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
2081 } else if (rd < 8) {
2082 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
2083 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2084 } else {
2085 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
2086 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2087 }
2088 break;
2089 }
2090 }
2091
2092 void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
2093 {
2094 unsigned int i;
2095 CPU_DoubleU u;
2096
2097 helper_check_align(addr, 3);
2098 addr = asi_address_mask(env, asi, addr);
2099
2100 switch (asi) {
2101 case 0xf0: /* UA2007/JPS1 Block load primary */
2102 case 0xf1: /* UA2007/JPS1 Block load secondary */
2103 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2104 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2105 if (rd & 7) {
2106 helper_raise_exception(env, TT_ILL_INSN);
2107 return;
2108 }
2109 helper_check_align(addr, 0x3f);
2110 for (i = 0; i < 16; i++) {
2111 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
2112 0);
2113 addr += 4;
2114 }
2115
2116 return;
2117 case 0x16: /* UA2007 Block load primary, user privilege */
2118 case 0x17: /* UA2007 Block load secondary, user privilege */
2119 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2120 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2121 case 0x70: /* JPS1 Block load primary, user privilege */
2122 case 0x71: /* JPS1 Block load secondary, user privilege */
2123 case 0x78: /* JPS1 Block load primary LE, user privilege */
2124 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2125 if (rd & 7) {
2126 helper_raise_exception(env, TT_ILL_INSN);
2127 return;
2128 }
2129 helper_check_align(addr, 0x3f);
2130 for (i = 0; i < 16; i++) {
2131 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x19, 4,
2132 0);
2133 addr += 4;
2134 }
2135
2136 return;
2137 default:
2138 break;
2139 }
2140
2141 switch (size) {
2142 default:
2143 case 4:
2144 *((uint32_t *)&env->fpr[rd]) = helper_ld_asi(addr, asi, size, 0);
2145 break;
2146 case 8:
2147 u.ll = helper_ld_asi(addr, asi, size, 0);
2148 *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
2149 *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
2150 break;
2151 case 16:
2152 u.ll = helper_ld_asi(addr, asi, 8, 0);
2153 *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
2154 *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
2155 u.ll = helper_ld_asi(addr + 8, asi, 8, 0);
2156 *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
2157 *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
2158 break;
2159 }
2160 }
2161
2162 void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
2163 {
2164 unsigned int i;
2165 target_ulong val = 0;
2166 CPU_DoubleU u;
2167
2168 helper_check_align(addr, 3);
2169 addr = asi_address_mask(env, asi, addr);
2170
2171 switch (asi) {
2172 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2173 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2174 case 0xf0: /* UA2007/JPS1 Block store primary */
2175 case 0xf1: /* UA2007/JPS1 Block store secondary */
2176 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2177 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2178 if (rd & 7) {
2179 helper_raise_exception(env, TT_ILL_INSN);
2180 return;
2181 }
2182 helper_check_align(addr, 0x3f);
2183 for (i = 0; i < 16; i++) {
2184 val = *(uint32_t *)&env->fpr[rd++];
2185 helper_st_asi(addr, val, asi & 0x8f, 4);
2186 addr += 4;
2187 }
2188
2189 return;
2190 case 0x16: /* UA2007 Block load primary, user privilege */
2191 case 0x17: /* UA2007 Block load secondary, user privilege */
2192 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2193 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2194 case 0x70: /* JPS1 Block store primary, user privilege */
2195 case 0x71: /* JPS1 Block store secondary, user privilege */
2196 case 0x78: /* JPS1 Block load primary LE, user privilege */
2197 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2198 if (rd & 7) {
2199 helper_raise_exception(env, TT_ILL_INSN);
2200 return;
2201 }
2202 helper_check_align(addr, 0x3f);
2203 for (i = 0; i < 16; i++) {
2204 val = *(uint32_t *)&env->fpr[rd++];
2205 helper_st_asi(addr, val, asi & 0x19, 4);
2206 addr += 4;
2207 }
2208
2209 return;
2210 default:
2211 break;
2212 }
2213
2214 switch (size) {
2215 default:
2216 case 4:
2217 helper_st_asi(addr, *(uint32_t *)&env->fpr[rd], asi, size);
2218 break;
2219 case 8:
2220 u.l.upper = *(uint32_t *)&env->fpr[rd++];
2221 u.l.lower = *(uint32_t *)&env->fpr[rd++];
2222 helper_st_asi(addr, u.ll, asi, size);
2223 break;
2224 case 16:
2225 u.l.upper = *(uint32_t *)&env->fpr[rd++];
2226 u.l.lower = *(uint32_t *)&env->fpr[rd++];
2227 helper_st_asi(addr, u.ll, asi, 8);
2228 u.l.upper = *(uint32_t *)&env->fpr[rd++];
2229 u.l.lower = *(uint32_t *)&env->fpr[rd++];
2230 helper_st_asi(addr + 8, u.ll, asi, 8);
2231 break;
2232 }
2233 }
2234
2235 target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2236 target_ulong val2, uint32_t asi)
2237 {
2238 target_ulong ret;
2239
2240 val2 &= 0xffffffffUL;
2241 ret = helper_ld_asi(addr, asi, 4, 0);
2242 ret &= 0xffffffffUL;
2243 if (val2 == ret) {
2244 helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
2245 }
2246 return ret;
2247 }
2248
2249 target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2250 target_ulong val2, uint32_t asi)
2251 {
2252 target_ulong ret;
2253
2254 ret = helper_ld_asi(addr, asi, 8, 0);
2255 if (val2 == ret) {
2256 helper_st_asi(addr, val1, asi, 8);
2257 }
2258 return ret;
2259 }
2260 #endif /* TARGET_SPARC64 */
2261
2262 static target_ulong helper_udiv_common(target_ulong a, target_ulong b, int cc)
2263 {
2264 int overflow = 0;
2265 uint64_t x0;
2266 uint32_t x1;
2267
2268 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
2269 x1 = (b & 0xffffffff);
2270
2271 if (x1 == 0) {
2272 helper_raise_exception(env, TT_DIV_ZERO);
2273 }
2274
2275 x0 = x0 / x1;
2276 if (x0 > 0xffffffff) {
2277 x0 = 0xffffffff;
2278 overflow = 1;
2279 }
2280
2281 if (cc) {
2282 env->cc_dst = x0;
2283 env->cc_src2 = overflow;
2284 env->cc_op = CC_OP_DIV;
2285 }
2286 return x0;
2287 }
2288
2289 target_ulong helper_udiv(target_ulong a, target_ulong b)
2290 {
2291 return helper_udiv_common(a, b, 0);
2292 }
2293
2294 target_ulong helper_udiv_cc(target_ulong a, target_ulong b)
2295 {
2296 return helper_udiv_common(a, b, 1);
2297 }
2298
2299 static target_ulong helper_sdiv_common(target_ulong a, target_ulong b, int cc)
2300 {
2301 int overflow = 0;
2302 int64_t x0;
2303 int32_t x1;
2304
2305 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
2306 x1 = (b & 0xffffffff);
2307
2308 if (x1 == 0) {
2309 helper_raise_exception(env, TT_DIV_ZERO);
2310 }
2311
2312 x0 = x0 / x1;
2313 if ((int32_t) x0 != x0) {
2314 x0 = x0 < 0 ? 0x80000000 : 0x7fffffff;
2315 overflow = 1;
2316 }
2317
2318 if (cc) {
2319 env->cc_dst = x0;
2320 env->cc_src2 = overflow;
2321 env->cc_op = CC_OP_DIV;
2322 }
2323 return x0;
2324 }
2325
2326 target_ulong helper_sdiv(target_ulong a, target_ulong b)
2327 {
2328 return helper_sdiv_common(a, b, 0);
2329 }
2330
2331 target_ulong helper_sdiv_cc(target_ulong a, target_ulong b)
2332 {
2333 return helper_sdiv_common(a, b, 1);
2334 }
2335
2336 void helper_stdf(target_ulong addr, int mem_idx)
2337 {
2338 helper_check_align(addr, 7);
2339 #if !defined(CONFIG_USER_ONLY)
2340 switch (mem_idx) {
2341 case MMU_USER_IDX:
2342 stfq_user(addr, DT0);
2343 break;
2344 case MMU_KERNEL_IDX:
2345 stfq_kernel(addr, DT0);
2346 break;
2347 #ifdef TARGET_SPARC64
2348 case MMU_HYPV_IDX:
2349 stfq_hypv(addr, DT0);
2350 break;
2351 #endif
2352 default:
2353 DPRINTF_MMU("helper_stdf: need to check MMU idx %d\n", mem_idx);
2354 break;
2355 }
2356 #else
2357 stfq_raw(address_mask(env, addr), DT0);
2358 #endif
2359 }
2360
2361 void helper_lddf(target_ulong addr, int mem_idx)
2362 {
2363 helper_check_align(addr, 7);
2364 #if !defined(CONFIG_USER_ONLY)
2365 switch (mem_idx) {
2366 case MMU_USER_IDX:
2367 DT0 = ldfq_user(addr);
2368 break;
2369 case MMU_KERNEL_IDX:
2370 DT0 = ldfq_kernel(addr);
2371 break;
2372 #ifdef TARGET_SPARC64
2373 case MMU_HYPV_IDX:
2374 DT0 = ldfq_hypv(addr);
2375 break;
2376 #endif
2377 default:
2378 DPRINTF_MMU("helper_lddf: need to check MMU idx %d\n", mem_idx);
2379 break;
2380 }
2381 #else
2382 DT0 = ldfq_raw(address_mask(env, addr));
2383 #endif
2384 }
2385
2386 void helper_ldqf(target_ulong addr, int mem_idx)
2387 {
2388 /* XXX add 128 bit load */
2389 CPU_QuadU u;
2390
2391 helper_check_align(addr, 7);
2392 #if !defined(CONFIG_USER_ONLY)
2393 switch (mem_idx) {
2394 case MMU_USER_IDX:
2395 u.ll.upper = ldq_user(addr);
2396 u.ll.lower = ldq_user(addr + 8);
2397 QT0 = u.q;
2398 break;
2399 case MMU_KERNEL_IDX:
2400 u.ll.upper = ldq_kernel(addr);
2401 u.ll.lower = ldq_kernel(addr + 8);
2402 QT0 = u.q;
2403 break;
2404 #ifdef TARGET_SPARC64
2405 case MMU_HYPV_IDX:
2406 u.ll.upper = ldq_hypv(addr);
2407 u.ll.lower = ldq_hypv(addr + 8);
2408 QT0 = u.q;
2409 break;
2410 #endif
2411 default:
2412 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
2413 break;
2414 }
2415 #else
2416 u.ll.upper = ldq_raw(address_mask(env, addr));
2417 u.ll.lower = ldq_raw(address_mask(env, addr + 8));
2418 QT0 = u.q;
2419 #endif
2420 }
2421
2422 void helper_stqf(target_ulong addr, int mem_idx)
2423 {
2424 /* XXX add 128 bit store */
2425 CPU_QuadU u;
2426
2427 helper_check_align(addr, 7);
2428 #if !defined(CONFIG_USER_ONLY)
2429 switch (mem_idx) {
2430 case MMU_USER_IDX:
2431 u.q = QT0;
2432 stq_user(addr, u.ll.upper);
2433 stq_user(addr + 8, u.ll.lower);
2434 break;
2435 case MMU_KERNEL_IDX:
2436 u.q = QT0;
2437 stq_kernel(addr, u.ll.upper);
2438 stq_kernel(addr + 8, u.ll.lower);
2439 break;
2440 #ifdef TARGET_SPARC64
2441 case MMU_HYPV_IDX:
2442 u.q = QT0;
2443 stq_hypv(addr, u.ll.upper);
2444 stq_hypv(addr + 8, u.ll.lower);
2445 break;
2446 #endif
2447 default:
2448 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
2449 break;
2450 }
2451 #else
2452 u.q = QT0;
2453 stq_raw(address_mask(env, addr), u.ll.upper);
2454 stq_raw(address_mask(env, addr + 8), u.ll.lower);
2455 #endif
2456 }
2457
2458 #ifdef TARGET_SPARC64
2459 static void do_modify_softint(const char *operation, uint32_t value)
2460 {
2461 if (env->softint != value) {
2462 env->softint = value;
2463 DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint);
2464 #if !defined(CONFIG_USER_ONLY)
2465 if (cpu_interrupts_enabled(env)) {
2466 cpu_check_irqs(env);
2467 }
2468 #endif
2469 }
2470 }
2471
2472 void helper_set_softint(uint64_t value)
2473 {
2474 do_modify_softint("helper_set_softint", env->softint | (uint32_t)value);
2475 }
2476
2477 void helper_clear_softint(uint64_t value)
2478 {
2479 do_modify_softint("helper_clear_softint", env->softint & (uint32_t)~value);
2480 }
2481
2482 void helper_write_softint(uint64_t value)
2483 {
2484 do_modify_softint("helper_write_softint", (uint32_t)value);
2485 }
2486 #endif
2487
2488 #if !defined(CONFIG_USER_ONLY)
2489
2490 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2491 void *retaddr);
2492
2493 #define MMUSUFFIX _mmu
2494 #define ALIGNED_ONLY
2495
2496 #define SHIFT 0
2497 #include "softmmu_template.h"
2498
2499 #define SHIFT 1
2500 #include "softmmu_template.h"
2501
2502 #define SHIFT 2
2503 #include "softmmu_template.h"
2504
2505 #define SHIFT 3
2506 #include "softmmu_template.h"
2507
2508 /* XXX: make it generic ? */
2509 static void cpu_restore_state2(void *retaddr)
2510 {
2511 TranslationBlock *tb;
2512 unsigned long pc;
2513
2514 if (retaddr) {
2515 /* now we have a real cpu fault */
2516 pc = (unsigned long)retaddr;
2517 tb = tb_find_pc(pc);
2518 if (tb) {
2519 /* the PC is inside the translated code. It means that we have
2520 a virtual CPU fault */
2521 cpu_restore_state(tb, env, pc);
2522 }
2523 }
2524 }
2525
2526 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2527 void *retaddr)
2528 {
2529 #ifdef DEBUG_UNALIGNED
2530 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2531 "\n", addr, env->pc);
2532 #endif
2533 cpu_restore_state2(retaddr);
2534 helper_raise_exception(env, TT_UNALIGNED);
2535 }
2536
2537 /* try to fill the TLB and return an exception if error. If retaddr is
2538 NULL, it means that the function was called in C code (i.e. not
2539 from generated code or from helper.c) */
2540 /* XXX: fix it to restore all registers */
2541 void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
2542 void *retaddr)
2543 {
2544 int ret;
2545 CPUState *saved_env;
2546
2547 saved_env = env;
2548 env = env1;
2549
2550 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx);
2551 if (ret) {
2552 cpu_restore_state2(retaddr);
2553 cpu_loop_exit(env);
2554 }
2555 env = saved_env;
2556 }
2557
2558 #endif /* !CONFIG_USER_ONLY */
2559
2560 #ifndef TARGET_SPARC64
2561 #if !defined(CONFIG_USER_ONLY)
2562 static void do_unassigned_access(target_phys_addr_t addr, int is_write,
2563 int is_exec, int is_asi, int size)
2564 {
2565 int fault_type;
2566
2567 #ifdef DEBUG_UNASSIGNED
2568 if (is_asi) {
2569 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2570 " asi 0x%02x from " TARGET_FMT_lx "\n",
2571 is_exec ? "exec" : is_write ? "write" : "read", size,
2572 size == 1 ? "" : "s", addr, is_asi, env->pc);
2573 } else {
2574 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2575 " from " TARGET_FMT_lx "\n",
2576 is_exec ? "exec" : is_write ? "write" : "read", size,
2577 size == 1 ? "" : "s", addr, env->pc);
2578 }
2579 #endif
2580 /* Don't overwrite translation and access faults */
2581 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
2582 if ((fault_type > 4) || (fault_type == 0)) {
2583 env->mmuregs[3] = 0; /* Fault status register */
2584 if (is_asi) {
2585 env->mmuregs[3] |= 1 << 16;
2586 }
2587 if (env->psrs) {
2588 env->mmuregs[3] |= 1 << 5;
2589 }
2590 if (is_exec) {
2591 env->mmuregs[3] |= 1 << 6;
2592 }
2593 if (is_write) {
2594 env->mmuregs[3] |= 1 << 7;
2595 }
2596 env->mmuregs[3] |= (5 << 2) | 2;
2597 /* SuperSPARC will never place instruction fault addresses in the FAR */
2598 if (!is_exec) {
2599 env->mmuregs[4] = addr; /* Fault address register */
2600 }
2601 }
2602 /* overflow (same type fault was not read before another fault) */
2603 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
2604 env->mmuregs[3] |= 1;
2605 }
2606
2607 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2608 if (is_exec) {
2609 helper_raise_exception(env, TT_CODE_ACCESS);
2610 } else {
2611 helper_raise_exception(env, TT_DATA_ACCESS);
2612 }
2613 }
2614
2615 /* flush neverland mappings created during no-fault mode,
2616 so the sequential MMU faults report proper fault types */
2617 if (env->mmuregs[0] & MMU_NF) {
2618 tlb_flush(env, 1);
2619 }
2620 }
2621 #endif
2622 #else
2623 #if defined(CONFIG_USER_ONLY)
2624 static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
2625 int is_asi, int size)
2626 #else
2627 static void do_unassigned_access(target_phys_addr_t addr, int is_write,
2628 int is_exec, int is_asi, int size)
2629 #endif
2630 {
2631 #ifdef DEBUG_UNASSIGNED
2632 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2633 "\n", addr, env->pc);
2634 #endif
2635
2636 if (is_exec) {
2637 helper_raise_exception(env, TT_CODE_ACCESS);
2638 } else {
2639 helper_raise_exception(env, TT_DATA_ACCESS);
2640 }
2641 }
2642 #endif
2643
2644 #if !defined(CONFIG_USER_ONLY)
2645 void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
2646 int is_write, int is_exec, int is_asi, int size)
2647 {
2648 CPUState *saved_env;
2649
2650 saved_env = env;
2651 env = env1;
2652 /* Ignore unassigned accesses outside of CPU context */
2653 if (env1) {
2654 do_unassigned_access(addr, is_write, is_exec, is_asi, size);
2655 }
2656 env = saved_env;
2657 }
2658 #endif
AR7 emulation for QEMU