2 * CRIS helper routines.
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "hw/core/tcg-cpu-ops.h"
25 #include "qemu/host-utils.h"
26 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
28 #include "exec/helper-proto.h"
31 //#define CRIS_HELPER_DEBUG
34 #ifdef CRIS_HELPER_DEBUG
36 #define D_LOG(...) qemu_log(__VA_ARGS__)
39 #define D_LOG(...) do { } while (0)
42 #if defined(CONFIG_USER_ONLY)
44 void cris_cpu_do_interrupt(CPUState
*cs
)
46 CRISCPU
*cpu
= CRIS_CPU(cs
);
47 CPUCRISState
*env
= &cpu
->env
;
49 cs
->exception_index
= -1;
50 env
->pregs
[PR_ERP
] = env
->pc
;
53 void crisv10_cpu_do_interrupt(CPUState
*cs
)
55 cris_cpu_do_interrupt(cs
);
58 bool cris_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
59 MMUAccessType access_type
, int mmu_idx
,
60 bool probe
, uintptr_t retaddr
)
62 CRISCPU
*cpu
= CRIS_CPU(cs
);
64 cs
->exception_index
= 0xaa;
65 cpu
->env
.pregs
[PR_EDA
] = address
;
66 cpu_loop_exit_restore(cs
, retaddr
);
69 #else /* !CONFIG_USER_ONLY */
72 static void cris_shift_ccs(CPUCRISState
*env
)
75 /* Apply the ccs shift. */
76 ccs
= env
->pregs
[PR_CCS
];
77 ccs
= ((ccs
& 0xc0000000) | ((ccs
<< 12) >> 2)) & ~0x3ff;
78 env
->pregs
[PR_CCS
] = ccs
;
81 bool cris_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
82 MMUAccessType access_type
, int mmu_idx
,
83 bool probe
, uintptr_t retaddr
)
85 CRISCPU
*cpu
= CRIS_CPU(cs
);
86 CPUCRISState
*env
= &cpu
->env
;
87 struct cris_mmu_result res
;
91 miss
= cris_mmu_translate(&res
, env
, address
& TARGET_PAGE_MASK
,
92 access_type
, mmu_idx
, 0);
95 * Mask off the cache selection bit. The ETRAX busses do not
98 phy
= res
.phy
& ~0x80000000;
100 tlb_set_page(cs
, address
& TARGET_PAGE_MASK
, phy
,
101 prot
, mmu_idx
, TARGET_PAGE_SIZE
);
109 if (cs
->exception_index
== EXCP_BUSFAULT
) {
110 cpu_abort(cs
, "CRIS: Illegal recursive bus fault."
111 "addr=%" VADDR_PRIx
" access_type=%d\n",
112 address
, access_type
);
115 env
->pregs
[PR_EDA
] = address
;
116 cs
->exception_index
= EXCP_BUSFAULT
;
117 env
->fault_vector
= res
.bf_vec
;
119 if (cpu_restore_state(cs
, retaddr
, true)) {
120 /* Evaluate flags after retranslation. */
121 helper_top_evaluate_flags(env
);
127 void crisv10_cpu_do_interrupt(CPUState
*cs
)
129 CRISCPU
*cpu
= CRIS_CPU(cs
);
130 CPUCRISState
*env
= &cpu
->env
;
133 D_LOG("exception index=%d interrupt_req=%d\n",
135 cs
->interrupt_request
);
138 /* CRISv10 never takes interrupts while in a delay-slot. */
139 cpu_abort(cs
, "CRIS: Interrupt on delay-slot\n");
142 assert(!(env
->pregs
[PR_CCS
] & PFIX_FLAG
));
143 switch (cs
->exception_index
) {
145 /* These exceptions are genereated by the core itself.
146 ERP should point to the insn following the brk. */
147 ex_vec
= env
->trap_vector
;
148 env
->pregs
[PRV10_BRP
] = env
->pc
;
152 /* NMI is hardwired to vector zero. */
154 env
->pregs
[PR_CCS
] &= ~M_FLAG_V10
;
155 env
->pregs
[PRV10_BRP
] = env
->pc
;
159 cpu_abort(cs
, "Unhandled busfault");
163 /* The interrupt controller gives us the vector. */
164 ex_vec
= env
->interrupt_vector
;
165 /* Normal interrupts are taken between
166 TB's. env->pc is valid here. */
167 env
->pregs
[PR_ERP
] = env
->pc
;
171 if (env
->pregs
[PR_CCS
] & U_FLAG
) {
172 /* Swap stack pointers. */
173 env
->pregs
[PR_USP
] = env
->regs
[R_SP
];
174 env
->regs
[R_SP
] = env
->ksp
;
177 /* Now that we are in kernel mode, load the handlers address. */
178 env
->pc
= cpu_ldl_code(env
, env
->pregs
[PR_EBP
] + ex_vec
* 4);
180 env
->pregs
[PR_CCS
] |= F_FLAG_V10
; /* set F. */
182 qemu_log_mask(CPU_LOG_INT
, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
183 __func__
, env
->pc
, ex_vec
,
189 void cris_cpu_do_interrupt(CPUState
*cs
)
191 CRISCPU
*cpu
= CRIS_CPU(cs
);
192 CPUCRISState
*env
= &cpu
->env
;
195 D_LOG("exception index=%d interrupt_req=%d\n",
197 cs
->interrupt_request
);
199 switch (cs
->exception_index
) {
201 /* These exceptions are genereated by the core itself.
202 ERP should point to the insn following the brk. */
203 ex_vec
= env
->trap_vector
;
204 env
->pregs
[PR_ERP
] = env
->pc
;
208 /* NMI is hardwired to vector zero. */
210 env
->pregs
[PR_CCS
] &= ~M_FLAG_V32
;
211 env
->pregs
[PR_NRP
] = env
->pc
;
215 ex_vec
= env
->fault_vector
;
216 env
->pregs
[PR_ERP
] = env
->pc
;
220 /* The interrupt controller gives us the vector. */
221 ex_vec
= env
->interrupt_vector
;
222 /* Normal interrupts are taken between
223 TB's. env->pc is valid here. */
224 env
->pregs
[PR_ERP
] = env
->pc
;
228 /* Fill in the IDX field. */
229 env
->pregs
[PR_EXS
] = (ex_vec
& 0xff) << 8;
232 D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
233 " ERP=%x pid=%x ccs=%x cc=%d %x\n",
234 ex_vec
, env
->pc
, env
->dslot
,
236 env
->pregs
[PR_ERP
], env
->pregs
[PR_PID
],
238 env
->cc_op
, env
->cc_mask
);
239 /* We loose the btarget, btaken state here so rexec the
241 env
->pregs
[PR_ERP
] -= env
->dslot
;
242 /* Exception starts with dslot cleared. */
246 if (env
->pregs
[PR_CCS
] & U_FLAG
) {
247 /* Swap stack pointers. */
248 env
->pregs
[PR_USP
] = env
->regs
[R_SP
];
249 env
->regs
[R_SP
] = env
->ksp
;
252 /* Apply the CRIS CCS shift. Clears U if set. */
255 /* Now that we are in kernel mode, load the handlers address.
256 This load may not fault, real hw leaves that behaviour as
258 env
->pc
= cpu_ldl_code(env
, env
->pregs
[PR_EBP
] + ex_vec
* 4);
260 /* Clear the excption_index to avoid spurios hw_aborts for recursive
262 cs
->exception_index
= -1;
264 D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
265 __func__
, env
->pc
, ex_vec
,
271 hwaddr
cris_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
273 CRISCPU
*cpu
= CRIS_CPU(cs
);
275 struct cris_mmu_result res
;
278 miss
= cris_mmu_translate(&res
, &cpu
->env
, addr
, 0, 0, 1);
279 /* If D TLB misses, try I TLB. */
281 miss
= cris_mmu_translate(&res
, &cpu
->env
, addr
, 2, 0, 1);
287 D(fprintf(stderr
, "%s %x -> %x\n", __func__
, addr
, phy
));
292 bool cris_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
294 CPUClass
*cc
= CPU_GET_CLASS(cs
);
295 CRISCPU
*cpu
= CRIS_CPU(cs
);
296 CPUCRISState
*env
= &cpu
->env
;
299 if (interrupt_request
& CPU_INTERRUPT_HARD
300 && (env
->pregs
[PR_CCS
] & I_FLAG
)
301 && !env
->locked_irq
) {
302 cs
->exception_index
= EXCP_IRQ
;
303 cc
->tcg_ops
->do_interrupt(cs
);
306 if (interrupt_request
& CPU_INTERRUPT_NMI
) {
307 unsigned int m_flag_archval
;
308 if (env
->pregs
[PR_VR
] < 32) {
309 m_flag_archval
= M_FLAG_V10
;
311 m_flag_archval
= M_FLAG_V32
;
313 if ((env
->pregs
[PR_CCS
] & m_flag_archval
)) {
314 cs
->exception_index
= EXCP_NMI
;
315 cc
->tcg_ops
->do_interrupt(cs
);