hw/s390x/s390-pci-bus.h

   1 /*
   2  * s390 PCI BUS definitions
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #ifndef HW_S390_PCI_BUS_H
  15 #define HW_S390_PCI_BUS_H
  16
  17 #include <hw/pci/pci.h>
  18 #include <hw/pci/pci_host.h>
  19 #include "hw/s390x/sclp.h"
  20 #include "hw/s390x/s390_flic.h"
  21 #include "hw/s390x/css.h"
  22
  23 #define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
  24 #define FH_VIRT 0x00ff0000
  25 #define ENABLE_BIT_OFFSET 31
  26 #define S390_PCIPT_ADAPTER 2
  27
  28 #define S390_PCI_HOST_BRIDGE(obj) \
  29     OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE)
  30
  31 #define HP_EVENT_TO_CONFIGURED        0x0301
  32 #define HP_EVENT_RESERVED_TO_STANDBY  0x0302
  33 #define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
  34 #define HP_EVENT_STANDBY_TO_RESERVED  0x0308
  35
  36 #define ERR_EVENT_INVALAS 0x1
  37 #define ERR_EVENT_OORANGE 0x2
  38 #define ERR_EVENT_INVALTF 0x3
  39 #define ERR_EVENT_TPROTE  0x4
  40 #define ERR_EVENT_APROTE  0x5
  41 #define ERR_EVENT_KEYE    0x6
  42 #define ERR_EVENT_INVALTE 0x7
  43 #define ERR_EVENT_INVALTL 0x8
  44 #define ERR_EVENT_TT      0x9
  45 #define ERR_EVENT_INVALMS 0xa
  46 #define ERR_EVENT_SERR    0xb
  47 #define ERR_EVENT_NOMSI   0x10
  48 #define ERR_EVENT_INVALBV 0x11
  49 #define ERR_EVENT_AIBV    0x12
  50 #define ERR_EVENT_AIRERR  0x13
  51 #define ERR_EVENT_FMBA    0x2a
  52 #define ERR_EVENT_FMBUP   0x2b
  53 #define ERR_EVENT_FMBPRO  0x2c
  54 #define ERR_EVENT_CCONF   0x30
  55 #define ERR_EVENT_SERVAC  0x3a
  56 #define ERR_EVENT_PERMERR 0x3b
  57
  58 #define ERR_EVENT_Q_BIT 0x2
  59 #define ERR_EVENT_MVN_OFFSET 16
  60
  61 #define ZPCI_MSI_VEC_BITS 11
  62 #define ZPCI_MSI_VEC_MASK 0x7ff
  63
  64 #define ZPCI_MSI_ADDR  0xfe00000000000000ULL
  65 #define ZPCI_SDMA_ADDR 0x100000000ULL
  66 #define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
  67
  68 #define PAGE_SHIFT      12
  69 #define PAGE_MASK       (~(PAGE_SIZE-1))
  70 #define PAGE_DEFAULT_ACC        0
  71 #define PAGE_DEFAULT_KEY        (PAGE_DEFAULT_ACC << 4)
  72
  73 /* I/O Translation Anchor (IOTA) */
  74 enum ZpciIoatDtype {
  75     ZPCI_IOTA_STO = 0,
  76     ZPCI_IOTA_RTTO = 1,
  77     ZPCI_IOTA_RSTO = 2,
  78     ZPCI_IOTA_RFTO = 3,
  79     ZPCI_IOTA_PFAA = 4,
  80     ZPCI_IOTA_IOPFAA = 5,
  81     ZPCI_IOTA_IOPTO = 7
  82 };
  83
  84 #define ZPCI_IOTA_IOT_ENABLED           0x800ULL
  85 #define ZPCI_IOTA_DT_ST                 (ZPCI_IOTA_STO  << 2)
  86 #define ZPCI_IOTA_DT_RT                 (ZPCI_IOTA_RTTO << 2)
  87 #define ZPCI_IOTA_DT_RS                 (ZPCI_IOTA_RSTO << 2)
  88 #define ZPCI_IOTA_DT_RF                 (ZPCI_IOTA_RFTO << 2)
  89 #define ZPCI_IOTA_DT_PF                 (ZPCI_IOTA_PFAA << 2)
  90 #define ZPCI_IOTA_FS_4K                 0
  91 #define ZPCI_IOTA_FS_1M                 1
  92 #define ZPCI_IOTA_FS_2G                 2
  93 #define ZPCI_KEY                        (PAGE_DEFAULT_KEY << 5)
  94
  95 #define ZPCI_IOTA_STO_FLAG  (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
  96 #define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
  97 #define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
  98 #define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
  99 #define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
 100                              ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
 101
 102 /* I/O Region and segment tables */
 103 #define ZPCI_INDEX_MASK         0x7ffULL
 104
 105 #define ZPCI_TABLE_TYPE_MASK    0xc
 106 #define ZPCI_TABLE_TYPE_RFX     0xc
 107 #define ZPCI_TABLE_TYPE_RSX     0x8
 108 #define ZPCI_TABLE_TYPE_RTX     0x4
 109 #define ZPCI_TABLE_TYPE_SX      0x0
 110
 111 #define ZPCI_TABLE_LEN_RFX      0x3
 112 #define ZPCI_TABLE_LEN_RSX      0x3
 113 #define ZPCI_TABLE_LEN_RTX      0x3
 114
 115 #define ZPCI_TABLE_OFFSET_MASK  0xc0
 116 #define ZPCI_TABLE_SIZE         0x4000
 117 #define ZPCI_TABLE_ALIGN        ZPCI_TABLE_SIZE
 118 #define ZPCI_TABLE_ENTRY_SIZE   (sizeof(unsigned long))
 119 #define ZPCI_TABLE_ENTRIES      (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
 120
 121 #define ZPCI_TABLE_BITS         11
 122 #define ZPCI_PT_BITS            8
 123 #define ZPCI_ST_SHIFT           (ZPCI_PT_BITS + PAGE_SHIFT)
 124 #define ZPCI_RT_SHIFT           (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
 125
 126 #define ZPCI_RTE_FLAG_MASK      0x3fffULL
 127 #define ZPCI_RTE_ADDR_MASK      (~ZPCI_RTE_FLAG_MASK)
 128 #define ZPCI_STE_FLAG_MASK      0x7ffULL
 129 #define ZPCI_STE_ADDR_MASK      (~ZPCI_STE_FLAG_MASK)
 130
 131 /* I/O Page tables */
 132 #define ZPCI_PTE_VALID_MASK             0x400
 133 #define ZPCI_PTE_INVALID                0x400
 134 #define ZPCI_PTE_VALID                  0x000
 135 #define ZPCI_PT_SIZE                    0x800
 136 #define ZPCI_PT_ALIGN                   ZPCI_PT_SIZE
 137 #define ZPCI_PT_ENTRIES                 (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
 138 #define ZPCI_PT_MASK                    (ZPCI_PT_ENTRIES - 1)
 139
 140 #define ZPCI_PTE_FLAG_MASK              0xfffULL
 141 #define ZPCI_PTE_ADDR_MASK              (~ZPCI_PTE_FLAG_MASK)
 142
 143 /* Shared bits */
 144 #define ZPCI_TABLE_VALID                0x00
 145 #define ZPCI_TABLE_INVALID              0x20
 146 #define ZPCI_TABLE_PROTECTED            0x200
 147 #define ZPCI_TABLE_UNPROTECTED          0x000
 148
 149 #define ZPCI_TABLE_VALID_MASK           0x20
 150 #define ZPCI_TABLE_PROT_MASK            0x200
 151
 152 typedef struct SeiContainer {
 153     QTAILQ_ENTRY(SeiContainer) link;
 154     uint32_t fid;
 155     uint32_t fh;
 156     uint8_t cc;
 157     uint16_t pec;
 158     uint64_t faddr;
 159     uint32_t e;
 160 } SeiContainer;
 161
 162 typedef struct PciCcdfErr {
 163     uint32_t reserved1;
 164     uint32_t fh;
 165     uint32_t fid;
 166     uint32_t e;
 167     uint64_t faddr;
 168     uint32_t reserved3;
 169     uint16_t reserved4;
 170     uint16_t pec;
 171 } QEMU_PACKED PciCcdfErr;
 172
 173 typedef struct PciCcdfAvail {
 174     uint32_t reserved1;
 175     uint32_t fh;
 176     uint32_t fid;
 177     uint32_t reserved2;
 178     uint32_t reserved3;
 179     uint32_t reserved4;
 180     uint32_t reserved5;
 181     uint16_t reserved6;
 182     uint16_t pec;
 183 } QEMU_PACKED PciCcdfAvail;
 184
 185 typedef struct ChscSeiNt2Res {
 186     uint16_t length;
 187     uint16_t code;
 188     uint16_t reserved1;
 189     uint8_t reserved2;
 190     uint8_t nt;
 191     uint8_t flags;
 192     uint8_t reserved3;
 193     uint8_t reserved4;
 194     uint8_t cc;
 195     uint32_t reserved5[13];
 196     uint8_t ccdf[4016];
 197 } QEMU_PACKED ChscSeiNt2Res;
 198
 199 typedef struct PciCfgSccb {
 200         SCCBHeader header;
 201         uint8_t atype;
 202         uint8_t reserved1;
 203         uint16_t reserved2;
 204         uint32_t aid;
 205 } QEMU_PACKED PciCfgSccb;
 206
 207 typedef struct S390MsixInfo {
 208     bool available;
 209     uint8_t table_bar;
 210     uint8_t pba_bar;
 211     uint16_t entries;
 212     uint32_t table_offset;
 213     uint32_t pba_offset;
 214 } S390MsixInfo;
 215
 216 typedef struct S390PCIBusDevice {
 217     PCIDevice *pdev;
 218     bool configured;
 219     bool error_state;
 220     bool lgstg_blocked;
 221     uint32_t fh;
 222     uint32_t fid;
 223     uint64_t g_iota;
 224     uint64_t pba;
 225     uint64_t pal;
 226     uint64_t fmb_addr;
 227     uint8_t isc;
 228     uint16_t noi;
 229     uint8_t sum;
 230     S390MsixInfo msix;
 231     AdapterRoutes routes;
 232     AddressSpace as;
 233     MemoryRegion mr;
 234     MemoryRegion iommu_mr;
 235 } S390PCIBusDevice;
 236
 237 typedef struct S390pciState {
 238     PCIHostState parent_obj;
 239     S390PCIBusDevice pbdev[PCI_SLOT_MAX];
 240     AddressSpace msix_notify_as;
 241     MemoryRegion msix_notify_mr;
 242     QTAILQ_HEAD(, SeiContainer) pending_sei;
 243 } S390pciState;
 244
 245 int chsc_sei_nt2_get_event(void *res);
 246 int chsc_sei_nt2_have_event(void);
 247 void s390_pci_sclp_configure(int configure, SCCB *sccb);
 248 void s390_pcihost_iommu_configure(S390PCIBusDevice *pbdev, bool enable);
 249 S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx);
 250 S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh);
 251 S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid);
 252
 253 #endif