hw/intc/arm_gic_common.c

   1 /*
   2  * ARM GIC support - common bits of emulated and KVM kernel model
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "gic_internal.h"
  22 #include "hw/arm/linux-boot-if.h"
  23
  24 static void gic_pre_save(void *opaque)
  25 {
  26     GICState *s = (GICState *)opaque;
  27     ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
  28
  29     if (c->pre_save) {
  30         c->pre_save(s);
  31     }
  32 }
  33
  34 static int gic_post_load(void *opaque, int version_id)
  35 {
  36     GICState *s = (GICState *)opaque;
  37     ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
  38
  39     if (c->post_load) {
  40         c->post_load(s);
  41     }
  42     return 0;
  43 }
  44
  45 static const VMStateDescription vmstate_gic_irq_state = {
  46     .name = "arm_gic_irq_state",
  47     .version_id = 1,
  48     .minimum_version_id = 1,
  49     .fields = (VMStateField[]) {
  50         VMSTATE_UINT8(enabled, gic_irq_state),
  51         VMSTATE_UINT8(pending, gic_irq_state),
  52         VMSTATE_UINT8(active, gic_irq_state),
  53         VMSTATE_UINT8(level, gic_irq_state),
  54         VMSTATE_BOOL(model, gic_irq_state),
  55         VMSTATE_BOOL(edge_trigger, gic_irq_state),
  56         VMSTATE_UINT8(group, gic_irq_state),
  57         VMSTATE_END_OF_LIST()
  58     }
  59 };
  60
  61 static const VMStateDescription vmstate_gic = {
  62     .name = "arm_gic",
  63     .version_id = 12,
  64     .minimum_version_id = 12,
  65     .pre_save = gic_pre_save,
  66     .post_load = gic_post_load,
  67     .fields = (VMStateField[]) {
  68         VMSTATE_UINT32(ctlr, GICState),
  69         VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU),
  70         VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
  71                              vmstate_gic_irq_state, gic_irq_state),
  72         VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
  73         VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
  74         VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
  75         VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
  76         VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU),
  77         VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU),
  78         VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
  79         VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU),
  80         VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU),
  81         VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
  82         VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU),
  83         VMSTATE_END_OF_LIST()
  84     }
  85 };
  86
  87 void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
  88                             const MemoryRegionOps *ops)
  89 {
  90     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
  91     int i = s->num_irq - GIC_INTERNAL;
  92
  93     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
  94      * GPIO array layout is thus:
  95      *  [0..N-1] SPIs
  96      *  [N..N+31] PPIs for CPU 0
  97      *  [N+32..N+63] PPIs for CPU 1
  98      *   ...
  99      */
 100     if (s->revision != REV_NVIC) {
 101         i += (GIC_INTERNAL * s->num_cpu);
 102     }
 103     qdev_init_gpio_in(DEVICE(s), handler, i);
 104
 105     for (i = 0; i < s->num_cpu; i++) {
 106         sysbus_init_irq(sbd, &s->parent_irq[i]);
 107     }
 108     for (i = 0; i < s->num_cpu; i++) {
 109         sysbus_init_irq(sbd, &s->parent_fiq[i]);
 110     }
 111
 112     /* Distributor */
 113     memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);
 114     sysbus_init_mmio(sbd, &s->iomem);
 115
 116     if (s->revision != REV_NVIC) {
 117         /* This is the main CPU interface "for this core". It is always
 118          * present because it is required by both software emulation and KVM.
 119          * NVIC is not handled here because its CPU interface is different,
 120          * neither it can use KVM.
 121          */
 122         memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL,
 123                               s, "gic_cpu", s->revision == 2 ? 0x1000 : 0x100);
 124         sysbus_init_mmio(sbd, &s->cpuiomem[0]);
 125     }
 126 }
 127
 128 static void arm_gic_common_realize(DeviceState *dev, Error **errp)
 129 {
 130     GICState *s = ARM_GIC_COMMON(dev);
 131     int num_irq = s->num_irq;
 132
 133     if (s->num_cpu > GIC_NCPU) {
 134         error_setg(errp, "requested %u CPUs exceeds GIC maximum %d",
 135                    s->num_cpu, GIC_NCPU);
 136         return;
 137     }
 138     s->num_irq += GIC_BASE_IRQ;
 139     if (s->num_irq > GIC_MAXIRQ) {
 140         error_setg(errp,
 141                    "requested %u interrupt lines exceeds GIC maximum %d",
 142                    num_irq, GIC_MAXIRQ);
 143         return;
 144     }
 145     /* ITLinesNumber is represented as (N / 32) - 1 (see
 146      * gic_dist_readb) so this is an implementation imposed
 147      * restriction, not an architectural one:
 148      */
 149     if (s->num_irq < 32 || (s->num_irq % 32)) {
 150         error_setg(errp,
 151                    "%d interrupt lines unsupported: not divisible by 32",
 152                    num_irq);
 153         return;
 154     }
 155
 156     if (s->security_extn &&
 157         (s->revision == REV_11MPCORE || s->revision == REV_NVIC)) {
 158         error_setg(errp, "this GIC revision does not implement "
 159                    "the security extensions");
 160         return;
 161     }
 162 }
 163
 164 static void arm_gic_common_reset(DeviceState *dev)
 165 {
 166     GICState *s = ARM_GIC_COMMON(dev);
 167     int i, j;
 168     int resetprio;
 169
 170     /* If we're resetting a TZ-aware GIC as if secure firmware
 171      * had set it up ready to start a kernel in non-secure,
 172      * we need to set interrupt priorities to a "zero for the
 173      * NS view" value. This is particularly critical for the
 174      * priority_mask[] values, because if they are zero then NS
 175      * code cannot ever rewrite the priority to anything else.
 176      */
 177     if (s->security_extn && s->irq_reset_nonsecure) {
 178         resetprio = 0x80;
 179     } else {
 180         resetprio = 0;
 181     }
 182
 183     memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
 184     for (i = 0 ; i < s->num_cpu; i++) {
 185         if (s->revision == REV_11MPCORE) {
 186             s->priority_mask[i] = 0xf0;
 187         } else {
 188             s->priority_mask[i] = resetprio;
 189         }
 190         s->current_pending[i] = 1023;
 191         s->running_priority[i] = 0x100;
 192         s->cpu_ctlr[i] = 0;
 193         s->bpr[i] = GIC_MIN_BPR;
 194         s->abpr[i] = GIC_MIN_ABPR;
 195         for (j = 0; j < GIC_INTERNAL; j++) {
 196             s->priority1[j][i] = resetprio;
 197         }
 198         for (j = 0; j < GIC_NR_SGIS; j++) {
 199             s->sgi_pending[j][i] = 0;
 200         }
 201     }
 202     for (i = 0; i < GIC_NR_SGIS; i++) {
 203         GIC_SET_ENABLED(i, ALL_CPU_MASK);
 204         GIC_SET_EDGE_TRIGGER(i);
 205     }
 206
 207     for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
 208         s->priority2[i] = resetprio;
 209     }
 210
 211     for (i = 0; i < GIC_MAXIRQ; i++) {
 212         /* For uniprocessor GICs all interrupts always target the sole CPU */
 213         if (s->num_cpu == 1) {
 214             s->irq_target[i] = 1;
 215         } else {
 216             s->irq_target[i] = 0;
 217         }
 218     }
 219     if (s->security_extn && s->irq_reset_nonsecure) {
 220         for (i = 0; i < GIC_MAXIRQ; i++) {
 221             GIC_SET_GROUP(i, ALL_CPU_MASK);
 222         }
 223     }
 224
 225     s->ctlr = 0;
 226 }
 227
 228 static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
 229                                       bool secure_boot)
 230 {
 231     GICState *s = ARM_GIC_COMMON(obj);
 232
 233     if (s->security_extn && !secure_boot) {
 234         /* We're directly booting a kernel into NonSecure. If this GIC
 235          * implements the security extensions then we must configure it
 236          * to have all the interrupts be NonSecure (this is a job that
 237          * is done by the Secure boot firmware in real hardware, and in
 238          * this mode QEMU is acting as a minimalist firmware-and-bootloader
 239          * equivalent).
 240          */
 241         s->irq_reset_nonsecure = true;
 242     }
 243 }
 244
 245 static Property arm_gic_common_properties[] = {
 246     DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
 247     DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
 248     /* Revision can be 1 or 2 for GIC architecture specification
 249      * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
 250      * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
 251      */
 252     DEFINE_PROP_UINT32("revision", GICState, revision, 1),
 253     /* True if the GIC should implement the security extensions */
 254     DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
 255     DEFINE_PROP_END_OF_LIST(),
 256 };
 257
 258 static void arm_gic_common_class_init(ObjectClass *klass, void *data)
 259 {
 260     DeviceClass *dc = DEVICE_CLASS(klass);
 261     ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
 262
 263     dc->reset = arm_gic_common_reset;
 264     dc->realize = arm_gic_common_realize;
 265     dc->props = arm_gic_common_properties;
 266     dc->vmsd = &vmstate_gic;
 267     albifc->arm_linux_init = arm_gic_common_linux_init;
 268 }
 269
 270 static const TypeInfo arm_gic_common_type = {
 271     .name = TYPE_ARM_GIC_COMMON,
 272     .parent = TYPE_SYS_BUS_DEVICE,
 273     .instance_size = sizeof(GICState),
 274     .class_size = sizeof(ARMGICCommonClass),
 275     .class_init = arm_gic_common_class_init,
 276     .abstract = true,
 277     .interfaces = (InterfaceInfo []) {
 278         { TYPE_ARM_LINUX_BOOT_IF },
 279         { },
 280     },
 281 };
 282
 283 static void register_types(void)
 284 {
 285     type_register_static(&arm_gic_common_type);
 286 }
 287
 288 type_init(register_types)