2 * CRISv10 emulation for qemu: main translation routines.
4 * Copyright (c) 2010 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "crisv10-decode.h"
24 static const char *regnames_v10
[] =
26 "$r0", "$r1", "$r2", "$r3",
27 "$r4", "$r5", "$r6", "$r7",
28 "$r8", "$r9", "$r10", "$r11",
29 "$r12", "$r13", "$sp", "$pc",
32 static const char *pregnames_v10
[] =
34 "$bz", "$vr", "$p2", "$p3",
35 "$wz", "$ccr", "$p6-prefix", "$mof",
36 "$dz", "$ibr", "$irp", "$srp",
37 "$bar", "$dccr", "$brp", "$usp",
40 /* We need this table to handle preg-moves with implicit width. */
41 static int preg_sizes_v10
[] = {
52 static inline int dec10_size(unsigned int size
)
60 static inline void cris_illegal_insn(DisasContext
*dc
)
62 qemu_log_mask(LOG_GUEST_ERROR
, "illegal insn at pc=%x\n", dc
->pc
);
63 t_gen_raise_exception(EXCP_BREAK
);
66 static void gen_store_v10_conditional(DisasContext
*dc
, TCGv addr
, TCGv val
,
67 unsigned int size
, int mem_index
)
69 TCGLabel
*l1
= gen_new_label();
70 TCGv taddr
= tcg_temp_local_new();
71 TCGv tval
= tcg_temp_local_new();
72 TCGv t1
= tcg_temp_local_new();
74 cris_evaluate_flags(dc
);
76 tcg_gen_mov_tl(taddr
, addr
);
77 tcg_gen_mov_tl(tval
, val
);
79 /* Store only if F flag isn't set */
80 tcg_gen_andi_tl(t1
, cpu_PR
[PR_CCS
], F_FLAG_V10
);
81 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
83 tcg_gen_qemu_st8(tval
, taddr
, mem_index
);
84 } else if (size
== 2) {
85 tcg_gen_qemu_st16(tval
, taddr
, mem_index
);
87 tcg_gen_qemu_st32(tval
, taddr
, mem_index
);
90 tcg_gen_shri_tl(t1
, t1
, 1); /* shift F to P position */
91 tcg_gen_or_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], t1
); /*P=F*/
97 static void gen_store_v10(DisasContext
*dc
, TCGv addr
, TCGv val
,
100 int mem_index
= cpu_mmu_index(&dc
->cpu
->env
, false);
102 /* If we get a fault on a delayslot we must keep the jmp state in
103 the cpu-state to be able to re-execute the jmp. */
104 if (dc
->delayed_branch
== 1) {
105 cris_store_direct_jmp(dc
);
108 /* Conditional writes. We only support the kind were X is known
109 at translation time. */
110 if (dc
->flagx_known
&& dc
->flags_x
) {
111 gen_store_v10_conditional(dc
, addr
, val
, size
, mem_index
);
116 tcg_gen_qemu_st8(val
, addr
, mem_index
);
117 } else if (size
== 2) {
118 tcg_gen_qemu_st16(val
, addr
, mem_index
);
120 tcg_gen_qemu_st32(val
, addr
, mem_index
);
125 /* Prefix flag and register are used to handle the more complex
127 static void cris_set_prefix(DisasContext
*dc
)
129 dc
->clear_prefix
= 0;
130 dc
->tb_flags
|= PFIX_FLAG
;
131 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], PFIX_FLAG
);
133 /* prefix insns don't clear the x flag. */
138 static void crisv10_prepare_memaddr(DisasContext
*dc
,
139 TCGv addr
, unsigned int size
)
141 if (dc
->tb_flags
& PFIX_FLAG
) {
142 tcg_gen_mov_tl(addr
, cpu_PR
[PR_PREFIX
]);
144 tcg_gen_mov_tl(addr
, cpu_R
[dc
->src
]);
148 static unsigned int crisv10_post_memaddr(DisasContext
*dc
, unsigned int size
)
150 unsigned int insn_len
= 0;
152 if (dc
->tb_flags
& PFIX_FLAG
) {
153 if (dc
->mode
== CRISV10_MODE_AUTOINC
) {
154 tcg_gen_mov_tl(cpu_R
[dc
->src
], cpu_PR
[PR_PREFIX
]);
157 if (dc
->mode
== CRISV10_MODE_AUTOINC
) {
159 insn_len
+= size
& ~1;
161 tcg_gen_addi_tl(cpu_R
[dc
->src
], cpu_R
[dc
->src
], size
);
168 static int dec10_prep_move_m(CPUCRISState
*env
, DisasContext
*dc
,
169 int s_ext
, int memsize
, TCGv dst
)
177 is_imm
= rs
== 15 && !(dc
->tb_flags
& PFIX_FLAG
);
178 LOG_DIS("rs=%d rd=%d is_imm=%d mode=%d pfix=%d\n",
179 rs
, dc
->dst
, is_imm
, dc
->mode
, dc
->tb_flags
& PFIX_FLAG
);
181 /* Load [$rs] onto T1. */
186 imm
= cpu_ldsb_code(env
, dc
->pc
+ 2);
188 imm
= cpu_ldsw_code(env
, dc
->pc
+ 2);
191 imm
= cpu_ldub_code(env
, dc
->pc
+ 2);
193 imm
= cpu_lduw_code(env
, dc
->pc
+ 2);
196 imm
= cpu_ldl_code(env
, dc
->pc
+ 2);
198 tcg_gen_movi_tl(dst
, imm
);
200 if (dc
->mode
== CRISV10_MODE_AUTOINC
) {
204 tcg_gen_addi_tl(cpu_R
[15], cpu_R
[15], insn_len
);
209 addr
= tcg_temp_new();
210 cris_flush_cc_state(dc
);
211 crisv10_prepare_memaddr(dc
, addr
, memsize
);
212 gen_load(dc
, dst
, addr
, memsize
, 0);
214 t_gen_sext(dst
, dst
, memsize
);
216 t_gen_zext(dst
, dst
, memsize
);
217 insn_len
+= crisv10_post_memaddr(dc
, memsize
);
221 if (dc
->mode
== CRISV10_MODE_INDIRECT
&& (dc
->tb_flags
& PFIX_FLAG
)) {
227 static unsigned int dec10_quick_imm(DisasContext
*dc
)
233 imm
= dc
->ir
& ((1 << 6) - 1);
234 simm
= (int8_t) (imm
<< 2);
236 switch (dc
->opcode
) {
237 case CRISV10_QIMM_BDAP_R0
:
238 case CRISV10_QIMM_BDAP_R1
:
239 case CRISV10_QIMM_BDAP_R2
:
240 case CRISV10_QIMM_BDAP_R3
:
241 simm
= (int8_t)dc
->ir
;
242 LOG_DIS("bdap %d $r%d\n", simm
, dc
->dst
);
243 LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
244 dc
->pc
, dc
->mode
, dc
->opcode
, dc
->src
, dc
->dst
);
247 tcg_gen_movi_tl(cpu_PR
[PR_PREFIX
], dc
->pc
+ 2 + simm
);
249 tcg_gen_addi_tl(cpu_PR
[PR_PREFIX
], cpu_R
[dc
->dst
], simm
);
253 case CRISV10_QIMM_MOVEQ
:
254 LOG_DIS("moveq %d, $r%d\n", simm
, dc
->dst
);
256 cris_cc_mask(dc
, CC_MASK_NZVC
);
257 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->dst
],
258 cpu_R
[dc
->dst
], tcg_const_tl(simm
), 4);
260 case CRISV10_QIMM_CMPQ
:
261 LOG_DIS("cmpq %d, $r%d\n", simm
, dc
->dst
);
263 cris_cc_mask(dc
, CC_MASK_NZVC
);
264 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->dst
],
265 cpu_R
[dc
->dst
], tcg_const_tl(simm
), 4);
267 case CRISV10_QIMM_ADDQ
:
268 LOG_DIS("addq %d, $r%d\n", imm
, dc
->dst
);
270 cris_cc_mask(dc
, CC_MASK_NZVC
);
271 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->dst
],
272 cpu_R
[dc
->dst
], tcg_const_tl(imm
), 4);
274 case CRISV10_QIMM_ANDQ
:
275 LOG_DIS("andq %d, $r%d\n", simm
, dc
->dst
);
277 cris_cc_mask(dc
, CC_MASK_NZVC
);
278 cris_alu(dc
, CC_OP_AND
, cpu_R
[dc
->dst
],
279 cpu_R
[dc
->dst
], tcg_const_tl(simm
), 4);
281 case CRISV10_QIMM_ASHQ
:
282 LOG_DIS("ashq %d, $r%d\n", simm
, dc
->dst
);
284 cris_cc_mask(dc
, CC_MASK_NZVC
);
288 cris_alu(dc
, CC_OP_ASR
, cpu_R
[dc
->dst
],
289 cpu_R
[dc
->dst
], tcg_const_tl(imm
), 4);
292 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
293 gen_helper_btst(cpu_PR
[PR_CCS
], cpu_env
, cpu_R
[dc
->dst
],
294 tcg_const_tl(imm
), cpu_PR
[PR_CCS
]);
297 case CRISV10_QIMM_LSHQ
:
298 LOG_DIS("lshq %d, $r%d\n", simm
, dc
->dst
);
301 if (imm
& (1 << 5)) {
305 cris_cc_mask(dc
, CC_MASK_NZVC
);
306 cris_alu(dc
, op
, cpu_R
[dc
->dst
],
307 cpu_R
[dc
->dst
], tcg_const_tl(imm
), 4);
309 case CRISV10_QIMM_SUBQ
:
310 LOG_DIS("subq %d, $r%d\n", imm
, dc
->dst
);
312 cris_cc_mask(dc
, CC_MASK_NZVC
);
313 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->dst
],
314 cpu_R
[dc
->dst
], tcg_const_tl(imm
), 4);
316 case CRISV10_QIMM_ORQ
:
317 LOG_DIS("andq %d, $r%d\n", simm
, dc
->dst
);
319 cris_cc_mask(dc
, CC_MASK_NZVC
);
320 cris_alu(dc
, CC_OP_OR
, cpu_R
[dc
->dst
],
321 cpu_R
[dc
->dst
], tcg_const_tl(simm
), 4);
324 case CRISV10_QIMM_BCC_R0
:
325 case CRISV10_QIMM_BCC_R1
:
326 case CRISV10_QIMM_BCC_R2
:
327 case CRISV10_QIMM_BCC_R3
:
329 /* bit 0 is a sign bit. */
331 imm
|= 0xffffff00; /* sign extend. */
332 imm
&= ~1; /* get rid of the sign bit. */
335 LOG_DIS("b%s %d\n", cc_name(dc
->cond
), imm
);
338 cris_prepare_cc_branch(dc
, imm
, dc
->cond
);
342 LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
343 dc
->pc
, dc
->mode
, dc
->opcode
, dc
->src
, dc
->dst
);
344 cpu_abort(CPU(dc
->cpu
), "Unhandled quickimm\n");
350 static unsigned int dec10_setclrf(DisasContext
*dc
)
353 unsigned int set
= ~dc
->opcode
& 1;
355 flags
= EXTRACT_FIELD(dc
->ir
, 0, 3)
356 | (EXTRACT_FIELD(dc
->ir
, 12, 15) << 4);
357 LOG_DIS("%s set=%d flags=%x\n", __func__
, set
, flags
);
360 if (flags
& X_FLAG
) {
363 dc
->flags_x
= X_FLAG
;
368 cris_evaluate_flags (dc
);
369 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
370 cris_update_cc_x(dc
);
371 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
374 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], flags
);
376 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
],
377 ~(flags
|F_FLAG_V10
|P_FLAG_V10
));
380 dc
->flags_uptodate
= 1;
386 static inline void dec10_reg_prep_sext(DisasContext
*dc
, int size
, int sext
,
387 TCGv dd
, TCGv ds
, TCGv sd
, TCGv ss
)
390 t_gen_sext(dd
, sd
, size
);
391 t_gen_sext(ds
, ss
, size
);
393 t_gen_zext(dd
, sd
, size
);
394 t_gen_zext(ds
, ss
, size
);
398 static void dec10_reg_alu(DisasContext
*dc
, int op
, int size
, int sext
)
402 t
[0] = tcg_temp_new();
403 t
[1] = tcg_temp_new();
404 dec10_reg_prep_sext(dc
, size
, sext
,
405 t
[0], t
[1], cpu_R
[dc
->dst
], cpu_R
[dc
->src
]);
407 if (op
== CC_OP_LSL
|| op
== CC_OP_LSR
|| op
== CC_OP_ASR
) {
408 tcg_gen_andi_tl(t
[1], t
[1], 63);
411 assert(dc
->dst
!= 15);
412 cris_alu(dc
, op
, cpu_R
[dc
->dst
], t
[0], t
[1], size
);
417 static void dec10_reg_bound(DisasContext
*dc
, int size
)
421 t
= tcg_temp_local_new();
422 t_gen_zext(t
, cpu_R
[dc
->src
], size
);
423 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->dst
], cpu_R
[dc
->dst
], t
, 4);
427 static void dec10_reg_mul(DisasContext
*dc
, int size
, int sext
)
429 int op
= sext
? CC_OP_MULS
: CC_OP_MULU
;
432 t
[0] = tcg_temp_new();
433 t
[1] = tcg_temp_new();
434 dec10_reg_prep_sext(dc
, size
, sext
,
435 t
[0], t
[1], cpu_R
[dc
->dst
], cpu_R
[dc
->src
]);
437 cris_alu(dc
, op
, cpu_R
[dc
->dst
], t
[0], t
[1], 4);
444 static void dec10_reg_movs(DisasContext
*dc
)
446 int size
= (dc
->size
& 1) + 1;
449 LOG_DIS("movx.%d $r%d, $r%d\n", size
, dc
->src
, dc
->dst
);
450 cris_cc_mask(dc
, CC_MASK_NZVC
);
454 t_gen_sext(t
, cpu_R
[dc
->src
], size
);
456 t_gen_zext(t
, cpu_R
[dc
->src
], size
);
458 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->dst
], cpu_R
[dc
->dst
], t
, 4);
462 static void dec10_reg_alux(DisasContext
*dc
, int op
)
464 int size
= (dc
->size
& 1) + 1;
467 LOG_DIS("movx.%d $r%d, $r%d\n", size
, dc
->src
, dc
->dst
);
468 cris_cc_mask(dc
, CC_MASK_NZVC
);
472 t_gen_sext(t
, cpu_R
[dc
->src
], size
);
474 t_gen_zext(t
, cpu_R
[dc
->src
], size
);
476 cris_alu(dc
, op
, cpu_R
[dc
->dst
], cpu_R
[dc
->dst
], t
, 4);
480 static void dec10_reg_mov_pr(DisasContext
*dc
)
482 LOG_DIS("move p%d r%d sz=%d\n", dc
->dst
, dc
->src
, preg_sizes_v10
[dc
->dst
]);
485 tcg_gen_mov_tl(env_btarget
, cpu_PR
[dc
->dst
]);
486 cris_prepare_jmp(dc
, JMP_INDIRECT
);
489 if (dc
->dst
== PR_CCS
) {
490 cris_evaluate_flags(dc
);
492 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->src
],
493 cpu_R
[dc
->src
], cpu_PR
[dc
->dst
], preg_sizes_v10
[dc
->dst
]);
496 static void dec10_reg_abs(DisasContext
*dc
)
500 LOG_DIS("abs $r%u, $r%u\n", dc
->src
, dc
->dst
);
502 assert(dc
->dst
!= 15);
504 tcg_gen_sari_tl(t0
, cpu_R
[dc
->src
], 31);
505 tcg_gen_xor_tl(cpu_R
[dc
->dst
], cpu_R
[dc
->src
], t0
);
506 tcg_gen_sub_tl(t0
, cpu_R
[dc
->dst
], t0
);
508 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->dst
], cpu_R
[dc
->dst
], t0
, 4);
512 static void dec10_reg_swap(DisasContext
*dc
)
516 LOG_DIS("not $r%d, $r%d\n", dc
->src
, dc
->dst
);
518 cris_cc_mask(dc
, CC_MASK_NZVC
);
520 tcg_gen_mov_tl(t0
, cpu_R
[dc
->src
]);
522 tcg_gen_not_tl(t0
, t0
);
529 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->src
], cpu_R
[dc
->src
], t0
, 4);
533 static void dec10_reg_scc(DisasContext
*dc
)
537 LOG_DIS("s%s $r%u\n", cc_name(cond
), dc
->src
);
539 gen_tst_cc(dc
, cpu_R
[dc
->src
], cond
);
540 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_R
[dc
->src
], cpu_R
[dc
->src
], 0);
545 static unsigned int dec10_reg(DisasContext
*dc
)
548 unsigned int insn_len
= 2;
549 unsigned int size
= dec10_size(dc
->size
);
553 switch (dc
->opcode
) {
554 case CRISV10_REG_MOVE_R
:
555 LOG_DIS("move.%d $r%d, $r%d\n", dc
->size
, dc
->src
, dc
->dst
);
556 cris_cc_mask(dc
, CC_MASK_NZVC
);
557 dec10_reg_alu(dc
, CC_OP_MOVE
, size
, 0);
559 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->dst
]);
560 cris_prepare_jmp(dc
, JMP_INDIRECT
);
561 dc
->delayed_branch
= 1;
564 case CRISV10_REG_MOVX
:
565 cris_cc_mask(dc
, CC_MASK_NZVC
);
568 case CRISV10_REG_ADDX
:
569 cris_cc_mask(dc
, CC_MASK_NZVC
);
570 dec10_reg_alux(dc
, CC_OP_ADD
);
572 case CRISV10_REG_SUBX
:
573 cris_cc_mask(dc
, CC_MASK_NZVC
);
574 dec10_reg_alux(dc
, CC_OP_SUB
);
576 case CRISV10_REG_ADD
:
577 LOG_DIS("add $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
578 cris_cc_mask(dc
, CC_MASK_NZVC
);
579 dec10_reg_alu(dc
, CC_OP_ADD
, size
, 0);
581 case CRISV10_REG_SUB
:
582 LOG_DIS("sub $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
583 cris_cc_mask(dc
, CC_MASK_NZVC
);
584 dec10_reg_alu(dc
, CC_OP_SUB
, size
, 0);
586 case CRISV10_REG_CMP
:
587 LOG_DIS("cmp $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
588 cris_cc_mask(dc
, CC_MASK_NZVC
);
589 dec10_reg_alu(dc
, CC_OP_CMP
, size
, 0);
591 case CRISV10_REG_BOUND
:
592 LOG_DIS("bound $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
593 cris_cc_mask(dc
, CC_MASK_NZVC
);
594 dec10_reg_bound(dc
, size
);
596 case CRISV10_REG_AND
:
597 LOG_DIS("and $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
598 cris_cc_mask(dc
, CC_MASK_NZVC
);
599 dec10_reg_alu(dc
, CC_OP_AND
, size
, 0);
601 case CRISV10_REG_ADDI
:
607 LOG_DIS("addi r%d r%d size=%d\n", dc
->src
, dc
->dst
, dc
->size
);
608 tcg_gen_shli_tl(t
, cpu_R
[dc
->dst
], dc
->size
& 3);
609 tcg_gen_add_tl(cpu_R
[dc
->src
], cpu_R
[dc
->src
], t
);
612 case CRISV10_REG_LSL
:
613 LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
614 cris_cc_mask(dc
, CC_MASK_NZVC
);
615 dec10_reg_alu(dc
, CC_OP_LSL
, size
, 0);
617 case CRISV10_REG_LSR
:
618 LOG_DIS("lsr $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
619 cris_cc_mask(dc
, CC_MASK_NZVC
);
620 dec10_reg_alu(dc
, CC_OP_LSR
, size
, 0);
622 case CRISV10_REG_ASR
:
623 LOG_DIS("asr $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
624 cris_cc_mask(dc
, CC_MASK_NZVC
);
625 dec10_reg_alu(dc
, CC_OP_ASR
, size
, 1);
628 LOG_DIS("or $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
629 cris_cc_mask(dc
, CC_MASK_NZVC
);
630 dec10_reg_alu(dc
, CC_OP_OR
, size
, 0);
632 case CRISV10_REG_NEG
:
633 LOG_DIS("neg $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
634 cris_cc_mask(dc
, CC_MASK_NZVC
);
635 dec10_reg_alu(dc
, CC_OP_NEG
, size
, 0);
637 case CRISV10_REG_BIAP
:
638 LOG_DIS("BIAP pc=%x reg %d r%d r%d size=%d\n", dc
->pc
,
639 dc
->opcode
, dc
->src
, dc
->dst
, size
);
641 case 4: tmp
= 2; break;
642 case 2: tmp
= 1; break;
643 case 1: tmp
= 0; break;
645 cpu_abort(CPU(dc
->cpu
), "Unhandled BIAP");
650 tcg_gen_shli_tl(t
, cpu_R
[dc
->dst
], tmp
);
652 tcg_gen_addi_tl(cpu_PR
[PR_PREFIX
], t
, ((dc
->pc
+2)| 1) + 1);
654 tcg_gen_add_tl(cpu_PR
[PR_PREFIX
], cpu_R
[dc
->src
], t
);
661 LOG_DIS("pc=%x reg %d r%d r%d\n", dc
->pc
,
662 dc
->opcode
, dc
->src
, dc
->dst
);
663 cpu_abort(CPU(dc
->cpu
), "Unhandled opcode");
667 switch (dc
->opcode
) {
668 case CRISV10_REG_MOVX
:
669 cris_cc_mask(dc
, CC_MASK_NZVC
);
672 case CRISV10_REG_ADDX
:
673 cris_cc_mask(dc
, CC_MASK_NZVC
);
674 dec10_reg_alux(dc
, CC_OP_ADD
);
676 case CRISV10_REG_SUBX
:
677 cris_cc_mask(dc
, CC_MASK_NZVC
);
678 dec10_reg_alux(dc
, CC_OP_SUB
);
680 case CRISV10_REG_MOVE_SPR_R
:
681 cris_evaluate_flags(dc
);
683 dec10_reg_mov_pr(dc
);
685 case CRISV10_REG_MOVE_R_SPR
:
686 LOG_DIS("move r%d p%d\n", dc
->src
, dc
->dst
);
687 cris_evaluate_flags(dc
);
688 if (dc
->src
!= 11) /* fast for srp. */
689 dc
->cpustate_changed
= 1;
690 t_gen_mov_preg_TN(dc
, dc
->dst
, cpu_R
[dc
->src
]);
692 case CRISV10_REG_SETF
:
693 case CRISV10_REG_CLEARF
:
696 case CRISV10_REG_SWAP
:
699 case CRISV10_REG_ABS
:
700 cris_cc_mask(dc
, CC_MASK_NZVC
);
704 LOG_DIS("lz $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
705 cris_cc_mask(dc
, CC_MASK_NZVC
);
706 dec10_reg_alu(dc
, CC_OP_LZ
, 4, 0);
708 case CRISV10_REG_XOR
:
709 LOG_DIS("xor $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
710 cris_cc_mask(dc
, CC_MASK_NZVC
);
711 dec10_reg_alu(dc
, CC_OP_XOR
, 4, 0);
713 case CRISV10_REG_BTST
:
714 LOG_DIS("btst $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
715 cris_cc_mask(dc
, CC_MASK_NZVC
);
716 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
717 gen_helper_btst(cpu_PR
[PR_CCS
], cpu_env
, cpu_R
[dc
->dst
],
718 cpu_R
[dc
->src
], cpu_PR
[PR_CCS
]);
720 case CRISV10_REG_DSTEP
:
721 LOG_DIS("dstep $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
722 cris_cc_mask(dc
, CC_MASK_NZVC
);
723 cris_alu(dc
, CC_OP_DSTEP
, cpu_R
[dc
->dst
],
724 cpu_R
[dc
->dst
], cpu_R
[dc
->src
], 4);
726 case CRISV10_REG_MSTEP
:
727 LOG_DIS("mstep $r%d, $r%d sz=%d\n", dc
->src
, dc
->dst
, size
);
728 cris_evaluate_flags(dc
);
729 cris_cc_mask(dc
, CC_MASK_NZVC
);
730 cris_alu(dc
, CC_OP_MSTEP
, cpu_R
[dc
->dst
],
731 cpu_R
[dc
->dst
], cpu_R
[dc
->src
], 4);
733 case CRISV10_REG_SCC
:
737 LOG_DIS("pc=%x reg %d r%d r%d\n", dc
->pc
,
738 dc
->opcode
, dc
->src
, dc
->dst
);
739 cpu_abort(CPU(dc
->cpu
), "Unhandled opcode");
746 static unsigned int dec10_ind_move_m_r(CPUCRISState
*env
, DisasContext
*dc
,
749 unsigned int insn_len
= 2;
752 LOG_DIS("%s: move.%d [$r%d], $r%d\n", __func__
,
753 size
, dc
->src
, dc
->dst
);
755 cris_cc_mask(dc
, CC_MASK_NZVC
);
757 insn_len
+= dec10_prep_move_m(env
, dc
, 0, size
, t
);
758 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->dst
], cpu_R
[dc
->dst
], t
, size
);
760 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->dst
]);
761 cris_prepare_jmp(dc
, JMP_INDIRECT
);
762 dc
->delayed_branch
= 1;
770 static unsigned int dec10_ind_move_r_m(DisasContext
*dc
, unsigned int size
)
772 unsigned int insn_len
= 2;
775 LOG_DIS("move.%d $r%d, [$r%d]\n", dc
->size
, dc
->src
, dc
->dst
);
776 addr
= tcg_temp_new();
777 crisv10_prepare_memaddr(dc
, addr
, size
);
778 gen_store_v10(dc
, addr
, cpu_R
[dc
->dst
], size
);
779 insn_len
+= crisv10_post_memaddr(dc
, size
);
784 static unsigned int dec10_ind_move_m_pr(CPUCRISState
*env
, DisasContext
*dc
)
786 unsigned int insn_len
= 2, rd
= dc
->dst
;
789 LOG_DIS("move.%d $p%d, [$r%d]\n", dc
->size
, dc
->dst
, dc
->src
);
792 addr
= tcg_temp_new();
794 insn_len
+= dec10_prep_move_m(env
, dc
, 0, 4, t
);
796 tcg_gen_mov_tl(env_btarget
, t
);
797 cris_prepare_jmp(dc
, JMP_INDIRECT
);
798 dc
->delayed_branch
= 1;
802 tcg_gen_mov_tl(cpu_PR
[rd
], t
);
803 dc
->cpustate_changed
= 1;
809 static unsigned int dec10_ind_move_pr_m(DisasContext
*dc
)
811 unsigned int insn_len
= 2, size
= preg_sizes_v10
[dc
->dst
];
814 LOG_DIS("move.%d $p%d, [$r%d]\n", dc
->size
, dc
->dst
, dc
->src
);
816 addr
= tcg_temp_new();
817 crisv10_prepare_memaddr(dc
, addr
, size
);
818 if (dc
->dst
== PR_CCS
) {
820 cris_evaluate_flags(dc
);
821 tcg_gen_andi_tl(t0
, cpu_PR
[PR_CCS
], ~PFIX_FLAG
);
822 gen_store_v10(dc
, addr
, t0
, size
);
825 gen_store_v10(dc
, addr
, cpu_PR
[dc
->dst
], size
);
828 insn_len
+= crisv10_post_memaddr(dc
, size
);
834 static void dec10_movem_r_m(DisasContext
*dc
)
836 int i
, pfix
= dc
->tb_flags
& PFIX_FLAG
;
839 LOG_DIS("%s r%d, [r%d] pi=%d ir=%x\n", __func__
,
840 dc
->dst
, dc
->src
, dc
->postinc
, dc
->ir
);
842 addr
= tcg_temp_new();
844 crisv10_prepare_memaddr(dc
, addr
, 4);
845 tcg_gen_mov_tl(t0
, addr
);
846 for (i
= dc
->dst
; i
>= 0; i
--) {
847 if ((pfix
&& dc
->mode
== CRISV10_MODE_AUTOINC
) && dc
->src
== i
) {
848 gen_store_v10(dc
, addr
, t0
, 4);
850 gen_store_v10(dc
, addr
, cpu_R
[i
], 4);
852 tcg_gen_addi_tl(addr
, addr
, 4);
855 if (pfix
&& dc
->mode
== CRISV10_MODE_AUTOINC
) {
856 tcg_gen_mov_tl(cpu_R
[dc
->src
], t0
);
859 if (!pfix
&& dc
->mode
== CRISV10_MODE_AUTOINC
) {
860 tcg_gen_mov_tl(cpu_R
[dc
->src
], addr
);
866 static void dec10_movem_m_r(DisasContext
*dc
)
868 int i
, pfix
= dc
->tb_flags
& PFIX_FLAG
;
871 LOG_DIS("%s [r%d], r%d pi=%d ir=%x\n", __func__
,
872 dc
->src
, dc
->dst
, dc
->postinc
, dc
->ir
);
874 addr
= tcg_temp_new();
876 crisv10_prepare_memaddr(dc
, addr
, 4);
877 tcg_gen_mov_tl(t0
, addr
);
878 for (i
= dc
->dst
; i
>= 0; i
--) {
879 gen_load(dc
, cpu_R
[i
], addr
, 4, 0);
880 tcg_gen_addi_tl(addr
, addr
, 4);
883 if (pfix
&& dc
->mode
== CRISV10_MODE_AUTOINC
) {
884 tcg_gen_mov_tl(cpu_R
[dc
->src
], t0
);
887 if (!pfix
&& dc
->mode
== CRISV10_MODE_AUTOINC
) {
888 tcg_gen_mov_tl(cpu_R
[dc
->src
], addr
);
894 static int dec10_ind_alu(CPUCRISState
*env
, DisasContext
*dc
,
895 int op
, unsigned int size
)
901 cris_alu_m_alloc_temps(t
);
902 insn_len
+= dec10_prep_move_m(env
, dc
, 0, size
, t
[0]);
903 cris_alu(dc
, op
, cpu_R
[dc
->dst
], cpu_R
[rd
], t
[0], size
);
905 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->dst
]);
906 cris_prepare_jmp(dc
, JMP_INDIRECT
);
907 dc
->delayed_branch
= 1;
911 cris_alu_m_free_temps(t
);
916 static int dec10_ind_bound(CPUCRISState
*env
, DisasContext
*dc
,
923 t
= tcg_temp_local_new();
924 insn_len
+= dec10_prep_move_m(env
, dc
, 0, size
, t
);
925 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->dst
], cpu_R
[rd
], t
, 4);
927 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->dst
]);
928 cris_prepare_jmp(dc
, JMP_INDIRECT
);
929 dc
->delayed_branch
= 1;
937 static int dec10_alux_m(CPUCRISState
*env
, DisasContext
*dc
, int op
)
939 unsigned int size
= (dc
->size
& 1) ? 2 : 1;
940 unsigned int sx
= !!(dc
->size
& 2);
945 LOG_DIS("addx size=%d sx=%d op=%d %d\n", size
, sx
, dc
->src
, dc
->dst
);
949 cris_cc_mask(dc
, CC_MASK_NZVC
);
950 insn_len
+= dec10_prep_move_m(env
, dc
, sx
, size
, t
);
951 cris_alu(dc
, op
, cpu_R
[dc
->dst
], cpu_R
[rd
], t
, 4);
953 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->dst
]);
954 cris_prepare_jmp(dc
, JMP_INDIRECT
);
955 dc
->delayed_branch
= 1;
963 static int dec10_dip(CPUCRISState
*env
, DisasContext
*dc
)
968 LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
969 dc
->pc
, dc
->opcode
, dc
->src
, dc
->dst
);
971 imm
= cpu_ldl_code(env
, dc
->pc
+ 2);
972 tcg_gen_movi_tl(cpu_PR
[PR_PREFIX
], imm
);
975 tcg_gen_addi_tl(cpu_R
[15], cpu_R
[15], insn_len
- 2);
977 gen_load(dc
, cpu_PR
[PR_PREFIX
], cpu_R
[dc
->src
], 4, 0);
979 tcg_gen_addi_tl(cpu_R
[dc
->src
], cpu_R
[dc
->src
], 4);
986 static int dec10_bdap_m(CPUCRISState
*env
, DisasContext
*dc
, int size
)
991 LOG_DIS("bdap_m pc=%x opcode=%d r%d r%d sz=%d\n",
992 dc
->pc
, dc
->opcode
, dc
->src
, dc
->dst
, size
);
994 assert(dc
->dst
!= 15);
996 /* 8bit embedded offset? */
997 if (!dc
->postinc
&& (dc
->ir
& (1 << 11))) {
998 int simm
= dc
->ir
& 0xff;
1000 /* cpu_abort(CPU(dc->cpu), "Unhandled opcode"); */
1001 /* sign extended. */
1002 simm
= (int8_t)simm
;
1004 tcg_gen_addi_tl(cpu_PR
[PR_PREFIX
], cpu_R
[dc
->dst
], simm
);
1006 cris_set_prefix(dc
);
1010 /* Now the rest of the modes are truly indirect. */
1011 insn_len
+= dec10_prep_move_m(env
, dc
, 1, size
, cpu_PR
[PR_PREFIX
]);
1012 tcg_gen_add_tl(cpu_PR
[PR_PREFIX
], cpu_PR
[PR_PREFIX
], cpu_R
[rd
]);
1013 cris_set_prefix(dc
);
1017 static unsigned int dec10_ind(CPUCRISState
*env
, DisasContext
*dc
)
1019 unsigned int insn_len
= 2;
1020 unsigned int size
= dec10_size(dc
->size
);
1025 if (dc
->size
!= 3) {
1026 switch (dc
->opcode
) {
1027 case CRISV10_IND_MOVE_M_R
:
1028 return dec10_ind_move_m_r(env
, dc
, size
);
1030 case CRISV10_IND_MOVE_R_M
:
1031 return dec10_ind_move_r_m(dc
, size
);
1033 case CRISV10_IND_CMP
:
1034 LOG_DIS("cmp size=%d op=%d %d\n", size
, dc
->src
, dc
->dst
);
1035 cris_cc_mask(dc
, CC_MASK_NZVC
);
1036 insn_len
+= dec10_ind_alu(env
, dc
, CC_OP_CMP
, size
);
1038 case CRISV10_IND_TEST
:
1039 LOG_DIS("test size=%d op=%d %d\n", size
, dc
->src
, dc
->dst
);
1041 cris_evaluate_flags(dc
);
1042 cris_cc_mask(dc
, CC_MASK_NZVC
);
1043 cris_alu_m_alloc_temps(t
);
1044 insn_len
+= dec10_prep_move_m(env
, dc
, 0, size
, t
[0]);
1045 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~3);
1046 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->dst
],
1047 t
[0], tcg_const_tl(0), size
);
1048 cris_alu_m_free_temps(t
);
1050 case CRISV10_IND_ADD
:
1051 LOG_DIS("add size=%d op=%d %d\n", size
, dc
->src
, dc
->dst
);
1052 cris_cc_mask(dc
, CC_MASK_NZVC
);
1053 insn_len
+= dec10_ind_alu(env
, dc
, CC_OP_ADD
, size
);
1055 case CRISV10_IND_SUB
:
1056 LOG_DIS("sub size=%d op=%d %d\n", size
, dc
->src
, dc
->dst
);
1057 cris_cc_mask(dc
, CC_MASK_NZVC
);
1058 insn_len
+= dec10_ind_alu(env
, dc
, CC_OP_SUB
, size
);
1060 case CRISV10_IND_BOUND
:
1061 LOG_DIS("bound size=%d op=%d %d\n", size
, dc
->src
, dc
->dst
);
1062 cris_cc_mask(dc
, CC_MASK_NZVC
);
1063 insn_len
+= dec10_ind_bound(env
, dc
, size
);
1065 case CRISV10_IND_AND
:
1066 LOG_DIS("and size=%d op=%d %d\n", size
, dc
->src
, dc
->dst
);
1067 cris_cc_mask(dc
, CC_MASK_NZVC
);
1068 insn_len
+= dec10_ind_alu(env
, dc
, CC_OP_AND
, size
);
1070 case CRISV10_IND_OR
:
1071 LOG_DIS("or size=%d op=%d %d\n", size
, dc
->src
, dc
->dst
);
1072 cris_cc_mask(dc
, CC_MASK_NZVC
);
1073 insn_len
+= dec10_ind_alu(env
, dc
, CC_OP_OR
, size
);
1075 case CRISV10_IND_MOVX
:
1076 insn_len
= dec10_alux_m(env
, dc
, CC_OP_MOVE
);
1078 case CRISV10_IND_ADDX
:
1079 insn_len
= dec10_alux_m(env
, dc
, CC_OP_ADD
);
1081 case CRISV10_IND_SUBX
:
1082 insn_len
= dec10_alux_m(env
, dc
, CC_OP_SUB
);
1084 case CRISV10_IND_CMPX
:
1085 insn_len
= dec10_alux_m(env
, dc
, CC_OP_CMP
);
1087 case CRISV10_IND_MUL
:
1088 /* This is a reg insn coded in the mem indir space. */
1089 LOG_DIS("mul pc=%x opcode=%d\n", dc
->pc
, dc
->opcode
);
1090 cris_cc_mask(dc
, CC_MASK_NZVC
);
1091 dec10_reg_mul(dc
, size
, dc
->ir
& (1 << 10));
1093 case CRISV10_IND_BDAP_M
:
1094 insn_len
= dec10_bdap_m(env
, dc
, size
);
1100 * Instruction format: ADDC [Rs],Rd
1102 * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
1103 * |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs)|
1104 * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
1106 * Instruction format: ADDC [Rs+],Rd
1108 * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
1109 * |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs)|
1110 * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
1112 if (dc
->opcode
== CRISV17_IND_ADDC
&& dc
->size
== 2 &&
1113 env
->pregs
[PR_VR
] == 17) {
1114 LOG_DIS("addc op=%d %d\n", dc
->src
, dc
->dst
);
1115 cris_cc_mask(dc
, CC_MASK_NZVC
);
1116 insn_len
+= dec10_ind_alu(env
, dc
, CC_OP_ADDC
, size
);
1120 LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
1121 dc
->pc
, size
, dc
->opcode
, dc
->src
, dc
->dst
);
1122 cpu_abort(CPU(dc
->cpu
), "Unhandled opcode");
1128 switch (dc
->opcode
) {
1129 case CRISV10_IND_MOVE_M_SPR
:
1130 insn_len
= dec10_ind_move_m_pr(env
, dc
);
1132 case CRISV10_IND_MOVE_SPR_M
:
1133 insn_len
= dec10_ind_move_pr_m(dc
);
1135 case CRISV10_IND_JUMP_M
:
1136 if (dc
->src
== 15) {
1137 LOG_DIS("jump.%d %d r%d r%d direct\n", size
,
1138 dc
->opcode
, dc
->src
, dc
->dst
);
1139 imm
= cpu_ldl_code(env
, dc
->pc
+ 2);
1140 if (dc
->mode
== CRISV10_MODE_AUTOINC
)
1143 t_gen_mov_preg_TN(dc
, dc
->dst
, tcg_const_tl(dc
->pc
+ insn_len
));
1145 cris_prepare_jmp(dc
, JMP_DIRECT
);
1146 dc
->delayed_branch
--; /* v10 has no dslot here. */
1148 if (dc
->dst
== 14) {
1149 LOG_DIS("break %d\n", dc
->src
);
1150 cris_evaluate_flags(dc
);
1151 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
1152 t_gen_mov_env_TN(trap_vector
, tcg_const_tl(dc
->src
+ 2));
1153 t_gen_raise_exception(EXCP_BREAK
);
1154 dc
->is_jmp
= DISAS_UPDATE
;
1157 LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__
, size
,
1158 dc
->opcode
, dc
->src
, dc
->dst
);
1159 t
[0] = tcg_temp_new();
1160 t_gen_mov_preg_TN(dc
, dc
->dst
, tcg_const_tl(dc
->pc
+ insn_len
));
1161 crisv10_prepare_memaddr(dc
, t
[0], size
);
1162 gen_load(dc
, env_btarget
, t
[0], 4, 0);
1163 insn_len
+= crisv10_post_memaddr(dc
, size
);
1164 cris_prepare_jmp(dc
, JMP_INDIRECT
);
1165 dc
->delayed_branch
--; /* v10 has no dslot here. */
1166 tcg_temp_free(t
[0]);
1170 case CRISV10_IND_MOVEM_R_M
:
1171 LOG_DIS("movem_r_m pc=%x opcode=%d r%d r%d\n",
1172 dc
->pc
, dc
->opcode
, dc
->dst
, dc
->src
);
1173 dec10_movem_r_m(dc
);
1175 case CRISV10_IND_MOVEM_M_R
:
1176 LOG_DIS("movem_m_r pc=%x opcode=%d\n", dc
->pc
, dc
->opcode
);
1177 dec10_movem_m_r(dc
);
1179 case CRISV10_IND_JUMP_R
:
1180 LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n",
1181 dc
->pc
, dc
->opcode
, dc
->dst
, dc
->src
);
1182 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->src
]);
1183 t_gen_mov_preg_TN(dc
, dc
->dst
, tcg_const_tl(dc
->pc
+ insn_len
));
1184 cris_prepare_jmp(dc
, JMP_INDIRECT
);
1185 dc
->delayed_branch
--; /* v10 has no dslot here. */
1187 case CRISV10_IND_MOVX
:
1188 insn_len
= dec10_alux_m(env
, dc
, CC_OP_MOVE
);
1190 case CRISV10_IND_ADDX
:
1191 insn_len
= dec10_alux_m(env
, dc
, CC_OP_ADD
);
1193 case CRISV10_IND_SUBX
:
1194 insn_len
= dec10_alux_m(env
, dc
, CC_OP_SUB
);
1196 case CRISV10_IND_CMPX
:
1197 insn_len
= dec10_alux_m(env
, dc
, CC_OP_CMP
);
1199 case CRISV10_IND_DIP
:
1200 insn_len
= dec10_dip(env
, dc
);
1202 case CRISV10_IND_BCC_M
:
1204 cris_cc_mask(dc
, 0);
1205 simm
= cpu_ldsw_code(env
, dc
->pc
+ 2);
1208 LOG_DIS("bcc_m: b%s %x\n", cc_name(dc
->cond
), dc
->pc
+ simm
);
1209 cris_prepare_cc_branch(dc
, simm
, dc
->cond
);
1213 LOG_DIS("ERROR pc=%x opcode=%d\n", dc
->pc
, dc
->opcode
);
1214 cpu_abort(CPU(dc
->cpu
), "Unhandled opcode");
1221 static unsigned int crisv10_decoder(CPUCRISState
*env
, DisasContext
*dc
)
1223 unsigned int insn_len
= 2;
1225 /* Load a halfword onto the instruction register. */
1226 dc
->ir
= cpu_lduw_code(env
, dc
->pc
);
1228 /* Now decode it. */
1229 dc
->opcode
= EXTRACT_FIELD(dc
->ir
, 6, 9);
1230 dc
->mode
= EXTRACT_FIELD(dc
->ir
, 10, 11);
1231 dc
->src
= EXTRACT_FIELD(dc
->ir
, 0, 3);
1232 dc
->size
= EXTRACT_FIELD(dc
->ir
, 4, 5);
1233 dc
->cond
= dc
->dst
= EXTRACT_FIELD(dc
->ir
, 12, 15);
1234 dc
->postinc
= EXTRACT_FIELD(dc
->ir
, 10, 10);
1236 dc
->clear_prefix
= 1;
1238 /* FIXME: What if this insn insn't 2 in length?? */
1239 if (dc
->src
== 15 || dc
->dst
== 15)
1240 tcg_gen_movi_tl(cpu_R
[15], dc
->pc
+ 2);
1243 case CRISV10_MODE_QIMMEDIATE
:
1244 insn_len
= dec10_quick_imm(dc
);
1246 case CRISV10_MODE_REG
:
1247 insn_len
= dec10_reg(dc
);
1249 case CRISV10_MODE_AUTOINC
:
1250 case CRISV10_MODE_INDIRECT
:
1251 insn_len
= dec10_ind(env
, dc
);
1255 if (dc
->clear_prefix
&& dc
->tb_flags
& PFIX_FLAG
) {
1256 dc
->tb_flags
&= ~PFIX_FLAG
;
1257 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~PFIX_FLAG
);
1258 if (dc
->tb_flags
!= dc
->tb
->flags
) {
1259 dc
->cpustate_changed
= 1;
1263 /* CRISv10 locks out interrupts on dslots. */
1264 if (dc
->delayed_branch
== 2) {
1270 void cris_initialize_crisv10_tcg(void)
1274 cc_x
= tcg_global_mem_new(cpu_env
,
1275 offsetof(CPUCRISState
, cc_x
), "cc_x");
1276 cc_src
= tcg_global_mem_new(cpu_env
,
1277 offsetof(CPUCRISState
, cc_src
), "cc_src");
1278 cc_dest
= tcg_global_mem_new(cpu_env
,
1279 offsetof(CPUCRISState
, cc_dest
),
1281 cc_result
= tcg_global_mem_new(cpu_env
,
1282 offsetof(CPUCRISState
, cc_result
),
1284 cc_op
= tcg_global_mem_new(cpu_env
,
1285 offsetof(CPUCRISState
, cc_op
), "cc_op");
1286 cc_size
= tcg_global_mem_new(cpu_env
,
1287 offsetof(CPUCRISState
, cc_size
),
1289 cc_mask
= tcg_global_mem_new(cpu_env
,
1290 offsetof(CPUCRISState
, cc_mask
),
1293 env_pc
= tcg_global_mem_new(cpu_env
,
1294 offsetof(CPUCRISState
, pc
),
1296 env_btarget
= tcg_global_mem_new(cpu_env
,
1297 offsetof(CPUCRISState
, btarget
),
1299 env_btaken
= tcg_global_mem_new(cpu_env
,
1300 offsetof(CPUCRISState
, btaken
),
1302 for (i
= 0; i
< 16; i
++) {
1303 cpu_R
[i
] = tcg_global_mem_new(cpu_env
,
1304 offsetof(CPUCRISState
, regs
[i
]),
1307 for (i
= 0; i
< 16; i
++) {
1308 cpu_PR
[i
] = tcg_global_mem_new(cpu_env
,
1309 offsetof(CPUCRISState
, pregs
[i
]),