2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include "qemu/osdep.h"
29 #include "qemu/main-loop.h"
31 #include "exec/helper-proto.h"
32 #include "qemu/host-utils.h"
33 #include "exec/exec-all.h"
34 #include "exec/cpu_ldst.h"
35 #include "exec/address-spaces.h"
36 #include "qemu/timer.h"
37 #include "fpu/softfloat.h"
39 void xtensa_cpu_do_unaligned_access(CPUState
*cs
,
40 vaddr addr
, MMUAccessType access_type
,
41 int mmu_idx
, uintptr_t retaddr
)
43 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
44 CPUXtensaState
*env
= &cpu
->env
;
46 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_UNALIGNED_EXCEPTION
) &&
47 !xtensa_option_enabled(env
->config
, XTENSA_OPTION_HW_ALIGNMENT
)) {
48 cpu_restore_state(CPU(cpu
), retaddr
);
49 HELPER(exception_cause_vaddr
)(env
,
50 env
->pc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
54 void tlb_fill(CPUState
*cs
, target_ulong vaddr
, int size
,
55 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
57 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
58 CPUXtensaState
*env
= &cpu
->env
;
62 int ret
= xtensa_get_physical_addr(env
, true, vaddr
, access_type
, mmu_idx
,
63 &paddr
, &page_size
, &access
);
65 qemu_log_mask(CPU_LOG_MMU
, "%s(%08x, %d, %d) -> %08x, ret = %d\n",
66 __func__
, vaddr
, access_type
, mmu_idx
, paddr
, ret
);
70 vaddr
& TARGET_PAGE_MASK
,
71 paddr
& TARGET_PAGE_MASK
,
72 access
, mmu_idx
, page_size
);
74 cpu_restore_state(cs
, retaddr
);
75 HELPER(exception_cause_vaddr
)(env
, env
->pc
, ret
, vaddr
);
79 void xtensa_cpu_do_unassigned_access(CPUState
*cs
, hwaddr addr
,
80 bool is_write
, bool is_exec
, int opaque
,
83 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
84 CPUXtensaState
*env
= &cpu
->env
;
86 HELPER(exception_cause_vaddr
)(env
, env
->pc
,
88 INSTR_PIF_ADDR_ERROR_CAUSE
:
89 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
90 is_exec
? addr
: cs
->mem_io_vaddr
);
93 static void tb_invalidate_virtual_addr(CPUXtensaState
*env
, uint32_t vaddr
)
98 int ret
= xtensa_get_physical_addr(env
, false, vaddr
, 2, 0,
99 &paddr
, &page_size
, &access
);
101 tb_invalidate_phys_addr(&address_space_memory
, paddr
);
105 void HELPER(exception
)(CPUXtensaState
*env
, uint32_t excp
)
107 CPUState
*cs
= CPU(xtensa_env_get_cpu(env
));
109 cs
->exception_index
= excp
;
110 if (excp
== EXCP_YIELD
) {
111 env
->yield_needed
= 0;
113 if (excp
== EXCP_DEBUG
) {
114 env
->exception_taken
= 0;
119 void HELPER(exception_cause
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t cause
)
124 if (env
->sregs
[PS
] & PS_EXCM
) {
125 if (env
->config
->ndepc
) {
126 env
->sregs
[DEPC
] = pc
;
128 env
->sregs
[EPC1
] = pc
;
132 env
->sregs
[EPC1
] = pc
;
133 vector
= (env
->sregs
[PS
] & PS_UM
) ? EXC_USER
: EXC_KERNEL
;
136 env
->sregs
[EXCCAUSE
] = cause
;
137 env
->sregs
[PS
] |= PS_EXCM
;
139 HELPER(exception
)(env
, vector
);
142 void HELPER(exception_cause_vaddr
)(CPUXtensaState
*env
,
143 uint32_t pc
, uint32_t cause
, uint32_t vaddr
)
145 env
->sregs
[EXCVADDR
] = vaddr
;
146 HELPER(exception_cause
)(env
, pc
, cause
);
149 void debug_exception_env(CPUXtensaState
*env
, uint32_t cause
)
151 if (xtensa_get_cintlevel(env
) < env
->config
->debug_level
) {
152 HELPER(debug_exception
)(env
, env
->pc
, cause
);
156 void HELPER(debug_exception
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t cause
)
158 unsigned level
= env
->config
->debug_level
;
161 env
->sregs
[DEBUGCAUSE
] = cause
;
162 env
->sregs
[EPC1
+ level
- 1] = pc
;
163 env
->sregs
[EPS2
+ level
- 2] = env
->sregs
[PS
];
164 env
->sregs
[PS
] = (env
->sregs
[PS
] & ~PS_INTLEVEL
) | PS_EXCM
|
165 (level
<< PS_INTLEVEL_SHIFT
);
166 HELPER(exception
)(env
, EXC_DEBUG
);
169 static void copy_window_from_phys(CPUXtensaState
*env
,
170 uint32_t window
, uint32_t phys
, uint32_t n
)
172 assert(phys
< env
->config
->nareg
);
173 if (phys
+ n
<= env
->config
->nareg
) {
174 memcpy(env
->regs
+ window
, env
->phys_regs
+ phys
,
175 n
* sizeof(uint32_t));
177 uint32_t n1
= env
->config
->nareg
- phys
;
178 memcpy(env
->regs
+ window
, env
->phys_regs
+ phys
,
179 n1
* sizeof(uint32_t));
180 memcpy(env
->regs
+ window
+ n1
, env
->phys_regs
,
181 (n
- n1
) * sizeof(uint32_t));
185 static void copy_phys_from_window(CPUXtensaState
*env
,
186 uint32_t phys
, uint32_t window
, uint32_t n
)
188 assert(phys
< env
->config
->nareg
);
189 if (phys
+ n
<= env
->config
->nareg
) {
190 memcpy(env
->phys_regs
+ phys
, env
->regs
+ window
,
191 n
* sizeof(uint32_t));
193 uint32_t n1
= env
->config
->nareg
- phys
;
194 memcpy(env
->phys_regs
+ phys
, env
->regs
+ window
,
195 n1
* sizeof(uint32_t));
196 memcpy(env
->phys_regs
, env
->regs
+ window
+ n1
,
197 (n
- n1
) * sizeof(uint32_t));
202 static inline unsigned windowbase_bound(unsigned a
, const CPUXtensaState
*env
)
204 return a
& (env
->config
->nareg
/ 4 - 1);
207 static inline unsigned windowstart_bit(unsigned a
, const CPUXtensaState
*env
)
209 return 1 << windowbase_bound(a
, env
);
212 void xtensa_sync_window_from_phys(CPUXtensaState
*env
)
214 copy_window_from_phys(env
, 0, env
->sregs
[WINDOW_BASE
] * 4, 16);
217 void xtensa_sync_phys_from_window(CPUXtensaState
*env
)
219 copy_phys_from_window(env
, env
->sregs
[WINDOW_BASE
] * 4, 0, 16);
222 static void rotate_window_abs(CPUXtensaState
*env
, uint32_t position
)
224 xtensa_sync_phys_from_window(env
);
225 env
->sregs
[WINDOW_BASE
] = windowbase_bound(position
, env
);
226 xtensa_sync_window_from_phys(env
);
229 static void rotate_window(CPUXtensaState
*env
, uint32_t delta
)
231 rotate_window_abs(env
, env
->sregs
[WINDOW_BASE
] + delta
);
234 void HELPER(wsr_windowbase
)(CPUXtensaState
*env
, uint32_t v
)
236 rotate_window_abs(env
, v
);
239 void HELPER(entry
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t s
, uint32_t imm
)
241 int callinc
= (env
->sregs
[PS
] & PS_CALLINC
) >> PS_CALLINC_SHIFT
;
242 if (s
> 3 || ((env
->sregs
[PS
] & (PS_WOE
| PS_EXCM
)) ^ PS_WOE
) != 0) {
243 qemu_log_mask(LOG_GUEST_ERROR
, "Illegal entry instruction(pc = %08x), PS = %08x\n",
245 HELPER(exception_cause
)(env
, pc
, ILLEGAL_INSTRUCTION_CAUSE
);
247 uint32_t windowstart
= xtensa_replicate_windowstart(env
) >>
248 (env
->sregs
[WINDOW_BASE
] + 1);
250 if (windowstart
& ((1 << callinc
) - 1)) {
251 HELPER(window_check
)(env
, pc
, callinc
);
253 env
->regs
[(callinc
<< 2) | (s
& 3)] = env
->regs
[s
] - imm
;
254 rotate_window(env
, callinc
);
255 env
->sregs
[WINDOW_START
] |=
256 windowstart_bit(env
->sregs
[WINDOW_BASE
], env
);
260 void HELPER(window_check
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t w
)
262 uint32_t windowbase
= windowbase_bound(env
->sregs
[WINDOW_BASE
], env
);
263 uint32_t windowstart
= xtensa_replicate_windowstart(env
) >>
264 (env
->sregs
[WINDOW_BASE
] + 1);
265 uint32_t n
= ctz32(windowstart
) + 1;
269 rotate_window(env
, n
);
270 env
->sregs
[PS
] = (env
->sregs
[PS
] & ~PS_OWB
) |
271 (windowbase
<< PS_OWB_SHIFT
) | PS_EXCM
;
272 env
->sregs
[EPC1
] = env
->pc
= pc
;
274 switch (ctz32(windowstart
>> n
)) {
276 HELPER(exception
)(env
, EXC_WINDOW_OVERFLOW4
);
279 HELPER(exception
)(env
, EXC_WINDOW_OVERFLOW8
);
282 HELPER(exception
)(env
, EXC_WINDOW_OVERFLOW12
);
287 uint32_t HELPER(retw
)(CPUXtensaState
*env
, uint32_t pc
)
289 int n
= (env
->regs
[0] >> 30) & 0x3;
291 uint32_t windowbase
= windowbase_bound(env
->sregs
[WINDOW_BASE
], env
);
292 uint32_t windowstart
= env
->sregs
[WINDOW_START
];
295 if (windowstart
& windowstart_bit(windowbase
- 1, env
)) {
297 } else if (windowstart
& windowstart_bit(windowbase
- 2, env
)) {
299 } else if (windowstart
& windowstart_bit(windowbase
- 3, env
)) {
303 if (n
== 0 || (m
!= 0 && m
!= n
) ||
304 ((env
->sregs
[PS
] & (PS_WOE
| PS_EXCM
)) ^ PS_WOE
) != 0) {
305 qemu_log_mask(LOG_GUEST_ERROR
, "Illegal retw instruction(pc = %08x), "
306 "PS = %08x, m = %d, n = %d\n",
307 pc
, env
->sregs
[PS
], m
, n
);
308 HELPER(exception_cause
)(env
, pc
, ILLEGAL_INSTRUCTION_CAUSE
);
310 int owb
= windowbase
;
312 ret_pc
= (pc
& 0xc0000000) | (env
->regs
[0] & 0x3fffffff);
314 rotate_window(env
, -n
);
315 if (windowstart
& windowstart_bit(env
->sregs
[WINDOW_BASE
], env
)) {
316 env
->sregs
[WINDOW_START
] &= ~windowstart_bit(owb
, env
);
318 /* window underflow */
319 env
->sregs
[PS
] = (env
->sregs
[PS
] & ~PS_OWB
) |
320 (windowbase
<< PS_OWB_SHIFT
) | PS_EXCM
;
321 env
->sregs
[EPC1
] = env
->pc
= pc
;
324 HELPER(exception
)(env
, EXC_WINDOW_UNDERFLOW4
);
326 HELPER(exception
)(env
, EXC_WINDOW_UNDERFLOW8
);
328 HELPER(exception
)(env
, EXC_WINDOW_UNDERFLOW12
);
335 void HELPER(rotw
)(CPUXtensaState
*env
, uint32_t imm4
)
337 rotate_window(env
, imm4
);
340 void HELPER(restore_owb
)(CPUXtensaState
*env
)
342 rotate_window_abs(env
, (env
->sregs
[PS
] & PS_OWB
) >> PS_OWB_SHIFT
);
345 void HELPER(movsp
)(CPUXtensaState
*env
, uint32_t pc
)
347 if ((env
->sregs
[WINDOW_START
] &
348 (windowstart_bit(env
->sregs
[WINDOW_BASE
] - 3, env
) |
349 windowstart_bit(env
->sregs
[WINDOW_BASE
] - 2, env
) |
350 windowstart_bit(env
->sregs
[WINDOW_BASE
] - 1, env
))) == 0) {
351 HELPER(exception_cause
)(env
, pc
, ALLOCA_CAUSE
);
355 void HELPER(wsr_lbeg
)(CPUXtensaState
*env
, uint32_t v
)
357 if (env
->sregs
[LBEG
] != v
) {
358 tb_invalidate_virtual_addr(env
, env
->sregs
[LEND
] - 1);
359 env
->sregs
[LBEG
] = v
;
363 void HELPER(wsr_lend
)(CPUXtensaState
*env
, uint32_t v
)
365 if (env
->sregs
[LEND
] != v
) {
366 tb_invalidate_virtual_addr(env
, env
->sregs
[LEND
] - 1);
367 env
->sregs
[LEND
] = v
;
368 tb_invalidate_virtual_addr(env
, env
->sregs
[LEND
] - 1);
372 void HELPER(dump_state
)(CPUXtensaState
*env
)
374 XtensaCPU
*cpu
= xtensa_env_get_cpu(env
);
376 cpu_dump_state(CPU(cpu
), stderr
, fprintf
, 0);
379 void HELPER(waiti
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t intlevel
)
384 env
->sregs
[PS
] = (env
->sregs
[PS
] & ~PS_INTLEVEL
) |
385 (intlevel
<< PS_INTLEVEL_SHIFT
);
387 qemu_mutex_lock_iothread();
388 check_interrupts(env
);
389 qemu_mutex_unlock_iothread();
391 if (env
->pending_irq_level
) {
392 cpu_loop_exit(CPU(xtensa_env_get_cpu(env
)));
396 cpu
= CPU(xtensa_env_get_cpu(env
));
398 HELPER(exception
)(env
, EXCP_HLT
);
401 void HELPER(update_ccount
)(CPUXtensaState
*env
)
403 uint64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
405 env
->ccount_time
= now
;
406 env
->sregs
[CCOUNT
] = env
->ccount_base
+
407 (uint32_t)((now
- env
->time_base
) *
408 env
->config
->clock_freq_khz
/ 1000000);
411 void HELPER(wsr_ccount
)(CPUXtensaState
*env
, uint32_t v
)
415 HELPER(update_ccount
)(env
);
416 env
->ccount_base
+= v
- env
->sregs
[CCOUNT
];
417 for (i
= 0; i
< env
->config
->nccompare
; ++i
) {
418 HELPER(update_ccompare
)(env
, i
);
422 void HELPER(update_ccompare
)(CPUXtensaState
*env
, uint32_t i
)
426 HELPER(update_ccount
)(env
);
427 dcc
= (uint64_t)(env
->sregs
[CCOMPARE
+ i
] - env
->sregs
[CCOUNT
] - 1) + 1;
428 timer_mod(env
->ccompare
[i
].timer
,
429 env
->ccount_time
+ (dcc
* 1000000) / env
->config
->clock_freq_khz
);
430 env
->yield_needed
= 1;
433 void HELPER(check_interrupts
)(CPUXtensaState
*env
)
435 qemu_mutex_lock_iothread();
436 check_interrupts(env
);
437 qemu_mutex_unlock_iothread();
440 void HELPER(itlb_hit_test
)(CPUXtensaState
*env
, uint32_t vaddr
)
442 get_page_addr_code(env
, vaddr
);
446 * Check vaddr accessibility/cache attributes and raise an exception if
447 * specified by the ATOMCTL SR.
449 * Note: local memory exclusion is not implemented
451 void HELPER(check_atomctl
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t vaddr
)
453 uint32_t paddr
, page_size
, access
;
454 uint32_t atomctl
= env
->sregs
[ATOMCTL
];
455 int rc
= xtensa_get_physical_addr(env
, true, vaddr
, 1,
456 xtensa_get_cring(env
), &paddr
, &page_size
, &access
);
459 * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
460 * see opcode description in the ISA
463 (access
& (PAGE_READ
| PAGE_WRITE
)) != (PAGE_READ
| PAGE_WRITE
)) {
464 rc
= STORE_PROHIBITED_CAUSE
;
468 HELPER(exception_cause_vaddr
)(env
, pc
, rc
, vaddr
);
472 * When data cache is not configured use ATOMCTL bypass field.
473 * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
474 * under the Conditional Store Option.
476 if (!xtensa_option_enabled(env
->config
, XTENSA_OPTION_DCACHE
)) {
477 access
= PAGE_CACHE_BYPASS
;
480 switch (access
& PAGE_CACHE_MASK
) {
487 case PAGE_CACHE_BYPASS
:
488 if ((atomctl
& 0x3) == 0) {
489 HELPER(exception_cause_vaddr
)(env
, pc
,
490 LOAD_STORE_ERROR_CAUSE
, vaddr
);
494 case PAGE_CACHE_ISOLATE
:
495 HELPER(exception_cause_vaddr
)(env
, pc
,
496 LOAD_STORE_ERROR_CAUSE
, vaddr
);
504 void HELPER(wsr_memctl
)(CPUXtensaState
*env
, uint32_t v
)
506 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_ICACHE
)) {
507 if (extract32(v
, MEMCTL_IUSEWAYS_SHIFT
, MEMCTL_IUSEWAYS_LEN
) >
508 env
->config
->icache_ways
) {
509 deposit32(v
, MEMCTL_IUSEWAYS_SHIFT
, MEMCTL_IUSEWAYS_LEN
,
510 env
->config
->icache_ways
);
513 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_DCACHE
)) {
514 if (extract32(v
, MEMCTL_DUSEWAYS_SHIFT
, MEMCTL_DUSEWAYS_LEN
) >
515 env
->config
->dcache_ways
) {
516 deposit32(v
, MEMCTL_DUSEWAYS_SHIFT
, MEMCTL_DUSEWAYS_LEN
,
517 env
->config
->dcache_ways
);
519 if (extract32(v
, MEMCTL_DALLOCWAYS_SHIFT
, MEMCTL_DALLOCWAYS_LEN
) >
520 env
->config
->dcache_ways
) {
521 deposit32(v
, MEMCTL_DALLOCWAYS_SHIFT
, MEMCTL_DALLOCWAYS_LEN
,
522 env
->config
->dcache_ways
);
525 env
->sregs
[MEMCTL
] = v
& env
->config
->memctl_mask
;
528 void HELPER(wsr_rasid
)(CPUXtensaState
*env
, uint32_t v
)
530 XtensaCPU
*cpu
= xtensa_env_get_cpu(env
);
532 v
= (v
& 0xffffff00) | 0x1;
533 if (v
!= env
->sregs
[RASID
]) {
534 env
->sregs
[RASID
] = v
;
539 static uint32_t get_page_size(const CPUXtensaState
*env
, bool dtlb
, uint32_t way
)
541 uint32_t tlbcfg
= env
->sregs
[dtlb
? DTLBCFG
: ITLBCFG
];
545 return (tlbcfg
>> 16) & 0x3;
548 return (tlbcfg
>> 20) & 0x1;
551 return (tlbcfg
>> 24) & 0x1;
559 * Get bit mask for the virtual address bits translated by the TLB way
561 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState
*env
, bool dtlb
, uint32_t way
)
563 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
564 bool varway56
= dtlb
?
565 env
->config
->dtlb
.varway56
:
566 env
->config
->itlb
.varway56
;
570 return 0xfff00000 << get_page_size(env
, dtlb
, way
) * 2;
574 return 0xf8000000 << get_page_size(env
, dtlb
, way
);
581 return 0xf0000000 << (1 - get_page_size(env
, dtlb
, way
));
590 return REGION_PAGE_MASK
;
595 * Get bit mask for the 'VPN without index' field.
596 * See ISA, 4.6.5.6, data format for RxTLB0
598 static uint32_t get_vpn_mask(const CPUXtensaState
*env
, bool dtlb
, uint32_t way
)
602 env
->config
->dtlb
.nrefillentries
:
603 env
->config
->itlb
.nrefillentries
) == 32;
604 return is32
? 0xffff8000 : 0xffffc000;
605 } else if (way
== 4) {
606 return xtensa_tlb_get_addr_mask(env
, dtlb
, way
) << 2;
607 } else if (way
<= 6) {
608 uint32_t mask
= xtensa_tlb_get_addr_mask(env
, dtlb
, way
);
609 bool varway56
= dtlb
?
610 env
->config
->dtlb
.varway56
:
611 env
->config
->itlb
.varway56
;
614 return mask
<< (way
== 5 ? 2 : 3);
624 * Split virtual address into VPN (with index) and entry index
625 * for the given TLB way
627 void split_tlb_entry_spec_way(const CPUXtensaState
*env
, uint32_t v
, bool dtlb
,
628 uint32_t *vpn
, uint32_t wi
, uint32_t *ei
)
630 bool varway56
= dtlb
?
631 env
->config
->dtlb
.varway56
:
632 env
->config
->itlb
.varway56
;
640 env
->config
->dtlb
.nrefillentries
:
641 env
->config
->itlb
.nrefillentries
) == 32;
642 *ei
= (v
>> 12) & (is32
? 0x7 : 0x3);
647 uint32_t eibase
= 20 + get_page_size(env
, dtlb
, wi
) * 2;
648 *ei
= (v
>> eibase
) & 0x3;
654 uint32_t eibase
= 27 + get_page_size(env
, dtlb
, wi
);
655 *ei
= (v
>> eibase
) & 0x3;
657 *ei
= (v
>> 27) & 0x1;
663 uint32_t eibase
= 29 - get_page_size(env
, dtlb
, wi
);
664 *ei
= (v
>> eibase
) & 0x7;
666 *ei
= (v
>> 28) & 0x1;
675 *vpn
= v
& xtensa_tlb_get_addr_mask(env
, dtlb
, wi
);
679 * Split TLB address into TLB way, entry index and VPN (with index).
680 * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
682 static void split_tlb_entry_spec(CPUXtensaState
*env
, uint32_t v
, bool dtlb
,
683 uint32_t *vpn
, uint32_t *wi
, uint32_t *ei
)
685 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
686 *wi
= v
& (dtlb
? 0xf : 0x7);
687 split_tlb_entry_spec_way(env
, v
, dtlb
, vpn
, *wi
, ei
);
689 *vpn
= v
& REGION_PAGE_MASK
;
691 *ei
= (v
>> 29) & 0x7;
695 static xtensa_tlb_entry
*get_tlb_entry(CPUXtensaState
*env
,
696 uint32_t v
, bool dtlb
, uint32_t *pwi
)
702 split_tlb_entry_spec(env
, v
, dtlb
, &vpn
, &wi
, &ei
);
706 return xtensa_tlb_get_entry(env
, dtlb
, wi
, ei
);
709 uint32_t HELPER(rtlb0
)(CPUXtensaState
*env
, uint32_t v
, uint32_t dtlb
)
711 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
713 const xtensa_tlb_entry
*entry
= get_tlb_entry(env
, v
, dtlb
, &wi
);
714 return (entry
->vaddr
& get_vpn_mask(env
, dtlb
, wi
)) | entry
->asid
;
716 return v
& REGION_PAGE_MASK
;
720 uint32_t HELPER(rtlb1
)(CPUXtensaState
*env
, uint32_t v
, uint32_t dtlb
)
722 const xtensa_tlb_entry
*entry
= get_tlb_entry(env
, v
, dtlb
, NULL
);
723 return entry
->paddr
| entry
->attr
;
726 void HELPER(itlb
)(CPUXtensaState
*env
, uint32_t v
, uint32_t dtlb
)
728 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
730 xtensa_tlb_entry
*entry
= get_tlb_entry(env
, v
, dtlb
, &wi
);
731 if (entry
->variable
&& entry
->asid
) {
732 tlb_flush_page(CPU(xtensa_env_get_cpu(env
)), entry
->vaddr
);
738 uint32_t HELPER(ptlb
)(CPUXtensaState
*env
, uint32_t v
, uint32_t dtlb
)
740 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
744 int res
= xtensa_tlb_lookup(env
, v
, dtlb
, &wi
, &ei
, &ring
);
748 if (ring
>= xtensa_get_ring(env
)) {
749 return (v
& 0xfffff000) | wi
| (dtlb
? 0x10 : 0x8);
753 case INST_TLB_MULTI_HIT_CAUSE
:
754 case LOAD_STORE_TLB_MULTI_HIT_CAUSE
:
755 HELPER(exception_cause_vaddr
)(env
, env
->pc
, res
, v
);
760 return (v
& REGION_PAGE_MASK
) | 0x1;
764 void xtensa_tlb_set_entry_mmu(const CPUXtensaState
*env
,
765 xtensa_tlb_entry
*entry
, bool dtlb
,
766 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
)
769 entry
->paddr
= pte
& xtensa_tlb_get_addr_mask(env
, dtlb
, wi
);
770 entry
->asid
= (env
->sregs
[RASID
] >> ((pte
>> 1) & 0x18)) & 0xff;
771 entry
->attr
= pte
& 0xf;
774 void xtensa_tlb_set_entry(CPUXtensaState
*env
, bool dtlb
,
775 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
)
777 XtensaCPU
*cpu
= xtensa_env_get_cpu(env
);
778 CPUState
*cs
= CPU(cpu
);
779 xtensa_tlb_entry
*entry
= xtensa_tlb_get_entry(env
, dtlb
, wi
, ei
);
781 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
782 if (entry
->variable
) {
784 tlb_flush_page(cs
, entry
->vaddr
);
786 xtensa_tlb_set_entry_mmu(env
, entry
, dtlb
, wi
, ei
, vpn
, pte
);
787 tlb_flush_page(cs
, entry
->vaddr
);
789 qemu_log_mask(LOG_GUEST_ERROR
, "%s %d, %d, %d trying to set immutable entry\n",
790 __func__
, dtlb
, wi
, ei
);
793 tlb_flush_page(cs
, entry
->vaddr
);
794 if (xtensa_option_enabled(env
->config
,
795 XTENSA_OPTION_REGION_TRANSLATION
)) {
796 entry
->paddr
= pte
& REGION_PAGE_MASK
;
798 entry
->attr
= pte
& 0xf;
802 void HELPER(wtlb
)(CPUXtensaState
*env
, uint32_t p
, uint32_t v
, uint32_t dtlb
)
807 split_tlb_entry_spec(env
, v
, dtlb
, &vpn
, &wi
, &ei
);
808 xtensa_tlb_set_entry(env
, dtlb
, wi
, ei
, vpn
, p
);
812 void HELPER(wsr_ibreakenable
)(CPUXtensaState
*env
, uint32_t v
)
814 uint32_t change
= v
^ env
->sregs
[IBREAKENABLE
];
817 for (i
= 0; i
< env
->config
->nibreak
; ++i
) {
818 if (change
& (1 << i
)) {
819 tb_invalidate_virtual_addr(env
, env
->sregs
[IBREAKA
+ i
]);
822 env
->sregs
[IBREAKENABLE
] = v
& ((1 << env
->config
->nibreak
) - 1);
825 void HELPER(wsr_ibreaka
)(CPUXtensaState
*env
, uint32_t i
, uint32_t v
)
827 if (env
->sregs
[IBREAKENABLE
] & (1 << i
) && env
->sregs
[IBREAKA
+ i
] != v
) {
828 tb_invalidate_virtual_addr(env
, env
->sregs
[IBREAKA
+ i
]);
829 tb_invalidate_virtual_addr(env
, v
);
831 env
->sregs
[IBREAKA
+ i
] = v
;
834 static void set_dbreak(CPUXtensaState
*env
, unsigned i
, uint32_t dbreaka
,
837 CPUState
*cs
= CPU(xtensa_env_get_cpu(env
));
838 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
839 uint32_t mask
= dbreakc
| ~DBREAKC_MASK
;
841 if (env
->cpu_watchpoint
[i
]) {
842 cpu_watchpoint_remove_by_ref(cs
, env
->cpu_watchpoint
[i
]);
844 if (dbreakc
& DBREAKC_SB
) {
845 flags
|= BP_MEM_WRITE
;
847 if (dbreakc
& DBREAKC_LB
) {
848 flags
|= BP_MEM_READ
;
850 /* contiguous mask after inversion is one less than some power of 2 */
851 if ((~mask
+ 1) & ~mask
) {
852 qemu_log_mask(LOG_GUEST_ERROR
, "DBREAKC mask is not contiguous: 0x%08x\n", dbreakc
);
853 /* cut mask after the first zero bit */
854 mask
= 0xffffffff << (32 - clo32(mask
));
856 if (cpu_watchpoint_insert(cs
, dbreaka
& mask
, ~mask
+ 1,
857 flags
, &env
->cpu_watchpoint
[i
])) {
858 env
->cpu_watchpoint
[i
] = NULL
;
859 qemu_log_mask(LOG_GUEST_ERROR
, "Failed to set data breakpoint at 0x%08x/%d\n",
860 dbreaka
& mask
, ~mask
+ 1);
864 void HELPER(wsr_dbreaka
)(CPUXtensaState
*env
, uint32_t i
, uint32_t v
)
866 uint32_t dbreakc
= env
->sregs
[DBREAKC
+ i
];
868 if ((dbreakc
& DBREAKC_SB_LB
) &&
869 env
->sregs
[DBREAKA
+ i
] != v
) {
870 set_dbreak(env
, i
, v
, dbreakc
);
872 env
->sregs
[DBREAKA
+ i
] = v
;
875 void HELPER(wsr_dbreakc
)(CPUXtensaState
*env
, uint32_t i
, uint32_t v
)
877 if ((env
->sregs
[DBREAKC
+ i
] ^ v
) & (DBREAKC_SB_LB
| DBREAKC_MASK
)) {
878 if (v
& DBREAKC_SB_LB
) {
879 set_dbreak(env
, i
, env
->sregs
[DBREAKA
+ i
], v
);
881 if (env
->cpu_watchpoint
[i
]) {
882 CPUState
*cs
= CPU(xtensa_env_get_cpu(env
));
884 cpu_watchpoint_remove_by_ref(cs
, env
->cpu_watchpoint
[i
]);
885 env
->cpu_watchpoint
[i
] = NULL
;
889 env
->sregs
[DBREAKC
+ i
] = v
;
892 void HELPER(wur_fcr
)(CPUXtensaState
*env
, uint32_t v
)
894 static const int rounding_mode
[] = {
895 float_round_nearest_even
,
901 env
->uregs
[FCR
] = v
& 0xfffff07f;
902 set_float_rounding_mode(rounding_mode
[v
& 3], &env
->fp_status
);
905 float32
HELPER(abs_s
)(float32 v
)
907 return float32_abs(v
);
910 float32
HELPER(neg_s
)(float32 v
)
912 return float32_chs(v
);
915 float32
HELPER(add_s
)(CPUXtensaState
*env
, float32 a
, float32 b
)
917 return float32_add(a
, b
, &env
->fp_status
);
920 float32
HELPER(sub_s
)(CPUXtensaState
*env
, float32 a
, float32 b
)
922 return float32_sub(a
, b
, &env
->fp_status
);
925 float32
HELPER(mul_s
)(CPUXtensaState
*env
, float32 a
, float32 b
)
927 return float32_mul(a
, b
, &env
->fp_status
);
930 float32
HELPER(madd_s
)(CPUXtensaState
*env
, float32 a
, float32 b
, float32 c
)
932 return float32_muladd(b
, c
, a
, 0,
936 float32
HELPER(msub_s
)(CPUXtensaState
*env
, float32 a
, float32 b
, float32 c
)
938 return float32_muladd(b
, c
, a
, float_muladd_negate_product
,
942 uint32_t HELPER(ftoi
)(float32 v
, uint32_t rounding_mode
, uint32_t scale
)
944 float_status fp_status
= {0};
946 set_float_rounding_mode(rounding_mode
, &fp_status
);
947 return float32_to_int32(
948 float32_scalbn(v
, scale
, &fp_status
), &fp_status
);
951 uint32_t HELPER(ftoui
)(float32 v
, uint32_t rounding_mode
, uint32_t scale
)
953 float_status fp_status
= {0};
956 set_float_rounding_mode(rounding_mode
, &fp_status
);
958 res
= float32_scalbn(v
, scale
, &fp_status
);
960 if (float32_is_neg(v
) && !float32_is_any_nan(v
)) {
961 return float32_to_int32(res
, &fp_status
);
963 return float32_to_uint32(res
, &fp_status
);
967 float32
HELPER(itof
)(CPUXtensaState
*env
, uint32_t v
, uint32_t scale
)
969 return float32_scalbn(int32_to_float32(v
, &env
->fp_status
),
970 (int32_t)scale
, &env
->fp_status
);
973 float32
HELPER(uitof
)(CPUXtensaState
*env
, uint32_t v
, uint32_t scale
)
975 return float32_scalbn(uint32_to_float32(v
, &env
->fp_status
),
976 (int32_t)scale
, &env
->fp_status
);
979 static inline void set_br(CPUXtensaState
*env
, bool v
, uint32_t br
)
982 env
->sregs
[BR
] |= br
;
984 env
->sregs
[BR
] &= ~br
;
988 void HELPER(un_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
990 set_br(env
, float32_unordered_quiet(a
, b
, &env
->fp_status
), br
);
993 void HELPER(oeq_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
995 set_br(env
, float32_eq_quiet(a
, b
, &env
->fp_status
), br
);
998 void HELPER(ueq_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
1000 int v
= float32_compare_quiet(a
, b
, &env
->fp_status
);
1001 set_br(env
, v
== float_relation_equal
|| v
== float_relation_unordered
, br
);
1004 void HELPER(olt_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
1006 set_br(env
, float32_lt_quiet(a
, b
, &env
->fp_status
), br
);
1009 void HELPER(ult_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
1011 int v
= float32_compare_quiet(a
, b
, &env
->fp_status
);
1012 set_br(env
, v
== float_relation_less
|| v
== float_relation_unordered
, br
);
1015 void HELPER(ole_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
1017 set_br(env
, float32_le_quiet(a
, b
, &env
->fp_status
), br
);
1020 void HELPER(ule_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
1022 int v
= float32_compare_quiet(a
, b
, &env
->fp_status
);
1023 set_br(env
, v
!= float_relation_greater
, br
);
1026 uint32_t HELPER(rer
)(CPUXtensaState
*env
, uint32_t addr
)
1028 return address_space_ldl(env
->address_space_er
, addr
,
1029 MEMTXATTRS_UNSPECIFIED
, NULL
);
1032 void HELPER(wer
)(CPUXtensaState
*env
, uint32_t data
, uint32_t addr
)
1034 address_space_stl(env
->address_space_er
, addr
, data
,
1035 MEMTXATTRS_UNSPECIFIED
, NULL
);