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pc: acpi: memhp: drop not needed stringify(MEMORY_foo) usage
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob42e60c1d3a9dee124bd1b3bba2ddf36226ab95f0
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "acpi-build.h"
24 #include <stddef.h>
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "qom/cpu.h"
32 #include "hw/i386/pc.h"
33 #include "target-i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "hw/mem/nvdimm.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47
48 /* Supported chipsets: */
49 #include "hw/acpi/piix4.h"
50 #include "hw/acpi/pcihp.h"
51 #include "hw/i386/ich9.h"
52 #include "hw/pci/pci_bus.h"
53 #include "hw/pci-host/q35.h"
54 #include "hw/i386/intel_iommu.h"
55
56 #include "hw/i386/q35-acpi-dsdt.hex"
57 #include "hw/i386/acpi-dsdt.hex"
58
59 #include "hw/acpi/aml-build.h"
60
61 #include "qapi/qmp/qint.h"
62 #include "qom/qom-qobject.h"
63
64 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
65 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
66 * a little bit, there should be plenty of free space since the DSDT
67 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
68 */
69 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
70 #define ACPI_BUILD_ALIGN_SIZE 0x1000
71
72 #define ACPI_BUILD_TABLE_SIZE 0x20000
73
74 /* #define DEBUG_ACPI_BUILD */
75 #ifdef DEBUG_ACPI_BUILD
76 #define ACPI_BUILD_DPRINTF(fmt, ...) \
77 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
78 #else
79 #define ACPI_BUILD_DPRINTF(fmt, ...)
80 #endif
81
82 typedef struct AcpiCpuInfo {
83 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
84 } AcpiCpuInfo;
85
86 typedef struct AcpiMcfgInfo {
87 uint64_t mcfg_base;
88 uint32_t mcfg_size;
89 } AcpiMcfgInfo;
90
91 typedef struct AcpiPmInfo {
92 bool s3_disabled;
93 bool s4_disabled;
94 bool pcihp_bridge_en;
95 uint8_t s4_val;
96 uint16_t sci_int;
97 uint8_t acpi_enable_cmd;
98 uint8_t acpi_disable_cmd;
99 uint32_t gpe0_blk;
100 uint32_t gpe0_blk_len;
101 uint32_t io_base;
102 uint16_t cpu_hp_io_base;
103 uint16_t cpu_hp_io_len;
104 uint16_t mem_hp_io_base;
105 uint16_t mem_hp_io_len;
106 uint16_t pcihp_io_base;
107 uint16_t pcihp_io_len;
108 } AcpiPmInfo;
109
110 typedef struct AcpiMiscInfo {
111 bool has_hpet;
112 TPMVersion tpm_version;
113 const unsigned char *dsdt_code;
114 unsigned dsdt_size;
115 uint16_t pvpanic_port;
116 uint16_t applesmc_io_base;
117 } AcpiMiscInfo;
118
119 typedef struct AcpiBuildPciBusHotplugState {
120 GArray *device_table;
121 GArray *notify_table;
122 struct AcpiBuildPciBusHotplugState *parent;
123 bool pcihp_bridge_en;
124 } AcpiBuildPciBusHotplugState;
125
126 static void acpi_get_dsdt(AcpiMiscInfo *info)
127 {
128 Object *piix = piix4_pm_find();
129 Object *lpc = ich9_lpc_find();
130 assert(!!piix != !!lpc);
131
132 if (piix) {
133 info->dsdt_code = AcpiDsdtAmlCode;
134 info->dsdt_size = sizeof AcpiDsdtAmlCode;
135 }
136 if (lpc) {
137 info->dsdt_code = Q35AcpiDsdtAmlCode;
138 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
139 }
140 }
141
142 static
143 int acpi_add_cpu_info(Object *o, void *opaque)
144 {
145 AcpiCpuInfo *cpu = opaque;
146 uint64_t apic_id;
147
148 if (object_dynamic_cast(o, TYPE_CPU)) {
149 apic_id = object_property_get_int(o, "apic-id", NULL);
150 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
151
152 set_bit(apic_id, cpu->found_cpus);
153 }
154
155 object_child_foreach(o, acpi_add_cpu_info, opaque);
156 return 0;
157 }
158
159 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
160 {
161 Object *root = object_get_root();
162
163 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
164 object_child_foreach(root, acpi_add_cpu_info, cpu);
165 }
166
167 static void acpi_get_pm_info(AcpiPmInfo *pm)
168 {
169 Object *piix = piix4_pm_find();
170 Object *lpc = ich9_lpc_find();
171 Object *obj = NULL;
172 QObject *o;
173
174 pm->cpu_hp_io_base = 0;
175 pm->pcihp_io_base = 0;
176 pm->pcihp_io_len = 0;
177 if (piix) {
178 obj = piix;
179 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
180 pm->pcihp_io_base =
181 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
182 pm->pcihp_io_len =
183 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
184 }
185 if (lpc) {
186 obj = lpc;
187 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
188 }
189 assert(obj);
190
191 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
192 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
193 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
194
195 /* Fill in optional s3/s4 related properties */
196 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
197 if (o) {
198 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
199 } else {
200 pm->s3_disabled = false;
201 }
202 qobject_decref(o);
203 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
204 if (o) {
205 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
206 } else {
207 pm->s4_disabled = false;
208 }
209 qobject_decref(o);
210 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
211 if (o) {
212 pm->s4_val = qint_get_int(qobject_to_qint(o));
213 } else {
214 pm->s4_val = false;
215 }
216 qobject_decref(o);
217
218 /* Fill in mandatory properties */
219 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
220
221 pm->acpi_enable_cmd = object_property_get_int(obj,
222 ACPI_PM_PROP_ACPI_ENABLE_CMD,
223 NULL);
224 pm->acpi_disable_cmd = object_property_get_int(obj,
225 ACPI_PM_PROP_ACPI_DISABLE_CMD,
226 NULL);
227 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
228 NULL);
229 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
230 NULL);
231 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
232 NULL);
233 pm->pcihp_bridge_en =
234 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
235 NULL);
236 }
237
238 static void acpi_get_misc_info(AcpiMiscInfo *info)
239 {
240 info->has_hpet = hpet_find();
241 info->tpm_version = tpm_get_version();
242 info->pvpanic_port = pvpanic_port();
243 info->applesmc_io_base = applesmc_port();
244 }
245
246 /*
247 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
248 * On i386 arch we only have two pci hosts, so we can look only for them.
249 */
250 static Object *acpi_get_i386_pci_host(void)
251 {
252 PCIHostState *host;
253
254 host = OBJECT_CHECK(PCIHostState,
255 object_resolve_path("/machine/i440fx", NULL),
256 TYPE_PCI_HOST_BRIDGE);
257 if (!host) {
258 host = OBJECT_CHECK(PCIHostState,
259 object_resolve_path("/machine/q35", NULL),
260 TYPE_PCI_HOST_BRIDGE);
261 }
262
263 return OBJECT(host);
264 }
265
266 static void acpi_get_pci_info(PcPciInfo *info)
267 {
268 Object *pci_host;
269
270
271 pci_host = acpi_get_i386_pci_host();
272 g_assert(pci_host);
273
274 info->w32.begin = object_property_get_int(pci_host,
275 PCI_HOST_PROP_PCI_HOLE_START,
276 NULL);
277 info->w32.end = object_property_get_int(pci_host,
278 PCI_HOST_PROP_PCI_HOLE_END,
279 NULL);
280 info->w64.begin = object_property_get_int(pci_host,
281 PCI_HOST_PROP_PCI_HOLE64_START,
282 NULL);
283 info->w64.end = object_property_get_int(pci_host,
284 PCI_HOST_PROP_PCI_HOLE64_END,
285 NULL);
286 }
287
288 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
289
290 static void acpi_align_size(GArray *blob, unsigned align)
291 {
292 /* Align size to multiple of given size. This reduces the chance
293 * we need to change size in the future (breaking cross version migration).
294 */
295 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
296 }
297
298 /* FACS */
299 static void
300 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
301 {
302 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
303 memcpy(&facs->signature, "FACS", 4);
304 facs->length = cpu_to_le32(sizeof(*facs));
305 }
306
307 /* Load chipset information in FADT */
308 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
309 {
310 fadt->model = 1;
311 fadt->reserved1 = 0;
312 fadt->sci_int = cpu_to_le16(pm->sci_int);
313 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
314 fadt->acpi_enable = pm->acpi_enable_cmd;
315 fadt->acpi_disable = pm->acpi_disable_cmd;
316 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
317 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
318 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
319 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
320 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
321 /* EVT, CNT, TMR length matches hw/acpi/core.c */
322 fadt->pm1_evt_len = 4;
323 fadt->pm1_cnt_len = 2;
324 fadt->pm_tmr_len = 4;
325 fadt->gpe0_blk_len = pm->gpe0_blk_len;
326 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
327 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
328 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
329 (1 << ACPI_FADT_F_PROC_C1) |
330 (1 << ACPI_FADT_F_SLP_BUTTON) |
331 (1 << ACPI_FADT_F_RTC_S4));
332 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
333 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
334 * For more than 8 CPUs, "Clustered Logical" mode has to be used
335 */
336 if (max_cpus > 8) {
337 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
338 }
339 fadt->century = RTC_CENTURY;
340 }
341
342
343 /* FADT */
344 static void
345 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
346 unsigned facs, unsigned dsdt)
347 {
348 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
349
350 fadt->firmware_ctrl = cpu_to_le32(facs);
351 /* FACS address to be filled by Guest linker */
352 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
353 ACPI_BUILD_TABLE_FILE,
354 table_data, &fadt->firmware_ctrl,
355 sizeof fadt->firmware_ctrl);
356
357 fadt->dsdt = cpu_to_le32(dsdt);
358 /* DSDT address to be filled by Guest linker */
359 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
360 ACPI_BUILD_TABLE_FILE,
361 table_data, &fadt->dsdt,
362 sizeof fadt->dsdt);
363
364 fadt_setup(fadt, pm);
365
366 build_header(linker, table_data,
367 (void *)fadt, "FACP", sizeof(*fadt), 1, NULL);
368 }
369
370 static void
371 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu,
372 PcGuestInfo *guest_info)
373 {
374 int madt_start = table_data->len;
375
376 AcpiMultipleApicTable *madt;
377 AcpiMadtIoApic *io_apic;
378 AcpiMadtIntsrcovr *intsrcovr;
379 AcpiMadtLocalNmi *local_nmi;
380 int i;
381
382 madt = acpi_data_push(table_data, sizeof *madt);
383 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
384 madt->flags = cpu_to_le32(1);
385
386 for (i = 0; i < guest_info->apic_id_limit; i++) {
387 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
388 apic->type = ACPI_APIC_PROCESSOR;
389 apic->length = sizeof(*apic);
390 apic->processor_id = i;
391 apic->local_apic_id = i;
392 if (test_bit(i, cpu->found_cpus)) {
393 apic->flags = cpu_to_le32(1);
394 } else {
395 apic->flags = cpu_to_le32(0);
396 }
397 }
398 io_apic = acpi_data_push(table_data, sizeof *io_apic);
399 io_apic->type = ACPI_APIC_IO;
400 io_apic->length = sizeof(*io_apic);
401 #define ACPI_BUILD_IOAPIC_ID 0x0
402 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
403 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
404 io_apic->interrupt = cpu_to_le32(0);
405
406 if (guest_info->apic_xrupt_override) {
407 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
408 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
409 intsrcovr->length = sizeof(*intsrcovr);
410 intsrcovr->source = 0;
411 intsrcovr->gsi = cpu_to_le32(2);
412 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
413 }
414 for (i = 1; i < 16; i++) {
415 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
416 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
417 /* No need for a INT source override structure. */
418 continue;
419 }
420 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
421 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
422 intsrcovr->length = sizeof(*intsrcovr);
423 intsrcovr->source = i;
424 intsrcovr->gsi = cpu_to_le32(i);
425 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
426 }
427
428 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
429 local_nmi->type = ACPI_APIC_LOCAL_NMI;
430 local_nmi->length = sizeof(*local_nmi);
431 local_nmi->processor_id = 0xff; /* all processors */
432 local_nmi->flags = cpu_to_le16(0);
433 local_nmi->lint = 1; /* ACPI_LINT1 */
434
435 build_header(linker, table_data,
436 (void *)(table_data->data + madt_start), "APIC",
437 table_data->len - madt_start, 1, NULL);
438 }
439
440 /* Assign BSEL property to all buses. In the future, this can be changed
441 * to only assign to buses that support hotplug.
442 */
443 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
444 {
445 unsigned *bsel_alloc = opaque;
446 unsigned *bus_bsel;
447
448 if (qbus_is_hotpluggable(BUS(bus))) {
449 bus_bsel = g_malloc(sizeof *bus_bsel);
450
451 *bus_bsel = (*bsel_alloc)++;
452 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
453 bus_bsel, NULL);
454 }
455
456 return bsel_alloc;
457 }
458
459 static void acpi_set_pci_info(void)
460 {
461 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
462 unsigned bsel_alloc = 0;
463
464 if (bus) {
465 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
466 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
467 }
468 }
469
470 static void build_append_pcihp_notify_entry(Aml *method, int slot)
471 {
472 Aml *if_ctx;
473 int32_t devfn = PCI_DEVFN(slot, 0);
474
475 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
476 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
477 aml_append(method, if_ctx);
478 }
479
480 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
481 bool pcihp_bridge_en)
482 {
483 Aml *dev, *notify_method, *method;
484 QObject *bsel;
485 PCIBus *sec;
486 int i;
487
488 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
489 if (bsel) {
490 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
491
492 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
493 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
494 }
495
496 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
497 DeviceClass *dc;
498 PCIDeviceClass *pc;
499 PCIDevice *pdev = bus->devices[i];
500 int slot = PCI_SLOT(i);
501 bool hotplug_enabled_dev;
502 bool bridge_in_acpi;
503
504 if (!pdev) {
505 if (bsel) { /* add hotplug slots for non present devices */
506 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
507 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
508 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
509 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
510 aml_append(method,
511 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
512 );
513 aml_append(dev, method);
514 aml_append(parent_scope, dev);
515
516 build_append_pcihp_notify_entry(notify_method, slot);
517 }
518 continue;
519 }
520
521 pc = PCI_DEVICE_GET_CLASS(pdev);
522 dc = DEVICE_GET_CLASS(pdev);
523
524 /* When hotplug for bridges is enabled, bridges are
525 * described in ACPI separately (see build_pci_bus_end).
526 * In this case they aren't themselves hot-pluggable.
527 * Hotplugged bridges *are* hot-pluggable.
528 */
529 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
530 !DEVICE(pdev)->hotplugged;
531
532 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
533
534 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
535 continue;
536 }
537
538 /* start to compose PCI slot descriptor */
539 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
540 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
541
542 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
543 /* add VGA specific AML methods */
544 int s3d;
545
546 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
547 s3d = 3;
548 } else {
549 s3d = 0;
550 }
551
552 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
553 aml_append(method, aml_return(aml_int(0)));
554 aml_append(dev, method);
555
556 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
557 aml_append(method, aml_return(aml_int(0)));
558 aml_append(dev, method);
559
560 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
561 aml_append(method, aml_return(aml_int(s3d)));
562 aml_append(dev, method);
563 } else if (hotplug_enabled_dev) {
564 /* add _SUN/_EJ0 to make slot hotpluggable */
565 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
566
567 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
568 aml_append(method,
569 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
570 );
571 aml_append(dev, method);
572
573 if (bsel) {
574 build_append_pcihp_notify_entry(notify_method, slot);
575 }
576 } else if (bridge_in_acpi) {
577 /*
578 * device is coldplugged bridge,
579 * add child device descriptions into its scope
580 */
581 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
582
583 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
584 }
585 /* slot descriptor has been composed, add it into parent context */
586 aml_append(parent_scope, dev);
587 }
588
589 if (bsel) {
590 aml_append(parent_scope, notify_method);
591 }
592
593 /* Append PCNT method to notify about events on local and child buses.
594 * Add unconditionally for root since DSDT expects it.
595 */
596 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
597
598 /* If bus supports hotplug select it and notify about local events */
599 if (bsel) {
600 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
601 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
602 aml_append(method,
603 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
604 );
605 aml_append(method,
606 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
607 );
608 }
609
610 /* Notify about child bus events in any case */
611 if (pcihp_bridge_en) {
612 QLIST_FOREACH(sec, &bus->child, sibling) {
613 int32_t devfn = sec->parent_dev->devfn;
614
615 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
616 }
617 }
618 aml_append(parent_scope, method);
619 qobject_decref(bsel);
620 }
621
622 /*
623 * initialize_route - Initialize the interrupt routing rule
624 * through a specific LINK:
625 * if (lnk_idx == idx)
626 * route using link 'link_name'
627 */
628 static Aml *initialize_route(Aml *route, const char *link_name,
629 Aml *lnk_idx, int idx)
630 {
631 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
632 Aml *pkg = aml_package(4);
633
634 aml_append(pkg, aml_int(0));
635 aml_append(pkg, aml_int(0));
636 aml_append(pkg, aml_name("%s", link_name));
637 aml_append(pkg, aml_int(0));
638 aml_append(if_ctx, aml_store(pkg, route));
639
640 return if_ctx;
641 }
642
643 /*
644 * build_prt - Define interrupt rounting rules
645 *
646 * Returns an array of 128 routes, one for each device,
647 * based on device location.
648 * The main goal is to equaly distribute the interrupts
649 * over the 4 existing ACPI links (works only for i440fx).
650 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
651 *
652 */
653 static Aml *build_prt(void)
654 {
655 Aml *method, *while_ctx, *pin, *res;
656
657 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
658 res = aml_local(0);
659 pin = aml_local(1);
660 aml_append(method, aml_store(aml_package(128), res));
661 aml_append(method, aml_store(aml_int(0), pin));
662
663 /* while (pin < 128) */
664 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
665 {
666 Aml *slot = aml_local(2);
667 Aml *lnk_idx = aml_local(3);
668 Aml *route = aml_local(4);
669
670 /* slot = pin >> 2 */
671 aml_append(while_ctx,
672 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
673 /* lnk_idx = (slot + pin) & 3 */
674 aml_append(while_ctx,
675 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
676 lnk_idx));
677
678 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
679 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
680 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
681 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
682 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
683
684 /* route[0] = 0x[slot]FFFF */
685 aml_append(while_ctx,
686 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
687 NULL),
688 aml_index(route, aml_int(0))));
689 /* route[1] = pin & 3 */
690 aml_append(while_ctx,
691 aml_store(aml_and(pin, aml_int(3), NULL),
692 aml_index(route, aml_int(1))));
693 /* res[pin] = route */
694 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
695 /* pin++ */
696 aml_append(while_ctx, aml_increment(pin));
697 }
698 aml_append(method, while_ctx);
699 /* return res*/
700 aml_append(method, aml_return(res));
701
702 return method;
703 }
704
705 typedef struct CrsRangeEntry {
706 uint64_t base;
707 uint64_t limit;
708 } CrsRangeEntry;
709
710 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
711 {
712 CrsRangeEntry *entry;
713
714 entry = g_malloc(sizeof(*entry));
715 entry->base = base;
716 entry->limit = limit;
717
718 g_ptr_array_add(ranges, entry);
719 }
720
721 static void crs_range_free(gpointer data)
722 {
723 CrsRangeEntry *entry = (CrsRangeEntry *)data;
724 g_free(entry);
725 }
726
727 static gint crs_range_compare(gconstpointer a, gconstpointer b)
728 {
729 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
730 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
731
732 return (int64_t)entry_a->base - (int64_t)entry_b->base;
733 }
734
735 /*
736 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
737 * interval, computes the 'free' ranges from the same interval.
738 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
739 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
740 */
741 static void crs_replace_with_free_ranges(GPtrArray *ranges,
742 uint64_t start, uint64_t end)
743 {
744 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
745 uint64_t free_base = start;
746 int i;
747
748 g_ptr_array_sort(ranges, crs_range_compare);
749 for (i = 0; i < ranges->len; i++) {
750 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
751
752 if (free_base < used->base) {
753 crs_range_insert(free_ranges, free_base, used->base - 1);
754 }
755
756 free_base = used->limit + 1;
757 }
758
759 if (free_base < end) {
760 crs_range_insert(free_ranges, free_base, end);
761 }
762
763 g_ptr_array_set_size(ranges, 0);
764 for (i = 0; i < free_ranges->len; i++) {
765 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
766 }
767
768 g_ptr_array_free(free_ranges, false);
769 }
770
771 /*
772 * crs_range_merge - merges adjacent ranges in the given array.
773 * Array elements are deleted and replaced with the merged ranges.
774 */
775 static void crs_range_merge(GPtrArray *range)
776 {
777 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
778 CrsRangeEntry *entry;
779 uint64_t range_base, range_limit;
780 int i;
781
782 if (!range->len) {
783 return;
784 }
785
786 g_ptr_array_sort(range, crs_range_compare);
787
788 entry = g_ptr_array_index(range, 0);
789 range_base = entry->base;
790 range_limit = entry->limit;
791 for (i = 1; i < range->len; i++) {
792 entry = g_ptr_array_index(range, i);
793 if (entry->base - 1 == range_limit) {
794 range_limit = entry->limit;
795 } else {
796 crs_range_insert(tmp, range_base, range_limit);
797 range_base = entry->base;
798 range_limit = entry->limit;
799 }
800 }
801 crs_range_insert(tmp, range_base, range_limit);
802
803 g_ptr_array_set_size(range, 0);
804 for (i = 0; i < tmp->len; i++) {
805 entry = g_ptr_array_index(tmp, i);
806 crs_range_insert(range, entry->base, entry->limit);
807 }
808 g_ptr_array_free(tmp, true);
809 }
810
811 static Aml *build_crs(PCIHostState *host,
812 GPtrArray *io_ranges, GPtrArray *mem_ranges)
813 {
814 Aml *crs = aml_resource_template();
815 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
816 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
817 CrsRangeEntry *entry;
818 uint8_t max_bus = pci_bus_num(host->bus);
819 uint8_t type;
820 int devfn;
821 int i;
822
823 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
824 uint64_t range_base, range_limit;
825 PCIDevice *dev = host->bus->devices[devfn];
826
827 if (!dev) {
828 continue;
829 }
830
831 for (i = 0; i < PCI_NUM_REGIONS; i++) {
832 PCIIORegion *r = &dev->io_regions[i];
833
834 range_base = r->addr;
835 range_limit = r->addr + r->size - 1;
836
837 /*
838 * Work-around for old bioses
839 * that do not support multiple root buses
840 */
841 if (!range_base || range_base > range_limit) {
842 continue;
843 }
844
845 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
846 crs_range_insert(host_io_ranges, range_base, range_limit);
847 } else { /* "memory" */
848 crs_range_insert(host_mem_ranges, range_base, range_limit);
849 }
850 }
851
852 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
853 if (type == PCI_HEADER_TYPE_BRIDGE) {
854 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
855 if (subordinate > max_bus) {
856 max_bus = subordinate;
857 }
858
859 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
860 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
861
862 /*
863 * Work-around for old bioses
864 * that do not support multiple root buses
865 */
866 if (range_base && range_base <= range_limit) {
867 crs_range_insert(host_io_ranges, range_base, range_limit);
868 }
869
870 range_base =
871 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
872 range_limit =
873 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
874
875 /*
876 * Work-around for old bioses
877 * that do not support multiple root buses
878 */
879 if (range_base && range_base <= range_limit) {
880 crs_range_insert(host_mem_ranges, range_base, range_limit);
881 }
882
883 range_base =
884 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
885 range_limit =
886 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
887
888 /*
889 * Work-around for old bioses
890 * that do not support multiple root buses
891 */
892 if (range_base && range_base <= range_limit) {
893 crs_range_insert(host_mem_ranges, range_base, range_limit);
894 }
895 }
896 }
897
898 crs_range_merge(host_io_ranges);
899 for (i = 0; i < host_io_ranges->len; i++) {
900 entry = g_ptr_array_index(host_io_ranges, i);
901 aml_append(crs,
902 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
903 AML_POS_DECODE, AML_ENTIRE_RANGE,
904 0, entry->base, entry->limit, 0,
905 entry->limit - entry->base + 1));
906 crs_range_insert(io_ranges, entry->base, entry->limit);
907 }
908 g_ptr_array_free(host_io_ranges, true);
909
910 crs_range_merge(host_mem_ranges);
911 for (i = 0; i < host_mem_ranges->len; i++) {
912 entry = g_ptr_array_index(host_mem_ranges, i);
913 aml_append(crs,
914 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
915 AML_MAX_FIXED, AML_NON_CACHEABLE,
916 AML_READ_WRITE,
917 0, entry->base, entry->limit, 0,
918 entry->limit - entry->base + 1));
919 crs_range_insert(mem_ranges, entry->base, entry->limit);
920 }
921 g_ptr_array_free(host_mem_ranges, true);
922
923 aml_append(crs,
924 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
925 0,
926 pci_bus_num(host->bus),
927 max_bus,
928 0,
929 max_bus - pci_bus_num(host->bus) + 1));
930
931 return crs;
932 }
933
934 static void build_memory_devices(Aml *sb_scope, int nr_mem,
935 uint16_t io_base, uint16_t io_len)
936 {
937 int i;
938 Aml *scope;
939 Aml *crs;
940 Aml *field;
941 Aml *dev;
942 Aml *method;
943 Aml *ifctx;
944
945 /* build memory devices */
946 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
947 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
948 aml_append(scope,
949 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
950 );
951
952 crs = aml_resource_template();
953 aml_append(crs,
954 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
955 );
956 aml_append(scope, aml_name_decl("_CRS", crs));
957
958 aml_append(scope, aml_operation_region(
959 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
960 io_base, io_len)
961 );
962
963 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
964 AML_NOLOCK, AML_PRESERVE);
965 aml_append(field, /* read only */
966 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
967 aml_append(field, /* read only */
968 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
969 aml_append(field, /* read only */
970 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
971 aml_append(field, /* read only */
972 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
973 aml_append(field, /* read only */
974 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
975 aml_append(scope, field);
976
977 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
978 AML_NOLOCK, AML_WRITE_AS_ZEROS);
979 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
980 aml_append(field, /* 1 if enabled, read only */
981 aml_named_field(MEMORY_SLOT_ENABLED, 1));
982 aml_append(field,
983 /*(read) 1 if has a insert event. (write) 1 to clear event */
984 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
985 aml_append(field,
986 /* (read) 1 if has a remove event. (write) 1 to clear event */
987 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
988 aml_append(field,
989 /* initiates device eject, write only */
990 aml_named_field(MEMORY_SLOT_EJECT, 1));
991 aml_append(scope, field);
992
993 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
994 AML_NOLOCK, AML_PRESERVE);
995 aml_append(field, /* DIMM selector, write only */
996 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
997 aml_append(field, /* _OST event code, write only */
998 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
999 aml_append(field, /* _OST status code, write only */
1000 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1001 aml_append(scope, field);
1002 aml_append(sb_scope, scope);
1003
1004 for (i = 0; i < nr_mem; i++) {
1005 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1006 const char *s;
1007
1008 dev = aml_device("MP%02X", i);
1009 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1010 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1011
1012 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1013 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1014 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1015 aml_append(dev, method);
1016
1017 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1018 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1019 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1020 aml_append(dev, method);
1021
1022 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1023 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1024 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1025 aml_append(dev, method);
1026
1027 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1028 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1029
1030 aml_append(method, aml_return(aml_call4(
1031 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1032 )));
1033 aml_append(dev, method);
1034
1035 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1036 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1037 aml_append(method, aml_return(aml_call2(
1038 s, aml_name("_UID"), aml_arg(0))));
1039 aml_append(dev, method);
1040
1041 aml_append(sb_scope, dev);
1042 }
1043
1044 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1045 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1046 */
1047 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1048 for (i = 0; i < nr_mem; i++) {
1049 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1050 aml_append(ifctx,
1051 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1052 );
1053 aml_append(method, ifctx);
1054 }
1055 aml_append(sb_scope, method);
1056 }
1057
1058 static void
1059 build_ssdt(GArray *table_data, GArray *linker,
1060 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
1061 PcPciInfo *pci, PcGuestInfo *guest_info)
1062 {
1063 MachineState *machine = MACHINE(qdev_get_machine());
1064 uint32_t nr_mem = machine->ram_slots;
1065 unsigned acpi_cpus = guest_info->apic_id_limit;
1066 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx;
1067 PCIBus *bus = NULL;
1068 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1069 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1070 CrsRangeEntry *entry;
1071 int root_bus_limit = 0xFF;
1072 int i;
1073
1074 ssdt = init_aml_allocator();
1075 /* The current AML generator can cover the APIC ID range [0..255],
1076 * inclusive, for VCPU hotplug. */
1077 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
1078 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
1079
1080 /* Reserve space for header */
1081 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
1082
1083 build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
1084 pm->mem_hp_io_len);
1085
1086 scope = aml_scope("\\_GPE");
1087 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
1088 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
1089 aml_append(scope, method);
1090 aml_append(ssdt, scope);
1091
1092 bus = PC_MACHINE(machine)->bus;
1093 if (bus) {
1094 QLIST_FOREACH(bus, &bus->child, sibling) {
1095 uint8_t bus_num = pci_bus_num(bus);
1096 uint8_t numa_node = pci_bus_numa_node(bus);
1097
1098 /* look only for expander root buses */
1099 if (!pci_bus_is_root(bus)) {
1100 continue;
1101 }
1102
1103 if (bus_num < root_bus_limit) {
1104 root_bus_limit = bus_num - 1;
1105 }
1106
1107 scope = aml_scope("\\_SB");
1108 dev = aml_device("PC%.02X", bus_num);
1109 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1110 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1111 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1112
1113 if (numa_node != NUMA_NODE_UNASSIGNED) {
1114 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1115 }
1116
1117 aml_append(dev, build_prt());
1118 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
1119 io_ranges, mem_ranges);
1120 aml_append(dev, aml_name_decl("_CRS", crs));
1121 aml_append(scope, dev);
1122 aml_append(ssdt, scope);
1123 }
1124 }
1125
1126 scope = aml_scope("\\_SB.PCI0");
1127 /* build PCI0._CRS */
1128 crs = aml_resource_template();
1129 aml_append(crs,
1130 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1131 0x0000, 0x0, root_bus_limit,
1132 0x0000, root_bus_limit + 1));
1133 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1134
1135 aml_append(crs,
1136 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1137 AML_POS_DECODE, AML_ENTIRE_RANGE,
1138 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1139
1140 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
1141 for (i = 0; i < io_ranges->len; i++) {
1142 entry = g_ptr_array_index(io_ranges, i);
1143 aml_append(crs,
1144 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1145 AML_POS_DECODE, AML_ENTIRE_RANGE,
1146 0x0000, entry->base, entry->limit,
1147 0x0000, entry->limit - entry->base + 1));
1148 }
1149
1150 aml_append(crs,
1151 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1152 AML_CACHEABLE, AML_READ_WRITE,
1153 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1154
1155 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
1156 for (i = 0; i < mem_ranges->len; i++) {
1157 entry = g_ptr_array_index(mem_ranges, i);
1158 aml_append(crs,
1159 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1160 AML_NON_CACHEABLE, AML_READ_WRITE,
1161 0, entry->base, entry->limit,
1162 0, entry->limit - entry->base + 1));
1163 }
1164
1165 if (pci->w64.begin) {
1166 aml_append(crs,
1167 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1168 AML_CACHEABLE, AML_READ_WRITE,
1169 0, pci->w64.begin, pci->w64.end - 1, 0,
1170 pci->w64.end - pci->w64.begin));
1171 }
1172 aml_append(scope, aml_name_decl("_CRS", crs));
1173
1174 /* reserve GPE0 block resources */
1175 dev = aml_device("GPE0");
1176 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1177 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1178 /* device present, functioning, decoding, not shown in UI */
1179 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1180 crs = aml_resource_template();
1181 aml_append(crs,
1182 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
1183 );
1184 aml_append(dev, aml_name_decl("_CRS", crs));
1185 aml_append(scope, dev);
1186
1187 g_ptr_array_free(io_ranges, true);
1188 g_ptr_array_free(mem_ranges, true);
1189
1190 /* reserve PCIHP resources */
1191 if (pm->pcihp_io_len) {
1192 dev = aml_device("PHPR");
1193 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1194 aml_append(dev,
1195 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1196 /* device present, functioning, decoding, not shown in UI */
1197 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1198 crs = aml_resource_template();
1199 aml_append(crs,
1200 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1201 pm->pcihp_io_len)
1202 );
1203 aml_append(dev, aml_name_decl("_CRS", crs));
1204 aml_append(scope, dev);
1205 }
1206 aml_append(ssdt, scope);
1207
1208 /* create S3_ / S4_ / S5_ packages if necessary */
1209 scope = aml_scope("\\");
1210 if (!pm->s3_disabled) {
1211 pkg = aml_package(4);
1212 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1213 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1214 aml_append(pkg, aml_int(0)); /* reserved */
1215 aml_append(pkg, aml_int(0)); /* reserved */
1216 aml_append(scope, aml_name_decl("_S3", pkg));
1217 }
1218
1219 if (!pm->s4_disabled) {
1220 pkg = aml_package(4);
1221 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1222 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1223 aml_append(pkg, aml_int(pm->s4_val));
1224 aml_append(pkg, aml_int(0)); /* reserved */
1225 aml_append(pkg, aml_int(0)); /* reserved */
1226 aml_append(scope, aml_name_decl("_S4", pkg));
1227 }
1228
1229 pkg = aml_package(4);
1230 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1231 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1232 aml_append(pkg, aml_int(0)); /* reserved */
1233 aml_append(pkg, aml_int(0)); /* reserved */
1234 aml_append(scope, aml_name_decl("_S5", pkg));
1235 aml_append(ssdt, scope);
1236
1237 if (misc->applesmc_io_base) {
1238 scope = aml_scope("\\_SB.PCI0.ISA");
1239 dev = aml_device("SMC");
1240
1241 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1242 /* device present, functioning, decoding, not shown in UI */
1243 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1244
1245 crs = aml_resource_template();
1246 aml_append(crs,
1247 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1248 0x01, APPLESMC_MAX_DATA_LENGTH)
1249 );
1250 aml_append(crs, aml_irq_no_flags(6));
1251 aml_append(dev, aml_name_decl("_CRS", crs));
1252
1253 aml_append(scope, dev);
1254 aml_append(ssdt, scope);
1255 }
1256
1257 if (misc->pvpanic_port) {
1258 scope = aml_scope("\\_SB.PCI0.ISA");
1259
1260 dev = aml_device("PEVT");
1261 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1262
1263 crs = aml_resource_template();
1264 aml_append(crs,
1265 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1266 );
1267 aml_append(dev, aml_name_decl("_CRS", crs));
1268
1269 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1270 misc->pvpanic_port, 1));
1271 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1272 aml_append(field, aml_named_field("PEPT", 8));
1273 aml_append(dev, field);
1274
1275 /* device present, functioning, decoding, shown in UI */
1276 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1277
1278 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
1279 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1280 aml_append(method, aml_return(aml_local(0)));
1281 aml_append(dev, method);
1282
1283 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
1284 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1285 aml_append(dev, method);
1286
1287 aml_append(scope, dev);
1288 aml_append(ssdt, scope);
1289 }
1290
1291 sb_scope = aml_scope("\\_SB");
1292 {
1293 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
1294 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
1295 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1296 aml_append(dev,
1297 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
1298 );
1299 /* device present, functioning, decoding, not shown in UI */
1300 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1301 crs = aml_resource_template();
1302 aml_append(crs,
1303 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
1304 pm->cpu_hp_io_len)
1305 );
1306 aml_append(dev, aml_name_decl("_CRS", crs));
1307 aml_append(sb_scope, dev);
1308 /* declare CPU hotplug MMIO region and PRS field to access it */
1309 aml_append(sb_scope, aml_operation_region(
1310 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
1311 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1312 aml_append(field, aml_named_field("PRS", 256));
1313 aml_append(sb_scope, field);
1314
1315 /* build Processor object for each processor */
1316 for (i = 0; i < acpi_cpus; i++) {
1317 dev = aml_processor(i, 0, 0, "CP%.02X", i);
1318
1319 method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
1320 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i))));
1321 aml_append(dev, method);
1322
1323 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1324 aml_append(method, aml_return(aml_call1("CPST", aml_int(i))));
1325 aml_append(dev, method);
1326
1327 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1328 aml_append(method,
1329 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0)))
1330 );
1331 aml_append(dev, method);
1332
1333 aml_append(sb_scope, dev);
1334 }
1335
1336 /* build this code:
1337 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1338 */
1339 /* Arg0 = Processor ID = APIC ID */
1340 method = aml_method("NTFY", 2, AML_NOTSERIALIZED);
1341 for (i = 0; i < acpi_cpus; i++) {
1342 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1343 aml_append(ifctx,
1344 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1345 );
1346 aml_append(method, ifctx);
1347 }
1348 aml_append(sb_scope, method);
1349
1350 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1351 *
1352 * Note: The ability to create variable-sized packages was first
1353 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1354 * ith up to 255 elements. Windows guests up to win2k8 fail when
1355 * VarPackageOp is used.
1356 */
1357 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1358 aml_varpackage(acpi_cpus);
1359
1360 for (i = 0; i < acpi_cpus; i++) {
1361 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1362 aml_append(pkg, aml_int(b));
1363 }
1364 aml_append(sb_scope, aml_name_decl("CPON", pkg));
1365
1366 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
1367 pm->mem_hp_io_len);
1368
1369 {
1370 Object *pci_host;
1371 PCIBus *bus = NULL;
1372
1373 pci_host = acpi_get_i386_pci_host();
1374 if (pci_host) {
1375 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1376 }
1377
1378 if (bus) {
1379 Aml *scope = aml_scope("PCI0");
1380 /* Scan all PCI buses. Generate tables to support hotplug. */
1381 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1382
1383 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
1384 dev = aml_device("ISA.TPM");
1385 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
1386 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1387 crs = aml_resource_template();
1388 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1389 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1390 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ));
1391 aml_append(dev, aml_name_decl("_CRS", crs));
1392 aml_append(scope, dev);
1393 }
1394
1395 aml_append(sb_scope, scope);
1396 }
1397 }
1398 aml_append(ssdt, sb_scope);
1399 }
1400
1401 /* copy AML table into ACPI tables blob and patch header there */
1402 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
1403 build_header(linker, table_data,
1404 (void *)(table_data->data + table_data->len - ssdt->buf->len),
1405 "SSDT", ssdt->buf->len, 1, NULL);
1406 free_aml_allocator();
1407 }
1408
1409 static void
1410 build_hpet(GArray *table_data, GArray *linker)
1411 {
1412 Acpi20Hpet *hpet;
1413
1414 hpet = acpi_data_push(table_data, sizeof(*hpet));
1415 /* Note timer_block_id value must be kept in sync with value advertised by
1416 * emulated hpet
1417 */
1418 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1419 hpet->addr.address = cpu_to_le64(HPET_BASE);
1420 build_header(linker, table_data,
1421 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL);
1422 }
1423
1424 static void
1425 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
1426 {
1427 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1428 uint64_t log_area_start_address = acpi_data_len(tcpalog);
1429
1430 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1431 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1432 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
1433
1434 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
1435 false /* high memory */);
1436
1437 /* log area start address to be filled by Guest linker */
1438 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1439 ACPI_BUILD_TPMLOG_FILE,
1440 table_data, &tcpa->log_area_start_address,
1441 sizeof(tcpa->log_area_start_address));
1442
1443 build_header(linker, table_data,
1444 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL);
1445
1446 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1447 }
1448
1449 static void
1450 build_tpm2(GArray *table_data, GArray *linker)
1451 {
1452 Acpi20TPM2 *tpm2_ptr;
1453
1454 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
1455
1456 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
1457 tpm2_ptr->control_area_address = cpu_to_le64(0);
1458 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
1459
1460 build_header(linker, table_data,
1461 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL);
1462 }
1463
1464 typedef enum {
1465 MEM_AFFINITY_NOFLAGS = 0,
1466 MEM_AFFINITY_ENABLED = (1 << 0),
1467 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
1468 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
1469 } MemoryAffinityFlags;
1470
1471 static void
1472 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
1473 uint64_t len, int node, MemoryAffinityFlags flags)
1474 {
1475 numamem->type = ACPI_SRAT_MEMORY;
1476 numamem->length = sizeof(*numamem);
1477 memset(numamem->proximity, 0, 4);
1478 numamem->proximity[0] = node;
1479 numamem->flags = cpu_to_le32(flags);
1480 numamem->base_addr = cpu_to_le64(base);
1481 numamem->range_length = cpu_to_le64(len);
1482 }
1483
1484 static void
1485 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
1486 {
1487 AcpiSystemResourceAffinityTable *srat;
1488 AcpiSratProcessorAffinity *core;
1489 AcpiSratMemoryAffinity *numamem;
1490
1491 int i;
1492 uint64_t curnode;
1493 int srat_start, numa_start, slots;
1494 uint64_t mem_len, mem_base, next_base;
1495 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1496 ram_addr_t hotplugabble_address_space_size =
1497 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
1498 NULL);
1499
1500 srat_start = table_data->len;
1501
1502 srat = acpi_data_push(table_data, sizeof *srat);
1503 srat->reserved1 = cpu_to_le32(1);
1504 core = (void *)(srat + 1);
1505
1506 for (i = 0; i < guest_info->apic_id_limit; ++i) {
1507 core = acpi_data_push(table_data, sizeof *core);
1508 core->type = ACPI_SRAT_PROCESSOR;
1509 core->length = sizeof(*core);
1510 core->local_apic_id = i;
1511 curnode = guest_info->node_cpu[i];
1512 core->proximity_lo = curnode;
1513 memset(core->proximity_hi, 0, 3);
1514 core->local_sapic_eid = 0;
1515 core->flags = cpu_to_le32(1);
1516 }
1517
1518
1519 /* the memory map is a bit tricky, it contains at least one hole
1520 * from 640k-1M and possibly another one from 3.5G-4G.
1521 */
1522 next_base = 0;
1523 numa_start = table_data->len;
1524
1525 numamem = acpi_data_push(table_data, sizeof *numamem);
1526 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
1527 next_base = 1024 * 1024;
1528 for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
1529 mem_base = next_base;
1530 mem_len = guest_info->node_mem[i - 1];
1531 if (i == 1) {
1532 mem_len -= 1024 * 1024;
1533 }
1534 next_base = mem_base + mem_len;
1535
1536 /* Cut out the ACPI_PCI hole */
1537 if (mem_base <= guest_info->ram_size_below_4g &&
1538 next_base > guest_info->ram_size_below_4g) {
1539 mem_len -= next_base - guest_info->ram_size_below_4g;
1540 if (mem_len > 0) {
1541 numamem = acpi_data_push(table_data, sizeof *numamem);
1542 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1543 MEM_AFFINITY_ENABLED);
1544 }
1545 mem_base = 1ULL << 32;
1546 mem_len = next_base - guest_info->ram_size_below_4g;
1547 next_base += (1ULL << 32) - guest_info->ram_size_below_4g;
1548 }
1549 numamem = acpi_data_push(table_data, sizeof *numamem);
1550 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1551 MEM_AFFINITY_ENABLED);
1552 }
1553 slots = (table_data->len - numa_start) / sizeof *numamem;
1554 for (; slots < guest_info->numa_nodes + 2; slots++) {
1555 numamem = acpi_data_push(table_data, sizeof *numamem);
1556 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1557 }
1558
1559 /*
1560 * Entry is required for Windows to enable memory hotplug in OS.
1561 * Memory devices may override proximity set by this entry,
1562 * providing _PXM method if necessary.
1563 */
1564 if (hotplugabble_address_space_size) {
1565 numamem = acpi_data_push(table_data, sizeof *numamem);
1566 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base,
1567 hotplugabble_address_space_size, 0,
1568 MEM_AFFINITY_HOTPLUGGABLE |
1569 MEM_AFFINITY_ENABLED);
1570 }
1571
1572 build_header(linker, table_data,
1573 (void *)(table_data->data + srat_start),
1574 "SRAT",
1575 table_data->len - srat_start, 1, NULL);
1576 }
1577
1578 static void
1579 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
1580 {
1581 AcpiTableMcfg *mcfg;
1582 const char *sig;
1583 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
1584
1585 mcfg = acpi_data_push(table_data, len);
1586 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
1587 /* Only a single allocation so no need to play with segments */
1588 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
1589 mcfg->allocation[0].start_bus_number = 0;
1590 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
1591
1592 /* MCFG is used for ECAM which can be enabled or disabled by guest.
1593 * To avoid table size changes (which create migration issues),
1594 * always create the table even if there are no allocations,
1595 * but set the signature to a reserved value in this case.
1596 * ACPI spec requires OSPMs to ignore such tables.
1597 */
1598 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
1599 /* Reserved signature: ignored by OSPM */
1600 sig = "QEMU";
1601 } else {
1602 sig = "MCFG";
1603 }
1604 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL);
1605 }
1606
1607 static void
1608 build_dmar_q35(GArray *table_data, GArray *linker)
1609 {
1610 int dmar_start = table_data->len;
1611
1612 AcpiTableDmar *dmar;
1613 AcpiDmarHardwareUnit *drhd;
1614
1615 dmar = acpi_data_push(table_data, sizeof(*dmar));
1616 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
1617 dmar->flags = 0; /* No intr_remap for now */
1618
1619 /* DMAR Remapping Hardware Unit Definition structure */
1620 drhd = acpi_data_push(table_data, sizeof(*drhd));
1621 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
1622 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
1623 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
1624 drhd->pci_segment = cpu_to_le16(0);
1625 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
1626
1627 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
1628 "DMAR", table_data->len - dmar_start, 1, NULL);
1629 }
1630
1631 static void
1632 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
1633 {
1634 AcpiTableHeader *dsdt;
1635
1636 assert(misc->dsdt_code && misc->dsdt_size);
1637
1638 dsdt = acpi_data_push(table_data, misc->dsdt_size);
1639 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size);
1640
1641 memset(dsdt, 0, sizeof *dsdt);
1642 build_header(linker, table_data, dsdt, "DSDT",
1643 misc->dsdt_size, 1, NULL);
1644 }
1645
1646 static GArray *
1647 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
1648 {
1649 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
1650
1651 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
1652 true /* fseg memory */);
1653
1654 memcpy(&rsdp->signature, "RSD PTR ", 8);
1655 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
1656 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
1657 /* Address to be filled by Guest linker */
1658 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
1659 ACPI_BUILD_TABLE_FILE,
1660 rsdp_table, &rsdp->rsdt_physical_address,
1661 sizeof rsdp->rsdt_physical_address);
1662 rsdp->checksum = 0;
1663 /* Checksum to be filled by Guest linker */
1664 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
1665 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
1666
1667 return rsdp_table;
1668 }
1669
1670 typedef
1671 struct AcpiBuildState {
1672 /* Copy of table in RAM (for patching). */
1673 MemoryRegion *table_mr;
1674 /* Is table patched? */
1675 uint8_t patched;
1676 PcGuestInfo *guest_info;
1677 void *rsdp;
1678 MemoryRegion *rsdp_mr;
1679 MemoryRegion *linker_mr;
1680 } AcpiBuildState;
1681
1682 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
1683 {
1684 Object *pci_host;
1685 QObject *o;
1686
1687 pci_host = acpi_get_i386_pci_host();
1688 g_assert(pci_host);
1689
1690 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
1691 if (!o) {
1692 return false;
1693 }
1694 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
1695 qobject_decref(o);
1696
1697 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
1698 assert(o);
1699 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
1700 qobject_decref(o);
1701 return true;
1702 }
1703
1704 static bool acpi_has_iommu(void)
1705 {
1706 bool ambiguous;
1707 Object *intel_iommu;
1708
1709 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
1710 &ambiguous);
1711 return intel_iommu && !ambiguous;
1712 }
1713
1714 static bool acpi_has_nvdimm(void)
1715 {
1716 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1717
1718 return pcms->nvdimm;
1719 }
1720
1721 static
1722 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
1723 {
1724 GArray *table_offsets;
1725 unsigned facs, ssdt, dsdt, rsdt;
1726 AcpiCpuInfo cpu;
1727 AcpiPmInfo pm;
1728 AcpiMiscInfo misc;
1729 AcpiMcfgInfo mcfg;
1730 PcPciInfo pci;
1731 uint8_t *u;
1732 size_t aml_len = 0;
1733 GArray *tables_blob = tables->table_data;
1734
1735 acpi_get_cpu_info(&cpu);
1736 acpi_get_pm_info(&pm);
1737 acpi_get_dsdt(&misc);
1738 acpi_get_misc_info(&misc);
1739 acpi_get_pci_info(&pci);
1740
1741 table_offsets = g_array_new(false, true /* clear */,
1742 sizeof(uint32_t));
1743 ACPI_BUILD_DPRINTF("init ACPI tables\n");
1744
1745 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
1746 64 /* Ensure FACS is aligned */,
1747 false /* high memory */);
1748
1749 /*
1750 * FACS is pointed to by FADT.
1751 * We place it first since it's the only table that has alignment
1752 * requirements.
1753 */
1754 facs = tables_blob->len;
1755 build_facs(tables_blob, tables->linker, guest_info);
1756
1757 /* DSDT is pointed to by FADT */
1758 dsdt = tables_blob->len;
1759 build_dsdt(tables_blob, tables->linker, &misc);
1760
1761 /* Count the size of the DSDT and SSDT, we will need it for legacy
1762 * sizing of ACPI tables.
1763 */
1764 aml_len += tables_blob->len - dsdt;
1765
1766 /* ACPI tables pointed to by RSDT */
1767 acpi_add_table(table_offsets, tables_blob);
1768 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt);
1769
1770 ssdt = tables_blob->len;
1771 acpi_add_table(table_offsets, tables_blob);
1772 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci,
1773 guest_info);
1774 aml_len += tables_blob->len - ssdt;
1775
1776 acpi_add_table(table_offsets, tables_blob);
1777 build_madt(tables_blob, tables->linker, &cpu, guest_info);
1778
1779 if (misc.has_hpet) {
1780 acpi_add_table(table_offsets, tables_blob);
1781 build_hpet(tables_blob, tables->linker);
1782 }
1783 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
1784 acpi_add_table(table_offsets, tables_blob);
1785 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
1786
1787 if (misc.tpm_version == TPM_VERSION_2_0) {
1788 acpi_add_table(table_offsets, tables_blob);
1789 build_tpm2(tables_blob, tables->linker);
1790 }
1791 }
1792 if (guest_info->numa_nodes) {
1793 acpi_add_table(table_offsets, tables_blob);
1794 build_srat(tables_blob, tables->linker, guest_info);
1795 }
1796 if (acpi_get_mcfg(&mcfg)) {
1797 acpi_add_table(table_offsets, tables_blob);
1798 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
1799 }
1800 if (acpi_has_iommu()) {
1801 acpi_add_table(table_offsets, tables_blob);
1802 build_dmar_q35(tables_blob, tables->linker);
1803 }
1804
1805 if (acpi_has_nvdimm()) {
1806 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
1807 }
1808
1809 /* Add tables supplied by user (if any) */
1810 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
1811 unsigned len = acpi_table_len(u);
1812
1813 acpi_add_table(table_offsets, tables_blob);
1814 g_array_append_vals(tables_blob, u, len);
1815 }
1816
1817 /* RSDT is pointed to by RSDP */
1818 rsdt = tables_blob->len;
1819 build_rsdt(tables_blob, tables->linker, table_offsets);
1820
1821 /* RSDP is in FSEG memory, so allocate it separately */
1822 build_rsdp(tables->rsdp, tables->linker, rsdt);
1823
1824 /* We'll expose it all to Guest so we want to reduce
1825 * chance of size changes.
1826 *
1827 * We used to align the tables to 4k, but of course this would
1828 * too simple to be enough. 4k turned out to be too small an
1829 * alignment very soon, and in fact it is almost impossible to
1830 * keep the table size stable for all (max_cpus, max_memory_slots)
1831 * combinations. So the table size is always 64k for pc-i440fx-2.1
1832 * and we give an error if the table grows beyond that limit.
1833 *
1834 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
1835 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
1836 * than 2.0 and we can always pad the smaller tables with zeros. We can
1837 * then use the exact size of the 2.0 tables.
1838 *
1839 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
1840 */
1841 if (guest_info->legacy_acpi_table_size) {
1842 /* Subtracting aml_len gives the size of fixed tables. Then add the
1843 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
1844 */
1845 int legacy_aml_len =
1846 guest_info->legacy_acpi_table_size +
1847 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
1848 int legacy_table_size =
1849 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
1850 ACPI_BUILD_ALIGN_SIZE);
1851 if (tables_blob->len > legacy_table_size) {
1852 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
1853 error_report("Warning: migration may not work.");
1854 }
1855 g_array_set_size(tables_blob, legacy_table_size);
1856 } else {
1857 /* Make sure we have a buffer in case we need to resize the tables. */
1858 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1859 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
1860 error_report("Warning: ACPI tables are larger than 64k.");
1861 error_report("Warning: migration may not work.");
1862 error_report("Warning: please remove CPUs, NUMA nodes, "
1863 "memory slots or PCI bridges.");
1864 }
1865 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1866 }
1867
1868 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
1869
1870 /* Cleanup memory that's no longer used. */
1871 g_array_free(table_offsets, true);
1872 }
1873
1874 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
1875 {
1876 uint32_t size = acpi_data_len(data);
1877
1878 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
1879 memory_region_ram_resize(mr, size, &error_abort);
1880
1881 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
1882 memory_region_set_dirty(mr, 0, size);
1883 }
1884
1885 static void acpi_build_update(void *build_opaque)
1886 {
1887 AcpiBuildState *build_state = build_opaque;
1888 AcpiBuildTables tables;
1889
1890 /* No state to update or already patched? Nothing to do. */
1891 if (!build_state || build_state->patched) {
1892 return;
1893 }
1894 build_state->patched = 1;
1895
1896 acpi_build_tables_init(&tables);
1897
1898 acpi_build(build_state->guest_info, &tables);
1899
1900 acpi_ram_update(build_state->table_mr, tables.table_data);
1901
1902 if (build_state->rsdp) {
1903 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
1904 } else {
1905 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
1906 }
1907
1908 acpi_ram_update(build_state->linker_mr, tables.linker);
1909 acpi_build_tables_cleanup(&tables, true);
1910 }
1911
1912 static void acpi_build_reset(void *build_opaque)
1913 {
1914 AcpiBuildState *build_state = build_opaque;
1915 build_state->patched = 0;
1916 }
1917
1918 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
1919 GArray *blob, const char *name,
1920 uint64_t max_size)
1921 {
1922 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
1923 name, acpi_build_update, build_state);
1924 }
1925
1926 static const VMStateDescription vmstate_acpi_build = {
1927 .name = "acpi_build",
1928 .version_id = 1,
1929 .minimum_version_id = 1,
1930 .fields = (VMStateField[]) {
1931 VMSTATE_UINT8(patched, AcpiBuildState),
1932 VMSTATE_END_OF_LIST()
1933 },
1934 };
1935
1936 void acpi_setup(PcGuestInfo *guest_info)
1937 {
1938 AcpiBuildTables tables;
1939 AcpiBuildState *build_state;
1940
1941 if (!guest_info->fw_cfg) {
1942 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
1943 return;
1944 }
1945
1946 if (!guest_info->has_acpi_build) {
1947 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
1948 return;
1949 }
1950
1951 if (!acpi_enabled) {
1952 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
1953 return;
1954 }
1955
1956 build_state = g_malloc0(sizeof *build_state);
1957
1958 build_state->guest_info = guest_info;
1959
1960 acpi_set_pci_info();
1961
1962 acpi_build_tables_init(&tables);
1963 acpi_build(build_state->guest_info, &tables);
1964
1965 /* Now expose it all to Guest */
1966 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
1967 ACPI_BUILD_TABLE_FILE,
1968 ACPI_BUILD_TABLE_MAX_SIZE);
1969 assert(build_state->table_mr != NULL);
1970
1971 build_state->linker_mr =
1972 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
1973
1974 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
1975 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
1976
1977 if (!guest_info->rsdp_in_ram) {
1978 /*
1979 * Keep for compatibility with old machine types.
1980 * Though RSDP is small, its contents isn't immutable, so
1981 * we'll update it along with the rest of tables on guest access.
1982 */
1983 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
1984
1985 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
1986 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
1987 acpi_build_update, build_state,
1988 build_state->rsdp, rsdp_size);
1989 build_state->rsdp_mr = NULL;
1990 } else {
1991 build_state->rsdp = NULL;
1992 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
1993 ACPI_BUILD_RSDP_FILE, 0);
1994 }
1995
1996 qemu_register_reset(acpi_build_reset, build_state);
1997 acpi_build_reset(build_state);
1998 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
1999
2000 /* Cleanup tables but don't free the memory: we track it
2001 * in build_state.
2002 */
2003 acpi_build_tables_cleanup(&tables, false);
2004 }
AR7 emulation for QEMU