hw/arm/stellaris.c

   1 /*
   2  * Luminary Micro Stellaris peripherals
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "hw/sysbus.h"
  13 #include "hw/ssi/ssi.h"
  14 #include "hw/arm/arm.h"
  15 #include "hw/devices.h"
  16 #include "qemu/timer.h"
  17 #include "hw/i2c/i2c.h"
  18 #include "net/net.h"
  19 #include "hw/boards.h"
  20 #include "qemu/log.h"
  21 #include "exec/address-spaces.h"
  22 #include "sysemu/sysemu.h"
  23 #include "hw/arm/armv7m.h"
  24 #include "hw/char/pl011.h"
  25 #include "hw/misc/unimp.h"
  26 #include "cpu.h"
  27
  28 #define GPIO_A 0
  29 #define GPIO_B 1
  30 #define GPIO_C 2
  31 #define GPIO_D 3
  32 #define GPIO_E 4
  33 #define GPIO_F 5
  34 #define GPIO_G 6
  35
  36 #define BP_OLED_I2C  0x01
  37 #define BP_OLED_SSI  0x02
  38 #define BP_GAMEPAD   0x04
  39
  40 #define NUM_IRQ_LINES 64
  41
  42 typedef const struct {
  43     const char *name;
  44     uint32_t did0;
  45     uint32_t did1;
  46     uint32_t dc0;
  47     uint32_t dc1;
  48     uint32_t dc2;
  49     uint32_t dc3;
  50     uint32_t dc4;
  51     uint32_t peripherals;
  52 } stellaris_board_info;
  53
  54 /* General purpose timer module.  */
  55
  56 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
  57 #define STELLARIS_GPTM(obj) \
  58     OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM)
  59
  60 typedef struct gptm_state {
  61     SysBusDevice parent_obj;
  62
  63     MemoryRegion iomem;
  64     uint32_t config;
  65     uint32_t mode[2];
  66     uint32_t control;
  67     uint32_t state;
  68     uint32_t mask;
  69     uint32_t load[2];
  70     uint32_t match[2];
  71     uint32_t prescale[2];
  72     uint32_t match_prescale[2];
  73     uint32_t rtc;
  74     int64_t tick[2];
  75     struct gptm_state *opaque[2];
  76     QEMUTimer *timer[2];
  77     /* The timers have an alternate output used to trigger the ADC.  */
  78     qemu_irq trigger;
  79     qemu_irq irq;
  80 } gptm_state;
  81
  82 static void gptm_update_irq(gptm_state *s)
  83 {
  84     int level;
  85     level = (s->state & s->mask) != 0;
  86     qemu_set_irq(s->irq, level);
  87 }
  88
  89 static void gptm_stop(gptm_state *s, int n)
  90 {
  91     timer_del(s->timer[n]);
  92 }
  93
  94 static void gptm_reload(gptm_state *s, int n, int reset)
  95 {
  96     int64_t tick;
  97     if (reset)
  98         tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  99     else
 100         tick = s->tick[n];
 101
 102     if (s->config == 0) {
 103         /* 32-bit CountDown.  */
 104         uint32_t count;
 105         count = s->load[0] | (s->load[1] << 16);
 106         tick += (int64_t)count * system_clock_scale;
 107     } else if (s->config == 1) {
 108         /* 32-bit RTC.  1Hz tick.  */
 109         tick += NANOSECONDS_PER_SECOND;
 110     } else if (s->mode[n] == 0xa) {
 111         /* PWM mode.  Not implemented.  */
 112     } else {
 113         qemu_log_mask(LOG_UNIMP,
 114                       "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
 115                       s->mode[n]);
 116         return;
 117     }
 118     s->tick[n] = tick;
 119     timer_mod(s->timer[n], tick);
 120 }
 121
 122 static void gptm_tick(void *opaque)
 123 {
 124     gptm_state **p = (gptm_state **)opaque;
 125     gptm_state *s;
 126     int n;
 127
 128     s = *p;
 129     n = p - s->opaque;
 130     if (s->config == 0) {
 131         s->state |= 1;
 132         if ((s->control & 0x20)) {
 133             /* Output trigger.  */
 134             qemu_irq_pulse(s->trigger);
 135         }
 136         if (s->mode[0] & 1) {
 137             /* One-shot.  */
 138             s->control &= ~1;
 139         } else {
 140             /* Periodic.  */
 141             gptm_reload(s, 0, 0);
 142         }
 143     } else if (s->config == 1) {
 144         /* RTC.  */
 145         uint32_t match;
 146         s->rtc++;
 147         match = s->match[0] | (s->match[1] << 16);
 148         if (s->rtc > match)
 149             s->rtc = 0;
 150         if (s->rtc == 0) {
 151             s->state |= 8;
 152         }
 153         gptm_reload(s, 0, 0);
 154     } else if (s->mode[n] == 0xa) {
 155         /* PWM mode.  Not implemented.  */
 156     } else {
 157         qemu_log_mask(LOG_UNIMP,
 158                       "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
 159                       s->mode[n]);
 160     }
 161     gptm_update_irq(s);
 162 }
 163
 164 static uint64_t gptm_read(void *opaque, hwaddr offset,
 165                           unsigned size)
 166 {
 167     gptm_state *s = (gptm_state *)opaque;
 168
 169     switch (offset) {
 170     case 0x00: /* CFG */
 171         return s->config;
 172     case 0x04: /* TAMR */
 173         return s->mode[0];
 174     case 0x08: /* TBMR */
 175         return s->mode[1];
 176     case 0x0c: /* CTL */
 177         return s->control;
 178     case 0x18: /* IMR */
 179         return s->mask;
 180     case 0x1c: /* RIS */
 181         return s->state;
 182     case 0x20: /* MIS */
 183         return s->state & s->mask;
 184     case 0x24: /* CR */
 185         return 0;
 186     case 0x28: /* TAILR */
 187         return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
 188     case 0x2c: /* TBILR */
 189         return s->load[1];
 190     case 0x30: /* TAMARCHR */
 191         return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
 192     case 0x34: /* TBMATCHR */
 193         return s->match[1];
 194     case 0x38: /* TAPR */
 195         return s->prescale[0];
 196     case 0x3c: /* TBPR */
 197         return s->prescale[1];
 198     case 0x40: /* TAPMR */
 199         return s->match_prescale[0];
 200     case 0x44: /* TBPMR */
 201         return s->match_prescale[1];
 202     case 0x48: /* TAR */
 203         if (s->config == 1) {
 204             return s->rtc;
 205         }
 206         qemu_log_mask(LOG_UNIMP,
 207                       "GPTM: read of TAR but timer read not supported\n");
 208         return 0;
 209     case 0x4c: /* TBR */
 210         qemu_log_mask(LOG_UNIMP,
 211                       "GPTM: read of TBR but timer read not supported\n");
 212         return 0;
 213     default:
 214         qemu_log_mask(LOG_GUEST_ERROR,
 215                       "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n",
 216                       offset);
 217         return 0;
 218     }
 219 }
 220
 221 static void gptm_write(void *opaque, hwaddr offset,
 222                        uint64_t value, unsigned size)
 223 {
 224     gptm_state *s = (gptm_state *)opaque;
 225     uint32_t oldval;
 226
 227     /* The timers should be disabled before changing the configuration.
 228        We take advantage of this and defer everything until the timer
 229        is enabled.  */
 230     switch (offset) {
 231     case 0x00: /* CFG */
 232         s->config = value;
 233         break;
 234     case 0x04: /* TAMR */
 235         s->mode[0] = value;
 236         break;
 237     case 0x08: /* TBMR */
 238         s->mode[1] = value;
 239         break;
 240     case 0x0c: /* CTL */
 241         oldval = s->control;
 242         s->control = value;
 243         /* TODO: Implement pause.  */
 244         if ((oldval ^ value) & 1) {
 245             if (value & 1) {
 246                 gptm_reload(s, 0, 1);
 247             } else {
 248                 gptm_stop(s, 0);
 249             }
 250         }
 251         if (((oldval ^ value) & 0x100) && s->config >= 4) {
 252             if (value & 0x100) {
 253                 gptm_reload(s, 1, 1);
 254             } else {
 255                 gptm_stop(s, 1);
 256             }
 257         }
 258         break;
 259     case 0x18: /* IMR */
 260         s->mask = value & 0x77;
 261         gptm_update_irq(s);
 262         break;
 263     case 0x24: /* CR */
 264         s->state &= ~value;
 265         break;
 266     case 0x28: /* TAILR */
 267         s->load[0] = value & 0xffff;
 268         if (s->config < 4) {
 269             s->load[1] = value >> 16;
 270         }
 271         break;
 272     case 0x2c: /* TBILR */
 273         s->load[1] = value & 0xffff;
 274         break;
 275     case 0x30: /* TAMARCHR */
 276         s->match[0] = value & 0xffff;
 277         if (s->config < 4) {
 278             s->match[1] = value >> 16;
 279         }
 280         break;
 281     case 0x34: /* TBMATCHR */
 282         s->match[1] = value >> 16;
 283         break;
 284     case 0x38: /* TAPR */
 285         s->prescale[0] = value;
 286         break;
 287     case 0x3c: /* TBPR */
 288         s->prescale[1] = value;
 289         break;
 290     case 0x40: /* TAPMR */
 291         s->match_prescale[0] = value;
 292         break;
 293     case 0x44: /* TBPMR */
 294         s->match_prescale[0] = value;
 295         break;
 296     default:
 297         qemu_log_mask(LOG_GUEST_ERROR,
 298                       "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n",
 299                       offset);
 300     }
 301     gptm_update_irq(s);
 302 }
 303
 304 static const MemoryRegionOps gptm_ops = {
 305     .read = gptm_read,
 306     .write = gptm_write,
 307     .endianness = DEVICE_NATIVE_ENDIAN,
 308 };
 309
 310 static const VMStateDescription vmstate_stellaris_gptm = {
 311     .name = "stellaris_gptm",
 312     .version_id = 1,
 313     .minimum_version_id = 1,
 314     .fields = (VMStateField[]) {
 315         VMSTATE_UINT32(config, gptm_state),
 316         VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
 317         VMSTATE_UINT32(control, gptm_state),
 318         VMSTATE_UINT32(state, gptm_state),
 319         VMSTATE_UINT32(mask, gptm_state),
 320         VMSTATE_UNUSED(8),
 321         VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
 322         VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
 323         VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
 324         VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
 325         VMSTATE_UINT32(rtc, gptm_state),
 326         VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
 327         VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
 328         VMSTATE_END_OF_LIST()
 329     }
 330 };
 331
 332 static void stellaris_gptm_init(Object *obj)
 333 {
 334     DeviceState *dev = DEVICE(obj);
 335     gptm_state *s = STELLARIS_GPTM(obj);
 336     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 337
 338     sysbus_init_irq(sbd, &s->irq);
 339     qdev_init_gpio_out(dev, &s->trigger, 1);
 340
 341     memory_region_init_io(&s->iomem, obj, &gptm_ops, s,
 342                           "gptm", 0x1000);
 343     sysbus_init_mmio(sbd, &s->iomem);
 344
 345     s->opaque[0] = s->opaque[1] = s;
 346     s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
 347     s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
 348 }
 349
 350
 351 /* System controller.  */
 352
 353 typedef struct {
 354     MemoryRegion iomem;
 355     uint32_t pborctl;
 356     uint32_t ldopctl;
 357     uint32_t int_status;
 358     uint32_t int_mask;
 359     uint32_t resc;
 360     uint32_t rcc;
 361     uint32_t rcc2;
 362     uint32_t rcgc[3];
 363     uint32_t scgc[3];
 364     uint32_t dcgc[3];
 365     uint32_t clkvclr;
 366     uint32_t ldoarst;
 367     uint32_t user0;
 368     uint32_t user1;
 369     qemu_irq irq;
 370     stellaris_board_info *board;
 371 } ssys_state;
 372
 373 static void ssys_update(ssys_state *s)
 374 {
 375   qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
 376 }
 377
 378 static uint32_t pllcfg_sandstorm[16] = {
 379     0x31c0, /* 1 Mhz */
 380     0x1ae0, /* 1.8432 Mhz */
 381     0x18c0, /* 2 Mhz */
 382     0xd573, /* 2.4576 Mhz */
 383     0x37a6, /* 3.57954 Mhz */
 384     0x1ae2, /* 3.6864 Mhz */
 385     0x0c40, /* 4 Mhz */
 386     0x98bc, /* 4.906 Mhz */
 387     0x935b, /* 4.9152 Mhz */
 388     0x09c0, /* 5 Mhz */
 389     0x4dee, /* 5.12 Mhz */
 390     0x0c41, /* 6 Mhz */
 391     0x75db, /* 6.144 Mhz */
 392     0x1ae6, /* 7.3728 Mhz */
 393     0x0600, /* 8 Mhz */
 394     0x585b /* 8.192 Mhz */
 395 };
 396
 397 static uint32_t pllcfg_fury[16] = {
 398     0x3200, /* 1 Mhz */
 399     0x1b20, /* 1.8432 Mhz */
 400     0x1900, /* 2 Mhz */
 401     0xf42b, /* 2.4576 Mhz */
 402     0x37e3, /* 3.57954 Mhz */
 403     0x1b21, /* 3.6864 Mhz */
 404     0x0c80, /* 4 Mhz */
 405     0x98ee, /* 4.906 Mhz */
 406     0xd5b4, /* 4.9152 Mhz */
 407     0x0a00, /* 5 Mhz */
 408     0x4e27, /* 5.12 Mhz */
 409     0x1902, /* 6 Mhz */
 410     0xec1c, /* 6.144 Mhz */
 411     0x1b23, /* 7.3728 Mhz */
 412     0x0640, /* 8 Mhz */
 413     0xb11c /* 8.192 Mhz */
 414 };
 415
 416 #define DID0_VER_MASK        0x70000000
 417 #define DID0_VER_0           0x00000000
 418 #define DID0_VER_1           0x10000000
 419
 420 #define DID0_CLASS_MASK      0x00FF0000
 421 #define DID0_CLASS_SANDSTORM 0x00000000
 422 #define DID0_CLASS_FURY      0x00010000
 423
 424 static int ssys_board_class(const ssys_state *s)
 425 {
 426     uint32_t did0 = s->board->did0;
 427     switch (did0 & DID0_VER_MASK) {
 428     case DID0_VER_0:
 429         return DID0_CLASS_SANDSTORM;
 430     case DID0_VER_1:
 431         switch (did0 & DID0_CLASS_MASK) {
 432         case DID0_CLASS_SANDSTORM:
 433         case DID0_CLASS_FURY:
 434             return did0 & DID0_CLASS_MASK;
 435         }
 436         /* for unknown classes, fall through */
 437     default:
 438         /* This can only happen if the hardwired constant did0 value
 439          * in this board's stellaris_board_info struct is wrong.
 440          */
 441         g_assert_not_reached();
 442     }
 443 }
 444
 445 static uint64_t ssys_read(void *opaque, hwaddr offset,
 446                           unsigned size)
 447 {
 448     ssys_state *s = (ssys_state *)opaque;
 449
 450     switch (offset) {
 451     case 0x000: /* DID0 */
 452         return s->board->did0;
 453     case 0x004: /* DID1 */
 454         return s->board->did1;
 455     case 0x008: /* DC0 */
 456         return s->board->dc0;
 457     case 0x010: /* DC1 */
 458         return s->board->dc1;
 459     case 0x014: /* DC2 */
 460         return s->board->dc2;
 461     case 0x018: /* DC3 */
 462         return s->board->dc3;
 463     case 0x01c: /* DC4 */
 464         return s->board->dc4;
 465     case 0x030: /* PBORCTL */
 466         return s->pborctl;
 467     case 0x034: /* LDOPCTL */
 468         return s->ldopctl;
 469     case 0x040: /* SRCR0 */
 470         return 0;
 471     case 0x044: /* SRCR1 */
 472         return 0;
 473     case 0x048: /* SRCR2 */
 474         return 0;
 475     case 0x050: /* RIS */
 476         return s->int_status;
 477     case 0x054: /* IMC */
 478         return s->int_mask;
 479     case 0x058: /* MISC */
 480         return s->int_status & s->int_mask;
 481     case 0x05c: /* RESC */
 482         return s->resc;
 483     case 0x060: /* RCC */
 484         return s->rcc;
 485     case 0x064: /* PLLCFG */
 486         {
 487             int xtal;
 488             xtal = (s->rcc >> 6) & 0xf;
 489             switch (ssys_board_class(s)) {
 490             case DID0_CLASS_FURY:
 491                 return pllcfg_fury[xtal];
 492             case DID0_CLASS_SANDSTORM:
 493                 return pllcfg_sandstorm[xtal];
 494             default:
 495                 g_assert_not_reached();
 496             }
 497         }
 498     case 0x070: /* RCC2 */
 499         return s->rcc2;
 500     case 0x100: /* RCGC0 */
 501         return s->rcgc[0];
 502     case 0x104: /* RCGC1 */
 503         return s->rcgc[1];
 504     case 0x108: /* RCGC2 */
 505         return s->rcgc[2];
 506     case 0x110: /* SCGC0 */
 507         return s->scgc[0];
 508     case 0x114: /* SCGC1 */
 509         return s->scgc[1];
 510     case 0x118: /* SCGC2 */
 511         return s->scgc[2];
 512     case 0x120: /* DCGC0 */
 513         return s->dcgc[0];
 514     case 0x124: /* DCGC1 */
 515         return s->dcgc[1];
 516     case 0x128: /* DCGC2 */
 517         return s->dcgc[2];
 518     case 0x150: /* CLKVCLR */
 519         return s->clkvclr;
 520     case 0x160: /* LDOARST */
 521         return s->ldoarst;
 522     case 0x1e0: /* USER0 */
 523         return s->user0;
 524     case 0x1e4: /* USER1 */
 525         return s->user1;
 526     default:
 527         qemu_log_mask(LOG_GUEST_ERROR,
 528                       "SSYS: read at bad offset 0x%x\n", (int)offset);
 529         return 0;
 530     }
 531 }
 532
 533 static bool ssys_use_rcc2(ssys_state *s)
 534 {
 535     return (s->rcc2 >> 31) & 0x1;
 536 }
 537
 538 /*
 539  * Caculate the sys. clock period in ms.
 540  */
 541 static void ssys_calculate_system_clock(ssys_state *s)
 542 {
 543     if (ssys_use_rcc2(s)) {
 544         system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
 545     } else {
 546         system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
 547     }
 548 }
 549
 550 static void ssys_write(void *opaque, hwaddr offset,
 551                        uint64_t value, unsigned size)
 552 {
 553     ssys_state *s = (ssys_state *)opaque;
 554
 555     switch (offset) {
 556     case 0x030: /* PBORCTL */
 557         s->pborctl = value & 0xffff;
 558         break;
 559     case 0x034: /* LDOPCTL */
 560         s->ldopctl = value & 0x1f;
 561         break;
 562     case 0x040: /* SRCR0 */
 563     case 0x044: /* SRCR1 */
 564     case 0x048: /* SRCR2 */
 565         qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n");
 566         break;
 567     case 0x054: /* IMC */
 568         s->int_mask = value & 0x7f;
 569         break;
 570     case 0x058: /* MISC */
 571         s->int_status &= ~value;
 572         break;
 573     case 0x05c: /* RESC */
 574         s->resc = value & 0x3f;
 575         break;
 576     case 0x060: /* RCC */
 577         if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 578             /* PLL enable.  */
 579             s->int_status |= (1 << 6);
 580         }
 581         s->rcc = value;
 582         ssys_calculate_system_clock(s);
 583         break;
 584     case 0x070: /* RCC2 */
 585         if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 586             break;
 587         }
 588
 589         if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 590             /* PLL enable.  */
 591             s->int_status |= (1 << 6);
 592         }
 593         s->rcc2 = value;
 594         ssys_calculate_system_clock(s);
 595         break;
 596     case 0x100: /* RCGC0 */
 597         s->rcgc[0] = value;
 598         break;
 599     case 0x104: /* RCGC1 */
 600         s->rcgc[1] = value;
 601         break;
 602     case 0x108: /* RCGC2 */
 603         s->rcgc[2] = value;
 604         break;
 605     case 0x110: /* SCGC0 */
 606         s->scgc[0] = value;
 607         break;
 608     case 0x114: /* SCGC1 */
 609         s->scgc[1] = value;
 610         break;
 611     case 0x118: /* SCGC2 */
 612         s->scgc[2] = value;
 613         break;
 614     case 0x120: /* DCGC0 */
 615         s->dcgc[0] = value;
 616         break;
 617     case 0x124: /* DCGC1 */
 618         s->dcgc[1] = value;
 619         break;
 620     case 0x128: /* DCGC2 */
 621         s->dcgc[2] = value;
 622         break;
 623     case 0x150: /* CLKVCLR */
 624         s->clkvclr = value;
 625         break;
 626     case 0x160: /* LDOARST */
 627         s->ldoarst = value;
 628         break;
 629     default:
 630         qemu_log_mask(LOG_GUEST_ERROR,
 631                       "SSYS: write at bad offset 0x%x\n", (int)offset);
 632     }
 633     ssys_update(s);
 634 }
 635
 636 static const MemoryRegionOps ssys_ops = {
 637     .read = ssys_read,
 638     .write = ssys_write,
 639     .endianness = DEVICE_NATIVE_ENDIAN,
 640 };
 641
 642 static void ssys_reset(void *opaque)
 643 {
 644     ssys_state *s = (ssys_state *)opaque;
 645
 646     s->pborctl = 0x7ffd;
 647     s->rcc = 0x078e3ac0;
 648
 649     if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 650         s->rcc2 = 0;
 651     } else {
 652         s->rcc2 = 0x07802810;
 653     }
 654     s->rcgc[0] = 1;
 655     s->scgc[0] = 1;
 656     s->dcgc[0] = 1;
 657     ssys_calculate_system_clock(s);
 658 }
 659
 660 static int stellaris_sys_post_load(void *opaque, int version_id)
 661 {
 662     ssys_state *s = opaque;
 663
 664     ssys_calculate_system_clock(s);
 665
 666     return 0;
 667 }
 668
 669 static const VMStateDescription vmstate_stellaris_sys = {
 670     .name = "stellaris_sys",
 671     .version_id = 2,
 672     .minimum_version_id = 1,
 673     .post_load = stellaris_sys_post_load,
 674     .fields = (VMStateField[]) {
 675         VMSTATE_UINT32(pborctl, ssys_state),
 676         VMSTATE_UINT32(ldopctl, ssys_state),
 677         VMSTATE_UINT32(int_mask, ssys_state),
 678         VMSTATE_UINT32(int_status, ssys_state),
 679         VMSTATE_UINT32(resc, ssys_state),
 680         VMSTATE_UINT32(rcc, ssys_state),
 681         VMSTATE_UINT32_V(rcc2, ssys_state, 2),
 682         VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
 683         VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
 684         VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
 685         VMSTATE_UINT32(clkvclr, ssys_state),
 686         VMSTATE_UINT32(ldoarst, ssys_state),
 687         VMSTATE_END_OF_LIST()
 688     }
 689 };
 690
 691 static int stellaris_sys_init(uint32_t base, qemu_irq irq,
 692                               stellaris_board_info * board,
 693                               uint8_t *macaddr)
 694 {
 695     ssys_state *s;
 696
 697     s = g_new0(ssys_state, 1);
 698     s->irq = irq;
 699     s->board = board;
 700     /* Most devices come preprogrammed with a MAC address in the user data. */
 701     s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
 702     s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
 703
 704     memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
 705     memory_region_add_subregion(get_system_memory(), base, &s->iomem);
 706     ssys_reset(s);
 707     vmstate_register(NULL, -1, &vmstate_stellaris_sys, s);
 708     return 0;
 709 }
 710
 711
 712 /* I2C controller.  */
 713
 714 #define TYPE_STELLARIS_I2C "stellaris-i2c"
 715 #define STELLARIS_I2C(obj) \
 716     OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C)
 717
 718 typedef struct {
 719     SysBusDevice parent_obj;
 720
 721     I2CBus *bus;
 722     qemu_irq irq;
 723     MemoryRegion iomem;
 724     uint32_t msa;
 725     uint32_t mcs;
 726     uint32_t mdr;
 727     uint32_t mtpr;
 728     uint32_t mimr;
 729     uint32_t mris;
 730     uint32_t mcr;
 731 } stellaris_i2c_state;
 732
 733 #define STELLARIS_I2C_MCS_BUSY    0x01
 734 #define STELLARIS_I2C_MCS_ERROR   0x02
 735 #define STELLARIS_I2C_MCS_ADRACK  0x04
 736 #define STELLARIS_I2C_MCS_DATACK  0x08
 737 #define STELLARIS_I2C_MCS_ARBLST  0x10
 738 #define STELLARIS_I2C_MCS_IDLE    0x20
 739 #define STELLARIS_I2C_MCS_BUSBSY  0x40
 740
 741 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
 742                                    unsigned size)
 743 {
 744     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 745
 746     switch (offset) {
 747     case 0x00: /* MSA */
 748         return s->msa;
 749     case 0x04: /* MCS */
 750         /* We don't emulate timing, so the controller is never busy.  */
 751         return s->mcs | STELLARIS_I2C_MCS_IDLE;
 752     case 0x08: /* MDR */
 753         return s->mdr;
 754     case 0x0c: /* MTPR */
 755         return s->mtpr;
 756     case 0x10: /* MIMR */
 757         return s->mimr;
 758     case 0x14: /* MRIS */
 759         return s->mris;
 760     case 0x18: /* MMIS */
 761         return s->mris & s->mimr;
 762     case 0x20: /* MCR */
 763         return s->mcr;
 764     default:
 765         qemu_log_mask(LOG_GUEST_ERROR,
 766                       "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
 767         return 0;
 768     }
 769 }
 770
 771 static void stellaris_i2c_update(stellaris_i2c_state *s)
 772 {
 773     int level;
 774
 775     level = (s->mris & s->mimr) != 0;
 776     qemu_set_irq(s->irq, level);
 777 }
 778
 779 static void stellaris_i2c_write(void *opaque, hwaddr offset,
 780                                 uint64_t value, unsigned size)
 781 {
 782     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 783
 784     switch (offset) {
 785     case 0x00: /* MSA */
 786         s->msa = value & 0xff;
 787         break;
 788     case 0x04: /* MCS */
 789         if ((s->mcr & 0x10) == 0) {
 790             /* Disabled.  Do nothing.  */
 791             break;
 792         }
 793         /* Grab the bus if this is starting a transfer.  */
 794         if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 795             if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
 796                 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
 797             } else {
 798                 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
 799                 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
 800             }
 801         }
 802         /* If we don't have the bus then indicate an error.  */
 803         if (!i2c_bus_busy(s->bus)
 804                 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 805             s->mcs |= STELLARIS_I2C_MCS_ERROR;
 806             break;
 807         }
 808         s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
 809         if (value & 1) {
 810             /* Transfer a byte.  */
 811             /* TODO: Handle errors.  */
 812             if (s->msa & 1) {
 813                 /* Recv */
 814                 s->mdr = i2c_recv(s->bus) & 0xff;
 815             } else {
 816                 /* Send */
 817                 i2c_send(s->bus, s->mdr);
 818             }
 819             /* Raise an interrupt.  */
 820             s->mris |= 1;
 821         }
 822         if (value & 4) {
 823             /* Finish transfer.  */
 824             i2c_end_transfer(s->bus);
 825             s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
 826         }
 827         break;
 828     case 0x08: /* MDR */
 829         s->mdr = value & 0xff;
 830         break;
 831     case 0x0c: /* MTPR */
 832         s->mtpr = value & 0xff;
 833         break;
 834     case 0x10: /* MIMR */
 835         s->mimr = 1;
 836         break;
 837     case 0x1c: /* MICR */
 838         s->mris &= ~value;
 839         break;
 840     case 0x20: /* MCR */
 841         if (value & 1) {
 842             qemu_log_mask(LOG_UNIMP,
 843                           "stellaris_i2c: Loopback not implemented\n");
 844         }
 845         if (value & 0x20) {
 846             qemu_log_mask(LOG_UNIMP,
 847                           "stellaris_i2c: Slave mode not implemented\n");
 848         }
 849         s->mcr = value & 0x31;
 850         break;
 851     default:
 852         qemu_log_mask(LOG_GUEST_ERROR,
 853                       "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
 854     }
 855     stellaris_i2c_update(s);
 856 }
 857
 858 static void stellaris_i2c_reset(stellaris_i2c_state *s)
 859 {
 860     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
 861         i2c_end_transfer(s->bus);
 862
 863     s->msa = 0;
 864     s->mcs = 0;
 865     s->mdr = 0;
 866     s->mtpr = 1;
 867     s->mimr = 0;
 868     s->mris = 0;
 869     s->mcr = 0;
 870     stellaris_i2c_update(s);
 871 }
 872
 873 static const MemoryRegionOps stellaris_i2c_ops = {
 874     .read = stellaris_i2c_read,
 875     .write = stellaris_i2c_write,
 876     .endianness = DEVICE_NATIVE_ENDIAN,
 877 };
 878
 879 static const VMStateDescription vmstate_stellaris_i2c = {
 880     .name = "stellaris_i2c",
 881     .version_id = 1,
 882     .minimum_version_id = 1,
 883     .fields = (VMStateField[]) {
 884         VMSTATE_UINT32(msa, stellaris_i2c_state),
 885         VMSTATE_UINT32(mcs, stellaris_i2c_state),
 886         VMSTATE_UINT32(mdr, stellaris_i2c_state),
 887         VMSTATE_UINT32(mtpr, stellaris_i2c_state),
 888         VMSTATE_UINT32(mimr, stellaris_i2c_state),
 889         VMSTATE_UINT32(mris, stellaris_i2c_state),
 890         VMSTATE_UINT32(mcr, stellaris_i2c_state),
 891         VMSTATE_END_OF_LIST()
 892     }
 893 };
 894
 895 static void stellaris_i2c_init(Object *obj)
 896 {
 897     DeviceState *dev = DEVICE(obj);
 898     stellaris_i2c_state *s = STELLARIS_I2C(obj);
 899     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 900     I2CBus *bus;
 901
 902     sysbus_init_irq(sbd, &s->irq);
 903     bus = i2c_init_bus(dev, "i2c");
 904     s->bus = bus;
 905
 906     memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
 907                           "i2c", 0x1000);
 908     sysbus_init_mmio(sbd, &s->iomem);
 909     /* ??? For now we only implement the master interface.  */
 910     stellaris_i2c_reset(s);
 911 }
 912
 913 /* Analogue to Digital Converter.  This is only partially implemented,
 914    enough for applications that use a combined ADC and timer tick.  */
 915
 916 #define STELLARIS_ADC_EM_CONTROLLER 0
 917 #define STELLARIS_ADC_EM_COMP       1
 918 #define STELLARIS_ADC_EM_EXTERNAL   4
 919 #define STELLARIS_ADC_EM_TIMER      5
 920 #define STELLARIS_ADC_EM_PWM0       6
 921 #define STELLARIS_ADC_EM_PWM1       7
 922 #define STELLARIS_ADC_EM_PWM2       8
 923
 924 #define STELLARIS_ADC_FIFO_EMPTY    0x0100
 925 #define STELLARIS_ADC_FIFO_FULL     0x1000
 926
 927 #define TYPE_STELLARIS_ADC "stellaris-adc"
 928 #define STELLARIS_ADC(obj) \
 929     OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC)
 930
 931 typedef struct StellarisADCState {
 932     SysBusDevice parent_obj;
 933
 934     MemoryRegion iomem;
 935     uint32_t actss;
 936     uint32_t ris;
 937     uint32_t im;
 938     uint32_t emux;
 939     uint32_t ostat;
 940     uint32_t ustat;
 941     uint32_t sspri;
 942     uint32_t sac;
 943     struct {
 944         uint32_t state;
 945         uint32_t data[16];
 946     } fifo[4];
 947     uint32_t ssmux[4];
 948     uint32_t ssctl[4];
 949     uint32_t noise;
 950     qemu_irq irq[4];
 951 } stellaris_adc_state;
 952
 953 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
 954 {
 955     int tail;
 956
 957     tail = s->fifo[n].state & 0xf;
 958     if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
 959         s->ustat |= 1 << n;
 960     } else {
 961         s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
 962         s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
 963         if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
 964             s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
 965     }
 966     return s->fifo[n].data[tail];
 967 }
 968
 969 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
 970                                      uint32_t value)
 971 {
 972     int head;
 973
 974     /* TODO: Real hardware has limited size FIFOs.  We have a full 16 entry
 975        FIFO fir each sequencer.  */
 976     head = (s->fifo[n].state >> 4) & 0xf;
 977     if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
 978         s->ostat |= 1 << n;
 979         return;
 980     }
 981     s->fifo[n].data[head] = value;
 982     head = (head + 1) & 0xf;
 983     s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
 984     s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
 985     if ((s->fifo[n].state & 0xf) == head)
 986         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
 987 }
 988
 989 static void stellaris_adc_update(stellaris_adc_state *s)
 990 {
 991     int level;
 992     int n;
 993
 994     for (n = 0; n < 4; n++) {
 995         level = (s->ris & s->im & (1 << n)) != 0;
 996         qemu_set_irq(s->irq[n], level);
 997     }
 998 }
 999
1000 static void stellaris_adc_trigger(void *opaque, int irq, int level)
1001 {
1002     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1003     int n;
1004
1005     for (n = 0; n < 4; n++) {
1006         if ((s->actss & (1 << n)) == 0) {
1007             continue;
1008         }
1009
1010         if (((s->emux >> (n * 4)) & 0xff) != 5) {
1011             continue;
1012         }
1013
1014         /* Some applications use the ADC as a random number source, so introduce
1015            some variation into the signal.  */
1016         s->noise = s->noise * 314159 + 1;
1017         /* ??? actual inputs not implemented.  Return an arbitrary value.  */
1018         stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
1019         s->ris |= (1 << n);
1020         stellaris_adc_update(s);
1021     }
1022 }
1023
1024 static void stellaris_adc_reset(stellaris_adc_state *s)
1025 {
1026     int n;
1027
1028     for (n = 0; n < 4; n++) {
1029         s->ssmux[n] = 0;
1030         s->ssctl[n] = 0;
1031         s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1032     }
1033 }
1034
1035 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
1036                                    unsigned size)
1037 {
1038     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1039
1040     /* TODO: Implement this.  */
1041     if (offset >= 0x40 && offset < 0xc0) {
1042         int n;
1043         n = (offset - 0x40) >> 5;
1044         switch (offset & 0x1f) {
1045         case 0x00: /* SSMUX */
1046             return s->ssmux[n];
1047         case 0x04: /* SSCTL */
1048             return s->ssctl[n];
1049         case 0x08: /* SSFIFO */
1050             return stellaris_adc_fifo_read(s, n);
1051         case 0x0c: /* SSFSTAT */
1052             return s->fifo[n].state;
1053         default:
1054             break;
1055         }
1056     }
1057     switch (offset) {
1058     case 0x00: /* ACTSS */
1059         return s->actss;
1060     case 0x04: /* RIS */
1061         return s->ris;
1062     case 0x08: /* IM */
1063         return s->im;
1064     case 0x0c: /* ISC */
1065         return s->ris & s->im;
1066     case 0x10: /* OSTAT */
1067         return s->ostat;
1068     case 0x14: /* EMUX */
1069         return s->emux;
1070     case 0x18: /* USTAT */
1071         return s->ustat;
1072     case 0x20: /* SSPRI */
1073         return s->sspri;
1074     case 0x30: /* SAC */
1075         return s->sac;
1076     default:
1077         qemu_log_mask(LOG_GUEST_ERROR,
1078                       "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
1079         return 0;
1080     }
1081 }
1082
1083 static void stellaris_adc_write(void *opaque, hwaddr offset,
1084                                 uint64_t value, unsigned size)
1085 {
1086     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1087
1088     /* TODO: Implement this.  */
1089     if (offset >= 0x40 && offset < 0xc0) {
1090         int n;
1091         n = (offset - 0x40) >> 5;
1092         switch (offset & 0x1f) {
1093         case 0x00: /* SSMUX */
1094             s->ssmux[n] = value & 0x33333333;
1095             return;
1096         case 0x04: /* SSCTL */
1097             if (value != 6) {
1098                 qemu_log_mask(LOG_UNIMP,
1099                               "ADC: Unimplemented sequence %" PRIx64 "\n",
1100                               value);
1101             }
1102             s->ssctl[n] = value;
1103             return;
1104         default:
1105             break;
1106         }
1107     }
1108     switch (offset) {
1109     case 0x00: /* ACTSS */
1110         s->actss = value & 0xf;
1111         break;
1112     case 0x08: /* IM */
1113         s->im = value;
1114         break;
1115     case 0x0c: /* ISC */
1116         s->ris &= ~value;
1117         break;
1118     case 0x10: /* OSTAT */
1119         s->ostat &= ~value;
1120         break;
1121     case 0x14: /* EMUX */
1122         s->emux = value;
1123         break;
1124     case 0x18: /* USTAT */
1125         s->ustat &= ~value;
1126         break;
1127     case 0x20: /* SSPRI */
1128         s->sspri = value;
1129         break;
1130     case 0x28: /* PSSI */
1131         qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
1132         break;
1133     case 0x30: /* SAC */
1134         s->sac = value;
1135         break;
1136     default:
1137         qemu_log_mask(LOG_GUEST_ERROR,
1138                       "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
1139     }
1140     stellaris_adc_update(s);
1141 }
1142
1143 static const MemoryRegionOps stellaris_adc_ops = {
1144     .read = stellaris_adc_read,
1145     .write = stellaris_adc_write,
1146     .endianness = DEVICE_NATIVE_ENDIAN,
1147 };
1148
1149 static const VMStateDescription vmstate_stellaris_adc = {
1150     .name = "stellaris_adc",
1151     .version_id = 1,
1152     .minimum_version_id = 1,
1153     .fields = (VMStateField[]) {
1154         VMSTATE_UINT32(actss, stellaris_adc_state),
1155         VMSTATE_UINT32(ris, stellaris_adc_state),
1156         VMSTATE_UINT32(im, stellaris_adc_state),
1157         VMSTATE_UINT32(emux, stellaris_adc_state),
1158         VMSTATE_UINT32(ostat, stellaris_adc_state),
1159         VMSTATE_UINT32(ustat, stellaris_adc_state),
1160         VMSTATE_UINT32(sspri, stellaris_adc_state),
1161         VMSTATE_UINT32(sac, stellaris_adc_state),
1162         VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1163         VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1164         VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1165         VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1166         VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1167         VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1168         VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1169         VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1170         VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1171         VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1172         VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1173         VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1174         VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1175         VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1176         VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1177         VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1178         VMSTATE_UINT32(noise, stellaris_adc_state),
1179         VMSTATE_END_OF_LIST()
1180     }
1181 };
1182
1183 static void stellaris_adc_init(Object *obj)
1184 {
1185     DeviceState *dev = DEVICE(obj);
1186     stellaris_adc_state *s = STELLARIS_ADC(obj);
1187     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1188     int n;
1189
1190     for (n = 0; n < 4; n++) {
1191         sysbus_init_irq(sbd, &s->irq[n]);
1192     }
1193
1194     memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
1195                           "adc", 0x1000);
1196     sysbus_init_mmio(sbd, &s->iomem);
1197     stellaris_adc_reset(s);
1198     qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
1199 }
1200
1201 static
1202 void do_sys_reset(void *opaque, int n, int level)
1203 {
1204     if (level) {
1205         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1206     }
1207 }
1208
1209 /* Board init.  */
1210 static stellaris_board_info stellaris_boards[] = {
1211   { "LM3S811EVB",
1212     0,
1213     0x0032000e,
1214     0x001f001f, /* dc0 */
1215     0x001132bf,
1216     0x01071013,
1217     0x3f0f01ff,
1218     0x0000001f,
1219     BP_OLED_I2C
1220   },
1221   { "LM3S6965EVB",
1222     0x10010002,
1223     0x1073402e,
1224     0x00ff007f, /* dc0 */
1225     0x001133ff,
1226     0x030f5317,
1227     0x0f0f87ff,
1228     0x5000007f,
1229     BP_OLED_SSI | BP_GAMEPAD
1230   }
1231 };
1232
1233 static void stellaris_init(MachineState *ms, stellaris_board_info *board)
1234 {
1235     static const int uart_irq[] = {5, 6, 33, 34};
1236     static const int timer_irq[] = {19, 21, 23, 35};
1237     static const uint32_t gpio_addr[7] =
1238       { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1239         0x40024000, 0x40025000, 0x40026000};
1240     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1241
1242     /* Memory map of SoC devices, from
1243      * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
1244      * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
1245      *
1246      * 40000000 wdtimer (unimplemented)
1247      * 40002000 i2c (unimplemented)
1248      * 40004000 GPIO
1249      * 40005000 GPIO
1250      * 40006000 GPIO
1251      * 40007000 GPIO
1252      * 40008000 SSI
1253      * 4000c000 UART
1254      * 4000d000 UART
1255      * 4000e000 UART
1256      * 40020000 i2c
1257      * 40021000 i2c (unimplemented)
1258      * 40024000 GPIO
1259      * 40025000 GPIO
1260      * 40026000 GPIO
1261      * 40028000 PWM (unimplemented)
1262      * 4002c000 QEI (unimplemented)
1263      * 4002d000 QEI (unimplemented)
1264      * 40030000 gptimer
1265      * 40031000 gptimer
1266      * 40032000 gptimer
1267      * 40033000 gptimer
1268      * 40038000 ADC
1269      * 4003c000 analogue comparator (unimplemented)
1270      * 40048000 ethernet
1271      * 400fc000 hibernation module (unimplemented)
1272      * 400fd000 flash memory control (unimplemented)
1273      * 400fe000 system control
1274      */
1275
1276     DeviceState *gpio_dev[7], *nvic;
1277     qemu_irq gpio_in[7][8];
1278     qemu_irq gpio_out[7][8];
1279     qemu_irq adc;
1280     int sram_size;
1281     int flash_size;
1282     I2CBus *i2c;
1283     DeviceState *dev;
1284     int i;
1285     int j;
1286
1287     MemoryRegion *sram = g_new(MemoryRegion, 1);
1288     MemoryRegion *flash = g_new(MemoryRegion, 1);
1289     MemoryRegion *system_memory = get_system_memory();
1290
1291     flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1292     sram_size = ((board->dc0 >> 18) + 1) * 1024;
1293
1294     /* Flash programming is done via the SCU, so pretend it is ROM.  */
1295     memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size,
1296                            &error_fatal);
1297     memory_region_set_readonly(flash, true);
1298     memory_region_add_subregion(system_memory, 0, flash);
1299
1300     memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1301                            &error_fatal);
1302     memory_region_add_subregion(system_memory, 0x20000000, sram);
1303
1304     nvic = qdev_create(NULL, TYPE_ARMV7M);
1305     qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
1306     qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
1307     qdev_prop_set_bit(nvic, "enable-bitband", true);
1308     object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()),
1309                                      "memory", &error_abort);
1310     /* This will exit with an error if the user passed us a bad cpu_type */
1311     qdev_init_nofail(nvic);
1312
1313     qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
1314                                 qemu_allocate_irq(&do_sys_reset, NULL, 0));
1315
1316     if (board->dc1 & (1 << 16)) {
1317         dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1318                                     qdev_get_gpio_in(nvic, 14),
1319                                     qdev_get_gpio_in(nvic, 15),
1320                                     qdev_get_gpio_in(nvic, 16),
1321                                     qdev_get_gpio_in(nvic, 17),
1322                                     NULL);
1323         adc = qdev_get_gpio_in(dev, 0);
1324     } else {
1325         adc = NULL;
1326     }
1327     for (i = 0; i < 4; i++) {
1328         if (board->dc2 & (0x10000 << i)) {
1329             dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
1330                                        0x40030000 + i * 0x1000,
1331                                        qdev_get_gpio_in(nvic, timer_irq[i]));
1332             /* TODO: This is incorrect, but we get away with it because
1333                the ADC output is only ever pulsed.  */
1334             qdev_connect_gpio_out(dev, 0, adc);
1335         }
1336     }
1337
1338     stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
1339                        board, nd_table[0].macaddr.a);
1340
1341     for (i = 0; i < 7; i++) {
1342         if (board->dc4 & (1 << i)) {
1343             gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1344                                                qdev_get_gpio_in(nvic,
1345                                                                 gpio_irq[i]));
1346             for (j = 0; j < 8; j++) {
1347                 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1348                 gpio_out[i][j] = NULL;
1349             }
1350         }
1351     }
1352
1353     if (board->dc2 & (1 << 12)) {
1354         dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
1355                                    qdev_get_gpio_in(nvic, 8));
1356         i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1357         if (board->peripherals & BP_OLED_I2C) {
1358             i2c_create_slave(i2c, "ssd0303", 0x3d);
1359         }
1360     }
1361
1362     for (i = 0; i < 4; i++) {
1363         if (board->dc2 & (1 << i)) {
1364             pl011_luminary_create(0x4000c000 + i * 0x1000,
1365                                   qdev_get_gpio_in(nvic, uart_irq[i]),
1366                                   serial_hd(i));
1367         }
1368     }
1369     if (board->dc2 & (1 << 4)) {
1370         dev = sysbus_create_simple("pl022", 0x40008000,
1371                                    qdev_get_gpio_in(nvic, 7));
1372         if (board->peripherals & BP_OLED_SSI) {
1373             void *bus;
1374             DeviceState *sddev;
1375             DeviceState *ssddev;
1376
1377             /* Some boards have both an OLED controller and SD card connected to
1378              * the same SSI port, with the SD card chip select connected to a
1379              * GPIO pin.  Technically the OLED chip select is connected to the
1380              * SSI Fss pin.  We do not bother emulating that as both devices
1381              * should never be selected simultaneously, and our OLED controller
1382              * ignores stray 0xff commands that occur when deselecting the SD
1383              * card.
1384              */
1385             bus = qdev_get_child_bus(dev, "ssi");
1386
1387             sddev = ssi_create_slave(bus, "ssi-sd");
1388             ssddev = ssi_create_slave(bus, "ssd0323");
1389             gpio_out[GPIO_D][0] = qemu_irq_split(
1390                     qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
1391                     qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1392             gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1393
1394             /* Make sure the select pin is high.  */
1395             qemu_irq_raise(gpio_out[GPIO_D][0]);
1396         }
1397     }
1398     if (board->dc4 & (1 << 28)) {
1399         DeviceState *enet;
1400
1401         qemu_check_nic_model(&nd_table[0], "stellaris");
1402
1403         enet = qdev_create(NULL, "stellaris_enet");
1404         qdev_set_nic_properties(enet, &nd_table[0]);
1405         qdev_init_nofail(enet);
1406         sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1407         sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1408     }
1409     if (board->peripherals & BP_GAMEPAD) {
1410         qemu_irq gpad_irq[5];
1411         static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1412
1413         gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1414         gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1415         gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1416         gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1417         gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1418
1419         stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1420     }
1421     for (i = 0; i < 7; i++) {
1422         if (board->dc4 & (1 << i)) {
1423             for (j = 0; j < 8; j++) {
1424                 if (gpio_out[i][j]) {
1425                     qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1426                 }
1427             }
1428         }
1429     }
1430
1431     /* Add dummy regions for the devices we don't implement yet,
1432      * so guest accesses don't cause unlogged crashes.
1433      */
1434     create_unimplemented_device("wdtimer", 0x40000000, 0x1000);
1435     create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1436     create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1437     create_unimplemented_device("PWM", 0x40028000, 0x1000);
1438     create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1439     create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1440     create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1441     create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1442     create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1443
1444     armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size);
1445 }
1446
1447 /* FIXME: Figure out how to generate these from stellaris_boards.  */
1448 static void lm3s811evb_init(MachineState *machine)
1449 {
1450     stellaris_init(machine, &stellaris_boards[0]);
1451 }
1452
1453 static void lm3s6965evb_init(MachineState *machine)
1454 {
1455     stellaris_init(machine, &stellaris_boards[1]);
1456 }
1457
1458 static void lm3s811evb_class_init(ObjectClass *oc, void *data)
1459 {
1460     MachineClass *mc = MACHINE_CLASS(oc);
1461
1462     mc->desc = "Stellaris LM3S811EVB";
1463     mc->init = lm3s811evb_init;
1464     mc->ignore_memory_transaction_failures = true;
1465     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1466 }
1467
1468 static const TypeInfo lm3s811evb_type = {
1469     .name = MACHINE_TYPE_NAME("lm3s811evb"),
1470     .parent = TYPE_MACHINE,
1471     .class_init = lm3s811evb_class_init,
1472 };
1473
1474 static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
1475 {
1476     MachineClass *mc = MACHINE_CLASS(oc);
1477
1478     mc->desc = "Stellaris LM3S6965EVB";
1479     mc->init = lm3s6965evb_init;
1480     mc->ignore_memory_transaction_failures = true;
1481     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1482 }
1483
1484 static const TypeInfo lm3s6965evb_type = {
1485     .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1486     .parent = TYPE_MACHINE,
1487     .class_init = lm3s6965evb_class_init,
1488 };
1489
1490 static void stellaris_machine_init(void)
1491 {
1492     type_register_static(&lm3s811evb_type);
1493     type_register_static(&lm3s6965evb_type);
1494 }
1495
1496 type_init(stellaris_machine_init)
1497
1498 static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1499 {
1500     DeviceClass *dc = DEVICE_CLASS(klass);
1501
1502     dc->vmsd = &vmstate_stellaris_i2c;
1503 }
1504
1505 static const TypeInfo stellaris_i2c_info = {
1506     .name          = TYPE_STELLARIS_I2C,
1507     .parent        = TYPE_SYS_BUS_DEVICE,
1508     .instance_size = sizeof(stellaris_i2c_state),
1509     .instance_init = stellaris_i2c_init,
1510     .class_init    = stellaris_i2c_class_init,
1511 };
1512
1513 static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
1514 {
1515     DeviceClass *dc = DEVICE_CLASS(klass);
1516
1517     dc->vmsd = &vmstate_stellaris_gptm;
1518 }
1519
1520 static const TypeInfo stellaris_gptm_info = {
1521     .name          = TYPE_STELLARIS_GPTM,
1522     .parent        = TYPE_SYS_BUS_DEVICE,
1523     .instance_size = sizeof(gptm_state),
1524     .instance_init = stellaris_gptm_init,
1525     .class_init    = stellaris_gptm_class_init,
1526 };
1527
1528 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1529 {
1530     DeviceClass *dc = DEVICE_CLASS(klass);
1531
1532     dc->vmsd = &vmstate_stellaris_adc;
1533 }
1534
1535 static const TypeInfo stellaris_adc_info = {
1536     .name          = TYPE_STELLARIS_ADC,
1537     .parent        = TYPE_SYS_BUS_DEVICE,
1538     .instance_size = sizeof(stellaris_adc_state),
1539     .instance_init = stellaris_adc_init,
1540     .class_init    = stellaris_adc_class_init,
1541 };
1542
1543 static void stellaris_register_types(void)
1544 {
1545     type_register_static(&stellaris_i2c_info);
1546     type_register_static(&stellaris_gptm_info);
1547     type_register_static(&stellaris_adc_info);
1548 }
1549
1550 type_init(stellaris_register_types)