target-arm/cpu64.c

   1 /*
   2  * QEMU AArch64 CPU
   3  *
   4  * Copyright (c) 2013 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "cpu.h"
  24 #include "qemu-common.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "hw/loader.h"
  27 #endif
  28 #include "hw/arm/arm.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/kvm.h"
  31
  32 static inline void set_feature(CPUARMState *env, int feature)
  33 {
  34     env->features |= 1ULL << feature;
  35 }
  36
  37 static inline void unset_feature(CPUARMState *env, int feature)
  38 {
  39     env->features &= ~(1ULL << feature);
  40 }
  41
  42 #ifndef CONFIG_USER_ONLY
  43 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
  44 {
  45     /* Number of processors is in [25:24]; otherwise we RAZ */
  46     return (smp_cpus - 1) << 24;
  47 }
  48 #endif
  49
  50 static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
  51 #ifndef CONFIG_USER_ONLY
  52     { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
  53       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
  54       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  55       .writefn = arm_cp_write_ignore },
  56     { .name = "L2CTLR",
  57       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
  58       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  59       .writefn = arm_cp_write_ignore },
  60 #endif
  61     { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
  62       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
  63       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  64     { .name = "L2ECTLR",
  65       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
  66       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  67     { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
  68       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
  69       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  70     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
  71       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
  72       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  73     { .name = "CPUACTLR",
  74       .cp = 15, .opc1 = 0, .crm = 15,
  75       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  76     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
  77       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
  78       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  79     { .name = "CPUECTLR",
  80       .cp = 15, .opc1 = 1, .crm = 15,
  81       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  82     { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
  83       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
  84       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  85     { .name = "CPUMERRSR",
  86       .cp = 15, .opc1 = 2, .crm = 15,
  87       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  88     { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
  89       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
  90       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  91     { .name = "L2MERRSR",
  92       .cp = 15, .opc1 = 3, .crm = 15,
  93       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  94     REGINFO_SENTINEL
  95 };
  96
  97 static void aarch64_a57_initfn(Object *obj)
  98 {
  99     ARMCPU *cpu = ARM_CPU(obj);
 100
 101     cpu->dtb_compatible = "arm,cortex-a57";
 102     set_feature(&cpu->env, ARM_FEATURE_V8);
 103     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 104     set_feature(&cpu->env, ARM_FEATURE_NEON);
 105     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 106     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 107     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 108     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 109     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 110     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 111     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 112     set_feature(&cpu->env, ARM_FEATURE_CRC);
 113     set_feature(&cpu->env, ARM_FEATURE_EL3);
 114     set_feature(&cpu->env, ARM_FEATURE_PMU);
 115     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
 116     cpu->midr = 0x411fd070;
 117     cpu->revidr = 0x00000000;
 118     cpu->reset_fpsid = 0x41034070;
 119     cpu->mvfr0 = 0x10110222;
 120     cpu->mvfr1 = 0x12111111;
 121     cpu->mvfr2 = 0x00000043;
 122     cpu->ctr = 0x8444c004;
 123     cpu->reset_sctlr = 0x00c50838;
 124     cpu->id_pfr0 = 0x00000131;
 125     cpu->id_pfr1 = 0x00011011;
 126     cpu->id_dfr0 = 0x03010066;
 127     cpu->id_afr0 = 0x00000000;
 128     cpu->id_mmfr0 = 0x10101105;
 129     cpu->id_mmfr1 = 0x40000000;
 130     cpu->id_mmfr2 = 0x01260000;
 131     cpu->id_mmfr3 = 0x02102211;
 132     cpu->id_isar0 = 0x02101110;
 133     cpu->id_isar1 = 0x13112111;
 134     cpu->id_isar2 = 0x21232042;
 135     cpu->id_isar3 = 0x01112131;
 136     cpu->id_isar4 = 0x00011142;
 137     cpu->id_isar5 = 0x00011121;
 138     cpu->id_aa64pfr0 = 0x00002222;
 139     cpu->id_aa64dfr0 = 0x10305106;
 140     cpu->pmceid0 = 0x00000000;
 141     cpu->pmceid1 = 0x00000000;
 142     cpu->id_aa64isar0 = 0x00011120;
 143     cpu->id_aa64mmfr0 = 0x00001124;
 144     cpu->dbgdidr = 0x3516d000;
 145     cpu->clidr = 0x0a200023;
 146     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 147     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 148     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 149     cpu->dcz_blocksize = 4; /* 64 bytes */
 150     define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
 151 }
 152
 153 static void aarch64_a53_initfn(Object *obj)
 154 {
 155     ARMCPU *cpu = ARM_CPU(obj);
 156
 157     cpu->dtb_compatible = "arm,cortex-a53";
 158     set_feature(&cpu->env, ARM_FEATURE_V8);
 159     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 160     set_feature(&cpu->env, ARM_FEATURE_NEON);
 161     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 162     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 163     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 164     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 165     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 166     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 167     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 168     set_feature(&cpu->env, ARM_FEATURE_CRC);
 169     set_feature(&cpu->env, ARM_FEATURE_EL3);
 170     set_feature(&cpu->env, ARM_FEATURE_PMU);
 171     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
 172     cpu->midr = 0x410fd034;
 173     cpu->revidr = 0x00000000;
 174     cpu->reset_fpsid = 0x41034070;
 175     cpu->mvfr0 = 0x10110222;
 176     cpu->mvfr1 = 0x12111111;
 177     cpu->mvfr2 = 0x00000043;
 178     cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 179     cpu->reset_sctlr = 0x00c50838;
 180     cpu->id_pfr0 = 0x00000131;
 181     cpu->id_pfr1 = 0x00011011;
 182     cpu->id_dfr0 = 0x03010066;
 183     cpu->id_afr0 = 0x00000000;
 184     cpu->id_mmfr0 = 0x10101105;
 185     cpu->id_mmfr1 = 0x40000000;
 186     cpu->id_mmfr2 = 0x01260000;
 187     cpu->id_mmfr3 = 0x02102211;
 188     cpu->id_isar0 = 0x02101110;
 189     cpu->id_isar1 = 0x13112111;
 190     cpu->id_isar2 = 0x21232042;
 191     cpu->id_isar3 = 0x01112131;
 192     cpu->id_isar4 = 0x00011142;
 193     cpu->id_isar5 = 0x00011121;
 194     cpu->id_aa64pfr0 = 0x00002222;
 195     cpu->id_aa64dfr0 = 0x10305106;
 196     cpu->id_aa64isar0 = 0x00011120;
 197     cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
 198     cpu->dbgdidr = 0x3516d000;
 199     cpu->clidr = 0x0a200023;
 200     cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 201     cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 202     cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
 203     cpu->dcz_blocksize = 4; /* 64 bytes */
 204     define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
 205 }
 206
 207 #ifdef CONFIG_USER_ONLY
 208 static void aarch64_any_initfn(Object *obj)
 209 {
 210     ARMCPU *cpu = ARM_CPU(obj);
 211
 212     set_feature(&cpu->env, ARM_FEATURE_V8);
 213     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 214     set_feature(&cpu->env, ARM_FEATURE_NEON);
 215     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 216     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 217     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 218     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 219     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 220     set_feature(&cpu->env, ARM_FEATURE_CRC);
 221     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
 222     cpu->dcz_blocksize = 7; /*  512 bytes */
 223 }
 224 #endif
 225
 226 typedef struct ARMCPUInfo {
 227     const char *name;
 228     void (*initfn)(Object *obj);
 229     void (*class_init)(ObjectClass *oc, void *data);
 230 } ARMCPUInfo;
 231
 232 static const ARMCPUInfo aarch64_cpus[] = {
 233     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
 234     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
 235 #ifdef CONFIG_USER_ONLY
 236     { .name = "any",         .initfn = aarch64_any_initfn },
 237 #endif
 238     { .name = NULL }
 239 };
 240
 241 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
 242 {
 243     ARMCPU *cpu = ARM_CPU(obj);
 244
 245     return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
 246 }
 247
 248 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
 249 {
 250     ARMCPU *cpu = ARM_CPU(obj);
 251
 252     /* At this time, this property is only allowed if KVM is enabled.  This
 253      * restriction allows us to avoid fixing up functionality that assumes a
 254      * uniform execution state like do_interrupt.
 255      */
 256     if (!kvm_enabled()) {
 257         error_setg(errp, "'aarch64' feature cannot be disabled "
 258                          "unless KVM is enabled");
 259         return;
 260     }
 261
 262     if (value == false) {
 263         unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
 264     } else {
 265         set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 266     }
 267 }
 268
 269 static void aarch64_cpu_initfn(Object *obj)
 270 {
 271     object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
 272                              aarch64_cpu_set_aarch64, NULL);
 273     object_property_set_description(obj, "aarch64",
 274                                     "Set on/off to enable/disable aarch64 "
 275                                     "execution state ",
 276                                     NULL);
 277 }
 278
 279 static void aarch64_cpu_finalizefn(Object *obj)
 280 {
 281 }
 282
 283 static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
 284 {
 285     ARMCPU *cpu = ARM_CPU(cs);
 286     /* It's OK to look at env for the current mode here, because it's
 287      * never possible for an AArch64 TB to chain to an AArch32 TB.
 288      * (Otherwise we would need to use synchronize_from_tb instead.)
 289      */
 290     if (is_a64(&cpu->env)) {
 291         cpu->env.pc = value;
 292     } else {
 293         cpu->env.regs[15] = value;
 294     }
 295 }
 296
 297 static gchar *aarch64_gdb_arch_name(CPUState *cs)
 298 {
 299     return g_strdup("aarch64");
 300 }
 301
 302 static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
 303 {
 304     CPUClass *cc = CPU_CLASS(oc);
 305
 306     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
 307     cc->set_pc = aarch64_cpu_set_pc;
 308     cc->gdb_read_register = aarch64_cpu_gdb_read_register;
 309     cc->gdb_write_register = aarch64_cpu_gdb_write_register;
 310     cc->gdb_num_core_regs = 34;
 311     cc->gdb_core_xml_file = "aarch64-core.xml";
 312     cc->gdb_arch_name = aarch64_gdb_arch_name;
 313 }
 314
 315 static void aarch64_cpu_register(const ARMCPUInfo *info)
 316 {
 317     TypeInfo type_info = {
 318         .parent = TYPE_AARCH64_CPU,
 319         .instance_size = sizeof(ARMCPU),
 320         .instance_init = info->initfn,
 321         .class_size = sizeof(ARMCPUClass),
 322         .class_init = info->class_init,
 323     };
 324
 325     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 326     type_register(&type_info);
 327     g_free((void *)type_info.name);
 328 }
 329
 330 static const TypeInfo aarch64_cpu_type_info = {
 331     .name = TYPE_AARCH64_CPU,
 332     .parent = TYPE_ARM_CPU,
 333     .instance_size = sizeof(ARMCPU),
 334     .instance_init = aarch64_cpu_initfn,
 335     .instance_finalize = aarch64_cpu_finalizefn,
 336     .abstract = true,
 337     .class_size = sizeof(AArch64CPUClass),
 338     .class_init = aarch64_cpu_class_init,
 339 };
 340
 341 static void aarch64_cpu_register_types(void)
 342 {
 343     const ARMCPUInfo *info = aarch64_cpus;
 344
 345     type_register_static(&aarch64_cpu_type_info);
 346
 347     while (info->name) {
 348         aarch64_cpu_register(info);
 349         info++;
 350     }
 351 }
 352
 353 type_init(aarch64_cpu_register_types)