hw/char/stm32f2xx_usart.c

   1 /*
   2  * STM32F2XX USART
   3  *
   4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/char/stm32f2xx_usart.h"
  27
  28 #ifndef STM_USART_ERR_DEBUG
  29 #define STM_USART_ERR_DEBUG 0
  30 #endif
  31
  32 #define DB_PRINT_L(lvl, fmt, args...) do { \
  33     if (STM_USART_ERR_DEBUG >= lvl) { \
  34         qemu_log("%s: " fmt, __func__, ## args); \
  35     } \
  36 } while (0);
  37
  38 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
  39
  40 static int stm32f2xx_usart_can_receive(void *opaque)
  41 {
  42     STM32F2XXUsartState *s = opaque;
  43
  44     if (!(s->usart_sr & USART_SR_RXNE)) {
  45         return 1;
  46     }
  47
  48     return 0;
  49 }
  50
  51 static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
  52 {
  53     STM32F2XXUsartState *s = opaque;
  54
  55     s->usart_dr = *buf;
  56
  57     if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
  58         /* USART not enabled - drop the chars */
  59         DB_PRINT("Dropping the chars\n");
  60         return;
  61     }
  62
  63     s->usart_sr |= USART_SR_RXNE;
  64
  65     if (s->usart_cr1 & USART_CR1_RXNEIE) {
  66         qemu_set_irq(s->irq, 1);
  67     }
  68
  69     DB_PRINT("Receiving: %c\n", s->usart_dr);
  70 }
  71
  72 static void stm32f2xx_usart_reset(DeviceState *dev)
  73 {
  74     STM32F2XXUsartState *s = STM32F2XX_USART(dev);
  75
  76     s->usart_sr = USART_SR_RESET;
  77     s->usart_dr = 0x00000000;
  78     s->usart_brr = 0x00000000;
  79     s->usart_cr1 = 0x00000000;
  80     s->usart_cr2 = 0x00000000;
  81     s->usart_cr3 = 0x00000000;
  82     s->usart_gtpr = 0x00000000;
  83
  84     qemu_set_irq(s->irq, 0);
  85 }
  86
  87 static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
  88                                        unsigned int size)
  89 {
  90     STM32F2XXUsartState *s = opaque;
  91     uint64_t retvalue;
  92
  93     DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
  94
  95     switch (addr) {
  96     case USART_SR:
  97         retvalue = s->usart_sr;
  98         s->usart_sr &= ~USART_SR_TC;
  99         if (s->chr) {
 100             qemu_chr_accept_input(s->chr);
 101         }
 102         return retvalue;
 103     case USART_DR:
 104         DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
 105         s->usart_sr |= USART_SR_TXE;
 106         s->usart_sr &= ~USART_SR_RXNE;
 107         if (s->chr) {
 108             qemu_chr_accept_input(s->chr);
 109         }
 110         qemu_set_irq(s->irq, 0);
 111         return s->usart_dr & 0x3FF;
 112     case USART_BRR:
 113         return s->usart_brr;
 114     case USART_CR1:
 115         return s->usart_cr1;
 116     case USART_CR2:
 117         return s->usart_cr2;
 118     case USART_CR3:
 119         return s->usart_cr3;
 120     case USART_GTPR:
 121         return s->usart_gtpr;
 122     default:
 123         qemu_log_mask(LOG_GUEST_ERROR,
 124                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 125         return 0;
 126     }
 127
 128     return 0;
 129 }
 130
 131 static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
 132                                   uint64_t val64, unsigned int size)
 133 {
 134     STM32F2XXUsartState *s = opaque;
 135     uint32_t value = val64;
 136     unsigned char ch;
 137
 138     DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);
 139
 140     switch (addr) {
 141     case USART_SR:
 142         if (value <= 0x3FF) {
 143             s->usart_sr = value;
 144         } else {
 145             s->usart_sr &= value;
 146         }
 147         if (!(s->usart_sr & USART_SR_RXNE)) {
 148             qemu_set_irq(s->irq, 0);
 149         }
 150         return;
 151     case USART_DR:
 152         if (value < 0xF000) {
 153             ch = value;
 154             if (s->chr) {
 155                 qemu_chr_fe_write_all(s->chr, &ch, 1);
 156             }
 157             s->usart_sr |= USART_SR_TC;
 158             s->usart_sr &= ~USART_SR_TXE;
 159         }
 160         return;
 161     case USART_BRR:
 162         s->usart_brr = value;
 163         return;
 164     case USART_CR1:
 165         s->usart_cr1 = value;
 166             if (s->usart_cr1 & USART_CR1_RXNEIE &&
 167                 s->usart_sr & USART_SR_RXNE) {
 168                 qemu_set_irq(s->irq, 1);
 169             }
 170         return;
 171     case USART_CR2:
 172         s->usart_cr2 = value;
 173         return;
 174     case USART_CR3:
 175         s->usart_cr3 = value;
 176         return;
 177     case USART_GTPR:
 178         s->usart_gtpr = value;
 179         return;
 180     default:
 181         qemu_log_mask(LOG_GUEST_ERROR,
 182                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 183     }
 184 }
 185
 186 static const MemoryRegionOps stm32f2xx_usart_ops = {
 187     .read = stm32f2xx_usart_read,
 188     .write = stm32f2xx_usart_write,
 189     .endianness = DEVICE_NATIVE_ENDIAN,
 190 };
 191
 192 static void stm32f2xx_usart_init(Object *obj)
 193 {
 194     STM32F2XXUsartState *s = STM32F2XX_USART(obj);
 195
 196     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 197
 198     memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
 199                           TYPE_STM32F2XX_USART, 0x2000);
 200     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 201
 202     /* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
 203     s->chr = qemu_char_get_next_serial();
 204
 205     if (s->chr) {
 206         qemu_chr_add_handlers(s->chr, stm32f2xx_usart_can_receive,
 207                               stm32f2xx_usart_receive, NULL, s);
 208     }
 209 }
 210
 211 static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
 212 {
 213     DeviceClass *dc = DEVICE_CLASS(klass);
 214
 215     dc->reset = stm32f2xx_usart_reset;
 216     /* Reason: instance_init() method uses qemu_char_get_next_serial() */
 217     dc->cannot_instantiate_with_device_add_yet = true;
 218 }
 219
 220 static const TypeInfo stm32f2xx_usart_info = {
 221     .name          = TYPE_STM32F2XX_USART,
 222     .parent        = TYPE_SYS_BUS_DEVICE,
 223     .instance_size = sizeof(STM32F2XXUsartState),
 224     .instance_init = stm32f2xx_usart_init,
 225     .class_init    = stm32f2xx_usart_class_init,
 226 };
 227
 228 static void stm32f2xx_usart_register_types(void)
 229 {
 230     type_register_static(&stm32f2xx_usart_info);
 231 }
 232
 233 type_init(stm32f2xx_usart_register_types)