2 * QEMU Xilinx OPB Interrupt Controller.
4 * Copyright (c) 2009 Edgar E. Iglesias.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "qemu/module.h"
29 #include "hw/qdev-properties.h"
30 #include "qom/object.h"
44 #define TYPE_XILINX_INTC "xlnx.xps-intc"
45 DECLARE_INSTANCE_CHECKER(struct xlx_pic
, XILINX_INTC
,
50 SysBusDevice parent_obj
;
55 /* Configuration reg chosen at synthesis-time. QEMU populates
56 the bits at board-setup. */
57 uint32_t c_kind_of_intr
;
59 /* Runtime control registers. */
61 /* state of the interrupt input pins */
62 uint32_t irq_pin_state
;
65 static void update_irq(struct xlx_pic
*p
)
69 /* level triggered interrupt */
70 if (p
->regs
[R_MER
] & 2) {
71 p
->regs
[R_ISR
] |= p
->irq_pin_state
& ~p
->c_kind_of_intr
;
74 /* Update the pending register. */
75 p
->regs
[R_IPR
] = p
->regs
[R_ISR
] & p
->regs
[R_IER
];
77 /* Update the vector register. */
78 for (i
= 0; i
< 32; i
++) {
79 if (p
->regs
[R_IPR
] & (1U << i
)) {
87 qemu_set_irq(p
->parent_irq
, (p
->regs
[R_MER
] & 1) && p
->regs
[R_IPR
]);
91 pic_read(void *opaque
, hwaddr addr
, unsigned int size
)
93 struct xlx_pic
*p
= opaque
;
100 if (addr
< ARRAY_SIZE(p
->regs
))
105 D(printf("%s %x=%x\n", __func__
, addr
* 4, r
));
110 pic_write(void *opaque
, hwaddr addr
,
111 uint64_t val64
, unsigned int size
)
113 struct xlx_pic
*p
= opaque
;
114 uint32_t value
= val64
;
117 D(qemu_log("%s addr=%x val=%x\n", __func__
, addr
* 4, value
));
121 p
->regs
[R_ISR
] &= ~value
; /* ACK. */
124 p
->regs
[R_IER
] |= value
; /* Atomic set ie. */
127 p
->regs
[R_IER
] &= ~value
; /* Atomic clear ie. */
130 p
->regs
[R_MER
] = value
& 0x3;
133 if ((p
->regs
[R_MER
] & 2)) {
138 if (addr
< ARRAY_SIZE(p
->regs
))
139 p
->regs
[addr
] = value
;
145 static const MemoryRegionOps pic_ops
= {
148 .endianness
= DEVICE_NATIVE_ENDIAN
,
150 .min_access_size
= 4,
155 static void irq_handler(void *opaque
, int irq
, int level
)
157 struct xlx_pic
*p
= opaque
;
159 /* edge triggered interrupt */
160 if (p
->c_kind_of_intr
& (1 << irq
) && p
->regs
[R_MER
] & 2) {
161 p
->regs
[R_ISR
] |= (level
<< irq
);
164 p
->irq_pin_state
&= ~(1 << irq
);
165 p
->irq_pin_state
|= level
<< irq
;
169 static void xilinx_intc_init(Object
*obj
)
171 struct xlx_pic
*p
= XILINX_INTC(obj
);
173 qdev_init_gpio_in(DEVICE(obj
), irq_handler
, 32);
174 sysbus_init_irq(SYS_BUS_DEVICE(obj
), &p
->parent_irq
);
176 memory_region_init_io(&p
->mmio
, obj
, &pic_ops
, p
, "xlnx.xps-intc",
178 sysbus_init_mmio(SYS_BUS_DEVICE(obj
), &p
->mmio
);
181 static Property xilinx_intc_properties
[] = {
182 DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic
, c_kind_of_intr
, 0),
183 DEFINE_PROP_END_OF_LIST(),
186 static void xilinx_intc_class_init(ObjectClass
*klass
, void *data
)
188 DeviceClass
*dc
= DEVICE_CLASS(klass
);
190 device_class_set_props(dc
, xilinx_intc_properties
);
193 static const TypeInfo xilinx_intc_info
= {
194 .name
= TYPE_XILINX_INTC
,
195 .parent
= TYPE_SYS_BUS_DEVICE
,
196 .instance_size
= sizeof(struct xlx_pic
),
197 .instance_init
= xilinx_intc_init
,
198 .class_init
= xilinx_intc_class_init
,
201 static void xilinx_intc_register_types(void)
203 type_register_static(&xilinx_intc_info
);
206 type_init(xilinx_intc_register_types
)