target-arm/helper-a64.c

   1 /*
   2  *  AArch64 specific helpers
   3  *
   4  *  Copyright (c) 2013 Alexander Graf <agraf@suse.de>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "exec/gdbstub.h"
  22 #include "exec/helper-proto.h"
  23 #include "qemu/host-utils.h"
  24 #include "sysemu/sysemu.h"
  25 #include "qemu/bitops.h"
  26 #include "internals.h"
  27 #include "qemu/crc32c.h"
  28 #include <zlib.h> /* For crc32 */
  29
  30 /* C2.4.7 Multiply and divide */
  31 /* special cases for 0 and LLONG_MIN are mandated by the standard */
  32 uint64_t HELPER(udiv64)(uint64_t num, uint64_t den)
  33 {
  34     if (den == 0) {
  35         return 0;
  36     }
  37     return num / den;
  38 }
  39
  40 int64_t HELPER(sdiv64)(int64_t num, int64_t den)
  41 {
  42     if (den == 0) {
  43         return 0;
  44     }
  45     if (num == LLONG_MIN && den == -1) {
  46         return LLONG_MIN;
  47     }
  48     return num / den;
  49 }
  50
  51 uint64_t HELPER(clz64)(uint64_t x)
  52 {
  53     return clz64(x);
  54 }
  55
  56 uint64_t HELPER(cls64)(uint64_t x)
  57 {
  58     return clrsb64(x);
  59 }
  60
  61 uint32_t HELPER(cls32)(uint32_t x)
  62 {
  63     return clrsb32(x);
  64 }
  65
  66 uint32_t HELPER(clz32)(uint32_t x)
  67 {
  68     return clz32(x);
  69 }
  70
  71 uint64_t HELPER(rbit64)(uint64_t x)
  72 {
  73     return revbit64(x);
  74 }
  75
  76 /* Convert a softfloat float_relation_ (as returned by
  77  * the float*_compare functions) to the correct ARM
  78  * NZCV flag state.
  79  */
  80 static inline uint32_t float_rel_to_flags(int res)
  81 {
  82     uint64_t flags;
  83     switch (res) {
  84     case float_relation_equal:
  85         flags = PSTATE_Z | PSTATE_C;
  86         break;
  87     case float_relation_less:
  88         flags = PSTATE_N;
  89         break;
  90     case float_relation_greater:
  91         flags = PSTATE_C;
  92         break;
  93     case float_relation_unordered:
  94     default:
  95         flags = PSTATE_C | PSTATE_V;
  96         break;
  97     }
  98     return flags;
  99 }
 100
 101 uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
 102 {
 103     return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
 104 }
 105
 106 uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status)
 107 {
 108     return float_rel_to_flags(float32_compare(x, y, fp_status));
 109 }
 110
 111 uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status)
 112 {
 113     return float_rel_to_flags(float64_compare_quiet(x, y, fp_status));
 114 }
 115
 116 uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status)
 117 {
 118     return float_rel_to_flags(float64_compare(x, y, fp_status));
 119 }
 120
 121 float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
 122 {
 123     float_status *fpst = fpstp;
 124
 125     a = float32_squash_input_denormal(a, fpst);
 126     b = float32_squash_input_denormal(b, fpst);
 127
 128     if ((float32_is_zero(a) && float32_is_infinity(b)) ||
 129         (float32_is_infinity(a) && float32_is_zero(b))) {
 130         /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
 131         return make_float32((1U << 30) |
 132                             ((float32_val(a) ^ float32_val(b)) & (1U << 31)));
 133     }
 134     return float32_mul(a, b, fpst);
 135 }
 136
 137 float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
 138 {
 139     float_status *fpst = fpstp;
 140
 141     a = float64_squash_input_denormal(a, fpst);
 142     b = float64_squash_input_denormal(b, fpst);
 143
 144     if ((float64_is_zero(a) && float64_is_infinity(b)) ||
 145         (float64_is_infinity(a) && float64_is_zero(b))) {
 146         /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
 147         return make_float64((1ULL << 62) |
 148                             ((float64_val(a) ^ float64_val(b)) & (1ULL << 63)));
 149     }
 150     return float64_mul(a, b, fpst);
 151 }
 152
 153 uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices,
 154                           uint32_t rn, uint32_t numregs)
 155 {
 156     /* Helper function for SIMD TBL and TBX. We have to do the table
 157      * lookup part for the 64 bits worth of indices we're passed in.
 158      * result is the initial results vector (either zeroes for TBL
 159      * or some guest values for TBX), rn the register number where
 160      * the table starts, and numregs the number of registers in the table.
 161      * We return the results of the lookups.
 162      */
 163     int shift;
 164
 165     for (shift = 0; shift < 64; shift += 8) {
 166         int index = extract64(indices, shift, 8);
 167         if (index < 16 * numregs) {
 168             /* Convert index (a byte offset into the virtual table
 169              * which is a series of 128-bit vectors concatenated)
 170              * into the correct vfp.regs[] element plus a bit offset
 171              * into that element, bearing in mind that the table
 172              * can wrap around from V31 to V0.
 173              */
 174             int elt = (rn * 2 + (index >> 3)) % 64;
 175             int bitidx = (index & 7) * 8;
 176             uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8);
 177
 178             result = deposit64(result, shift, 8, val);
 179         }
 180     }
 181     return result;
 182 }
 183
 184 /* 64bit/double versions of the neon float compare functions */
 185 uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
 186 {
 187     float_status *fpst = fpstp;
 188     return -float64_eq_quiet(a, b, fpst);
 189 }
 190
 191 uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp)
 192 {
 193     float_status *fpst = fpstp;
 194     return -float64_le(b, a, fpst);
 195 }
 196
 197 uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
 198 {
 199     float_status *fpst = fpstp;
 200     return -float64_lt(b, a, fpst);
 201 }
 202
 203 /* Reciprocal step and sqrt step. Note that unlike the A32/T32
 204  * versions, these do a fully fused multiply-add or
 205  * multiply-add-and-halve.
 206  */
 207 #define float32_two make_float32(0x40000000)
 208 #define float32_three make_float32(0x40400000)
 209 #define float32_one_point_five make_float32(0x3fc00000)
 210
 211 #define float64_two make_float64(0x4000000000000000ULL)
 212 #define float64_three make_float64(0x4008000000000000ULL)
 213 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
 214
 215 float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
 216 {
 217     float_status *fpst = fpstp;
 218
 219     a = float32_squash_input_denormal(a, fpst);
 220     b = float32_squash_input_denormal(b, fpst);
 221
 222     a = float32_chs(a);
 223     if ((float32_is_infinity(a) && float32_is_zero(b)) ||
 224         (float32_is_infinity(b) && float32_is_zero(a))) {
 225         return float32_two;
 226     }
 227     return float32_muladd(a, b, float32_two, 0, fpst);
 228 }
 229
 230 float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
 231 {
 232     float_status *fpst = fpstp;
 233
 234     a = float64_squash_input_denormal(a, fpst);
 235     b = float64_squash_input_denormal(b, fpst);
 236
 237     a = float64_chs(a);
 238     if ((float64_is_infinity(a) && float64_is_zero(b)) ||
 239         (float64_is_infinity(b) && float64_is_zero(a))) {
 240         return float64_two;
 241     }
 242     return float64_muladd(a, b, float64_two, 0, fpst);
 243 }
 244
 245 float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
 246 {
 247     float_status *fpst = fpstp;
 248
 249     a = float32_squash_input_denormal(a, fpst);
 250     b = float32_squash_input_denormal(b, fpst);
 251
 252     a = float32_chs(a);
 253     if ((float32_is_infinity(a) && float32_is_zero(b)) ||
 254         (float32_is_infinity(b) && float32_is_zero(a))) {
 255         return float32_one_point_five;
 256     }
 257     return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
 258 }
 259
 260 float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
 261 {
 262     float_status *fpst = fpstp;
 263
 264     a = float64_squash_input_denormal(a, fpst);
 265     b = float64_squash_input_denormal(b, fpst);
 266
 267     a = float64_chs(a);
 268     if ((float64_is_infinity(a) && float64_is_zero(b)) ||
 269         (float64_is_infinity(b) && float64_is_zero(a))) {
 270         return float64_one_point_five;
 271     }
 272     return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
 273 }
 274
 275 /* Pairwise long add: add pairs of adjacent elements into
 276  * double-width elements in the result (eg _s8 is an 8x8->16 op)
 277  */
 278 uint64_t HELPER(neon_addlp_s8)(uint64_t a)
 279 {
 280     uint64_t nsignmask = 0x0080008000800080ULL;
 281     uint64_t wsignmask = 0x8000800080008000ULL;
 282     uint64_t elementmask = 0x00ff00ff00ff00ffULL;
 283     uint64_t tmp1, tmp2;
 284     uint64_t res, signres;
 285
 286     /* Extract odd elements, sign extend each to a 16 bit field */
 287     tmp1 = a & elementmask;
 288     tmp1 ^= nsignmask;
 289     tmp1 |= wsignmask;
 290     tmp1 = (tmp1 - nsignmask) ^ wsignmask;
 291     /* Ditto for the even elements */
 292     tmp2 = (a >> 8) & elementmask;
 293     tmp2 ^= nsignmask;
 294     tmp2 |= wsignmask;
 295     tmp2 = (tmp2 - nsignmask) ^ wsignmask;
 296
 297     /* calculate the result by summing bits 0..14, 16..22, etc,
 298      * and then adjusting the sign bits 15, 23, etc manually.
 299      * This ensures the addition can't overflow the 16 bit field.
 300      */
 301     signres = (tmp1 ^ tmp2) & wsignmask;
 302     res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask);
 303     res ^= signres;
 304
 305     return res;
 306 }
 307
 308 uint64_t HELPER(neon_addlp_u8)(uint64_t a)
 309 {
 310     uint64_t tmp;
 311
 312     tmp = a & 0x00ff00ff00ff00ffULL;
 313     tmp += (a >> 8) & 0x00ff00ff00ff00ffULL;
 314     return tmp;
 315 }
 316
 317 uint64_t HELPER(neon_addlp_s16)(uint64_t a)
 318 {
 319     int32_t reslo, reshi;
 320
 321     reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16);
 322     reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48);
 323
 324     return (uint32_t)reslo | (((uint64_t)reshi) << 32);
 325 }
 326
 327 uint64_t HELPER(neon_addlp_u16)(uint64_t a)
 328 {
 329     uint64_t tmp;
 330
 331     tmp = a & 0x0000ffff0000ffffULL;
 332     tmp += (a >> 16) & 0x0000ffff0000ffffULL;
 333     return tmp;
 334 }
 335
 336 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
 337 float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
 338 {
 339     float_status *fpst = fpstp;
 340     uint32_t val32, sbit;
 341     int32_t exp;
 342
 343     if (float32_is_any_nan(a)) {
 344         float32 nan = a;
 345         if (float32_is_signaling_nan(a)) {
 346             float_raise(float_flag_invalid, fpst);
 347             nan = float32_maybe_silence_nan(a);
 348         }
 349         if (fpst->default_nan_mode) {
 350             nan = float32_default_nan;
 351         }
 352         return nan;
 353     }
 354
 355     val32 = float32_val(a);
 356     sbit = 0x80000000ULL & val32;
 357     exp = extract32(val32, 23, 8);
 358
 359     if (exp == 0) {
 360         return make_float32(sbit | (0xfe << 23));
 361     } else {
 362         return make_float32(sbit | (~exp & 0xff) << 23);
 363     }
 364 }
 365
 366 float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
 367 {
 368     float_status *fpst = fpstp;
 369     uint64_t val64, sbit;
 370     int64_t exp;
 371
 372     if (float64_is_any_nan(a)) {
 373         float64 nan = a;
 374         if (float64_is_signaling_nan(a)) {
 375             float_raise(float_flag_invalid, fpst);
 376             nan = float64_maybe_silence_nan(a);
 377         }
 378         if (fpst->default_nan_mode) {
 379             nan = float64_default_nan;
 380         }
 381         return nan;
 382     }
 383
 384     val64 = float64_val(a);
 385     sbit = 0x8000000000000000ULL & val64;
 386     exp = extract64(float64_val(a), 52, 11);
 387
 388     if (exp == 0) {
 389         return make_float64(sbit | (0x7feULL << 52));
 390     } else {
 391         return make_float64(sbit | (~exp & 0x7ffULL) << 52);
 392     }
 393 }
 394
 395 float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
 396 {
 397     /* Von Neumann rounding is implemented by using round-to-zero
 398      * and then setting the LSB of the result if Inexact was raised.
 399      */
 400     float32 r;
 401     float_status *fpst = &env->vfp.fp_status;
 402     float_status tstat = *fpst;
 403     int exflags;
 404
 405     set_float_rounding_mode(float_round_to_zero, &tstat);
 406     set_float_exception_flags(0, &tstat);
 407     r = float64_to_float32(a, &tstat);
 408     r = float32_maybe_silence_nan(r);
 409     exflags = get_float_exception_flags(&tstat);
 410     if (exflags & float_flag_inexact) {
 411         r = make_float32(float32_val(r) | 1);
 412     }
 413     exflags |= get_float_exception_flags(fpst);
 414     set_float_exception_flags(exflags, fpst);
 415     return r;
 416 }
 417
 418 /* 64-bit versions of the CRC helpers. Note that although the operation
 419  * (and the prototypes of crc32c() and crc32() mean that only the bottom
 420  * 32 bits of the accumulator and result are used, we pass and return
 421  * uint64_t for convenience of the generated code. Unlike the 32-bit
 422  * instruction set versions, val may genuinely have 64 bits of data in it.
 423  * The upper bytes of val (above the number specified by 'bytes') must have
 424  * been zeroed out by the caller.
 425  */
 426 uint64_t HELPER(crc32_64)(uint64_t acc, uint64_t val, uint32_t bytes)
 427 {
 428     uint8_t buf[8];
 429
 430     stq_le_p(buf, val);
 431
 432     /* zlib crc32 converts the accumulator and output to one's complement.  */
 433     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
 434 }
 435
 436 uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
 437 {
 438     uint8_t buf[8];
 439
 440     stq_le_p(buf, val);
 441
 442     /* Linux crc32c converts the output to one's complement.  */
 443     return crc32c(acc, buf, bytes) ^ 0xffffffff;
 444 }
 445
 446 #if !defined(CONFIG_USER_ONLY)
 447
 448 /* Handle a CPU exception.  */
 449 void aarch64_cpu_do_interrupt(CPUState *cs)
 450 {
 451     ARMCPU *cpu = ARM_CPU(cs);
 452     CPUARMState *env = &cpu->env;
 453     unsigned int new_el = env->exception.target_el;
 454     target_ulong addr = env->cp15.vbar_el[new_el];
 455     unsigned int new_mode = aarch64_pstate_mode(new_el, true);
 456
 457     if (arm_current_el(env) < new_el) {
 458         if (env->aarch64) {
 459             addr += 0x400;
 460         } else {
 461             addr += 0x600;
 462         }
 463     } else if (pstate_read(env) & PSTATE_SP) {
 464         addr += 0x200;
 465     }
 466
 467     arm_log_exception(cs->exception_index);
 468     qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
 469                   new_el);
 470     if (qemu_loglevel_mask(CPU_LOG_INT)
 471         && !excp_is_internal(cs->exception_index)) {
 472         qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%" PRIx32 "\n",
 473                       env->exception.syndrome);
 474     }
 475
 476     if (arm_is_psci_call(cpu, cs->exception_index)) {
 477         arm_handle_psci_call(cpu);
 478         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
 479         return;
 480     }
 481
 482     switch (cs->exception_index) {
 483     case EXCP_PREFETCH_ABORT:
 484     case EXCP_DATA_ABORT:
 485         env->cp15.far_el[new_el] = env->exception.vaddress;
 486         qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
 487                       env->cp15.far_el[new_el]);
 488         /* fall through */
 489     case EXCP_BKPT:
 490     case EXCP_UDEF:
 491     case EXCP_SWI:
 492     case EXCP_HVC:
 493     case EXCP_HYP_TRAP:
 494     case EXCP_SMC:
 495         env->cp15.esr_el[new_el] = env->exception.syndrome;
 496         break;
 497     case EXCP_IRQ:
 498     case EXCP_VIRQ:
 499         addr += 0x80;
 500         break;
 501     case EXCP_FIQ:
 502     case EXCP_VFIQ:
 503         addr += 0x100;
 504         break;
 505     case EXCP_SEMIHOST:
 506         qemu_log_mask(CPU_LOG_INT,
 507                       "...handling as semihosting call 0x%" PRIx64 "\n",
 508                       env->xregs[0]);
 509         env->xregs[0] = do_arm_semihosting(env);
 510         return;
 511     default:
 512         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
 513     }
 514
 515     if (is_a64(env)) {
 516         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
 517         aarch64_save_sp(env, arm_current_el(env));
 518         env->elr_el[new_el] = env->pc;
 519     } else {
 520         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
 521         if (!env->thumb) {
 522             env->cp15.esr_el[new_el] |= 1 << 25;
 523         }
 524         env->elr_el[new_el] = env->regs[15];
 525
 526         aarch64_sync_32_to_64(env);
 527
 528         env->condexec_bits = 0;
 529     }
 530     qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
 531                   env->elr_el[new_el]);
 532
 533     pstate_write(env, PSTATE_DAIF | new_mode);
 534     env->aarch64 = 1;
 535     aarch64_restore_sp(env, new_el);
 536
 537     env->pc = addr;
 538     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 539 }
 540 #endif