tcg/aarch64/tcg-target.h

   1 /*
   2  * Initial TCG Implementation for aarch64
   3  *
   4  * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH
   5  * Written by Claudio Fontana
   6  *
   7  * This work is licensed under the terms of the GNU GPL, version 2 or
   8  * (at your option) any later version.
   9  *
  10  * See the COPYING file in the top-level directory for details.
  11  */
  12
  13 #ifndef AARCH64_TCG_TARGET_H
  14 #define AARCH64_TCG_TARGET_H
  15
  16 #include "host/cpuinfo.h"
  17
  18 #define TCG_TARGET_INSN_UNIT_SIZE  4
  19 #define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
  20
  21 typedef enum {
  22     TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
  23     TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,
  24     TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,
  25     TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
  26     TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19,
  27     TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23,
  28     TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27,
  29     TCG_REG_X28, TCG_REG_X29, TCG_REG_X30,
  30
  31     /* X31 is either the stack pointer or zero, depending on context.  */
  32     TCG_REG_SP = 31,
  33     TCG_REG_XZR = 31,
  34
  35     TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
  36     TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
  37     TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
  38     TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
  39     TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
  40     TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
  41     TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
  42     TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
  43
  44     /* Aliases.  */
  45     TCG_REG_FP = TCG_REG_X29,
  46     TCG_REG_LR = TCG_REG_X30,
  47     TCG_AREG0  = TCG_REG_X19,
  48 } TCGReg;
  49
  50 #define TCG_TARGET_NB_REGS 64
  51
  52 /* used for function call generation */
  53 #define TCG_REG_CALL_STACK              TCG_REG_SP
  54 #define TCG_TARGET_STACK_ALIGN          16
  55 #define TCG_TARGET_CALL_STACK_OFFSET    0
  56 #define TCG_TARGET_CALL_ARG_I32         TCG_CALL_ARG_NORMAL
  57 #define TCG_TARGET_CALL_ARG_I64         TCG_CALL_ARG_NORMAL
  58 #ifdef CONFIG_DARWIN
  59 # define TCG_TARGET_CALL_ARG_I128       TCG_CALL_ARG_NORMAL
  60 #else
  61 # define TCG_TARGET_CALL_ARG_I128       TCG_CALL_ARG_EVEN
  62 #endif
  63 #define TCG_TARGET_CALL_RET_I128        TCG_CALL_RET_NORMAL
  64
  65 #define have_lse    (cpuinfo & CPUINFO_LSE)
  66 #define have_lse2   (cpuinfo & CPUINFO_LSE2)
  67
  68 /* optional instructions */
  69 #define TCG_TARGET_HAS_div_i32          1
  70 #define TCG_TARGET_HAS_rem_i32          1
  71 #define TCG_TARGET_HAS_ext8s_i32        1
  72 #define TCG_TARGET_HAS_ext16s_i32       1
  73 #define TCG_TARGET_HAS_ext8u_i32        1
  74 #define TCG_TARGET_HAS_ext16u_i32       1
  75 #define TCG_TARGET_HAS_bswap16_i32      1
  76 #define TCG_TARGET_HAS_bswap32_i32      1
  77 #define TCG_TARGET_HAS_not_i32          1
  78 #define TCG_TARGET_HAS_rot_i32          1
  79 #define TCG_TARGET_HAS_andc_i32         1
  80 #define TCG_TARGET_HAS_orc_i32          1
  81 #define TCG_TARGET_HAS_eqv_i32          1
  82 #define TCG_TARGET_HAS_nand_i32         0
  83 #define TCG_TARGET_HAS_nor_i32          0
  84 #define TCG_TARGET_HAS_clz_i32          1
  85 #define TCG_TARGET_HAS_ctz_i32          1
  86 #define TCG_TARGET_HAS_ctpop_i32        0
  87 #define TCG_TARGET_HAS_deposit_i32      1
  88 #define TCG_TARGET_HAS_extract_i32      1
  89 #define TCG_TARGET_HAS_sextract_i32     1
  90 #define TCG_TARGET_HAS_extract2_i32     1
  91 #define TCG_TARGET_HAS_negsetcond_i32   1
  92 #define TCG_TARGET_HAS_add2_i32         1
  93 #define TCG_TARGET_HAS_sub2_i32         1
  94 #define TCG_TARGET_HAS_mulu2_i32        0
  95 #define TCG_TARGET_HAS_muls2_i32        0
  96 #define TCG_TARGET_HAS_muluh_i32        0
  97 #define TCG_TARGET_HAS_mulsh_i32        0
  98 #define TCG_TARGET_HAS_extr_i64_i32     0
  99 #define TCG_TARGET_HAS_qemu_st8_i32     0
 100
 101 #define TCG_TARGET_HAS_div_i64          1
 102 #define TCG_TARGET_HAS_rem_i64          1
 103 #define TCG_TARGET_HAS_ext8s_i64        1
 104 #define TCG_TARGET_HAS_ext16s_i64       1
 105 #define TCG_TARGET_HAS_ext32s_i64       1
 106 #define TCG_TARGET_HAS_ext8u_i64        1
 107 #define TCG_TARGET_HAS_ext16u_i64       1
 108 #define TCG_TARGET_HAS_ext32u_i64       1
 109 #define TCG_TARGET_HAS_bswap16_i64      1
 110 #define TCG_TARGET_HAS_bswap32_i64      1
 111 #define TCG_TARGET_HAS_bswap64_i64      1
 112 #define TCG_TARGET_HAS_not_i64          1
 113 #define TCG_TARGET_HAS_rot_i64          1
 114 #define TCG_TARGET_HAS_andc_i64         1
 115 #define TCG_TARGET_HAS_orc_i64          1
 116 #define TCG_TARGET_HAS_eqv_i64          1
 117 #define TCG_TARGET_HAS_nand_i64         0
 118 #define TCG_TARGET_HAS_nor_i64          0
 119 #define TCG_TARGET_HAS_clz_i64          1
 120 #define TCG_TARGET_HAS_ctz_i64          1
 121 #define TCG_TARGET_HAS_ctpop_i64        0
 122 #define TCG_TARGET_HAS_deposit_i64      1
 123 #define TCG_TARGET_HAS_extract_i64      1
 124 #define TCG_TARGET_HAS_sextract_i64     1
 125 #define TCG_TARGET_HAS_extract2_i64     1
 126 #define TCG_TARGET_HAS_negsetcond_i64   1
 127 #define TCG_TARGET_HAS_add2_i64         1
 128 #define TCG_TARGET_HAS_sub2_i64         1
 129 #define TCG_TARGET_HAS_mulu2_i64        0
 130 #define TCG_TARGET_HAS_muls2_i64        0
 131 #define TCG_TARGET_HAS_muluh_i64        1
 132 #define TCG_TARGET_HAS_mulsh_i64        1
 133
 134 /*
 135  * Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load,
 136  * which requires writable pages.  We must defer to the helper for user-only,
 137  * but in system mode all ram is writable for the host.
 138  */
 139 #ifdef CONFIG_USER_ONLY
 140 #define TCG_TARGET_HAS_qemu_ldst_i128   have_lse2
 141 #else
 142 #define TCG_TARGET_HAS_qemu_ldst_i128   1
 143 #endif
 144
 145 #define TCG_TARGET_HAS_tst              1
 146
 147 #define TCG_TARGET_HAS_v64              1
 148 #define TCG_TARGET_HAS_v128             1
 149 #define TCG_TARGET_HAS_v256             0
 150
 151 #define TCG_TARGET_HAS_andc_vec         1
 152 #define TCG_TARGET_HAS_orc_vec          1
 153 #define TCG_TARGET_HAS_nand_vec         0
 154 #define TCG_TARGET_HAS_nor_vec          0
 155 #define TCG_TARGET_HAS_eqv_vec          0
 156 #define TCG_TARGET_HAS_not_vec          1
 157 #define TCG_TARGET_HAS_neg_vec          1
 158 #define TCG_TARGET_HAS_abs_vec          1
 159 #define TCG_TARGET_HAS_roti_vec         0
 160 #define TCG_TARGET_HAS_rots_vec         0
 161 #define TCG_TARGET_HAS_rotv_vec         0
 162 #define TCG_TARGET_HAS_shi_vec          1
 163 #define TCG_TARGET_HAS_shs_vec          0
 164 #define TCG_TARGET_HAS_shv_vec          1
 165 #define TCG_TARGET_HAS_mul_vec          1
 166 #define TCG_TARGET_HAS_sat_vec          1
 167 #define TCG_TARGET_HAS_minmax_vec       1
 168 #define TCG_TARGET_HAS_bitsel_vec       1
 169 #define TCG_TARGET_HAS_cmpsel_vec       0
 170
 171 #define TCG_TARGET_DEFAULT_MO (0)
 172 #define TCG_TARGET_NEED_LDST_LABELS
 173 #define TCG_TARGET_NEED_POOL_LABELS
 174
 175 #endif /* AARCH64_TCG_TARGET_H */