3 #include "exec/gdbstub.h"
4 #include "exec/helper-proto.h"
5 #include "qemu/host-utils.h"
6 #include "sysemu/arch_init.h"
7 #include "sysemu/sysemu.h"
8 #include "qemu/bitops.h"
9 #include "qemu/crc32c.h"
10 #include "exec/cpu_ldst.h"
12 #include <zlib.h> /* For crc32 */
14 #ifndef CONFIG_USER_ONLY
15 static inline bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
16 int access_type
, ARMMMUIdx mmu_idx
,
17 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
18 target_ulong
*page_size
, uint32_t *fsr
);
20 /* Definitions for the PMCCNTR and PMCR registers */
26 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
30 /* VFP data registers are always little-endian. */
31 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
33 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
36 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
37 /* Aliases for Q regs. */
40 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
41 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
45 switch (reg
- nregs
) {
46 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
47 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
48 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
53 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
57 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
59 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
62 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
65 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
66 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
70 switch (reg
- nregs
) {
71 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
72 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
73 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
78 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
82 /* 128 bit FP register */
83 stfq_le_p(buf
, env
->vfp
.regs
[reg
* 2]);
84 stfq_le_p(buf
+ 8, env
->vfp
.regs
[reg
* 2 + 1]);
88 stl_p(buf
, vfp_get_fpsr(env
));
92 stl_p(buf
, vfp_get_fpcr(env
));
99 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
103 /* 128 bit FP register */
104 env
->vfp
.regs
[reg
* 2] = ldfq_le_p(buf
);
105 env
->vfp
.regs
[reg
* 2 + 1] = ldfq_le_p(buf
+ 8);
109 vfp_set_fpsr(env
, ldl_p(buf
));
113 vfp_set_fpcr(env
, ldl_p(buf
));
120 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
122 assert(ri
->fieldoffset
);
123 if (cpreg_field_is_64bit(ri
)) {
124 return CPREG_FIELD64(env
, ri
);
126 return CPREG_FIELD32(env
, ri
);
130 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
133 assert(ri
->fieldoffset
);
134 if (cpreg_field_is_64bit(ri
)) {
135 CPREG_FIELD64(env
, ri
) = value
;
137 CPREG_FIELD32(env
, ri
) = value
;
141 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
143 return (char *)env
+ ri
->fieldoffset
;
146 static uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
148 /* Raw read of a coprocessor register (as needed for migration, etc). */
149 if (ri
->type
& ARM_CP_CONST
) {
150 return ri
->resetvalue
;
151 } else if (ri
->raw_readfn
) {
152 return ri
->raw_readfn(env
, ri
);
153 } else if (ri
->readfn
) {
154 return ri
->readfn(env
, ri
);
156 return raw_read(env
, ri
);
160 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
163 /* Raw write of a coprocessor register (as needed for migration, etc).
164 * Note that constant registers are treated as write-ignored; the
165 * caller should check for success by whether a readback gives the
168 if (ri
->type
& ARM_CP_CONST
) {
170 } else if (ri
->raw_writefn
) {
171 ri
->raw_writefn(env
, ri
, v
);
172 } else if (ri
->writefn
) {
173 ri
->writefn(env
, ri
, v
);
175 raw_write(env
, ri
, v
);
179 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
181 /* Return true if the regdef would cause an assertion if you called
182 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
183 * program bug for it not to have the NO_RAW flag).
184 * NB that returning false here doesn't necessarily mean that calling
185 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
186 * read/write access functions which are safe for raw use" from "has
187 * read/write access functions which have side effects but has forgotten
188 * to provide raw access functions".
189 * The tests here line up with the conditions in read/write_raw_cp_reg()
190 * and assertions in raw_read()/raw_write().
192 if ((ri
->type
& ARM_CP_CONST
) ||
194 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
200 bool write_cpustate_to_list(ARMCPU
*cpu
)
202 /* Write the coprocessor state from cpu->env to the (index,value) list. */
206 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
207 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
208 const ARMCPRegInfo
*ri
;
210 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
215 if (ri
->type
& ARM_CP_NO_RAW
) {
218 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
223 bool write_list_to_cpustate(ARMCPU
*cpu
)
228 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
229 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
230 uint64_t v
= cpu
->cpreg_values
[i
];
231 const ARMCPRegInfo
*ri
;
233 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
238 if (ri
->type
& ARM_CP_NO_RAW
) {
241 /* Write value and confirm it reads back as written
242 * (to catch read-only registers and partially read-only
243 * registers where the incoming migration value doesn't match)
245 write_raw_cp_reg(&cpu
->env
, ri
, v
);
246 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
253 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
255 ARMCPU
*cpu
= opaque
;
257 const ARMCPRegInfo
*ri
;
259 regidx
= *(uint32_t *)key
;
260 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
262 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
263 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
264 /* The value array need not be initialized at this point */
265 cpu
->cpreg_array_len
++;
269 static void count_cpreg(gpointer key
, gpointer opaque
)
271 ARMCPU
*cpu
= opaque
;
273 const ARMCPRegInfo
*ri
;
275 regidx
= *(uint32_t *)key
;
276 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
278 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
279 cpu
->cpreg_array_len
++;
283 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
285 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
286 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
297 void init_cpreg_list(ARMCPU
*cpu
)
299 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
300 * Note that we require cpreg_tuples[] to be sorted by key ID.
305 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
306 keys
= g_list_sort(keys
, cpreg_key_compare
);
308 cpu
->cpreg_array_len
= 0;
310 g_list_foreach(keys
, count_cpreg
, cpu
);
312 arraylen
= cpu
->cpreg_array_len
;
313 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
314 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
315 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
316 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
317 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
318 cpu
->cpreg_array_len
= 0;
320 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
322 assert(cpu
->cpreg_array_len
== arraylen
);
327 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
329 ARMCPU
*cpu
= arm_env_get_cpu(env
);
331 raw_write(env
, ri
, value
);
332 tlb_flush(CPU(cpu
), 1); /* Flush TLB as domain not tracked in TLB */
335 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
337 ARMCPU
*cpu
= arm_env_get_cpu(env
);
339 if (raw_read(env
, ri
) != value
) {
340 /* Unlike real hardware the qemu TLB uses virtual addresses,
341 * not modified virtual addresses, so this causes a TLB flush.
343 tlb_flush(CPU(cpu
), 1);
344 raw_write(env
, ri
, value
);
348 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
351 ARMCPU
*cpu
= arm_env_get_cpu(env
);
353 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_MPU
)
354 && !extended_addresses_enabled(env
)) {
355 /* For VMSA (when not using the LPAE long descriptor page table
356 * format) this register includes the ASID, so do a TLB flush.
357 * For PMSA it is purely a process ID and no action is needed.
359 tlb_flush(CPU(cpu
), 1);
361 raw_write(env
, ri
, value
);
364 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
367 /* Invalidate all (TLBIALL) */
368 ARMCPU
*cpu
= arm_env_get_cpu(env
);
370 tlb_flush(CPU(cpu
), 1);
373 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
376 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
377 ARMCPU
*cpu
= arm_env_get_cpu(env
);
379 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
382 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
385 /* Invalidate by ASID (TLBIASID) */
386 ARMCPU
*cpu
= arm_env_get_cpu(env
);
388 tlb_flush(CPU(cpu
), value
== 0);
391 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
394 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
395 ARMCPU
*cpu
= arm_env_get_cpu(env
);
397 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
400 /* IS variants of TLB operations must affect all cores */
401 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
406 CPU_FOREACH(other_cs
) {
407 tlb_flush(other_cs
, 1);
411 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
416 CPU_FOREACH(other_cs
) {
417 tlb_flush(other_cs
, value
== 0);
421 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
426 CPU_FOREACH(other_cs
) {
427 tlb_flush_page(other_cs
, value
& TARGET_PAGE_MASK
);
431 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
436 CPU_FOREACH(other_cs
) {
437 tlb_flush_page(other_cs
, value
& TARGET_PAGE_MASK
);
441 static const ARMCPRegInfo cp_reginfo
[] = {
442 /* Define the secure and non-secure FCSE identifier CP registers
443 * separately because there is no secure bank in V8 (no _EL3). This allows
444 * the secure register to be properly reset and migrated. There is also no
445 * v8 EL1 version of the register so the non-secure instance stands alone.
447 { .name
= "FCSEIDR(NS)",
448 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
449 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
450 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
451 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
452 { .name
= "FCSEIDR(S)",
453 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
454 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
455 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
456 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
457 /* Define the secure and non-secure context identifier CP registers
458 * separately because there is no secure bank in V8 (no _EL3). This allows
459 * the secure register to be properly reset and migrated. In the
460 * non-secure case, the 32-bit register will have reset and migration
461 * disabled during registration as it is handled by the 64-bit instance.
463 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
464 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
465 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
466 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
467 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
468 { .name
= "CONTEXTIDR(S)", .state
= ARM_CP_STATE_AA32
,
469 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
470 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
471 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
472 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
476 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
477 /* NB: Some of these registers exist in v8 but with more precise
478 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
480 /* MMU Domain access control / MPU write buffer control */
482 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
483 .access
= PL1_RW
, .resetvalue
= 0,
484 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
485 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
486 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
487 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
488 * For v6 and v5, these mappings are overly broad.
490 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
491 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
492 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
493 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
494 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
495 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
496 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
497 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
498 /* Cache maintenance ops; some of this space may be overridden later. */
499 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
500 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
501 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
505 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
506 /* Not all pre-v6 cores implemented this WFI, so this is slightly
509 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
510 .access
= PL1_W
, .type
= ARM_CP_WFI
},
514 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
515 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
516 * is UNPREDICTABLE; we choose to NOP as most implementations do).
518 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
519 .access
= PL1_W
, .type
= ARM_CP_WFI
},
520 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
521 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
522 * OMAPCP will override this space.
524 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
525 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
527 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
528 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
530 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
531 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
532 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
534 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
535 * implementing it as RAZ means the "debug architecture version" bits
536 * will read as a reserved value, which should cause Linux to not try
537 * to use the debug hardware.
539 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
540 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
541 /* MMU TLB control. Note that the wildcarding means we cover not just
542 * the unified TLB ops but also the dside/iside/inner-shareable variants.
544 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
545 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
546 .type
= ARM_CP_NO_RAW
},
547 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
548 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
549 .type
= ARM_CP_NO_RAW
},
550 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
551 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
552 .type
= ARM_CP_NO_RAW
},
553 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
554 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
555 .type
= ARM_CP_NO_RAW
},
556 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
557 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
558 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
559 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
563 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
568 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
569 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
570 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
571 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
572 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
574 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
575 /* VFP coprocessor: cp10 & cp11 [23:20] */
576 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
578 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
579 /* ASEDIS [31] bit is RAO/WI */
583 /* VFPv3 and upwards with NEON implement 32 double precision
584 * registers (D0-D31).
586 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
587 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
588 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
594 env
->cp15
.cpacr_el1
= value
;
597 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
599 if (arm_feature(env
, ARM_FEATURE_V8
)) {
600 /* Check if CPACR accesses are to be trapped to EL2 */
601 if (arm_current_el(env
) == 1 &&
602 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
603 return CP_ACCESS_TRAP_EL2
;
604 /* Check if CPACR accesses are to be trapped to EL3 */
605 } else if (arm_current_el(env
) < 3 &&
606 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
607 return CP_ACCESS_TRAP_EL3
;
614 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
616 /* Check if CPTR accesses are set to trap to EL3 */
617 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
618 return CP_ACCESS_TRAP_EL3
;
624 static const ARMCPRegInfo v6_cp_reginfo
[] = {
625 /* prefetch by MVA in v6, NOP in v7 */
626 { .name
= "MVA_prefetch",
627 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
628 .access
= PL1_W
, .type
= ARM_CP_NOP
},
629 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
630 .access
= PL0_W
, .type
= ARM_CP_NOP
},
631 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
632 .access
= PL0_W
, .type
= ARM_CP_NOP
},
633 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
634 .access
= PL0_W
, .type
= ARM_CP_NOP
},
635 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
637 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
638 offsetof(CPUARMState
, cp15
.ifar_ns
) },
640 /* Watchpoint Fault Address Register : should actually only be present
641 * for 1136, 1176, 11MPCore.
643 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
644 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
645 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
646 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
647 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
648 .resetvalue
= 0, .writefn
= cpacr_write
},
652 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
654 /* Performance monitor registers user accessibility is controlled
657 if (arm_current_el(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
658 return CP_ACCESS_TRAP
;
663 #ifndef CONFIG_USER_ONLY
665 static inline bool arm_ccnt_enabled(CPUARMState
*env
)
667 /* This does not support checking PMCCFILTR_EL0 register */
669 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
676 void pmccntr_sync(CPUARMState
*env
)
680 temp_ticks
= muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
),
681 get_ticks_per_sec(), 1000000);
683 if (env
->cp15
.c9_pmcr
& PMCRD
) {
684 /* Increment once every 64 processor clock cycles */
688 if (arm_ccnt_enabled(env
)) {
689 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
693 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
699 /* The counter has been reset */
700 env
->cp15
.c15_ccnt
= 0;
703 /* only the DP, X, D and E bits are writable */
704 env
->cp15
.c9_pmcr
&= ~0x39;
705 env
->cp15
.c9_pmcr
|= (value
& 0x39);
710 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
712 uint64_t total_ticks
;
714 if (!arm_ccnt_enabled(env
)) {
715 /* Counter is disabled, do not change value */
716 return env
->cp15
.c15_ccnt
;
719 total_ticks
= muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
),
720 get_ticks_per_sec(), 1000000);
722 if (env
->cp15
.c9_pmcr
& PMCRD
) {
723 /* Increment once every 64 processor clock cycles */
726 return total_ticks
- env
->cp15
.c15_ccnt
;
729 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
732 uint64_t total_ticks
;
734 if (!arm_ccnt_enabled(env
)) {
735 /* Counter is disabled, set the absolute value */
736 env
->cp15
.c15_ccnt
= value
;
740 total_ticks
= muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
),
741 get_ticks_per_sec(), 1000000);
743 if (env
->cp15
.c9_pmcr
& PMCRD
) {
744 /* Increment once every 64 processor clock cycles */
747 env
->cp15
.c15_ccnt
= total_ticks
- value
;
750 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
753 uint64_t cur_val
= pmccntr_read(env
, NULL
);
755 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
758 #else /* CONFIG_USER_ONLY */
760 void pmccntr_sync(CPUARMState
*env
)
766 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
770 env
->cp15
.pmccfiltr_el0
= value
& 0x7E000000;
774 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
778 env
->cp15
.c9_pmcnten
|= value
;
781 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
785 env
->cp15
.c9_pmcnten
&= ~value
;
788 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
791 env
->cp15
.c9_pmovsr
&= ~value
;
794 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
797 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
800 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
803 env
->cp15
.c9_pmuserenr
= value
& 1;
806 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
809 /* We have no event counters so only the C bit can be changed */
811 env
->cp15
.c9_pminten
|= value
;
814 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
818 env
->cp15
.c9_pminten
&= ~value
;
821 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
824 /* Note that even though the AArch64 view of this register has bits
825 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
826 * architectural requirements for bits which are RES0 only in some
827 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
828 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
830 raw_write(env
, ri
, value
& ~0x1FULL
);
833 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
835 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
836 * For bits that vary between AArch32/64, code needs to check the
837 * current execution mode before directly using the feature bit.
839 uint32_t valid_mask
= SCR_AARCH64_MASK
| SCR_AARCH32_MASK
;
841 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
842 valid_mask
&= ~SCR_HCE
;
844 /* On ARMv7, SMD (or SCD as it is called in v7) is only
845 * supported if EL2 exists. The bit is UNK/SBZP when
846 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
847 * when EL2 is unavailable.
848 * On ARMv8, this bit is always available.
850 if (arm_feature(env
, ARM_FEATURE_V7
) &&
851 !arm_feature(env
, ARM_FEATURE_V8
)) {
852 valid_mask
&= ~SCR_SMD
;
856 /* Clear all-context RES0 bits. */
858 raw_write(env
, ri
, value
);
861 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
863 ARMCPU
*cpu
= arm_env_get_cpu(env
);
865 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
868 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
869 ri
->secure
& ARM_CP_SECSTATE_S
);
871 return cpu
->ccsidr
[index
];
874 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
877 raw_write(env
, ri
, value
& 0xf);
880 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
882 CPUState
*cs
= ENV_GET_CPU(env
);
885 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
888 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
891 /* External aborts are not possible in QEMU so A bit is always clear */
895 static const ARMCPRegInfo v7_cp_reginfo
[] = {
896 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
897 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
898 .access
= PL1_W
, .type
= ARM_CP_NOP
},
899 /* Performance monitors are implementation defined in v7,
900 * but with an ARM recommended set of registers, which we
901 * follow (although we don't actually implement any counters)
903 * Performance registers fall into three categories:
904 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
905 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
906 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
907 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
908 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
910 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
911 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
912 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
913 .writefn
= pmcntenset_write
,
914 .accessfn
= pmreg_access
,
915 .raw_writefn
= raw_write
},
916 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
917 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
918 .access
= PL0_RW
, .accessfn
= pmreg_access
,
919 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
920 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
921 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
923 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
924 .accessfn
= pmreg_access
,
925 .writefn
= pmcntenclr_write
,
926 .type
= ARM_CP_ALIAS
},
927 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
928 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
929 .access
= PL0_RW
, .accessfn
= pmreg_access
,
930 .type
= ARM_CP_ALIAS
,
931 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
932 .writefn
= pmcntenclr_write
},
933 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
934 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
935 .accessfn
= pmreg_access
,
936 .writefn
= pmovsr_write
,
937 .raw_writefn
= raw_write
},
938 /* Unimplemented so WI. */
939 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
940 .access
= PL0_W
, .accessfn
= pmreg_access
, .type
= ARM_CP_NOP
},
941 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
942 * We choose to RAZ/WI.
944 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
945 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
946 .accessfn
= pmreg_access
},
947 #ifndef CONFIG_USER_ONLY
948 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
949 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_IO
,
950 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
951 .accessfn
= pmreg_access
},
952 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
953 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
954 .access
= PL0_RW
, .accessfn
= pmreg_access
,
956 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
, },
958 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
959 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
960 .writefn
= pmccfiltr_write
,
961 .access
= PL0_RW
, .accessfn
= pmreg_access
,
963 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
965 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
967 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
968 .accessfn
= pmreg_access
, .writefn
= pmxevtyper_write
,
969 .raw_writefn
= raw_write
},
970 /* Unimplemented, RAZ/WI. */
971 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
972 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
973 .accessfn
= pmreg_access
},
974 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
975 .access
= PL0_R
| PL1_RW
,
976 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
978 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
979 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
981 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
983 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
984 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
985 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
986 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
987 .writefn
= pmintenclr_write
, },
988 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
989 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
990 .access
= PL1_RW
, .writefn
= vbar_write
,
991 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
992 offsetof(CPUARMState
, cp15
.vbar_ns
) },
994 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
995 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
996 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
997 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
998 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
999 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
1000 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
1001 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
1002 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1003 * just RAZ for all cores:
1005 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
1006 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
1007 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1008 /* Auxiliary fault status registers: these also are IMPDEF, and we
1009 * choose to RAZ/WI for all cores.
1011 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1012 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
1013 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1014 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1015 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
1016 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1017 /* MAIR can just read-as-written because we don't implement caches
1018 * and so don't need to care about memory attributes.
1020 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
1021 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
1022 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
1024 /* For non-long-descriptor page tables these are PRRR and NMRR;
1025 * regardless they still act as reads-as-written for QEMU.
1027 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1028 * allows them to assign the correct fieldoffset based on the endianness
1029 * handled in the field definitions.
1031 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
1032 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
1033 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
1034 offsetof(CPUARMState
, cp15
.mair0_ns
) },
1035 .resetfn
= arm_cp_reset_ignore
},
1036 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
1037 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
1038 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
1039 offsetof(CPUARMState
, cp15
.mair1_ns
) },
1040 .resetfn
= arm_cp_reset_ignore
},
1041 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
1042 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
1043 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
1044 /* 32 bit ITLB invalidates */
1045 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
1046 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1047 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
1048 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1049 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
1050 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1051 /* 32 bit DTLB invalidates */
1052 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
1053 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1054 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
1055 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1056 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
1057 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1058 /* 32 bit TLB invalidates */
1059 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1060 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1061 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1062 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1063 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1064 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1065 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1066 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
1070 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
1071 /* 32 bit TLB invalidates, Inner Shareable */
1072 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1073 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
1074 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1075 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
1076 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1077 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1078 .writefn
= tlbiasid_is_write
},
1079 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1080 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1081 .writefn
= tlbimvaa_is_write
},
1085 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1092 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1094 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
1095 return CP_ACCESS_TRAP
;
1097 return CP_ACCESS_OK
;
1100 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
1101 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
1102 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
1104 .writefn
= teecr_write
},
1105 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
1106 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
1107 .accessfn
= teehbr_access
, .resetvalue
= 0 },
1111 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
1112 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
1113 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
1115 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
1116 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
1118 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
1119 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
1120 .resetfn
= arm_cp_reset_ignore
},
1121 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
1122 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
1123 .access
= PL0_R
|PL1_W
,
1124 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
1126 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
1127 .access
= PL0_R
|PL1_W
,
1128 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
1129 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
1130 .resetfn
= arm_cp_reset_ignore
},
1131 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
1132 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
1134 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
1135 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
1137 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
1138 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
1143 #ifndef CONFIG_USER_ONLY
1145 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1147 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1148 if (arm_current_el(env
) == 0 && !extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
1149 return CP_ACCESS_TRAP
;
1151 return CP_ACCESS_OK
;
1154 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
)
1156 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1157 if (arm_current_el(env
) == 0 &&
1158 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
1159 return CP_ACCESS_TRAP
;
1161 return CP_ACCESS_OK
;
1164 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
)
1166 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1167 * EL0[PV]TEN is zero.
1169 if (arm_current_el(env
) == 0 &&
1170 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
1171 return CP_ACCESS_TRAP
;
1173 return CP_ACCESS_OK
;
1176 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
1177 const ARMCPRegInfo
*ri
)
1179 return gt_counter_access(env
, GTIMER_PHYS
);
1182 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
1183 const ARMCPRegInfo
*ri
)
1185 return gt_counter_access(env
, GTIMER_VIRT
);
1188 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1190 return gt_timer_access(env
, GTIMER_PHYS
);
1193 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1195 return gt_timer_access(env
, GTIMER_VIRT
);
1198 static uint64_t gt_get_countervalue(CPUARMState
*env
)
1200 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
1203 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
1205 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
1208 /* Timer enabled: calculate and set current ISTATUS, irq, and
1209 * reset timer to when ISTATUS next has to change
1211 uint64_t count
= gt_get_countervalue(&cpu
->env
);
1212 /* Note that this must be unsigned 64 bit arithmetic: */
1213 int istatus
= count
>= gt
->cval
;
1216 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
1217 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
1218 (istatus
&& !(gt
->ctl
& 2)));
1220 /* Next transition is when count rolls back over to zero */
1221 nexttick
= UINT64_MAX
;
1223 /* Next transition is when we hit cval */
1224 nexttick
= gt
->cval
;
1226 /* Note that the desired next expiry time might be beyond the
1227 * signed-64-bit range of a QEMUTimer -- in this case we just
1228 * set the timer for as far in the future as possible. When the
1229 * timer expires we will reset the timer for any remaining period.
1231 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
1232 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
1234 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
1236 /* Timer disabled: ISTATUS and timer output always clear */
1238 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
1239 timer_del(cpu
->gt_timer
[timeridx
]);
1243 static void gt_cnt_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1245 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1246 int timeridx
= ri
->opc1
& 1;
1248 timer_del(cpu
->gt_timer
[timeridx
]);
1251 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1253 return gt_get_countervalue(env
);
1256 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1259 int timeridx
= ri
->opc1
& 1;
1261 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
1262 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1265 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1267 int timeridx
= ri
->crm
& 1;
1269 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
1270 gt_get_countervalue(env
));
1273 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1276 int timeridx
= ri
->crm
& 1;
1278 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) +
1279 sextract64(value
, 0, 32);
1280 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1283 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1286 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1287 int timeridx
= ri
->crm
& 1;
1288 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
1290 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
1291 if ((oldval
^ value
) & 1) {
1292 /* Enable toggled */
1293 gt_recalc_timer(cpu
, timeridx
);
1294 } else if ((oldval
^ value
) & 2) {
1295 /* IMASK toggled: don't need to recalculate,
1296 * just set the interrupt line based on ISTATUS
1298 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
1299 (oldval
& 4) && !(value
& 2));
1303 void arm_gt_ptimer_cb(void *opaque
)
1305 ARMCPU
*cpu
= opaque
;
1307 gt_recalc_timer(cpu
, GTIMER_PHYS
);
1310 void arm_gt_vtimer_cb(void *opaque
)
1312 ARMCPU
*cpu
= opaque
;
1314 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1317 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1318 /* Note that CNTFRQ is purely reads-as-written for the benefit
1319 * of software; writing it doesn't actually change the timer frequency.
1320 * Our reset value matches the fixed frequency we implement the timer at.
1322 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
1323 .type
= ARM_CP_ALIAS
,
1324 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1325 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
1327 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
1328 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
1329 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1330 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
1331 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
1333 /* overall control: mostly access permissions */
1334 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
1335 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
1337 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
1340 /* per-timer control */
1341 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1342 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1343 .accessfn
= gt_ptimer_access
,
1344 .fieldoffset
= offsetoflow32(CPUARMState
,
1345 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1346 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1348 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1349 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
1350 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1351 .accessfn
= gt_ptimer_access
,
1352 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1354 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1356 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
1357 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1358 .accessfn
= gt_vtimer_access
,
1359 .fieldoffset
= offsetoflow32(CPUARMState
,
1360 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1361 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1363 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1364 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
1365 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1366 .accessfn
= gt_vtimer_access
,
1367 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1369 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1371 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1372 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1373 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1374 .accessfn
= gt_ptimer_access
,
1375 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1377 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1378 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
1379 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1380 .accessfn
= gt_ptimer_access
,
1381 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1383 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
1384 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1385 .accessfn
= gt_vtimer_access
,
1386 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1388 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1389 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
1390 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1391 .accessfn
= gt_vtimer_access
,
1392 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1394 /* The counter itself */
1395 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
1396 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
1397 .accessfn
= gt_pct_access
,
1398 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1400 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
1401 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
1402 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1403 .accessfn
= gt_pct_access
,
1404 .readfn
= gt_cnt_read
, .resetfn
= gt_cnt_reset
,
1406 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
1407 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
1408 .accessfn
= gt_vct_access
,
1409 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1411 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
1412 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
1413 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1414 .accessfn
= gt_vct_access
,
1415 .readfn
= gt_cnt_read
, .resetfn
= gt_cnt_reset
,
1417 /* Comparison value, indicating when the timer goes off */
1418 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
1419 .access
= PL1_RW
| PL0_R
,
1420 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
1421 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1422 .accessfn
= gt_ptimer_access
,
1423 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1425 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1426 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
1427 .access
= PL1_RW
| PL0_R
,
1429 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1430 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
1431 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1433 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
1434 .access
= PL1_RW
| PL0_R
,
1435 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
1436 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1437 .accessfn
= gt_vtimer_access
,
1438 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1440 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1441 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
1442 .access
= PL1_RW
| PL0_R
,
1444 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1445 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
1446 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1452 /* In user-mode none of the generic timer registers are accessible,
1453 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1454 * so instead just don't register any of them.
1456 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1462 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1464 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1465 raw_write(env
, ri
, value
);
1466 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
1467 raw_write(env
, ri
, value
& 0xfffff6ff);
1469 raw_write(env
, ri
, value
& 0xfffff1ff);
1473 #ifndef CONFIG_USER_ONLY
1474 /* get_phys_addr() isn't present for user-mode-only targets */
1476 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1479 /* Other states are only available with TrustZone; in
1480 * a non-TZ implementation these registers don't exist
1481 * at all, which is an Uncategorized trap. This underdecoding
1482 * is safe because the reginfo is NO_RAW.
1484 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1486 return CP_ACCESS_OK
;
1489 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
1490 int access_type
, ARMMMUIdx mmu_idx
)
1493 target_ulong page_size
;
1498 MemTxAttrs attrs
= {};
1500 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
,
1501 &phys_addr
, &attrs
, &prot
, &page_size
, &fsr
);
1502 if (extended_addresses_enabled(env
)) {
1503 /* fsr is a DFSR/IFSR value for the long descriptor
1504 * translation table format, but with WnR always clear.
1505 * Convert it to a 64-bit PAR.
1507 par64
= (1 << 11); /* LPAE bit always set */
1509 par64
|= phys_addr
& ~0xfffULL
;
1510 if (!attrs
.secure
) {
1511 par64
|= (1 << 9); /* NS */
1513 /* We don't set the ATTR or SH fields in the PAR. */
1516 par64
|= (fsr
& 0x3f) << 1; /* FS */
1517 /* Note that S2WLK and FSTAGE are always zero, because we don't
1518 * implement virtualization and therefore there can't be a stage 2
1523 /* fsr is a DFSR/IFSR value for the short descriptor
1524 * translation table format (with WnR always clear).
1525 * Convert it to a 32-bit PAR.
1528 /* We do not set any attribute bits in the PAR */
1529 if (page_size
== (1 << 24)
1530 && arm_feature(env
, ARM_FEATURE_V7
)) {
1531 par64
= (phys_addr
& 0xff000000) | (1 << 1);
1533 par64
= phys_addr
& 0xfffff000;
1535 if (!attrs
.secure
) {
1536 par64
|= (1 << 9); /* NS */
1539 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
1540 ((fsr
& 0xf) << 1) | 1;
1546 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1548 int access_type
= ri
->opc2
& 1;
1551 int el
= arm_current_el(env
);
1552 bool secure
= arm_is_secure_below_el3(env
);
1554 switch (ri
->opc2
& 6) {
1556 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1559 mmu_idx
= ARMMMUIdx_S1E3
;
1562 mmu_idx
= ARMMMUIdx_S1NSE1
;
1565 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
1568 g_assert_not_reached();
1572 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1575 mmu_idx
= ARMMMUIdx_S1SE0
;
1578 mmu_idx
= ARMMMUIdx_S1NSE0
;
1581 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
1584 g_assert_not_reached();
1588 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1589 mmu_idx
= ARMMMUIdx_S12NSE1
;
1592 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1593 mmu_idx
= ARMMMUIdx_S12NSE0
;
1596 g_assert_not_reached();
1599 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
1601 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
1604 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1607 int access_type
= ri
->opc2
& 1;
1609 int secure
= arm_is_secure_below_el3(env
);
1611 switch (ri
->opc2
& 6) {
1614 case 0: /* AT S1E1R, AT S1E1W */
1615 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
1617 case 4: /* AT S1E2R, AT S1E2W */
1618 mmu_idx
= ARMMMUIdx_S1E2
;
1620 case 6: /* AT S1E3R, AT S1E3W */
1621 mmu_idx
= ARMMMUIdx_S1E3
;
1624 g_assert_not_reached();
1627 case 2: /* AT S1E0R, AT S1E0W */
1628 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
1630 case 4: /* AT S12E1R, AT S12E1W */
1631 mmu_idx
= ARMMMUIdx_S12NSE1
;
1633 case 6: /* AT S12E0R, AT S12E0W */
1634 mmu_idx
= ARMMMUIdx_S12NSE0
;
1637 g_assert_not_reached();
1640 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
1644 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
1645 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
1646 .access
= PL1_RW
, .resetvalue
= 0,
1647 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
1648 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
1649 .writefn
= par_write
},
1650 #ifndef CONFIG_USER_ONLY
1651 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
1652 .access
= PL1_W
, .accessfn
= ats_access
,
1653 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
},
1658 /* Return basic MPU access permission bits. */
1659 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1666 for (i
= 0; i
< 16; i
+= 2) {
1667 ret
|= (val
>> i
) & mask
;
1673 /* Pad basic MPU access permission bits to extended format. */
1674 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1681 for (i
= 0; i
< 16; i
+= 2) {
1682 ret
|= (val
& mask
) << i
;
1688 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1691 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
1694 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1696 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
1699 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1702 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
1705 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1707 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
1710 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1712 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
1718 u32p
+= env
->cp15
.c6_rgnr
;
1722 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1725 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1726 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
1732 u32p
+= env
->cp15
.c6_rgnr
;
1733 tlb_flush(CPU(cpu
), 1); /* Mappings may have changed - purge! */
1737 static void pmsav7_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1739 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1740 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
1746 memset(u32p
, 0, sizeof(*u32p
) * cpu
->pmsav7_dregion
);
1749 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1752 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1753 uint32_t nrgs
= cpu
->pmsav7_dregion
;
1755 if (value
>= nrgs
) {
1756 qemu_log_mask(LOG_GUEST_ERROR
,
1757 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
1758 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
1762 raw_write(env
, ri
, value
);
1765 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
1766 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
1767 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
1768 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
1769 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
, .resetfn
= pmsav7_reset
},
1770 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
1771 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
1772 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
1773 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
, .resetfn
= pmsav7_reset
},
1774 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
1775 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
1776 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
1777 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
, .resetfn
= pmsav7_reset
},
1778 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
1780 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_rgnr
),
1781 .writefn
= pmsav7_rgnr_write
},
1785 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
1786 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
1787 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
1788 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
1789 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
1790 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
1791 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
1792 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
1793 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
1794 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
1796 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
1798 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
1800 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
1802 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
1804 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
1805 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
1807 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
1808 /* Protection region base and size registers */
1809 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
1810 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1811 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
1812 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
1813 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1814 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
1815 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
1816 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1817 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
1818 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
1819 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1820 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
1821 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
1822 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1823 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
1824 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
1825 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1826 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
1827 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
1828 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1829 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
1830 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
1831 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1832 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
1836 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1839 TCR
*tcr
= raw_ptr(env
, ri
);
1840 int maskshift
= extract32(value
, 0, 3);
1842 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
1843 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
1844 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1845 * using Long-desciptor translation table format */
1846 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
1847 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1848 /* In an implementation that includes the Security Extensions
1849 * TTBCR has additional fields PD0 [4] and PD1 [5] for
1850 * Short-descriptor translation table format.
1852 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
1858 /* Update the masks corresponding to the the TCR bank being written
1859 * Note that we always calculate mask and base_mask, but
1860 * they are only used for short-descriptor tables (ie if EAE is 0);
1861 * for long-descriptor tables the TCR fields are used differently
1862 * and the mask and base_mask values are meaningless.
1864 tcr
->raw_tcr
= value
;
1865 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
1866 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
1869 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1872 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1874 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1875 /* With LPAE the TTBCR could result in a change of ASID
1876 * via the TTBCR.A1 bit, so do a TLB flush.
1878 tlb_flush(CPU(cpu
), 1);
1880 vmsa_ttbcr_raw_write(env
, ri
, value
);
1883 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1885 TCR
*tcr
= raw_ptr(env
, ri
);
1887 /* Reset both the TCR as well as the masks corresponding to the bank of
1888 * the TCR being reset.
1892 tcr
->base_mask
= 0xffffc000u
;
1895 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1898 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1899 TCR
*tcr
= raw_ptr(env
, ri
);
1901 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1902 tlb_flush(CPU(cpu
), 1);
1903 tcr
->raw_tcr
= value
;
1906 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1909 /* 64 bit accesses to the TTBRs can change the ASID and so we
1910 * must flush the TLB.
1912 if (cpreg_field_is_64bit(ri
)) {
1913 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1915 tlb_flush(CPU(cpu
), 1);
1917 raw_write(env
, ri
, value
);
1920 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
1921 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
1922 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
1923 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
1924 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
1925 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
1926 .access
= PL1_RW
, .resetvalue
= 0,
1927 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
1928 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
1929 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
1930 .access
= PL1_RW
, .resetvalue
= 0,
1931 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
1932 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
1933 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
1934 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
1935 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
1940 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
1941 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
1942 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
1944 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
1945 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1946 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
1947 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
1948 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
1949 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
1950 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1951 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
1952 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
1953 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
1954 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
1955 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
1956 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
1957 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
1958 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
1959 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
1960 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
1961 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
1962 .raw_writefn
= vmsa_ttbcr_raw_write
,
1963 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
1964 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
1968 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1971 env
->cp15
.c15_ticonfig
= value
& 0xe7;
1972 /* The OS_TYPE bit in this register changes the reported CPUID! */
1973 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
1974 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1977 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1980 env
->cp15
.c15_threadid
= value
& 0xffff;
1983 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1986 /* Wait-for-interrupt (deprecated) */
1987 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
1990 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1993 /* On OMAP there are registers indicating the max/min index of dcache lines
1994 * containing a dirty line; cache flush operations have to reset these.
1996 env
->cp15
.c15_i_max
= 0x000;
1997 env
->cp15
.c15_i_min
= 0xff0;
2000 static const ARMCPRegInfo omap_cp_reginfo
[] = {
2001 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
2002 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
2003 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
2005 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2006 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2007 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2009 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
2010 .writefn
= omap_ticonfig_write
},
2011 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
2013 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
2014 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
2015 .access
= PL1_RW
, .resetvalue
= 0xff0,
2016 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
2017 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
2019 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
2020 .writefn
= omap_threadid_write
},
2021 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
2022 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2023 .type
= ARM_CP_NO_RAW
,
2024 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
2025 /* TODO: Peripheral port remap register:
2026 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2027 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2030 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
2031 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
2032 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
2033 .writefn
= omap_cachemaint_write
},
2034 { .name
= "C9", .cp
= 15, .crn
= 9,
2035 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
2036 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
2040 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2043 env
->cp15
.c15_cpar
= value
& 0x3fff;
2046 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
2047 { .name
= "XSCALE_CPAR",
2048 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2049 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
2050 .writefn
= xscale_cpar_write
, },
2051 { .name
= "XSCALE_AUXCR",
2052 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
2053 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
2055 /* XScale specific cache-lockdown: since we have no cache we NOP these
2056 * and hope the guest does not really rely on cache behaviour.
2058 { .name
= "XSCALE_LOCK_ICACHE_LINE",
2059 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2060 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2061 { .name
= "XSCALE_UNLOCK_ICACHE",
2062 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2063 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2064 { .name
= "XSCALE_DCACHE_LOCK",
2065 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
2066 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2067 { .name
= "XSCALE_UNLOCK_DCACHE",
2068 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
2069 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2073 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
2074 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2075 * implementation of this implementation-defined space.
2076 * Ideally this should eventually disappear in favour of actually
2077 * implementing the correct behaviour for all cores.
2079 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
2080 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2082 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
2087 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
2088 /* Cache status: RAZ because we have no cache so it's always clean */
2089 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
2090 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2095 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
2096 /* We never have a a block transfer operation in progress */
2097 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
2098 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2100 /* The cache ops themselves: these all NOP for QEMU */
2101 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
2102 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2103 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
2104 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2105 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
2106 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2107 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
2108 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2109 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
2110 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2111 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
2112 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2116 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
2117 /* The cache test-and-clean instructions always return (1 << 30)
2118 * to indicate that there are no dirty cache lines.
2120 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
2121 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2122 .resetvalue
= (1 << 30) },
2123 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
2124 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2125 .resetvalue
= (1 << 30) },
2129 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
2130 /* Ignore ReadBuffer accesses */
2131 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
2132 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2133 .access
= PL1_RW
, .resetvalue
= 0,
2134 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
2138 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2140 ARMCPU
*cpu
= ARM_CPU(arm_env_get_cpu(env
));
2141 uint64_t mpidr
= cpu
->mp_affinity
;
2143 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
2144 mpidr
|= (1U << 31);
2145 /* Cores which are uniprocessor (non-coherent)
2146 * but still implement the MP extensions set
2147 * bit 30. (For instance, Cortex-R5).
2149 if (cpu
->mp_is_up
) {
2150 mpidr
|= (1u << 30);
2156 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
2157 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
2158 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
2159 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
2163 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
2165 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
2166 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
2167 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2169 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2170 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
2171 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2173 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
2174 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
2175 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
2176 offsetof(CPUARMState
, cp15
.par_ns
)} },
2177 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
2178 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2179 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2180 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
2181 .writefn
= vmsa_ttbr_write
, },
2182 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
2183 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2184 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2185 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
2186 .writefn
= vmsa_ttbr_write
, },
2190 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2192 return vfp_get_fpcr(env
);
2195 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2198 vfp_set_fpcr(env
, value
);
2201 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2203 return vfp_get_fpsr(env
);
2206 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2209 vfp_set_fpsr(env
, value
);
2212 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2214 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
2215 return CP_ACCESS_TRAP
;
2217 return CP_ACCESS_OK
;
2220 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2223 env
->daif
= value
& PSTATE_DAIF
;
2226 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
2227 const ARMCPRegInfo
*ri
)
2229 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2230 * SCTLR_EL1.UCI is set.
2232 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
2233 return CP_ACCESS_TRAP
;
2235 return CP_ACCESS_OK
;
2238 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2239 * Page D4-1736 (DDI0487A.b)
2242 static void tlbi_aa64_va_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2245 /* Invalidate by VA (AArch64 version) */
2246 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2247 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2249 tlb_flush_page(CPU(cpu
), pageaddr
);
2252 static void tlbi_aa64_vaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2255 /* Invalidate by VA, all ASIDs (AArch64 version) */
2256 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2257 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2259 tlb_flush_page(CPU(cpu
), pageaddr
);
2262 static void tlbi_aa64_asid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2265 /* Invalidate by ASID (AArch64 version) */
2266 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2267 int asid
= extract64(value
, 48, 16);
2268 tlb_flush(CPU(cpu
), asid
== 0);
2271 static void tlbi_aa64_va_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2275 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2277 CPU_FOREACH(other_cs
) {
2278 tlb_flush_page(other_cs
, pageaddr
);
2282 static void tlbi_aa64_vaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2286 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2288 CPU_FOREACH(other_cs
) {
2289 tlb_flush_page(other_cs
, pageaddr
);
2293 static void tlbi_aa64_asid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2297 int asid
= extract64(value
, 48, 16);
2299 CPU_FOREACH(other_cs
) {
2300 tlb_flush(other_cs
, asid
== 0);
2304 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2306 /* We don't implement EL2, so the only control on DC ZVA is the
2307 * bit in the SCTLR which can prohibit access for EL0.
2309 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
2310 return CP_ACCESS_TRAP
;
2312 return CP_ACCESS_OK
;
2315 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2317 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2318 int dzp_bit
= 1 << 4;
2320 /* DZP indicates whether DC ZVA access is allowed */
2321 if (aa64_zva_access(env
, NULL
) == CP_ACCESS_OK
) {
2324 return cpu
->dcz_blocksize
| dzp_bit
;
2327 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2329 if (!(env
->pstate
& PSTATE_SP
)) {
2330 /* Access to SP_EL0 is undefined if it's being used as
2331 * the stack pointer.
2333 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2335 return CP_ACCESS_OK
;
2338 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2340 return env
->pstate
& PSTATE_SP
;
2343 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
2345 update_spsel(env
, val
);
2348 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2351 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2353 if (raw_read(env
, ri
) == value
) {
2354 /* Skip the TLB flush if nothing actually changed; Linux likes
2355 * to do a lot of pointless SCTLR writes.
2360 raw_write(env
, ri
, value
);
2361 /* ??? Lots of these bits are not implemented. */
2362 /* This may enable/disable the MMU, so do a TLB flush. */
2363 tlb_flush(CPU(cpu
), 1);
2366 static const ARMCPRegInfo v8_cp_reginfo
[] = {
2367 /* Minimal set of EL0-visible registers. This will need to be expanded
2368 * significantly for system emulation of AArch64 CPUs.
2370 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
2371 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
2372 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
2373 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
2374 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
2375 .type
= ARM_CP_NO_RAW
,
2376 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
2377 .fieldoffset
= offsetof(CPUARMState
, daif
),
2378 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
2379 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
2380 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
2381 .access
= PL0_RW
, .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
2382 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
2383 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
2384 .access
= PL0_RW
, .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
2385 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
2386 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
2387 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
2388 .readfn
= aa64_dczid_read
},
2389 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
2390 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
2391 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
2392 #ifndef CONFIG_USER_ONLY
2393 /* Avoid overhead of an access check that always passes in user-mode */
2394 .accessfn
= aa64_zva_access
,
2397 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
2398 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
2399 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
2400 /* Cache ops: all NOPs since we don't emulate caches */
2401 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
2402 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
2403 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2404 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
2405 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
2406 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2407 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
2408 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
2409 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2410 .accessfn
= aa64_cacheop_access
},
2411 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
2412 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
2413 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2414 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
2415 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
2416 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2417 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
2418 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
2419 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2420 .accessfn
= aa64_cacheop_access
},
2421 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
2422 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
2423 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2424 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
2425 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
2426 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2427 .accessfn
= aa64_cacheop_access
},
2428 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
2429 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
2430 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2431 .accessfn
= aa64_cacheop_access
},
2432 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
2433 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
2434 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2435 /* TLBI operations */
2436 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
2437 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
2438 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
2439 .writefn
= tlbiall_write
},
2440 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
2441 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
2442 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
2443 .writefn
= tlbiall_write
},
2444 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
2445 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2446 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2447 .writefn
= tlbiall_is_write
},
2448 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
2449 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2450 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2451 .writefn
= tlbi_aa64_va_is_write
},
2452 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
2453 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2454 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2455 .writefn
= tlbi_aa64_asid_is_write
},
2456 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
2457 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2458 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2459 .writefn
= tlbi_aa64_vaa_is_write
},
2460 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
2461 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
2462 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2463 .writefn
= tlbi_aa64_va_is_write
},
2464 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
2465 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
2466 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2467 .writefn
= tlbi_aa64_vaa_is_write
},
2468 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
2469 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2470 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2471 .writefn
= tlbiall_write
},
2472 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
2473 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2474 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2475 .writefn
= tlbi_aa64_va_write
},
2476 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
2477 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2478 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2479 .writefn
= tlbi_aa64_asid_write
},
2480 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
2481 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2482 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2483 .writefn
= tlbi_aa64_vaa_write
},
2484 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
2485 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
2486 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2487 .writefn
= tlbi_aa64_va_write
},
2488 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
2489 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
2490 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2491 .writefn
= tlbi_aa64_vaa_write
},
2492 #ifndef CONFIG_USER_ONLY
2493 /* 64 bit address translation operations */
2494 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
2495 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
2496 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
2497 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
2498 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
2499 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
2500 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
2501 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
2502 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
2503 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
2504 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
2505 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
2507 /* TLB invalidate last level of translation table walk */
2508 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
2509 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
2510 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
2511 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2512 .writefn
= tlbimvaa_is_write
},
2513 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
2514 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2515 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
2516 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
2517 /* 32 bit cache operations */
2518 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
2519 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2520 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
2521 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2522 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
2523 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2524 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
2525 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2526 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
2527 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2528 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
2529 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2530 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
2531 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2532 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
2533 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2534 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
2535 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2536 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
2537 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2538 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
2539 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2540 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
2541 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2542 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
2543 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2544 /* MMU Domain access control / MPU write buffer control */
2545 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
2546 .access
= PL1_RW
, .resetvalue
= 0,
2547 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
2548 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
2549 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
2550 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
2551 .type
= ARM_CP_ALIAS
,
2552 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
2554 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
2555 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
2556 .type
= ARM_CP_ALIAS
,
2557 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
2558 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[1]) },
2559 /* We rely on the access checks not allowing the guest to write to the
2560 * state field when SPSel indicates that it's being used as the stack
2563 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
2564 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
2565 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
2566 .type
= ARM_CP_ALIAS
,
2567 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
2568 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
2569 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
2570 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
2571 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
2572 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
2573 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
2574 .type
= ARM_CP_NO_RAW
,
2575 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
2579 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
2580 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
2581 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
2582 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
2584 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
2585 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
2586 .type
= ARM_CP_NO_RAW
,
2587 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
2589 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
2590 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
2591 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
2592 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2593 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
2594 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
2595 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
2597 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
2598 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
2599 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2600 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
2601 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
2602 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2603 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
2604 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
2605 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2606 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
2607 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
2608 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2609 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
2610 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
2611 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2612 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
2613 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
2618 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2620 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2621 uint64_t valid_mask
= HCR_MASK
;
2623 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2624 valid_mask
&= ~HCR_HCD
;
2626 valid_mask
&= ~HCR_TSC
;
2629 /* Clear RES0 bits. */
2630 value
&= valid_mask
;
2632 /* These bits change the MMU setup:
2633 * HCR_VM enables stage 2 translation
2634 * HCR_PTW forbids certain page-table setups
2635 * HCR_DC Disables stage1 and enables stage2 translation
2637 if ((raw_read(env
, ri
) ^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
2638 tlb_flush(CPU(cpu
), 1);
2640 raw_write(env
, ri
, value
);
2643 static const ARMCPRegInfo el2_cp_reginfo
[] = {
2644 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
2645 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
2646 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
2647 .writefn
= hcr_write
},
2648 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
2649 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
2650 .access
= PL2_RW
, .resetvalue
= 0,
2651 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
2652 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
2653 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
2654 .type
= ARM_CP_ALIAS
,
2655 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
2657 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
2658 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_AA64
,
2659 .type
= ARM_CP_ALIAS
,
2660 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
2661 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
2662 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
2663 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
2664 .access
= PL2_RW
, .resetvalue
= 0,
2665 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
2666 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_AA64
,
2667 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
2668 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
2669 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
2670 .type
= ARM_CP_ALIAS
,
2671 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
2672 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[6]) },
2673 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
2674 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
2675 .access
= PL2_RW
, .writefn
= vbar_write
,
2676 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
2678 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
2679 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
2680 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
2681 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
2682 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
2683 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
2684 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
2685 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]) },
2686 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
2687 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
2688 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
2690 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
2691 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
2692 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
2693 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
2694 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
2695 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
2696 .access
= PL2_RW
, .writefn
= vmsa_tcr_el1_write
,
2697 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
2698 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
2699 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
2700 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
2701 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
2702 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
2703 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
2704 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
2705 .access
= PL2_RW
, .resetvalue
= 0,
2706 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
2707 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
2708 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
2709 .access
= PL2_RW
, .resetvalue
= 0,
2710 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
2711 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
2712 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2713 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
2714 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
2715 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
2716 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
2717 .writefn
= tlbiall_write
},
2718 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
2719 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
2720 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
2721 .writefn
= tlbi_aa64_vaa_write
},
2722 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
2723 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
2724 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
2725 .writefn
= tlbi_aa64_vaa_write
},
2729 static const ARMCPRegInfo el3_cp_reginfo
[] = {
2730 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
2731 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
2732 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
2733 .resetvalue
= 0, .writefn
= scr_write
},
2734 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
2735 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
2736 .access
= PL3_RW
, .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
2737 .writefn
= scr_write
},
2738 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
2739 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
2740 .access
= PL3_RW
, .resetvalue
= 0,
2741 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
2743 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
2744 .access
= PL3_RW
, .resetvalue
= 0,
2745 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
2746 /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
2747 { .name
= "NSACR", .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
2748 .access
= PL3_W
| PL1_R
, .resetvalue
= 0,
2749 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
) },
2750 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
2751 .access
= PL3_RW
, .writefn
= vbar_write
, .resetvalue
= 0,
2752 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
2753 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
2754 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
2755 .access
= PL3_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
2756 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]) },
2757 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
2758 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
2759 .access
= PL3_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2760 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
2761 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
2762 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
2763 .access
= PL3_RW
, .writefn
= vmsa_tcr_el1_write
,
2764 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
2765 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
2766 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
2767 .type
= ARM_CP_ALIAS
,
2768 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
2770 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
2771 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
2772 .type
= ARM_CP_ALIAS
,
2773 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
2774 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
2775 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
2776 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
2777 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
2778 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
2779 .type
= ARM_CP_ALIAS
,
2780 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
2781 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[7]) },
2782 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
2783 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
2784 .access
= PL3_RW
, .writefn
= vbar_write
,
2785 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
2787 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
2788 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
2789 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
2790 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
2794 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2796 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2797 * but the AArch32 CTR has its own reginfo struct)
2799 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
2800 return CP_ACCESS_TRAP
;
2802 return CP_ACCESS_OK
;
2805 static const ARMCPRegInfo debug_cp_reginfo
[] = {
2806 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
2807 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
2808 * unlike DBGDRAR it is never accessible from EL0.
2809 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
2812 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
2813 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2814 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
2815 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
2816 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2817 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
2818 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2819 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
2820 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
2821 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
2823 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
2825 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
2826 * We don't implement the configurable EL0 access.
2828 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
2829 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
2830 .type
= ARM_CP_ALIAS
,
2832 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
2833 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2834 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
2835 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
2836 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2837 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
2838 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
2839 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
2840 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2841 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
2842 * implement vector catch debug events yet.
2845 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
2846 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2850 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
2851 /* 64 bit access versions of the (dummy) debug registers */
2852 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
2853 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
2854 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
2855 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
2859 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
2861 CPUARMState
*env
= &cpu
->env
;
2863 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
2864 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
2866 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
2868 if (env
->cpu_watchpoint
[n
]) {
2869 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
2870 env
->cpu_watchpoint
[n
] = NULL
;
2873 if (!extract64(wcr
, 0, 1)) {
2874 /* E bit clear : watchpoint disabled */
2878 switch (extract64(wcr
, 3, 2)) {
2880 /* LSC 00 is reserved and must behave as if the wp is disabled */
2883 flags
|= BP_MEM_READ
;
2886 flags
|= BP_MEM_WRITE
;
2889 flags
|= BP_MEM_ACCESS
;
2893 /* Attempts to use both MASK and BAS fields simultaneously are
2894 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
2895 * thus generating a watchpoint for every byte in the masked region.
2897 mask
= extract64(wcr
, 24, 4);
2898 if (mask
== 1 || mask
== 2) {
2899 /* Reserved values of MASK; we must act as if the mask value was
2900 * some non-reserved value, or as if the watchpoint were disabled.
2901 * We choose the latter.
2905 /* Watchpoint covers an aligned area up to 2GB in size */
2907 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
2908 * whether the watchpoint fires when the unmasked bits match; we opt
2909 * to generate the exceptions.
2913 /* Watchpoint covers bytes defined by the byte address select bits */
2914 int bas
= extract64(wcr
, 5, 8);
2918 /* This must act as if the watchpoint is disabled */
2922 if (extract64(wvr
, 2, 1)) {
2923 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
2924 * ignored, and BAS[3:0] define which bytes to watch.
2928 /* The BAS bits are supposed to be programmed to indicate a contiguous
2929 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
2930 * we fire for each byte in the word/doubleword addressed by the WVR.
2931 * We choose to ignore any non-zero bits after the first range of 1s.
2933 basstart
= ctz32(bas
);
2934 len
= cto32(bas
>> basstart
);
2938 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
2939 &env
->cpu_watchpoint
[n
]);
2942 void hw_watchpoint_update_all(ARMCPU
*cpu
)
2945 CPUARMState
*env
= &cpu
->env
;
2947 /* Completely clear out existing QEMU watchpoints and our array, to
2948 * avoid possible stale entries following migration load.
2950 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
2951 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
2953 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
2954 hw_watchpoint_update(cpu
, i
);
2958 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2961 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2964 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
2965 * register reads and behaves as if values written are sign extended.
2966 * Bits [1:0] are RES0.
2968 value
= sextract64(value
, 0, 49) & ~3ULL;
2970 raw_write(env
, ri
, value
);
2971 hw_watchpoint_update(cpu
, i
);
2974 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2977 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2980 raw_write(env
, ri
, value
);
2981 hw_watchpoint_update(cpu
, i
);
2984 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
2986 CPUARMState
*env
= &cpu
->env
;
2987 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
2988 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
2993 if (env
->cpu_breakpoint
[n
]) {
2994 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
2995 env
->cpu_breakpoint
[n
] = NULL
;
2998 if (!extract64(bcr
, 0, 1)) {
2999 /* E bit clear : watchpoint disabled */
3003 bt
= extract64(bcr
, 20, 4);
3006 case 4: /* unlinked address mismatch (reserved if AArch64) */
3007 case 5: /* linked address mismatch (reserved if AArch64) */
3008 qemu_log_mask(LOG_UNIMP
,
3009 "arm: address mismatch breakpoint types not implemented");
3011 case 0: /* unlinked address match */
3012 case 1: /* linked address match */
3014 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
3015 * we behave as if the register was sign extended. Bits [1:0] are
3016 * RES0. The BAS field is used to allow setting breakpoints on 16
3017 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
3018 * a bp will fire if the addresses covered by the bp and the addresses
3019 * covered by the insn overlap but the insn doesn't start at the
3020 * start of the bp address range. We choose to require the insn and
3021 * the bp to have the same address. The constraints on writing to
3022 * BAS enforced in dbgbcr_write mean we have only four cases:
3023 * 0b0000 => no breakpoint
3024 * 0b0011 => breakpoint on addr
3025 * 0b1100 => breakpoint on addr + 2
3026 * 0b1111 => breakpoint on addr
3027 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
3029 int bas
= extract64(bcr
, 5, 4);
3030 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
3039 case 2: /* unlinked context ID match */
3040 case 8: /* unlinked VMID match (reserved if no EL2) */
3041 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
3042 qemu_log_mask(LOG_UNIMP
,
3043 "arm: unlinked context breakpoint types not implemented");
3045 case 9: /* linked VMID match (reserved if no EL2) */
3046 case 11: /* linked context ID and VMID match (reserved if no EL2) */
3047 case 3: /* linked context ID match */
3049 /* We must generate no events for Linked context matches (unless
3050 * they are linked to by some other bp/wp, which is handled in
3051 * updates for the linking bp/wp). We choose to also generate no events
3052 * for reserved values.
3057 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
3060 void hw_breakpoint_update_all(ARMCPU
*cpu
)
3063 CPUARMState
*env
= &cpu
->env
;
3065 /* Completely clear out existing QEMU breakpoints and our array, to
3066 * avoid possible stale entries following migration load.
3068 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
3069 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
3071 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
3072 hw_breakpoint_update(cpu
, i
);
3076 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3079 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3082 raw_write(env
, ri
, value
);
3083 hw_breakpoint_update(cpu
, i
);
3086 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3089 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3092 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
3095 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
3096 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
3098 raw_write(env
, ri
, value
);
3099 hw_breakpoint_update(cpu
, i
);
3102 static void define_debug_regs(ARMCPU
*cpu
)
3104 /* Define v7 and v8 architectural debug registers.
3105 * These are just dummy implementations for now.
3108 int wrps
, brps
, ctx_cmps
;
3109 ARMCPRegInfo dbgdidr
= {
3110 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
3111 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
3114 /* Note that all these register fields hold "number of Xs minus 1". */
3115 brps
= extract32(cpu
->dbgdidr
, 24, 4);
3116 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
3117 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
3119 assert(ctx_cmps
<= brps
);
3121 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
3122 * of the debug registers such as number of breakpoints;
3123 * check that if they both exist then they agree.
3125 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
3126 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
3127 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
3128 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
3131 define_one_arm_cp_reg(cpu
, &dbgdidr
);
3132 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
3134 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
3135 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
3138 for (i
= 0; i
< brps
+ 1; i
++) {
3139 ARMCPRegInfo dbgregs
[] = {
3140 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
3141 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
3143 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
3144 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
3146 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
3147 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
3149 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
3150 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
3154 define_arm_cp_regs(cpu
, dbgregs
);
3157 for (i
= 0; i
< wrps
+ 1; i
++) {
3158 ARMCPRegInfo dbgregs
[] = {
3159 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
3160 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
3162 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
3163 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
3165 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
3166 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
3168 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
3169 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
3173 define_arm_cp_regs(cpu
, dbgregs
);
3177 void register_cp_regs_for_features(ARMCPU
*cpu
)
3179 /* Register all the coprocessor registers based on feature bits */
3180 CPUARMState
*env
= &cpu
->env
;
3181 if (arm_feature(env
, ARM_FEATURE_M
)) {
3182 /* M profile has no coprocessor registers */
3186 define_arm_cp_regs(cpu
, cp_reginfo
);
3187 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3188 /* Must go early as it is full of wildcards that may be
3189 * overridden by later definitions.
3191 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
3194 if (arm_feature(env
, ARM_FEATURE_V6
)) {
3195 /* The ID registers all have impdef reset values */
3196 ARMCPRegInfo v6_idregs
[] = {
3197 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
3198 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
3199 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3200 .resetvalue
= cpu
->id_pfr0
},
3201 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
3202 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
3203 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3204 .resetvalue
= cpu
->id_pfr1
},
3205 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
3206 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
3207 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3208 .resetvalue
= cpu
->id_dfr0
},
3209 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
3210 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
3211 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3212 .resetvalue
= cpu
->id_afr0
},
3213 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
3214 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
3215 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3216 .resetvalue
= cpu
->id_mmfr0
},
3217 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
3218 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
3219 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3220 .resetvalue
= cpu
->id_mmfr1
},
3221 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
3222 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
3223 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3224 .resetvalue
= cpu
->id_mmfr2
},
3225 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
3226 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
3227 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3228 .resetvalue
= cpu
->id_mmfr3
},
3229 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
3230 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
3231 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3232 .resetvalue
= cpu
->id_isar0
},
3233 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
3234 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
3235 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3236 .resetvalue
= cpu
->id_isar1
},
3237 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
3238 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
3239 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3240 .resetvalue
= cpu
->id_isar2
},
3241 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
3242 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
3243 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3244 .resetvalue
= cpu
->id_isar3
},
3245 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
3246 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
3247 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3248 .resetvalue
= cpu
->id_isar4
},
3249 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
3250 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
3251 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3252 .resetvalue
= cpu
->id_isar5
},
3253 /* 6..7 are as yet unallocated and must RAZ */
3254 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
3255 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
3257 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
3258 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
3262 define_arm_cp_regs(cpu
, v6_idregs
);
3263 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
3265 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
3267 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
3268 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
3270 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
3271 !arm_feature(env
, ARM_FEATURE_MPU
)) {
3272 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
3274 if (arm_feature(env
, ARM_FEATURE_V7
)) {
3275 /* v7 performance monitor control register: same implementor
3276 * field as main ID register, and we implement only the cycle
3279 #ifndef CONFIG_USER_ONLY
3280 ARMCPRegInfo pmcr
= {
3281 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
3283 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
3284 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
3285 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
3286 .raw_writefn
= raw_write
,
3288 ARMCPRegInfo pmcr64
= {
3289 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
3290 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
3291 .access
= PL0_RW
, .accessfn
= pmreg_access
,
3293 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
3294 .resetvalue
= cpu
->midr
& 0xff000000,
3295 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
3297 define_one_arm_cp_reg(cpu
, &pmcr
);
3298 define_one_arm_cp_reg(cpu
, &pmcr64
);
3300 ARMCPRegInfo clidr
= {
3301 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
3302 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
3303 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
3305 define_one_arm_cp_reg(cpu
, &clidr
);
3306 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
3307 define_debug_regs(cpu
);
3309 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
3311 if (arm_feature(env
, ARM_FEATURE_V8
)) {
3312 /* AArch64 ID registers, which all have impdef reset values */
3313 ARMCPRegInfo v8_idregs
[] = {
3314 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
3315 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
3316 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3317 .resetvalue
= cpu
->id_aa64pfr0
},
3318 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
3319 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
3320 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3321 .resetvalue
= cpu
->id_aa64pfr1
},
3322 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
3323 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
3324 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3325 /* We mask out the PMUVer field, because we don't currently
3326 * implement the PMU. Not advertising it prevents the guest
3327 * from trying to use it and getting UNDEFs on registers we
3330 .resetvalue
= cpu
->id_aa64dfr0
& ~0xf00 },
3331 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
3332 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
3333 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3334 .resetvalue
= cpu
->id_aa64dfr1
},
3335 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
3336 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
3337 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3338 .resetvalue
= cpu
->id_aa64afr0
},
3339 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
3340 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
3341 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3342 .resetvalue
= cpu
->id_aa64afr1
},
3343 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
3344 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
3345 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3346 .resetvalue
= cpu
->id_aa64isar0
},
3347 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
3348 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
3349 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3350 .resetvalue
= cpu
->id_aa64isar1
},
3351 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
3352 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
3353 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3354 .resetvalue
= cpu
->id_aa64mmfr0
},
3355 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
3356 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
3357 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3358 .resetvalue
= cpu
->id_aa64mmfr1
},
3359 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
3360 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
3361 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3362 .resetvalue
= cpu
->mvfr0
},
3363 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
3364 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
3365 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3366 .resetvalue
= cpu
->mvfr1
},
3367 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
3368 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
3369 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3370 .resetvalue
= cpu
->mvfr2
},
3373 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
3374 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
3375 !arm_feature(env
, ARM_FEATURE_EL2
)) {
3376 ARMCPRegInfo rvbar
= {
3377 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
3378 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
3379 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
3381 define_one_arm_cp_reg(cpu
, &rvbar
);
3383 define_arm_cp_regs(cpu
, v8_idregs
);
3384 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
3386 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3387 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
3388 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
3389 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
3390 ARMCPRegInfo rvbar
= {
3391 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3392 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
3393 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
3395 define_one_arm_cp_reg(cpu
, &rvbar
);
3398 /* If EL2 is missing but higher ELs are enabled, we need to
3399 * register the no_el2 reginfos.
3401 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3402 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
3405 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3406 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
3407 ARMCPRegInfo rvbar
= {
3408 .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
3409 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
3410 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
3412 define_one_arm_cp_reg(cpu
, &rvbar
);
3414 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
3415 if (arm_feature(env
, ARM_FEATURE_V6
)) {
3416 /* PMSAv6 not implemented */
3417 assert(arm_feature(env
, ARM_FEATURE_V7
));
3418 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
3419 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
3421 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
3424 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
3425 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
3427 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
3428 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
3430 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
3431 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
3433 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
3434 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
3436 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
3437 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
3439 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
3440 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
3442 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
3443 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
3445 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
3446 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
3448 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
3449 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
3451 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
3452 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
3454 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
3455 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
3457 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3458 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
3460 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
3461 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
3462 * be read-only (ie write causes UNDEF exception).
3465 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
3466 /* Pre-v8 MIDR space.
3467 * Note that the MIDR isn't a simple constant register because
3468 * of the TI925 behaviour where writes to another register can
3469 * cause the MIDR value to change.
3471 * Unimplemented registers in the c15 0 0 0 space default to
3472 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
3473 * and friends override accordingly.
3476 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
3477 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
3478 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
3479 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
3480 .type
= ARM_CP_OVERRIDE
},
3481 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
3483 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
3484 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3486 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
3487 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3489 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
3490 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3492 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
3493 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3495 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
3496 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3499 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
3500 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
3501 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
3502 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
},
3503 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
3504 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
3505 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
3506 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
3507 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
3508 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
3509 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
3510 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
3511 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
3512 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
3515 ARMCPRegInfo id_cp_reginfo
[] = {
3516 /* These are common to v8 and pre-v8 */
3518 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
3519 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
3520 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
3521 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
3522 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
3523 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
3524 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
3526 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
3527 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3530 /* TLBTR is specific to VMSA */
3531 ARMCPRegInfo id_tlbtr_reginfo
= {
3533 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
3534 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
3536 /* MPUIR is specific to PMSA V6+ */
3537 ARMCPRegInfo id_mpuir_reginfo
= {
3539 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
3540 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3541 .resetvalue
= cpu
->pmsav7_dregion
<< 8
3543 ARMCPRegInfo crn0_wi_reginfo
= {
3544 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
3545 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
3546 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
3548 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
3549 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
3551 /* Register the blanket "writes ignored" value first to cover the
3552 * whole space. Then update the specific ID registers to allow write
3553 * access, so that they ignore writes rather than causing them to
3556 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
3557 for (r
= id_pre_v8_midr_cp_reginfo
;
3558 r
->type
!= ARM_CP_SENTINEL
; r
++) {
3561 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
3564 id_tlbtr_reginfo
.access
= PL1_RW
;
3565 id_tlbtr_reginfo
.access
= PL1_RW
;
3567 if (arm_feature(env
, ARM_FEATURE_V8
)) {
3568 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
3570 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
3572 define_arm_cp_regs(cpu
, id_cp_reginfo
);
3573 if (!arm_feature(env
, ARM_FEATURE_MPU
)) {
3574 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
3575 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3576 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
3580 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
3581 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
3584 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
3585 ARMCPRegInfo auxcr
= {
3586 .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
3587 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
3588 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3589 .resetvalue
= cpu
->reset_auxcr
3591 define_one_arm_cp_reg(cpu
, &auxcr
);
3594 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
3595 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
3596 /* 32 bit view is [31:18] 0...0 [43:32]. */
3597 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
3598 | extract64(cpu
->reset_cbar
, 32, 12);
3599 ARMCPRegInfo cbar_reginfo
[] = {
3601 .type
= ARM_CP_CONST
,
3602 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
3603 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
3604 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
3605 .type
= ARM_CP_CONST
,
3606 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
3607 .access
= PL1_R
, .resetvalue
= cbar32
},
3610 /* We don't implement a r/w 64 bit CBAR currently */
3611 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
3612 define_arm_cp_regs(cpu
, cbar_reginfo
);
3614 ARMCPRegInfo cbar
= {
3616 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
3617 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
3618 .fieldoffset
= offsetof(CPUARMState
,
3619 cp15
.c15_config_base_address
)
3621 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
3622 cbar
.access
= PL1_R
;
3623 cbar
.fieldoffset
= 0;
3624 cbar
.type
= ARM_CP_CONST
;
3626 define_one_arm_cp_reg(cpu
, &cbar
);
3630 /* Generic registers whose values depend on the implementation */
3632 ARMCPRegInfo sctlr
= {
3633 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
3634 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
3636 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
3637 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
3638 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
3639 .raw_writefn
= raw_write
,
3641 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
3642 /* Normally we would always end the TB on an SCTLR write, but Linux
3643 * arch/arm/mach-pxa/sleep.S expects two instructions following
3644 * an MMU enable to execute from cache. Imitate this behaviour.
3646 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
3648 define_one_arm_cp_reg(cpu
, &sctlr
);
3652 ARMCPU
*cpu_arm_init(const char *cpu_model
)
3654 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU
, cpu_model
));
3657 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
3659 CPUState
*cs
= CPU(cpu
);
3660 CPUARMState
*env
= &cpu
->env
;
3662 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
3663 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
3664 aarch64_fpu_gdb_set_reg
,
3665 34, "aarch64-fpu.xml", 0);
3666 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
3667 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
3668 51, "arm-neon.xml", 0);
3669 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
3670 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
3671 35, "arm-vfp3.xml", 0);
3672 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
3673 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
3674 19, "arm-vfp.xml", 0);
3678 /* Sort alphabetically by type name, except for "any". */
3679 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
3681 ObjectClass
*class_a
= (ObjectClass
*)a
;
3682 ObjectClass
*class_b
= (ObjectClass
*)b
;
3683 const char *name_a
, *name_b
;
3685 name_a
= object_class_get_name(class_a
);
3686 name_b
= object_class_get_name(class_b
);
3687 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
3689 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
3692 return strcmp(name_a
, name_b
);
3696 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
3698 ObjectClass
*oc
= data
;
3699 CPUListState
*s
= user_data
;
3700 const char *typename
;
3703 typename
= object_class_get_name(oc
);
3704 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
3705 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
3710 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
3714 .cpu_fprintf
= cpu_fprintf
,
3718 list
= object_class_get_list(TYPE_ARM_CPU
, false);
3719 list
= g_slist_sort(list
, arm_cpu_list_compare
);
3720 (*cpu_fprintf
)(f
, "Available CPUs:\n");
3721 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
3724 /* The 'host' CPU type is dynamically registered only if KVM is
3725 * enabled, so we have to special-case it here:
3727 (*cpu_fprintf
)(f
, " host (only available in KVM mode)\n");
3731 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
3733 ObjectClass
*oc
= data
;
3734 CpuDefinitionInfoList
**cpu_list
= user_data
;
3735 CpuDefinitionInfoList
*entry
;
3736 CpuDefinitionInfo
*info
;
3737 const char *typename
;
3739 typename
= object_class_get_name(oc
);
3740 info
= g_malloc0(sizeof(*info
));
3741 info
->name
= g_strndup(typename
,
3742 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
3744 entry
= g_malloc0(sizeof(*entry
));
3745 entry
->value
= info
;
3746 entry
->next
= *cpu_list
;
3750 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
3752 CpuDefinitionInfoList
*cpu_list
= NULL
;
3755 list
= object_class_get_list(TYPE_ARM_CPU
, false);
3756 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
3762 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
3763 void *opaque
, int state
, int secstate
,
3764 int crm
, int opc1
, int opc2
)
3766 /* Private utility function for define_one_arm_cp_reg_with_opaque():
3767 * add a single reginfo struct to the hash table.
3769 uint32_t *key
= g_new(uint32_t, 1);
3770 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
3771 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
3772 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
3774 /* Reset the secure state to the specific incoming state. This is
3775 * necessary as the register may have been defined with both states.
3777 r2
->secure
= secstate
;
3779 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
3780 /* Register is banked (using both entries in array).
3781 * Overwriting fieldoffset as the array is only used to define
3782 * banked registers but later only fieldoffset is used.
3784 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
3787 if (state
== ARM_CP_STATE_AA32
) {
3788 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
3789 /* If the register is banked then we don't need to migrate or
3790 * reset the 32-bit instance in certain cases:
3792 * 1) If the register has both 32-bit and 64-bit instances then we
3793 * can count on the 64-bit instance taking care of the
3795 * 2) If ARMv8 is enabled then we can count on a 64-bit version
3796 * taking care of the secure bank. This requires that separate
3797 * 32 and 64-bit definitions are provided.
3799 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
3800 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
3801 r2
->type
|= ARM_CP_ALIAS
;
3803 } else if ((secstate
!= r
->secure
) && !ns
) {
3804 /* The register is not banked so we only want to allow migration of
3805 * the non-secure instance.
3807 r2
->type
|= ARM_CP_ALIAS
;
3810 if (r
->state
== ARM_CP_STATE_BOTH
) {
3811 /* We assume it is a cp15 register if the .cp field is left unset.
3817 #ifdef HOST_WORDS_BIGENDIAN
3818 if (r2
->fieldoffset
) {
3819 r2
->fieldoffset
+= sizeof(uint32_t);
3824 if (state
== ARM_CP_STATE_AA64
) {
3825 /* To allow abbreviation of ARMCPRegInfo
3826 * definitions, we treat cp == 0 as equivalent to
3827 * the value for "standard guest-visible sysreg".
3828 * STATE_BOTH definitions are also always "standard
3829 * sysreg" in their AArch64 view (the .cp value may
3830 * be non-zero for the benefit of the AArch32 view).
3832 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
3833 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
3835 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
3836 r2
->opc0
, opc1
, opc2
);
3838 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
3841 r2
->opaque
= opaque
;
3843 /* reginfo passed to helpers is correct for the actual access,
3844 * and is never ARM_CP_STATE_BOTH:
3847 /* Make sure reginfo passed to helpers for wildcarded regs
3848 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
3853 /* By convention, for wildcarded registers only the first
3854 * entry is used for migration; the others are marked as
3855 * ALIAS so we don't try to transfer the register
3856 * multiple times. Special registers (ie NOP/WFI) are
3857 * never migratable and not even raw-accessible.
3859 if ((r
->type
& ARM_CP_SPECIAL
)) {
3860 r2
->type
|= ARM_CP_NO_RAW
;
3862 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
3863 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
3864 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
3865 r2
->type
|= ARM_CP_ALIAS
;
3868 /* Check that raw accesses are either forbidden or handled. Note that
3869 * we can't assert this earlier because the setup of fieldoffset for
3870 * banked registers has to be done first.
3872 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
3873 assert(!raw_accessors_invalid(r2
));
3876 /* Overriding of an existing definition must be explicitly
3879 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
3880 ARMCPRegInfo
*oldreg
;
3881 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
3882 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
3883 fprintf(stderr
, "Register redefined: cp=%d %d bit "
3884 "crn=%d crm=%d opc1=%d opc2=%d, "
3885 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
3886 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
3887 oldreg
->name
, r2
->name
);
3888 g_assert_not_reached();
3891 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
3895 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
3896 const ARMCPRegInfo
*r
, void *opaque
)
3898 /* Define implementations of coprocessor registers.
3899 * We store these in a hashtable because typically
3900 * there are less than 150 registers in a space which
3901 * is 16*16*16*8*8 = 262144 in size.
3902 * Wildcarding is supported for the crm, opc1 and opc2 fields.
3903 * If a register is defined twice then the second definition is
3904 * used, so this can be used to define some generic registers and
3905 * then override them with implementation specific variations.
3906 * At least one of the original and the second definition should
3907 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
3908 * against accidental use.
3910 * The state field defines whether the register is to be
3911 * visible in the AArch32 or AArch64 execution state. If the
3912 * state is set to ARM_CP_STATE_BOTH then we synthesise a
3913 * reginfo structure for the AArch32 view, which sees the lower
3914 * 32 bits of the 64 bit register.
3916 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
3917 * be wildcarded. AArch64 registers are always considered to be 64
3918 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
3919 * the register, if any.
3921 int crm
, opc1
, opc2
, state
;
3922 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
3923 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
3924 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
3925 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
3926 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
3927 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
3928 /* 64 bit registers have only CRm and Opc1 fields */
3929 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
3930 /* op0 only exists in the AArch64 encodings */
3931 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
3932 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
3933 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
3934 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
3935 * encodes a minimum access level for the register. We roll this
3936 * runtime check into our general permission check code, so check
3937 * here that the reginfo's specified permissions are strict enough
3938 * to encompass the generic architectural permission check.
3940 if (r
->state
!= ARM_CP_STATE_AA32
) {
3943 case 0: case 1: case 2:
3956 /* unallocated encoding, so not possible */
3964 /* min_EL EL1, secure mode only (we don't check the latter) */
3968 /* broken reginfo with out-of-range opc1 */
3972 /* assert our permissions are not too lax (stricter is fine) */
3973 assert((r
->access
& ~mask
) == 0);
3976 /* Check that the register definition has enough info to handle
3977 * reads and writes if they are permitted.
3979 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
3980 if (r
->access
& PL3_R
) {
3981 assert((r
->fieldoffset
||
3982 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
3985 if (r
->access
& PL3_W
) {
3986 assert((r
->fieldoffset
||
3987 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
3991 /* Bad type field probably means missing sentinel at end of reg list */
3992 assert(cptype_valid(r
->type
));
3993 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
3994 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
3995 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
3996 for (state
= ARM_CP_STATE_AA32
;
3997 state
<= ARM_CP_STATE_AA64
; state
++) {
3998 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
4001 if (state
== ARM_CP_STATE_AA32
) {
4002 /* Under AArch32 CP registers can be common
4003 * (same for secure and non-secure world) or banked.
4005 switch (r
->secure
) {
4006 case ARM_CP_SECSTATE_S
:
4007 case ARM_CP_SECSTATE_NS
:
4008 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
4009 r
->secure
, crm
, opc1
, opc2
);
4012 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
4015 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
4021 /* AArch64 registers get mapped to non-secure instance
4023 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
4033 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
4034 const ARMCPRegInfo
*regs
, void *opaque
)
4036 /* Define a whole list of registers */
4037 const ARMCPRegInfo
*r
;
4038 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
4039 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
4043 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
4045 return g_hash_table_lookup(cpregs
, &encoded_cp
);
4048 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4051 /* Helper coprocessor write function for write-ignore registers */
4054 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4056 /* Helper coprocessor write function for read-as-zero registers */
4060 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
4062 /* Helper coprocessor reset function for do-nothing-on-reset registers */
4065 static int bad_mode_switch(CPUARMState
*env
, int mode
)
4067 /* Return true if it is not valid for us to switch to
4068 * this CPU mode (ie all the UNPREDICTABLE cases in
4069 * the ARM ARM CPSRWriteByInstr pseudocode).
4072 case ARM_CPU_MODE_USR
:
4073 case ARM_CPU_MODE_SYS
:
4074 case ARM_CPU_MODE_SVC
:
4075 case ARM_CPU_MODE_ABT
:
4076 case ARM_CPU_MODE_UND
:
4077 case ARM_CPU_MODE_IRQ
:
4078 case ARM_CPU_MODE_FIQ
:
4080 case ARM_CPU_MODE_MON
:
4081 return !arm_is_secure(env
);
4087 uint32_t cpsr_read(CPUARMState
*env
)
4090 ZF
= (env
->ZF
== 0);
4091 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
4092 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
4093 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
4094 | ((env
->condexec_bits
& 0xfc) << 8)
4095 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
4098 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
4100 uint32_t changed_daif
;
4102 if (mask
& CPSR_NZCV
) {
4103 env
->ZF
= (~val
) & CPSR_Z
;
4105 env
->CF
= (val
>> 29) & 1;
4106 env
->VF
= (val
<< 3) & 0x80000000;
4109 env
->QF
= ((val
& CPSR_Q
) != 0);
4111 env
->thumb
= ((val
& CPSR_T
) != 0);
4112 if (mask
& CPSR_IT_0_1
) {
4113 env
->condexec_bits
&= ~3;
4114 env
->condexec_bits
|= (val
>> 25) & 3;
4116 if (mask
& CPSR_IT_2_7
) {
4117 env
->condexec_bits
&= 3;
4118 env
->condexec_bits
|= (val
>> 8) & 0xfc;
4120 if (mask
& CPSR_GE
) {
4121 env
->GE
= (val
>> 16) & 0xf;
4124 /* In a V7 implementation that includes the security extensions but does
4125 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
4126 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
4127 * bits respectively.
4129 * In a V8 implementation, it is permitted for privileged software to
4130 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
4132 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
4133 arm_feature(env
, ARM_FEATURE_EL3
) &&
4134 !arm_feature(env
, ARM_FEATURE_EL2
) &&
4135 !arm_is_secure(env
)) {
4137 changed_daif
= (env
->daif
^ val
) & mask
;
4139 if (changed_daif
& CPSR_A
) {
4140 /* Check to see if we are allowed to change the masking of async
4141 * abort exceptions from a non-secure state.
4143 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
4144 qemu_log_mask(LOG_GUEST_ERROR
,
4145 "Ignoring attempt to switch CPSR_A flag from "
4146 "non-secure world with SCR.AW bit clear\n");
4151 if (changed_daif
& CPSR_F
) {
4152 /* Check to see if we are allowed to change the masking of FIQ
4153 * exceptions from a non-secure state.
4155 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
4156 qemu_log_mask(LOG_GUEST_ERROR
,
4157 "Ignoring attempt to switch CPSR_F flag from "
4158 "non-secure world with SCR.FW bit clear\n");
4162 /* Check whether non-maskable FIQ (NMFI) support is enabled.
4163 * If this bit is set software is not allowed to mask
4164 * FIQs, but is allowed to set CPSR_F to 0.
4166 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
4168 qemu_log_mask(LOG_GUEST_ERROR
,
4169 "Ignoring attempt to enable CPSR_F flag "
4170 "(non-maskable FIQ [NMFI] support enabled)\n");
4176 env
->daif
&= ~(CPSR_AIF
& mask
);
4177 env
->daif
|= val
& CPSR_AIF
& mask
;
4179 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
4180 if (bad_mode_switch(env
, val
& CPSR_M
)) {
4181 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
4182 * We choose to ignore the attempt and leave the CPSR M field
4187 switch_mode(env
, val
& CPSR_M
);
4190 mask
&= ~CACHED_CPSR_BITS
;
4191 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
4194 /* Sign/zero extend */
4195 uint32_t HELPER(sxtb16
)(uint32_t x
)
4198 res
= (uint16_t)(int8_t)x
;
4199 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
4203 uint32_t HELPER(uxtb16
)(uint32_t x
)
4206 res
= (uint16_t)(uint8_t)x
;
4207 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
4211 uint32_t HELPER(clz
)(uint32_t x
)
4216 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
4220 if (num
== INT_MIN
&& den
== -1)
4225 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
4232 uint32_t HELPER(rbit
)(uint32_t x
)
4234 x
= ((x
& 0xff000000) >> 24)
4235 | ((x
& 0x00ff0000) >> 8)
4236 | ((x
& 0x0000ff00) << 8)
4237 | ((x
& 0x000000ff) << 24);
4238 x
= ((x
& 0xf0f0f0f0) >> 4)
4239 | ((x
& 0x0f0f0f0f) << 4);
4240 x
= ((x
& 0x88888888) >> 3)
4241 | ((x
& 0x44444444) >> 1)
4242 | ((x
& 0x22222222) << 1)
4243 | ((x
& 0x11111111) << 3);
4247 #if defined(CONFIG_USER_ONLY)
4249 /* These should probably raise undefined insn exceptions. */
4250 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
4252 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4254 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
4257 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
4259 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4261 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
4265 void switch_mode(CPUARMState
*env
, int mode
)
4267 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4269 if (mode
!= ARM_CPU_MODE_USR
) {
4270 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
4274 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
4276 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4278 cpu_abort(CPU(cpu
), "banked r13 write\n");
4281 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
4283 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4285 cpu_abort(CPU(cpu
), "banked r13 read\n");
4289 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
4290 uint32_t cur_el
, bool secure
)
4295 void aarch64_sync_64_to_32(CPUARMState
*env
)
4297 g_assert_not_reached();
4302 /* Map CPU modes onto saved register banks. */
4303 int bank_number(int mode
)
4306 case ARM_CPU_MODE_USR
:
4307 case ARM_CPU_MODE_SYS
:
4309 case ARM_CPU_MODE_SVC
:
4311 case ARM_CPU_MODE_ABT
:
4313 case ARM_CPU_MODE_UND
:
4315 case ARM_CPU_MODE_IRQ
:
4317 case ARM_CPU_MODE_FIQ
:
4319 case ARM_CPU_MODE_HYP
:
4321 case ARM_CPU_MODE_MON
:
4324 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode
);
4327 void switch_mode(CPUARMState
*env
, int mode
)
4332 old_mode
= env
->uncached_cpsr
& CPSR_M
;
4333 if (mode
== old_mode
)
4336 if (old_mode
== ARM_CPU_MODE_FIQ
) {
4337 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
4338 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
4339 } else if (mode
== ARM_CPU_MODE_FIQ
) {
4340 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
4341 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
4344 i
= bank_number(old_mode
);
4345 env
->banked_r13
[i
] = env
->regs
[13];
4346 env
->banked_r14
[i
] = env
->regs
[14];
4347 env
->banked_spsr
[i
] = env
->spsr
;
4349 i
= bank_number(mode
);
4350 env
->regs
[13] = env
->banked_r13
[i
];
4351 env
->regs
[14] = env
->banked_r14
[i
];
4352 env
->spsr
= env
->banked_spsr
[i
];
4355 /* Physical Interrupt Target EL Lookup Table
4357 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
4359 * The below multi-dimensional table is used for looking up the target
4360 * exception level given numerous condition criteria. Specifically, the
4361 * target EL is based on SCR and HCR routing controls as well as the
4362 * currently executing EL and secure state.
4365 * target_el_table[2][2][2][2][2][4]
4366 * | | | | | +--- Current EL
4367 * | | | | +------ Non-secure(0)/Secure(1)
4368 * | | | +--------- HCR mask override
4369 * | | +------------ SCR exec state control
4370 * | +--------------- SCR mask override
4371 * +------------------ 32-bit(0)/64-bit(1) EL3
4373 * The table values are as such:
4377 * The ARM ARM target EL table includes entries indicating that an "exception
4378 * is not taken". The two cases where this is applicable are:
4379 * 1) An exception is taken from EL3 but the SCR does not have the exception
4381 * 2) An exception is taken from EL2 but the HCR does not have the exception
4383 * In these two cases, the below table contain a target of EL1. This value is
4384 * returned as it is expected that the consumer of the table data will check
4385 * for "target EL >= current EL" to ensure the exception is not taken.
4389 * BIT IRQ IMO Non-secure Secure
4390 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
4392 const int8_t target_el_table
[2][2][2][2][2][4] = {
4393 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
4394 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
4395 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
4396 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
4397 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
4398 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
4399 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
4400 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
4401 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
4402 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
4403 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
4404 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
4405 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
4406 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
4407 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
4408 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
4412 * Determine the target EL for physical exceptions
4414 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
4415 uint32_t cur_el
, bool secure
)
4417 CPUARMState
*env
= cs
->env_ptr
;
4418 int rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
4422 int is64
= arm_el_is_aa64(env
, 3);
4426 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
4427 hcr
= ((env
->cp15
.hcr_el2
& HCR_IMO
) == HCR_IMO
);
4430 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
4431 hcr
= ((env
->cp15
.hcr_el2
& HCR_FMO
) == HCR_FMO
);
4434 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
4435 hcr
= ((env
->cp15
.hcr_el2
& HCR_AMO
) == HCR_AMO
);
4439 /* If HCR.TGE is set then HCR is treated as being 1 */
4440 hcr
|= ((env
->cp15
.hcr_el2
& HCR_TGE
) == HCR_TGE
);
4442 /* Perform a table-lookup for the target EL given the current state */
4443 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
4445 assert(target_el
> 0);
4450 static void v7m_push(CPUARMState
*env
, uint32_t val
)
4452 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
4455 stl_phys(cs
->as
, env
->regs
[13], val
);
4458 static uint32_t v7m_pop(CPUARMState
*env
)
4460 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
4463 val
= ldl_phys(cs
->as
, env
->regs
[13]);
4468 /* Switch to V7M main or process stack pointer. */
4469 static void switch_v7m_sp(CPUARMState
*env
, int process
)
4472 if (env
->v7m
.current_sp
!= process
) {
4473 tmp
= env
->v7m
.other_sp
;
4474 env
->v7m
.other_sp
= env
->regs
[13];
4475 env
->regs
[13] = tmp
;
4476 env
->v7m
.current_sp
= process
;
4480 static void do_v7m_exception_exit(CPUARMState
*env
)
4485 type
= env
->regs
[15];
4486 if (env
->v7m
.exception
!= 0)
4487 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
4489 /* Switch to the target stack. */
4490 switch_v7m_sp(env
, (type
& 4) != 0);
4491 /* Pop registers. */
4492 env
->regs
[0] = v7m_pop(env
);
4493 env
->regs
[1] = v7m_pop(env
);
4494 env
->regs
[2] = v7m_pop(env
);
4495 env
->regs
[3] = v7m_pop(env
);
4496 env
->regs
[12] = v7m_pop(env
);
4497 env
->regs
[14] = v7m_pop(env
);
4498 env
->regs
[15] = v7m_pop(env
);
4499 if (env
->regs
[15] & 1) {
4500 qemu_log_mask(LOG_GUEST_ERROR
,
4501 "M profile return from interrupt with misaligned "
4502 "PC is UNPREDICTABLE\n");
4503 /* Actual hardware seems to ignore the lsbit, and there are several
4504 * RTOSes out there which incorrectly assume the r15 in the stack
4505 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
4507 env
->regs
[15] &= ~1U;
4509 xpsr
= v7m_pop(env
);
4510 xpsr_write(env
, xpsr
, 0xfffffdff);
4511 /* Undo stack alignment. */
4514 /* ??? The exception return type specifies Thread/Handler mode. However
4515 this is also implied by the xPSR value. Not sure what to do
4516 if there is a mismatch. */
4517 /* ??? Likewise for mismatches between the CONTROL register and the stack
4521 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
4523 ARMCPU
*cpu
= ARM_CPU(cs
);
4524 CPUARMState
*env
= &cpu
->env
;
4525 uint32_t xpsr
= xpsr_read(env
);
4529 arm_log_exception(cs
->exception_index
);
4532 if (env
->v7m
.current_sp
)
4534 if (env
->v7m
.exception
== 0)
4537 /* For exceptions we just mark as pending on the NVIC, and let that
4539 /* TODO: Need to escalate if the current priority is higher than the
4540 one we're raising. */
4541 switch (cs
->exception_index
) {
4543 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
4546 /* The PC already points to the next instruction. */
4547 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
4549 case EXCP_PREFETCH_ABORT
:
4550 case EXCP_DATA_ABORT
:
4551 /* TODO: if we implemented the MPU registers, this is where we
4552 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
4554 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
4557 if (semihosting_enabled
) {
4559 nr
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
4562 env
->regs
[0] = do_arm_semihosting(env
);
4563 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
4567 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
4570 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
4572 case EXCP_EXCEPTION_EXIT
:
4573 do_v7m_exception_exit(env
);
4576 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
4577 return; /* Never happens. Keep compiler happy. */
4580 /* Align stack pointer. */
4581 /* ??? Should only do this if Configuration Control Register
4582 STACKALIGN bit is set. */
4583 if (env
->regs
[13] & 4) {
4587 /* Switch to the handler mode. */
4588 v7m_push(env
, xpsr
);
4589 v7m_push(env
, env
->regs
[15]);
4590 v7m_push(env
, env
->regs
[14]);
4591 v7m_push(env
, env
->regs
[12]);
4592 v7m_push(env
, env
->regs
[3]);
4593 v7m_push(env
, env
->regs
[2]);
4594 v7m_push(env
, env
->regs
[1]);
4595 v7m_push(env
, env
->regs
[0]);
4596 switch_v7m_sp(env
, 0);
4598 env
->condexec_bits
= 0;
4600 addr
= ldl_phys(cs
->as
, env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
4601 env
->regs
[15] = addr
& 0xfffffffe;
4602 env
->thumb
= addr
& 1;
4605 /* Function used to synchronize QEMU's AArch64 register set with AArch32
4606 * register set. This is necessary when switching between AArch32 and AArch64
4609 void aarch64_sync_32_to_64(CPUARMState
*env
)
4612 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
4614 /* We can blanket copy R[0:7] to X[0:7] */
4615 for (i
= 0; i
< 8; i
++) {
4616 env
->xregs
[i
] = env
->regs
[i
];
4619 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
4620 * Otherwise, they come from the banked user regs.
4622 if (mode
== ARM_CPU_MODE_FIQ
) {
4623 for (i
= 8; i
< 13; i
++) {
4624 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
4627 for (i
= 8; i
< 13; i
++) {
4628 env
->xregs
[i
] = env
->regs
[i
];
4632 /* Registers x13-x23 are the various mode SP and FP registers. Registers
4633 * r13 and r14 are only copied if we are in that mode, otherwise we copy
4634 * from the mode banked register.
4636 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
4637 env
->xregs
[13] = env
->regs
[13];
4638 env
->xregs
[14] = env
->regs
[14];
4640 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
4641 /* HYP is an exception in that it is copied from r14 */
4642 if (mode
== ARM_CPU_MODE_HYP
) {
4643 env
->xregs
[14] = env
->regs
[14];
4645 env
->xregs
[14] = env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)];
4649 if (mode
== ARM_CPU_MODE_HYP
) {
4650 env
->xregs
[15] = env
->regs
[13];
4652 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
4655 if (mode
== ARM_CPU_MODE_IRQ
) {
4656 env
->xregs
[16] = env
->regs
[13];
4657 env
->xregs
[17] = env
->regs
[14];
4659 env
->xregs
[16] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
4660 env
->xregs
[17] = env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)];
4663 if (mode
== ARM_CPU_MODE_SVC
) {
4664 env
->xregs
[18] = env
->regs
[13];
4665 env
->xregs
[19] = env
->regs
[14];
4667 env
->xregs
[18] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
4668 env
->xregs
[19] = env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)];
4671 if (mode
== ARM_CPU_MODE_ABT
) {
4672 env
->xregs
[20] = env
->regs
[13];
4673 env
->xregs
[21] = env
->regs
[14];
4675 env
->xregs
[20] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
4676 env
->xregs
[21] = env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)];
4679 if (mode
== ARM_CPU_MODE_UND
) {
4680 env
->xregs
[22] = env
->regs
[13];
4681 env
->xregs
[23] = env
->regs
[14];
4683 env
->xregs
[22] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
4684 env
->xregs
[23] = env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)];
4687 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
4688 * mode, then we can copy from r8-r14. Otherwise, we copy from the
4689 * FIQ bank for r8-r14.
4691 if (mode
== ARM_CPU_MODE_FIQ
) {
4692 for (i
= 24; i
< 31; i
++) {
4693 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
4696 for (i
= 24; i
< 29; i
++) {
4697 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
4699 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
4700 env
->xregs
[30] = env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)];
4703 env
->pc
= env
->regs
[15];
4706 /* Function used to synchronize QEMU's AArch32 register set with AArch64
4707 * register set. This is necessary when switching between AArch32 and AArch64
4710 void aarch64_sync_64_to_32(CPUARMState
*env
)
4713 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
4715 /* We can blanket copy X[0:7] to R[0:7] */
4716 for (i
= 0; i
< 8; i
++) {
4717 env
->regs
[i
] = env
->xregs
[i
];
4720 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
4721 * Otherwise, we copy x8-x12 into the banked user regs.
4723 if (mode
== ARM_CPU_MODE_FIQ
) {
4724 for (i
= 8; i
< 13; i
++) {
4725 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
4728 for (i
= 8; i
< 13; i
++) {
4729 env
->regs
[i
] = env
->xregs
[i
];
4733 /* Registers r13 & r14 depend on the current mode.
4734 * If we are in a given mode, we copy the corresponding x registers to r13
4735 * and r14. Otherwise, we copy the x register to the banked r13 and r14
4738 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
4739 env
->regs
[13] = env
->xregs
[13];
4740 env
->regs
[14] = env
->xregs
[14];
4742 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
4744 /* HYP is an exception in that it does not have its own banked r14 but
4745 * shares the USR r14
4747 if (mode
== ARM_CPU_MODE_HYP
) {
4748 env
->regs
[14] = env
->xregs
[14];
4750 env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
4754 if (mode
== ARM_CPU_MODE_HYP
) {
4755 env
->regs
[13] = env
->xregs
[15];
4757 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
4760 if (mode
== ARM_CPU_MODE_IRQ
) {
4761 env
->regs
[13] = env
->xregs
[16];
4762 env
->regs
[14] = env
->xregs
[17];
4764 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
4765 env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
4768 if (mode
== ARM_CPU_MODE_SVC
) {
4769 env
->regs
[13] = env
->xregs
[18];
4770 env
->regs
[14] = env
->xregs
[19];
4772 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
4773 env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
4776 if (mode
== ARM_CPU_MODE_ABT
) {
4777 env
->regs
[13] = env
->xregs
[20];
4778 env
->regs
[14] = env
->xregs
[21];
4780 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
4781 env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
4784 if (mode
== ARM_CPU_MODE_UND
) {
4785 env
->regs
[13] = env
->xregs
[22];
4786 env
->regs
[14] = env
->xregs
[23];
4788 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
4789 env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
4792 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
4793 * mode, then we can copy to r8-r14. Otherwise, we copy to the
4794 * FIQ bank for r8-r14.
4796 if (mode
== ARM_CPU_MODE_FIQ
) {
4797 for (i
= 24; i
< 31; i
++) {
4798 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
4801 for (i
= 24; i
< 29; i
++) {
4802 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
4804 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
4805 env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
4808 env
->regs
[15] = env
->pc
;
4811 /* Handle a CPU exception. */
4812 void arm_cpu_do_interrupt(CPUState
*cs
)
4814 ARMCPU
*cpu
= ARM_CPU(cs
);
4815 CPUARMState
*env
= &cpu
->env
;
4824 arm_log_exception(cs
->exception_index
);
4826 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
4827 arm_handle_psci_call(cpu
);
4828 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
4832 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
4833 switch (env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
) {
4835 case EC_BREAKPOINT_SAME_EL
:
4839 case EC_WATCHPOINT_SAME_EL
:
4845 case EC_VECTORCATCH
:
4854 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
4857 /* TODO: Vectored interrupt controller. */
4858 switch (cs
->exception_index
) {
4860 new_mode
= ARM_CPU_MODE_UND
;
4869 if (semihosting_enabled
) {
4870 /* Check for semihosting interrupt. */
4872 mask
= arm_lduw_code(env
, env
->regs
[15] - 2, env
->bswap_code
)
4875 mask
= arm_ldl_code(env
, env
->regs
[15] - 4, env
->bswap_code
)
4878 /* Only intercept calls from privileged modes, to provide some
4879 semblance of security. */
4880 if (((mask
== 0x123456 && !env
->thumb
)
4881 || (mask
== 0xab && env
->thumb
))
4882 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
4883 env
->regs
[0] = do_arm_semihosting(env
);
4884 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
4888 new_mode
= ARM_CPU_MODE_SVC
;
4891 /* The PC already points to the next instruction. */
4895 /* See if this is a semihosting syscall. */
4896 if (env
->thumb
&& semihosting_enabled
) {
4897 mask
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
4899 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
4901 env
->regs
[0] = do_arm_semihosting(env
);
4902 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
4906 env
->exception
.fsr
= 2;
4907 /* Fall through to prefetch abort. */
4908 case EXCP_PREFETCH_ABORT
:
4909 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
4910 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
4911 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
4912 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
4913 new_mode
= ARM_CPU_MODE_ABT
;
4915 mask
= CPSR_A
| CPSR_I
;
4918 case EXCP_DATA_ABORT
:
4919 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
4920 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
4921 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
4923 (uint32_t)env
->exception
.vaddress
);
4924 new_mode
= ARM_CPU_MODE_ABT
;
4926 mask
= CPSR_A
| CPSR_I
;
4930 new_mode
= ARM_CPU_MODE_IRQ
;
4932 /* Disable IRQ and imprecise data aborts. */
4933 mask
= CPSR_A
| CPSR_I
;
4935 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
4936 /* IRQ routed to monitor mode */
4937 new_mode
= ARM_CPU_MODE_MON
;
4942 new_mode
= ARM_CPU_MODE_FIQ
;
4944 /* Disable FIQ, IRQ and imprecise data aborts. */
4945 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
4946 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
4947 /* FIQ routed to monitor mode */
4948 new_mode
= ARM_CPU_MODE_MON
;
4953 new_mode
= ARM_CPU_MODE_MON
;
4955 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
4959 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
4960 return; /* Never happens. Keep compiler happy. */
4963 if (new_mode
== ARM_CPU_MODE_MON
) {
4964 addr
+= env
->cp15
.mvbar
;
4965 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
4966 /* High vectors. When enabled, base address cannot be remapped. */
4969 /* ARM v7 architectures provide a vector base address register to remap
4970 * the interrupt vector table.
4971 * This register is only followed in non-monitor mode, and is banked.
4972 * Note: only bits 31:5 are valid.
4974 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
4977 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
4978 env
->cp15
.scr_el3
&= ~SCR_NS
;
4981 switch_mode (env
, new_mode
);
4982 /* For exceptions taken to AArch32 we must clear the SS bit in both
4983 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
4985 env
->uncached_cpsr
&= ~PSTATE_SS
;
4986 env
->spsr
= cpsr_read(env
);
4987 /* Clear IT bits. */
4988 env
->condexec_bits
= 0;
4989 /* Switch to the new mode, and to the correct instruction set. */
4990 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
4992 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
4993 * and we should just guard the thumb mode on V4 */
4994 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
4995 env
->thumb
= (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
4997 env
->regs
[14] = env
->regs
[15] + offset
;
4998 env
->regs
[15] = addr
;
4999 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
5003 /* Return the exception level which controls this address translation regime */
5004 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5007 case ARMMMUIdx_S2NS
:
5008 case ARMMMUIdx_S1E2
:
5010 case ARMMMUIdx_S1E3
:
5012 case ARMMMUIdx_S1SE0
:
5013 return arm_el_is_aa64(env
, 3) ? 1 : 3;
5014 case ARMMMUIdx_S1SE1
:
5015 case ARMMMUIdx_S1NSE0
:
5016 case ARMMMUIdx_S1NSE1
:
5019 g_assert_not_reached();
5023 /* Return true if this address translation regime is secure */
5024 static inline bool regime_is_secure(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5027 case ARMMMUIdx_S12NSE0
:
5028 case ARMMMUIdx_S12NSE1
:
5029 case ARMMMUIdx_S1NSE0
:
5030 case ARMMMUIdx_S1NSE1
:
5031 case ARMMMUIdx_S1E2
:
5032 case ARMMMUIdx_S2NS
:
5034 case ARMMMUIdx_S1E3
:
5035 case ARMMMUIdx_S1SE0
:
5036 case ARMMMUIdx_S1SE1
:
5039 g_assert_not_reached();
5043 /* Return the SCTLR value which controls this address translation regime */
5044 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5046 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
5049 /* Return true if the specified stage of address translation is disabled */
5050 static inline bool regime_translation_disabled(CPUARMState
*env
,
5053 if (mmu_idx
== ARMMMUIdx_S2NS
) {
5054 return (env
->cp15
.hcr_el2
& HCR_VM
) == 0;
5056 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
5059 /* Return the TCR controlling this translation regime */
5060 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5062 if (mmu_idx
== ARMMMUIdx_S2NS
) {
5063 /* TODO: return VTCR_EL2 */
5064 g_assert_not_reached();
5066 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
5069 /* Return the TTBR associated with this translation regime */
5070 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
5073 if (mmu_idx
== ARMMMUIdx_S2NS
) {
5074 /* TODO: return VTTBR_EL2 */
5075 g_assert_not_reached();
5078 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
5080 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
5084 /* Return true if the translation regime is using LPAE format page tables */
5085 static inline bool regime_using_lpae_format(CPUARMState
*env
,
5088 int el
= regime_el(env
, mmu_idx
);
5089 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
5092 if (arm_feature(env
, ARM_FEATURE_LPAE
)
5093 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
5099 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5102 case ARMMMUIdx_S1SE0
:
5103 case ARMMMUIdx_S1NSE0
:
5107 case ARMMMUIdx_S12NSE0
:
5108 case ARMMMUIdx_S12NSE1
:
5109 g_assert_not_reached();
5113 /* Translate section/page access permissions to page
5114 * R/W protection flags
5117 * @mmu_idx: MMU index indicating required translation regime
5118 * @ap: The 3-bit access permissions (AP[2:0])
5119 * @domain_prot: The 2-bit domain access permissions
5121 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
5122 int ap
, int domain_prot
)
5124 bool is_user
= regime_is_user(env
, mmu_idx
);
5126 if (domain_prot
== 3) {
5127 return PAGE_READ
| PAGE_WRITE
;
5132 if (arm_feature(env
, ARM_FEATURE_V7
)) {
5135 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
5137 return is_user
? 0 : PAGE_READ
;
5144 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
5149 return PAGE_READ
| PAGE_WRITE
;
5152 return PAGE_READ
| PAGE_WRITE
;
5153 case 4: /* Reserved. */
5156 return is_user
? 0 : PAGE_READ
;
5160 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
5165 g_assert_not_reached();
5169 /* Translate section/page access permissions to page
5170 * R/W protection flags.
5172 * @ap: The 2-bit simple AP (AP[2:1])
5173 * @is_user: TRUE if accessing from PL0
5175 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
5179 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
5181 return PAGE_READ
| PAGE_WRITE
;
5183 return is_user
? 0 : PAGE_READ
;
5187 g_assert_not_reached();
5192 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
5194 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
5197 /* Translate section/page access permissions to protection flags
5200 * @mmu_idx: MMU index indicating required translation regime
5201 * @is_aa64: TRUE if AArch64
5202 * @ap: The 2-bit simple AP (AP[2:1])
5203 * @ns: NS (non-secure) bit
5204 * @xn: XN (execute-never) bit
5205 * @pxn: PXN (privileged execute-never) bit
5207 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
5208 int ap
, int ns
, int xn
, int pxn
)
5210 bool is_user
= regime_is_user(env
, mmu_idx
);
5211 int prot_rw
, user_rw
;
5215 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
5217 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
5221 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
5224 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
5228 /* TODO have_wxn should be replaced with
5229 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
5230 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
5231 * compatible processors have EL2, which is required for [U]WXN.
5233 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
5236 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
5240 switch (regime_el(env
, mmu_idx
)) {
5243 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
5250 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
5251 switch (regime_el(env
, mmu_idx
)) {
5255 xn
= xn
|| !(user_rw
& PAGE_READ
);
5259 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
5261 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
5262 (uwxn
&& (user_rw
& PAGE_WRITE
));
5272 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
5275 return prot_rw
| PAGE_EXEC
;
5278 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
5279 uint32_t *table
, uint32_t address
)
5281 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
5282 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
5284 if (address
& tcr
->mask
) {
5285 if (tcr
->raw_tcr
& TTBCR_PD1
) {
5286 /* Translation table walk disabled for TTBR1 */
5289 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
5291 if (tcr
->raw_tcr
& TTBCR_PD0
) {
5292 /* Translation table walk disabled for TTBR0 */
5295 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
5297 *table
|= (address
>> 18) & 0x3ffc;
5301 /* All loads done in the course of a page table walk go through here.
5302 * TODO: rather than ignoring errors from physical memory reads (which
5303 * are external aborts in ARM terminology) we should propagate this
5304 * error out so that we can turn it into a Data Abort if this walk
5305 * was being done for a CPU load/store or an address translation instruction
5306 * (but not if it was for a debug access).
5308 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
)
5310 MemTxAttrs attrs
= {};
5312 attrs
.secure
= is_secure
;
5313 return address_space_ldl(cs
->as
, addr
, attrs
, NULL
);
5316 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
)
5318 MemTxAttrs attrs
= {};
5320 attrs
.secure
= is_secure
;
5321 return address_space_ldq(cs
->as
, addr
, attrs
, NULL
);
5324 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
5325 int access_type
, ARMMMUIdx mmu_idx
,
5326 hwaddr
*phys_ptr
, int *prot
,
5327 target_ulong
*page_size
, uint32_t *fsr
)
5329 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
5340 /* Pagetable walk. */
5341 /* Lookup l1 descriptor. */
5342 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
5343 /* Section translation fault if page walk is disabled by PD0 or PD1 */
5347 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
));
5349 domain
= (desc
>> 5) & 0x0f;
5350 if (regime_el(env
, mmu_idx
) == 1) {
5351 dacr
= env
->cp15
.dacr_ns
;
5353 dacr
= env
->cp15
.dacr_s
;
5355 domain_prot
= (dacr
>> (domain
* 2)) & 3;
5357 /* Section translation fault. */
5361 if (domain_prot
== 0 || domain_prot
== 2) {
5363 code
= 9; /* Section domain fault. */
5365 code
= 11; /* Page domain fault. */
5370 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
5371 ap
= (desc
>> 10) & 3;
5373 *page_size
= 1024 * 1024;
5375 /* Lookup l2 entry. */
5377 /* Coarse pagetable. */
5378 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
5380 /* Fine pagetable. */
5381 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
5383 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
));
5385 case 0: /* Page translation fault. */
5388 case 1: /* 64k page. */
5389 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
5390 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
5391 *page_size
= 0x10000;
5393 case 2: /* 4k page. */
5394 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
5395 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
5396 *page_size
= 0x1000;
5398 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
5400 /* ARMv6/XScale extended small page format */
5401 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
5402 || arm_feature(env
, ARM_FEATURE_V6
)) {
5403 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
5404 *page_size
= 0x1000;
5406 /* UNPREDICTABLE in ARMv5; we choose to take a
5407 * page translation fault.
5413 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
5416 ap
= (desc
>> 4) & 3;
5419 /* Never happens, but compiler isn't smart enough to tell. */
5424 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
5425 *prot
|= *prot
? PAGE_EXEC
: 0;
5426 if (!(*prot
& (1 << access_type
))) {
5427 /* Access permission fault. */
5430 *phys_ptr
= phys_addr
;
5433 *fsr
= code
| (domain
<< 4);
5437 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
5438 int access_type
, ARMMMUIdx mmu_idx
,
5439 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
5440 target_ulong
*page_size
, uint32_t *fsr
)
5442 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
5456 /* Pagetable walk. */
5457 /* Lookup l1 descriptor. */
5458 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
5459 /* Section translation fault if page walk is disabled by PD0 or PD1 */
5463 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
));
5465 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
5466 /* Section translation fault, or attempt to use the encoding
5467 * which is Reserved on implementations without PXN.
5472 if ((type
== 1) || !(desc
& (1 << 18))) {
5473 /* Page or Section. */
5474 domain
= (desc
>> 5) & 0x0f;
5476 if (regime_el(env
, mmu_idx
) == 1) {
5477 dacr
= env
->cp15
.dacr_ns
;
5479 dacr
= env
->cp15
.dacr_s
;
5481 domain_prot
= (dacr
>> (domain
* 2)) & 3;
5482 if (domain_prot
== 0 || domain_prot
== 2) {
5484 code
= 9; /* Section domain fault. */
5486 code
= 11; /* Page domain fault. */
5491 if (desc
& (1 << 18)) {
5493 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
5494 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
5495 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
5496 *page_size
= 0x1000000;
5499 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
5500 *page_size
= 0x100000;
5502 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
5503 xn
= desc
& (1 << 4);
5506 ns
= extract32(desc
, 19, 1);
5508 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
5509 pxn
= (desc
>> 2) & 1;
5511 ns
= extract32(desc
, 3, 1);
5512 /* Lookup l2 entry. */
5513 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
5514 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
));
5515 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
5517 case 0: /* Page translation fault. */
5520 case 1: /* 64k page. */
5521 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
5522 xn
= desc
& (1 << 15);
5523 *page_size
= 0x10000;
5525 case 2: case 3: /* 4k page. */
5526 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
5528 *page_size
= 0x1000;
5531 /* Never happens, but compiler isn't smart enough to tell. */
5536 if (domain_prot
== 3) {
5537 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
5539 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
5542 if (xn
&& access_type
== 2)
5545 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
5546 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
5547 /* The simplified model uses AP[0] as an access control bit. */
5548 if ((ap
& 1) == 0) {
5549 /* Access flag fault. */
5550 code
= (code
== 15) ? 6 : 3;
5553 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
5555 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
5560 if (!(*prot
& (1 << access_type
))) {
5561 /* Access permission fault. */
5566 /* The NS bit will (as required by the architecture) have no effect if
5567 * the CPU doesn't support TZ or this is a non-secure translation
5568 * regime, because the attribute will already be non-secure.
5570 attrs
->secure
= false;
5572 *phys_ptr
= phys_addr
;
5575 *fsr
= code
| (domain
<< 4);
5579 /* Fault type for long-descriptor MMU fault reporting; this corresponds
5580 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
5583 translation_fault
= 1,
5585 permission_fault
= 3,
5588 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
5589 int access_type
, ARMMMUIdx mmu_idx
,
5590 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
5591 target_ulong
*page_size_ptr
, uint32_t *fsr
)
5593 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
5594 /* Read an LPAE long-descriptor translation table. */
5595 MMUFaultType fault_type
= translation_fault
;
5602 hwaddr descaddr
, descmask
;
5603 uint32_t tableattrs
;
5604 target_ulong page_size
;
5606 int32_t granule_sz
= 9;
5607 int32_t va_size
= 32;
5609 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
5610 int ap
, ns
, xn
, pxn
;
5611 uint32_t el
= regime_el(env
, mmu_idx
);
5612 bool ttbr1_valid
= true;
5615 * This code does not handle the different format TCR for VTCR_EL2.
5616 * This code also does not support shareability levels.
5617 * Attribute and permission bit handling should also be checked when adding
5618 * support for those page table walks.
5620 if (arm_el_is_aa64(env
, el
)) {
5623 tbi
= extract64(tcr
->raw_tcr
, 20, 1);
5625 if (extract64(address
, 55, 1)) {
5626 tbi
= extract64(tcr
->raw_tcr
, 38, 1);
5628 tbi
= extract64(tcr
->raw_tcr
, 37, 1);
5633 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
5637 ttbr1_valid
= false;
5641 /* Determine whether this address is in the region controlled by
5642 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
5643 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
5644 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
5646 uint32_t t0sz
= extract32(tcr
->raw_tcr
, 0, 6);
5647 if (va_size
== 64) {
5648 t0sz
= MIN(t0sz
, 39);
5649 t0sz
= MAX(t0sz
, 16);
5651 uint32_t t1sz
= extract32(tcr
->raw_tcr
, 16, 6);
5652 if (va_size
== 64) {
5653 t1sz
= MIN(t1sz
, 39);
5654 t1sz
= MAX(t1sz
, 16);
5656 if (t0sz
&& !extract64(address
, va_size
- t0sz
, t0sz
- tbi
)) {
5657 /* there is a ttbr0 region and we are in it (high bits all zero) */
5659 } else if (ttbr1_valid
&& t1sz
&&
5660 !extract64(~address
, va_size
- t1sz
, t1sz
- tbi
)) {
5661 /* there is a ttbr1 region and we are in it (high bits all one) */
5664 /* ttbr0 region is "everything not in the ttbr1 region" */
5666 } else if (!t1sz
&& ttbr1_valid
) {
5667 /* ttbr1 region is "everything not in the ttbr0 region" */
5670 /* in the gap between the two regions, this is a Translation fault */
5671 fault_type
= translation_fault
;
5675 /* Note that QEMU ignores shareability and cacheability attributes,
5676 * so we don't need to do anything with the SH, ORGN, IRGN fields
5677 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
5678 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
5679 * implement any ASID-like capability so we can ignore it (instead
5680 * we will always flush the TLB any time the ASID is changed).
5682 if (ttbr_select
== 0) {
5683 ttbr
= regime_ttbr(env
, mmu_idx
, 0);
5684 epd
= extract32(tcr
->raw_tcr
, 7, 1);
5687 tg
= extract32(tcr
->raw_tcr
, 14, 2);
5688 if (tg
== 1) { /* 64KB pages */
5691 if (tg
== 2) { /* 16KB pages */
5695 /* We should only be here if TTBR1 is valid */
5696 assert(ttbr1_valid
);
5698 ttbr
= regime_ttbr(env
, mmu_idx
, 1);
5699 epd
= extract32(tcr
->raw_tcr
, 23, 1);
5702 tg
= extract32(tcr
->raw_tcr
, 30, 2);
5703 if (tg
== 3) { /* 64KB pages */
5706 if (tg
== 1) { /* 16KB pages */
5711 /* Here we should have set up all the parameters for the translation:
5712 * va_size, ttbr, epd, tsz, granule_sz, tbi
5716 /* Translation table walk disabled => Translation fault on TLB miss
5717 * Note: This is always 0 on 64-bit EL2 and EL3.
5722 /* The starting level depends on the virtual address size (which can be
5723 * up to 48 bits) and the translation granule size. It indicates the number
5724 * of strides (granule_sz bits at a time) needed to consume the bits
5725 * of the input address. In the pseudocode this is:
5726 * level = 4 - RoundUp((inputsize - grainsize) / stride)
5727 * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
5728 * our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
5729 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
5730 * = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
5731 * = 4 - (va_size - tsz - 4) / granule_sz;
5733 level
= 4 - (va_size
- tsz
- 4) / granule_sz
;
5735 /* Clear the vaddr bits which aren't part of the within-region address,
5736 * so that we don't have to special case things when calculating the
5737 * first descriptor address.
5740 address
&= (1ULL << (va_size
- tsz
)) - 1;
5743 descmask
= (1ULL << (granule_sz
+ 3)) - 1;
5745 /* Now we can extract the actual base address from the TTBR */
5746 descaddr
= extract64(ttbr
, 0, 48);
5747 descaddr
&= ~((1ULL << (va_size
- tsz
- (granule_sz
* (4 - level
)))) - 1);
5749 /* Secure accesses start with the page table in secure memory and
5750 * can be downgraded to non-secure at any step. Non-secure accesses
5751 * remain non-secure. We implement this by just ORing in the NSTable/NS
5752 * bits at each step.
5754 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
5756 uint64_t descriptor
;
5759 descaddr
|= (address
>> (granule_sz
* (4 - level
))) & descmask
;
5761 nstable
= extract32(tableattrs
, 4, 1);
5762 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
);
5763 if (!(descriptor
& 1) ||
5764 (!(descriptor
& 2) && (level
== 3))) {
5765 /* Invalid, or the Reserved level 3 encoding */
5768 descaddr
= descriptor
& 0xfffffff000ULL
;
5770 if ((descriptor
& 2) && (level
< 3)) {
5771 /* Table entry. The top five bits are attributes which may
5772 * propagate down through lower levels of the table (and
5773 * which are all arranged so that 0 means "no effect", so
5774 * we can gather them up by ORing in the bits at each level).
5776 tableattrs
|= extract64(descriptor
, 59, 5);
5780 /* Block entry at level 1 or 2, or page entry at level 3.
5781 * These are basically the same thing, although the number
5782 * of bits we pull in from the vaddr varies.
5784 page_size
= (1ULL << ((granule_sz
* (4 - level
)) + 3));
5785 descaddr
|= (address
& (page_size
- 1));
5786 /* Extract attributes from the descriptor and merge with table attrs */
5787 attrs
= extract64(descriptor
, 2, 10)
5788 | (extract64(descriptor
, 52, 12) << 10);
5789 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
5790 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
5791 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
5792 * means "force PL1 access only", which means forcing AP[1] to 0.
5794 if (extract32(tableattrs
, 2, 1)) {
5797 attrs
|= nstable
<< 3; /* NS */
5800 /* Here descaddr is the final physical address, and attributes
5803 fault_type
= access_fault
;
5804 if ((attrs
& (1 << 8)) == 0) {
5809 ap
= extract32(attrs
, 4, 2);
5810 ns
= extract32(attrs
, 3, 1);
5811 xn
= extract32(attrs
, 12, 1);
5812 pxn
= extract32(attrs
, 11, 1);
5814 *prot
= get_S1prot(env
, mmu_idx
, va_size
== 64, ap
, ns
, xn
, pxn
);
5816 fault_type
= permission_fault
;
5817 if (!(*prot
& (1 << access_type
))) {
5822 /* The NS bit will (as required by the architecture) have no effect if
5823 * the CPU doesn't support TZ or this is a non-secure translation
5824 * regime, because the attribute will already be non-secure.
5826 txattrs
->secure
= false;
5828 *phys_ptr
= descaddr
;
5829 *page_size_ptr
= page_size
;
5833 /* Long-descriptor format IFSR/DFSR value */
5834 *fsr
= (1 << 9) | (fault_type
<< 2) | level
;
5838 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
5840 int32_t address
, int *prot
)
5842 *prot
= PAGE_READ
| PAGE_WRITE
;
5844 case 0xF0000000 ... 0xFFFFFFFF:
5845 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) { /* hivecs execing is ok */
5849 case 0x00000000 ... 0x7FFFFFFF:
5856 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
5857 int access_type
, ARMMMUIdx mmu_idx
,
5858 hwaddr
*phys_ptr
, int *prot
, uint32_t *fsr
)
5860 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5862 bool is_user
= regime_is_user(env
, mmu_idx
);
5864 *phys_ptr
= address
;
5867 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
5868 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
5869 } else { /* MPU enabled */
5870 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
5872 uint32_t base
= env
->pmsav7
.drbar
[n
];
5873 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
5877 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
5882 qemu_log_mask(LOG_GUEST_ERROR
, "DRSR.Rsize field can not be 0");
5886 rmask
= (1ull << rsize
) - 1;
5889 qemu_log_mask(LOG_GUEST_ERROR
, "DRBAR %" PRIx32
" misaligned "
5890 "to DRSR region size, mask = %" PRIx32
,
5895 if (address
< base
|| address
> base
+ rmask
) {
5899 /* Region matched */
5901 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
5903 uint32_t srdis_mask
;
5905 rsize
-= 3; /* sub region size (power of 2) */
5906 snd
= ((address
- base
) >> rsize
) & 0x7;
5907 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
5909 srdis_mask
= srdis
? 0x3 : 0x0;
5910 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
5911 /* This will check in groups of 2, 4 and then 8, whether
5912 * the subregion bits are consistent. rsize is incremented
5913 * back up to give the region size, considering consistent
5914 * adjacent subregions as one region. Stop testing if rsize
5915 * is already big enough for an entire QEMU page.
5917 int snd_rounded
= snd
& ~(i
- 1);
5918 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
5919 snd_rounded
+ 8, i
);
5920 if (srdis_mask
^ srdis_multi
) {
5923 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
5927 if (rsize
< TARGET_PAGE_BITS
) {
5928 qemu_log_mask(LOG_UNIMP
, "No support for MPU (sub)region"
5929 "alignment of %" PRIu32
" bits. Minimum is %d\n",
5930 rsize
, TARGET_PAGE_BITS
);
5939 if (n
== -1) { /* no hits */
5940 if (cpu
->pmsav7_dregion
&&
5941 (is_user
|| !(regime_sctlr(env
, mmu_idx
) & SCTLR_BR
))) {
5942 /* background fault */
5946 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
5947 } else { /* a MPU hit! */
5948 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
5950 if (is_user
) { /* User mode AP bit decoding */
5955 break; /* no access */
5957 *prot
|= PAGE_WRITE
;
5961 *prot
|= PAGE_READ
| PAGE_EXEC
;
5964 qemu_log_mask(LOG_GUEST_ERROR
,
5965 "Bad value for AP bits in DRACR %"
5968 } else { /* Priv. mode AP bits decoding */
5971 break; /* no access */
5975 *prot
|= PAGE_WRITE
;
5979 *prot
|= PAGE_READ
| PAGE_EXEC
;
5982 qemu_log_mask(LOG_GUEST_ERROR
,
5983 "Bad value for AP bits in DRACR %"
5989 if (env
->pmsav7
.dracr
[n
] & (1 << 12)) {
5990 *prot
&= ~PAGE_EXEC
;
5995 *fsr
= 0x00d; /* Permission fault */
5996 return !(*prot
& (1 << access_type
));
5999 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
6000 int access_type
, ARMMMUIdx mmu_idx
,
6001 hwaddr
*phys_ptr
, int *prot
, uint32_t *fsr
)
6006 bool is_user
= regime_is_user(env
, mmu_idx
);
6008 *phys_ptr
= address
;
6009 for (n
= 7; n
>= 0; n
--) {
6010 base
= env
->cp15
.c6_region
[n
];
6011 if ((base
& 1) == 0) {
6014 mask
= 1 << ((base
>> 1) & 0x1f);
6015 /* Keep this shift separate from the above to avoid an
6016 (undefined) << 32. */
6017 mask
= (mask
<< 1) - 1;
6018 if (((base
^ address
) & ~mask
) == 0) {
6027 if (access_type
== 2) {
6028 mask
= env
->cp15
.pmsav5_insn_ap
;
6030 mask
= env
->cp15
.pmsav5_data_ap
;
6032 mask
= (mask
>> (n
* 4)) & 0xf;
6042 *prot
= PAGE_READ
| PAGE_WRITE
;
6047 *prot
|= PAGE_WRITE
;
6051 *prot
= PAGE_READ
| PAGE_WRITE
;
6064 /* Bad permission. */
6072 /* get_phys_addr - get the physical address for this virtual address
6074 * Find the physical address corresponding to the given virtual address,
6075 * by doing a translation table walk on MMU based systems or using the
6076 * MPU state on MPU based systems.
6078 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
6079 * prot and page_size may not be filled in, and the populated fsr value provides
6080 * information on why the translation aborted, in the format of a
6081 * DFSR/IFSR fault register, with the following caveats:
6082 * * we honour the short vs long DFSR format differences.
6083 * * the WnR bit is never set (the caller must do this).
6084 * * for PSMAv5 based systems we don't bother to return a full FSR format
6088 * @address: virtual address to get physical address for
6089 * @access_type: 0 for read, 1 for write, 2 for execute
6090 * @mmu_idx: MMU index indicating required translation regime
6091 * @phys_ptr: set to the physical address corresponding to the virtual address
6092 * @attrs: set to the memory transaction attributes to use
6093 * @prot: set to the permissions for the page containing phys_ptr
6094 * @page_size: set to the size of the page containing phys_ptr
6095 * @fsr: set to the DFSR/IFSR value on failure
6097 static inline bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
6098 int access_type
, ARMMMUIdx mmu_idx
,
6099 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
6100 target_ulong
*page_size
, uint32_t *fsr
)
6102 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
6103 /* TODO: when we support EL2 we should here call ourselves recursively
6104 * to do the stage 1 and then stage 2 translations. The arm_ld*_ptw
6105 * functions will also need changing to perform ARMMMUIdx_S2NS loads
6106 * rather than direct physical memory loads when appropriate.
6107 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
6109 assert(!arm_feature(env
, ARM_FEATURE_EL2
));
6110 mmu_idx
+= ARMMMUIdx_S1NSE0
;
6113 /* The page table entries may downgrade secure to non-secure, but
6114 * cannot upgrade an non-secure translation regime's attributes
6117 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
6118 attrs
->user
= regime_is_user(env
, mmu_idx
);
6120 /* Fast Context Switch Extension. This doesn't exist at all in v8.
6121 * In v7 and earlier it affects all stage 1 translations.
6123 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
6124 && !arm_feature(env
, ARM_FEATURE_V8
)) {
6125 if (regime_el(env
, mmu_idx
) == 3) {
6126 address
+= env
->cp15
.fcseidr_s
;
6128 address
+= env
->cp15
.fcseidr_ns
;
6132 /* pmsav7 has special handling for when MPU is disabled so call it before
6133 * the common MMU/MPU disabled check below.
6135 if (arm_feature(env
, ARM_FEATURE_MPU
) &&
6136 arm_feature(env
, ARM_FEATURE_V7
)) {
6137 *page_size
= TARGET_PAGE_SIZE
;
6138 return get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
6139 phys_ptr
, prot
, fsr
);
6142 if (regime_translation_disabled(env
, mmu_idx
)) {
6143 /* MMU/MPU disabled. */
6144 *phys_ptr
= address
;
6145 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
6146 *page_size
= TARGET_PAGE_SIZE
;
6150 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
6152 *page_size
= TARGET_PAGE_SIZE
;
6153 return get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
6154 phys_ptr
, prot
, fsr
);
6157 if (regime_using_lpae_format(env
, mmu_idx
)) {
6158 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
, phys_ptr
,
6159 attrs
, prot
, page_size
, fsr
);
6160 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
6161 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
, phys_ptr
,
6162 attrs
, prot
, page_size
, fsr
);
6164 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
, phys_ptr
,
6165 prot
, page_size
, fsr
);
6169 /* Walk the page table and (if the mapping exists) add the page
6170 * to the TLB. Return false on success, or true on failure. Populate
6171 * fsr with ARM DFSR/IFSR fault register format value on failure.
6173 bool arm_tlb_fill(CPUState
*cs
, vaddr address
,
6174 int access_type
, int mmu_idx
, uint32_t *fsr
)
6176 ARMCPU
*cpu
= ARM_CPU(cs
);
6177 CPUARMState
*env
= &cpu
->env
;
6179 target_ulong page_size
;
6182 MemTxAttrs attrs
= {};
6184 ret
= get_phys_addr(env
, address
, access_type
, mmu_idx
, &phys_addr
,
6185 &attrs
, &prot
, &page_size
, fsr
);
6187 /* Map a single [sub]page. */
6188 phys_addr
&= TARGET_PAGE_MASK
;
6189 address
&= TARGET_PAGE_MASK
;
6190 tlb_set_page_with_attrs(cs
, address
, phys_addr
, attrs
,
6191 prot
, mmu_idx
, page_size
);
6198 hwaddr
arm_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
6200 ARMCPU
*cpu
= ARM_CPU(cs
);
6201 CPUARMState
*env
= &cpu
->env
;
6203 target_ulong page_size
;
6207 MemTxAttrs attrs
= {};
6209 ret
= get_phys_addr(env
, addr
, 0, cpu_mmu_index(env
), &phys_addr
,
6210 &attrs
, &prot
, &page_size
, &fsr
);
6219 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
6221 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
6222 env
->regs
[13] = val
;
6224 env
->banked_r13
[bank_number(mode
)] = val
;
6228 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
6230 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
6231 return env
->regs
[13];
6233 return env
->banked_r13
[bank_number(mode
)];
6237 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
6239 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6243 return xpsr_read(env
) & 0xf8000000;
6245 return xpsr_read(env
) & 0xf80001ff;
6247 return xpsr_read(env
) & 0xff00fc00;
6249 return xpsr_read(env
) & 0xff00fdff;
6251 return xpsr_read(env
) & 0x000001ff;
6253 return xpsr_read(env
) & 0x0700fc00;
6255 return xpsr_read(env
) & 0x0700edff;
6257 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
6259 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
6260 case 16: /* PRIMASK */
6261 return (env
->daif
& PSTATE_I
) != 0;
6262 case 17: /* BASEPRI */
6263 case 18: /* BASEPRI_MAX */
6264 return env
->v7m
.basepri
;
6265 case 19: /* FAULTMASK */
6266 return (env
->daif
& PSTATE_F
) != 0;
6267 case 20: /* CONTROL */
6268 return env
->v7m
.control
;
6270 /* ??? For debugging only. */
6271 cpu_abort(CPU(cpu
), "Unimplemented system register read (%d)\n", reg
);
6276 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
6278 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6282 xpsr_write(env
, val
, 0xf8000000);
6285 xpsr_write(env
, val
, 0xf8000000);
6288 xpsr_write(env
, val
, 0xfe00fc00);
6291 xpsr_write(env
, val
, 0xfe00fc00);
6294 /* IPSR bits are readonly. */
6297 xpsr_write(env
, val
, 0x0600fc00);
6300 xpsr_write(env
, val
, 0x0600fc00);
6303 if (env
->v7m
.current_sp
)
6304 env
->v7m
.other_sp
= val
;
6306 env
->regs
[13] = val
;
6309 if (env
->v7m
.current_sp
)
6310 env
->regs
[13] = val
;
6312 env
->v7m
.other_sp
= val
;
6314 case 16: /* PRIMASK */
6316 env
->daif
|= PSTATE_I
;
6318 env
->daif
&= ~PSTATE_I
;
6321 case 17: /* BASEPRI */
6322 env
->v7m
.basepri
= val
& 0xff;
6324 case 18: /* BASEPRI_MAX */
6326 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
6327 env
->v7m
.basepri
= val
;
6329 case 19: /* FAULTMASK */
6331 env
->daif
|= PSTATE_F
;
6333 env
->daif
&= ~PSTATE_F
;
6336 case 20: /* CONTROL */
6337 env
->v7m
.control
= val
& 3;
6338 switch_v7m_sp(env
, (val
& 2) != 0);
6341 /* ??? For debugging only. */
6342 cpu_abort(CPU(cpu
), "Unimplemented system register write (%d)\n", reg
);
6349 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
6351 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
6352 * Note that we do not implement the (architecturally mandated)
6353 * alignment fault for attempts to use this on Device memory
6354 * (which matches the usual QEMU behaviour of not implementing either
6355 * alignment faults or any memory attribute handling).
6358 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6359 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
6360 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
6362 #ifndef CONFIG_USER_ONLY
6364 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
6365 * the block size so we might have to do more than one TLB lookup.
6366 * We know that in fact for any v8 CPU the page size is at least 4K
6367 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
6368 * 1K as an artefact of legacy v5 subpage support being present in the
6369 * same QEMU executable.
6371 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
6372 void *hostaddr
[maxidx
];
6374 unsigned mmu_idx
= cpu_mmu_index(env
);
6375 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
6377 for (try = 0; try < 2; try++) {
6379 for (i
= 0; i
< maxidx
; i
++) {
6380 hostaddr
[i
] = tlb_vaddr_to_host(env
,
6381 vaddr
+ TARGET_PAGE_SIZE
* i
,
6388 /* If it's all in the TLB it's fair game for just writing to;
6389 * we know we don't need to update dirty status, etc.
6391 for (i
= 0; i
< maxidx
- 1; i
++) {
6392 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
6394 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
6397 /* OK, try a store and see if we can populate the tlb. This
6398 * might cause an exception if the memory isn't writable,
6399 * in which case we will longjmp out of here. We must for
6400 * this purpose use the actual register value passed to us
6401 * so that we get the fault address right.
6403 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETRA());
6404 /* Now we can populate the other TLB entries, if any */
6405 for (i
= 0; i
< maxidx
; i
++) {
6406 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
6407 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
6408 helper_ret_stb_mmu(env
, va
, 0, oi
, GETRA());
6413 /* Slow path (probably attempt to do this to an I/O device or
6414 * similar, or clearing of a block of code we have translations
6415 * cached for). Just do a series of byte writes as the architecture
6416 * demands. It's not worth trying to use a cpu_physical_memory_map(),
6417 * memset(), unmap() sequence here because:
6418 * + we'd need to account for the blocksize being larger than a page
6419 * + the direct-RAM access case is almost always going to be dealt
6420 * with in the fastpath code above, so there's no speed benefit
6421 * + we would have to deal with the map returning NULL because the
6422 * bounce buffer was in use
6424 for (i
= 0; i
< blocklen
; i
++) {
6425 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETRA());
6429 memset(g2h(vaddr
), 0, blocklen
);
6433 /* Note that signed overflow is undefined in C. The following routines are
6434 careful to use unsigned types where modulo arithmetic is required.
6435 Failure to do so _will_ break on newer gcc. */
6437 /* Signed saturating arithmetic. */
6439 /* Perform 16-bit signed saturating addition. */
6440 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
6445 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
6454 /* Perform 8-bit signed saturating addition. */
6455 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
6460 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
6469 /* Perform 16-bit signed saturating subtraction. */
6470 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
6475 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
6484 /* Perform 8-bit signed saturating subtraction. */
6485 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
6490 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
6499 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
6500 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
6501 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
6502 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
6505 #include "op_addsub.h"
6507 /* Unsigned saturating arithmetic. */
6508 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
6517 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
6525 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
6534 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
6542 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
6543 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
6544 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
6545 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
6548 #include "op_addsub.h"
6550 /* Signed modulo arithmetic. */
6551 #define SARITH16(a, b, n, op) do { \
6553 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6554 RESULT(sum, n, 16); \
6556 ge |= 3 << (n * 2); \
6559 #define SARITH8(a, b, n, op) do { \
6561 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6562 RESULT(sum, n, 8); \
6568 #define ADD16(a, b, n) SARITH16(a, b, n, +)
6569 #define SUB16(a, b, n) SARITH16(a, b, n, -)
6570 #define ADD8(a, b, n) SARITH8(a, b, n, +)
6571 #define SUB8(a, b, n) SARITH8(a, b, n, -)
6575 #include "op_addsub.h"
6577 /* Unsigned modulo arithmetic. */
6578 #define ADD16(a, b, n) do { \
6580 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
6581 RESULT(sum, n, 16); \
6582 if ((sum >> 16) == 1) \
6583 ge |= 3 << (n * 2); \
6586 #define ADD8(a, b, n) do { \
6588 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
6589 RESULT(sum, n, 8); \
6590 if ((sum >> 8) == 1) \
6594 #define SUB16(a, b, n) do { \
6596 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
6597 RESULT(sum, n, 16); \
6598 if ((sum >> 16) == 0) \
6599 ge |= 3 << (n * 2); \
6602 #define SUB8(a, b, n) do { \
6604 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
6605 RESULT(sum, n, 8); \
6606 if ((sum >> 8) == 0) \
6613 #include "op_addsub.h"
6615 /* Halved signed arithmetic. */
6616 #define ADD16(a, b, n) \
6617 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
6618 #define SUB16(a, b, n) \
6619 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
6620 #define ADD8(a, b, n) \
6621 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
6622 #define SUB8(a, b, n) \
6623 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
6626 #include "op_addsub.h"
6628 /* Halved unsigned arithmetic. */
6629 #define ADD16(a, b, n) \
6630 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
6631 #define SUB16(a, b, n) \
6632 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
6633 #define ADD8(a, b, n) \
6634 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
6635 #define SUB8(a, b, n) \
6636 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
6639 #include "op_addsub.h"
6641 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
6649 /* Unsigned sum of absolute byte differences. */
6650 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
6653 sum
= do_usad(a
, b
);
6654 sum
+= do_usad(a
>> 8, b
>> 8);
6655 sum
+= do_usad(a
>> 16, b
>>16);
6656 sum
+= do_usad(a
>> 24, b
>> 24);
6660 /* For ARMv6 SEL instruction. */
6661 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
6674 return (a
& mask
) | (b
& ~mask
);
6677 /* VFP support. We follow the convention used for VFP instructions:
6678 Single precision routines have a "s" suffix, double precision a
6681 /* Convert host exception flags to vfp form. */
6682 static inline int vfp_exceptbits_from_host(int host_bits
)
6684 int target_bits
= 0;
6686 if (host_bits
& float_flag_invalid
)
6688 if (host_bits
& float_flag_divbyzero
)
6690 if (host_bits
& float_flag_overflow
)
6692 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
6694 if (host_bits
& float_flag_inexact
)
6695 target_bits
|= 0x10;
6696 if (host_bits
& float_flag_input_denormal
)
6697 target_bits
|= 0x80;
6701 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
6706 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
6707 | (env
->vfp
.vec_len
<< 16)
6708 | (env
->vfp
.vec_stride
<< 20);
6709 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
6710 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
6711 fpscr
|= vfp_exceptbits_from_host(i
);
6715 uint32_t vfp_get_fpscr(CPUARMState
*env
)
6717 return HELPER(vfp_get_fpscr
)(env
);
6720 /* Convert vfp exception flags to target form. */
6721 static inline int vfp_exceptbits_to_host(int target_bits
)
6725 if (target_bits
& 1)
6726 host_bits
|= float_flag_invalid
;
6727 if (target_bits
& 2)
6728 host_bits
|= float_flag_divbyzero
;
6729 if (target_bits
& 4)
6730 host_bits
|= float_flag_overflow
;
6731 if (target_bits
& 8)
6732 host_bits
|= float_flag_underflow
;
6733 if (target_bits
& 0x10)
6734 host_bits
|= float_flag_inexact
;
6735 if (target_bits
& 0x80)
6736 host_bits
|= float_flag_input_denormal
;
6740 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
6745 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
6746 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
6747 env
->vfp
.vec_len
= (val
>> 16) & 7;
6748 env
->vfp
.vec_stride
= (val
>> 20) & 3;
6751 if (changed
& (3 << 22)) {
6752 i
= (val
>> 22) & 3;
6754 case FPROUNDING_TIEEVEN
:
6755 i
= float_round_nearest_even
;
6757 case FPROUNDING_POSINF
:
6760 case FPROUNDING_NEGINF
:
6761 i
= float_round_down
;
6763 case FPROUNDING_ZERO
:
6764 i
= float_round_to_zero
;
6767 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
6769 if (changed
& (1 << 24)) {
6770 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
6771 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
6773 if (changed
& (1 << 25))
6774 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
6776 i
= vfp_exceptbits_to_host(val
);
6777 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
6778 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
6781 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
6783 HELPER(vfp_set_fpscr
)(env
, val
);
6786 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
6788 #define VFP_BINOP(name) \
6789 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
6791 float_status *fpst = fpstp; \
6792 return float32_ ## name(a, b, fpst); \
6794 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
6796 float_status *fpst = fpstp; \
6797 return float64_ ## name(a, b, fpst); \
6809 float32
VFP_HELPER(neg
, s
)(float32 a
)
6811 return float32_chs(a
);
6814 float64
VFP_HELPER(neg
, d
)(float64 a
)
6816 return float64_chs(a
);
6819 float32
VFP_HELPER(abs
, s
)(float32 a
)
6821 return float32_abs(a
);
6824 float64
VFP_HELPER(abs
, d
)(float64 a
)
6826 return float64_abs(a
);
6829 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
6831 return float32_sqrt(a
, &env
->vfp
.fp_status
);
6834 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
6836 return float64_sqrt(a
, &env
->vfp
.fp_status
);
6839 /* XXX: check quiet/signaling case */
6840 #define DO_VFP_cmp(p, type) \
6841 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
6844 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
6845 case 0: flags = 0x6; break; \
6846 case -1: flags = 0x8; break; \
6847 case 1: flags = 0x2; break; \
6848 default: case 2: flags = 0x3; break; \
6850 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
6851 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
6853 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
6856 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
6857 case 0: flags = 0x6; break; \
6858 case -1: flags = 0x8; break; \
6859 case 1: flags = 0x2; break; \
6860 default: case 2: flags = 0x3; break; \
6862 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
6863 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
6865 DO_VFP_cmp(s
, float32
)
6866 DO_VFP_cmp(d
, float64
)
6869 /* Integer to float and float to integer conversions */
6871 #define CONV_ITOF(name, fsz, sign) \
6872 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
6874 float_status *fpst = fpstp; \
6875 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
6878 #define CONV_FTOI(name, fsz, sign, round) \
6879 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
6881 float_status *fpst = fpstp; \
6882 if (float##fsz##_is_any_nan(x)) { \
6883 float_raise(float_flag_invalid, fpst); \
6886 return float##fsz##_to_##sign##int32##round(x, fpst); \
6889 #define FLOAT_CONVS(name, p, fsz, sign) \
6890 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
6891 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
6892 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
6894 FLOAT_CONVS(si
, s
, 32, )
6895 FLOAT_CONVS(si
, d
, 64, )
6896 FLOAT_CONVS(ui
, s
, 32, u
)
6897 FLOAT_CONVS(ui
, d
, 64, u
)
6903 /* floating point conversion */
6904 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
6906 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
6907 /* ARM requires that S<->D conversion of any kind of NaN generates
6908 * a quiet NaN by forcing the most significant frac bit to 1.
6910 return float64_maybe_silence_nan(r
);
6913 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
6915 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
6916 /* ARM requires that S<->D conversion of any kind of NaN generates
6917 * a quiet NaN by forcing the most significant frac bit to 1.
6919 return float32_maybe_silence_nan(r
);
6922 /* VFP3 fixed point conversion. */
6923 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
6924 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
6927 float_status *fpst = fpstp; \
6929 tmp = itype##_to_##float##fsz(x, fpst); \
6930 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
6933 /* Notice that we want only input-denormal exception flags from the
6934 * scalbn operation: the other possible flags (overflow+inexact if
6935 * we overflow to infinity, output-denormal) aren't correct for the
6936 * complete scale-and-convert operation.
6938 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
6939 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
6943 float_status *fpst = fpstp; \
6944 int old_exc_flags = get_float_exception_flags(fpst); \
6946 if (float##fsz##_is_any_nan(x)) { \
6947 float_raise(float_flag_invalid, fpst); \
6950 tmp = float##fsz##_scalbn(x, shift, fpst); \
6951 old_exc_flags |= get_float_exception_flags(fpst) \
6952 & float_flag_input_denormal; \
6953 set_float_exception_flags(old_exc_flags, fpst); \
6954 return float##fsz##_to_##itype##round(tmp, fpst); \
6957 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
6958 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
6959 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
6960 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
6962 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
6963 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
6964 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
6966 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
6967 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
6968 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
6969 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
6970 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
6971 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
6972 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
6973 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
6974 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
6975 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
6976 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
6977 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
6979 #undef VFP_CONV_FIX_FLOAT
6980 #undef VFP_CONV_FLOAT_FIX_ROUND
6982 /* Set the current fp rounding mode and return the old one.
6983 * The argument is a softfloat float_round_ value.
6985 uint32_t HELPER(set_rmode
)(uint32_t rmode
, CPUARMState
*env
)
6987 float_status
*fp_status
= &env
->vfp
.fp_status
;
6989 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
6990 set_float_rounding_mode(rmode
, fp_status
);
6995 /* Set the current fp rounding mode in the standard fp status and return
6996 * the old one. This is for NEON instructions that need to change the
6997 * rounding mode but wish to use the standard FPSCR values for everything
6998 * else. Always set the rounding mode back to the correct value after
7000 * The argument is a softfloat float_round_ value.
7002 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
7004 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
7006 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
7007 set_float_rounding_mode(rmode
, fp_status
);
7012 /* Half precision conversions. */
7013 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
7015 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
7016 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
7018 return float32_maybe_silence_nan(r
);
7023 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
7025 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
7026 float16 r
= float32_to_float16(a
, ieee
, s
);
7028 r
= float16_maybe_silence_nan(r
);
7030 return float16_val(r
);
7033 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
7035 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
7038 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
7040 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
7043 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
7045 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
7048 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
7050 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
7053 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, CPUARMState
*env
)
7055 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
7056 float64 r
= float16_to_float64(make_float16(a
), ieee
, &env
->vfp
.fp_status
);
7058 return float64_maybe_silence_nan(r
);
7063 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, CPUARMState
*env
)
7065 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
7066 float16 r
= float64_to_float16(a
, ieee
, &env
->vfp
.fp_status
);
7068 r
= float16_maybe_silence_nan(r
);
7070 return float16_val(r
);
7073 #define float32_two make_float32(0x40000000)
7074 #define float32_three make_float32(0x40400000)
7075 #define float32_one_point_five make_float32(0x3fc00000)
7077 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
7079 float_status
*s
= &env
->vfp
.standard_fp_status
;
7080 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
7081 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
7082 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
7083 float_raise(float_flag_input_denormal
, s
);
7087 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
7090 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
7092 float_status
*s
= &env
->vfp
.standard_fp_status
;
7094 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
7095 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
7096 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
7097 float_raise(float_flag_input_denormal
, s
);
7099 return float32_one_point_five
;
7101 product
= float32_mul(a
, b
, s
);
7102 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
7107 /* Constants 256 and 512 are used in some helpers; we avoid relying on
7108 * int->float conversions at run-time. */
7109 #define float64_256 make_float64(0x4070000000000000LL)
7110 #define float64_512 make_float64(0x4080000000000000LL)
7111 #define float32_maxnorm make_float32(0x7f7fffff)
7112 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
7114 /* Reciprocal functions
7116 * The algorithm that must be used to calculate the estimate
7117 * is specified by the ARM ARM, see FPRecipEstimate()
7120 static float64
recip_estimate(float64 a
, float_status
*real_fp_status
)
7122 /* These calculations mustn't set any fp exception flags,
7123 * so we use a local copy of the fp_status.
7125 float_status dummy_status
= *real_fp_status
;
7126 float_status
*s
= &dummy_status
;
7127 /* q = (int)(a * 512.0) */
7128 float64 q
= float64_mul(float64_512
, a
, s
);
7129 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
7131 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
7132 q
= int64_to_float64(q_int
, s
);
7133 q
= float64_add(q
, float64_half
, s
);
7134 q
= float64_div(q
, float64_512
, s
);
7135 q
= float64_div(float64_one
, q
, s
);
7137 /* s = (int)(256.0 * r + 0.5) */
7138 q
= float64_mul(q
, float64_256
, s
);
7139 q
= float64_add(q
, float64_half
, s
);
7140 q_int
= float64_to_int64_round_to_zero(q
, s
);
7142 /* return (double)s / 256.0 */
7143 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
7146 /* Common wrapper to call recip_estimate */
7147 static float64
call_recip_estimate(float64 num
, int off
, float_status
*fpst
)
7149 uint64_t val64
= float64_val(num
);
7150 uint64_t frac
= extract64(val64
, 0, 52);
7151 int64_t exp
= extract64(val64
, 52, 11);
7153 float64 scaled
, estimate
;
7155 /* Generate the scaled number for the estimate function */
7157 if (extract64(frac
, 51, 1) == 0) {
7159 frac
= extract64(frac
, 0, 50) << 2;
7161 frac
= extract64(frac
, 0, 51) << 1;
7165 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
7166 scaled
= make_float64((0x3feULL
<< 52)
7167 | extract64(frac
, 44, 8) << 44);
7169 estimate
= recip_estimate(scaled
, fpst
);
7171 /* Build new result */
7172 val64
= float64_val(estimate
);
7173 sbit
= 0x8000000000000000ULL
& val64
;
7175 frac
= extract64(val64
, 0, 52);
7178 frac
= 1ULL << 51 | extract64(frac
, 1, 51);
7179 } else if (exp
== -1) {
7180 frac
= 1ULL << 50 | extract64(frac
, 2, 50);
7184 return make_float64(sbit
| (exp
<< 52) | frac
);
7187 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
7189 switch (fpst
->float_rounding_mode
) {
7190 case float_round_nearest_even
: /* Round to Nearest */
7192 case float_round_up
: /* Round to +Inf */
7194 case float_round_down
: /* Round to -Inf */
7196 case float_round_to_zero
: /* Round to Zero */
7200 g_assert_not_reached();
7203 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
7205 float_status
*fpst
= fpstp
;
7206 float32 f32
= float32_squash_input_denormal(input
, fpst
);
7207 uint32_t f32_val
= float32_val(f32
);
7208 uint32_t f32_sbit
= 0x80000000ULL
& f32_val
;
7209 int32_t f32_exp
= extract32(f32_val
, 23, 8);
7210 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
7216 if (float32_is_any_nan(f32
)) {
7218 if (float32_is_signaling_nan(f32
)) {
7219 float_raise(float_flag_invalid
, fpst
);
7220 nan
= float32_maybe_silence_nan(f32
);
7222 if (fpst
->default_nan_mode
) {
7223 nan
= float32_default_nan
;
7226 } else if (float32_is_infinity(f32
)) {
7227 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
7228 } else if (float32_is_zero(f32
)) {
7229 float_raise(float_flag_divbyzero
, fpst
);
7230 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
7231 } else if ((f32_val
& ~(1ULL << 31)) < (1ULL << 21)) {
7232 /* Abs(value) < 2.0^-128 */
7233 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
7234 if (round_to_inf(fpst
, f32_sbit
)) {
7235 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
7237 return float32_set_sign(float32_maxnorm
, float32_is_neg(f32
));
7239 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
7240 float_raise(float_flag_underflow
, fpst
);
7241 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
7245 f64
= make_float64(((int64_t)(f32_exp
) << 52) | (int64_t)(f32_frac
) << 29);
7246 r64
= call_recip_estimate(f64
, 253, fpst
);
7247 r64_val
= float64_val(r64
);
7248 r64_exp
= extract64(r64_val
, 52, 11);
7249 r64_frac
= extract64(r64_val
, 0, 52);
7251 /* result = sign : result_exp<7:0> : fraction<51:29>; */
7252 return make_float32(f32_sbit
|
7253 (r64_exp
& 0xff) << 23 |
7254 extract64(r64_frac
, 29, 24));
7257 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
7259 float_status
*fpst
= fpstp
;
7260 float64 f64
= float64_squash_input_denormal(input
, fpst
);
7261 uint64_t f64_val
= float64_val(f64
);
7262 uint64_t f64_sbit
= 0x8000000000000000ULL
& f64_val
;
7263 int64_t f64_exp
= extract64(f64_val
, 52, 11);
7269 /* Deal with any special cases */
7270 if (float64_is_any_nan(f64
)) {
7272 if (float64_is_signaling_nan(f64
)) {
7273 float_raise(float_flag_invalid
, fpst
);
7274 nan
= float64_maybe_silence_nan(f64
);
7276 if (fpst
->default_nan_mode
) {
7277 nan
= float64_default_nan
;
7280 } else if (float64_is_infinity(f64
)) {
7281 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
7282 } else if (float64_is_zero(f64
)) {
7283 float_raise(float_flag_divbyzero
, fpst
);
7284 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
7285 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
7286 /* Abs(value) < 2.0^-1024 */
7287 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
7288 if (round_to_inf(fpst
, f64_sbit
)) {
7289 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
7291 return float64_set_sign(float64_maxnorm
, float64_is_neg(f64
));
7293 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
7294 float_raise(float_flag_underflow
, fpst
);
7295 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
7298 r64
= call_recip_estimate(f64
, 2045, fpst
);
7299 r64_val
= float64_val(r64
);
7300 r64_exp
= extract64(r64_val
, 52, 11);
7301 r64_frac
= extract64(r64_val
, 0, 52);
7303 /* result = sign : result_exp<10:0> : fraction<51:0> */
7304 return make_float64(f64_sbit
|
7305 ((r64_exp
& 0x7ff) << 52) |
7309 /* The algorithm that must be used to calculate the estimate
7310 * is specified by the ARM ARM.
7312 static float64
recip_sqrt_estimate(float64 a
, float_status
*real_fp_status
)
7314 /* These calculations mustn't set any fp exception flags,
7315 * so we use a local copy of the fp_status.
7317 float_status dummy_status
= *real_fp_status
;
7318 float_status
*s
= &dummy_status
;
7322 if (float64_lt(a
, float64_half
, s
)) {
7323 /* range 0.25 <= a < 0.5 */
7325 /* a in units of 1/512 rounded down */
7326 /* q0 = (int)(a * 512.0); */
7327 q
= float64_mul(float64_512
, a
, s
);
7328 q_int
= float64_to_int64_round_to_zero(q
, s
);
7330 /* reciprocal root r */
7331 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
7332 q
= int64_to_float64(q_int
, s
);
7333 q
= float64_add(q
, float64_half
, s
);
7334 q
= float64_div(q
, float64_512
, s
);
7335 q
= float64_sqrt(q
, s
);
7336 q
= float64_div(float64_one
, q
, s
);
7338 /* range 0.5 <= a < 1.0 */
7340 /* a in units of 1/256 rounded down */
7341 /* q1 = (int)(a * 256.0); */
7342 q
= float64_mul(float64_256
, a
, s
);
7343 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
7345 /* reciprocal root r */
7346 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
7347 q
= int64_to_float64(q_int
, s
);
7348 q
= float64_add(q
, float64_half
, s
);
7349 q
= float64_div(q
, float64_256
, s
);
7350 q
= float64_sqrt(q
, s
);
7351 q
= float64_div(float64_one
, q
, s
);
7353 /* r in units of 1/256 rounded to nearest */
7354 /* s = (int)(256.0 * r + 0.5); */
7356 q
= float64_mul(q
, float64_256
,s
);
7357 q
= float64_add(q
, float64_half
, s
);
7358 q_int
= float64_to_int64_round_to_zero(q
, s
);
7360 /* return (double)s / 256.0;*/
7361 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
7364 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
7366 float_status
*s
= fpstp
;
7367 float32 f32
= float32_squash_input_denormal(input
, s
);
7368 uint32_t val
= float32_val(f32
);
7369 uint32_t f32_sbit
= 0x80000000 & val
;
7370 int32_t f32_exp
= extract32(val
, 23, 8);
7371 uint32_t f32_frac
= extract32(val
, 0, 23);
7377 if (float32_is_any_nan(f32
)) {
7379 if (float32_is_signaling_nan(f32
)) {
7380 float_raise(float_flag_invalid
, s
);
7381 nan
= float32_maybe_silence_nan(f32
);
7383 if (s
->default_nan_mode
) {
7384 nan
= float32_default_nan
;
7387 } else if (float32_is_zero(f32
)) {
7388 float_raise(float_flag_divbyzero
, s
);
7389 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
7390 } else if (float32_is_neg(f32
)) {
7391 float_raise(float_flag_invalid
, s
);
7392 return float32_default_nan
;
7393 } else if (float32_is_infinity(f32
)) {
7394 return float32_zero
;
7397 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
7398 * preserving the parity of the exponent. */
7400 f64_frac
= ((uint64_t) f32_frac
) << 29;
7402 while (extract64(f64_frac
, 51, 1) == 0) {
7403 f64_frac
= f64_frac
<< 1;
7404 f32_exp
= f32_exp
-1;
7406 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
7409 if (extract64(f32_exp
, 0, 1) == 0) {
7410 f64
= make_float64(((uint64_t) f32_sbit
) << 32
7414 f64
= make_float64(((uint64_t) f32_sbit
) << 32
7419 result_exp
= (380 - f32_exp
) / 2;
7421 f64
= recip_sqrt_estimate(f64
, s
);
7423 val64
= float64_val(f64
);
7425 val
= ((result_exp
& 0xff) << 23)
7426 | ((val64
>> 29) & 0x7fffff);
7427 return make_float32(val
);
7430 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
7432 float_status
*s
= fpstp
;
7433 float64 f64
= float64_squash_input_denormal(input
, s
);
7434 uint64_t val
= float64_val(f64
);
7435 uint64_t f64_sbit
= 0x8000000000000000ULL
& val
;
7436 int64_t f64_exp
= extract64(val
, 52, 11);
7437 uint64_t f64_frac
= extract64(val
, 0, 52);
7439 uint64_t result_frac
;
7441 if (float64_is_any_nan(f64
)) {
7443 if (float64_is_signaling_nan(f64
)) {
7444 float_raise(float_flag_invalid
, s
);
7445 nan
= float64_maybe_silence_nan(f64
);
7447 if (s
->default_nan_mode
) {
7448 nan
= float64_default_nan
;
7451 } else if (float64_is_zero(f64
)) {
7452 float_raise(float_flag_divbyzero
, s
);
7453 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
7454 } else if (float64_is_neg(f64
)) {
7455 float_raise(float_flag_invalid
, s
);
7456 return float64_default_nan
;
7457 } else if (float64_is_infinity(f64
)) {
7458 return float64_zero
;
7461 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
7462 * preserving the parity of the exponent. */
7465 while (extract64(f64_frac
, 51, 1) == 0) {
7466 f64_frac
= f64_frac
<< 1;
7467 f64_exp
= f64_exp
- 1;
7469 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
7472 if (extract64(f64_exp
, 0, 1) == 0) {
7473 f64
= make_float64(f64_sbit
7477 f64
= make_float64(f64_sbit
7482 result_exp
= (3068 - f64_exp
) / 2;
7484 f64
= recip_sqrt_estimate(f64
, s
);
7486 result_frac
= extract64(float64_val(f64
), 0, 52);
7488 return make_float64(f64_sbit
|
7489 ((result_exp
& 0x7ff) << 52) |
7493 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
7495 float_status
*s
= fpstp
;
7498 if ((a
& 0x80000000) == 0) {
7502 f64
= make_float64((0x3feULL
<< 52)
7503 | ((int64_t)(a
& 0x7fffffff) << 21));
7505 f64
= recip_estimate(f64
, s
);
7507 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
7510 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
7512 float_status
*fpst
= fpstp
;
7515 if ((a
& 0xc0000000) == 0) {
7519 if (a
& 0x80000000) {
7520 f64
= make_float64((0x3feULL
<< 52)
7521 | ((uint64_t)(a
& 0x7fffffff) << 21));
7522 } else { /* bits 31-30 == '01' */
7523 f64
= make_float64((0x3fdULL
<< 52)
7524 | ((uint64_t)(a
& 0x3fffffff) << 22));
7527 f64
= recip_sqrt_estimate(f64
, fpst
);
7529 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
7532 /* VFPv4 fused multiply-accumulate */
7533 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
7535 float_status
*fpst
= fpstp
;
7536 return float32_muladd(a
, b
, c
, 0, fpst
);
7539 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
7541 float_status
*fpst
= fpstp
;
7542 return float64_muladd(a
, b
, c
, 0, fpst
);
7545 /* ARMv8 round to integral */
7546 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
7548 return float32_round_to_int(x
, fp_status
);
7551 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
7553 return float64_round_to_int(x
, fp_status
);
7556 float32
HELPER(rints
)(float32 x
, void *fp_status
)
7558 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
7561 ret
= float32_round_to_int(x
, fp_status
);
7563 /* Suppress any inexact exceptions the conversion produced */
7564 if (!(old_flags
& float_flag_inexact
)) {
7565 new_flags
= get_float_exception_flags(fp_status
);
7566 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
7572 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
7574 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
7577 ret
= float64_round_to_int(x
, fp_status
);
7579 new_flags
= get_float_exception_flags(fp_status
);
7581 /* Suppress any inexact exceptions the conversion produced */
7582 if (!(old_flags
& float_flag_inexact
)) {
7583 new_flags
= get_float_exception_flags(fp_status
);
7584 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
7590 /* Convert ARM rounding mode to softfloat */
7591 int arm_rmode_to_sf(int rmode
)
7594 case FPROUNDING_TIEAWAY
:
7595 rmode
= float_round_ties_away
;
7597 case FPROUNDING_ODD
:
7598 /* FIXME: add support for TIEAWAY and ODD */
7599 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
7601 case FPROUNDING_TIEEVEN
:
7603 rmode
= float_round_nearest_even
;
7605 case FPROUNDING_POSINF
:
7606 rmode
= float_round_up
;
7608 case FPROUNDING_NEGINF
:
7609 rmode
= float_round_down
;
7611 case FPROUNDING_ZERO
:
7612 rmode
= float_round_to_zero
;
7619 * The upper bytes of val (above the number specified by 'bytes') must have
7620 * been zeroed out by the caller.
7622 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
7628 /* zlib crc32 converts the accumulator and output to one's complement. */
7629 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
7632 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
7638 /* Linux crc32c converts the output to one's complement. */
7639 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;