target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #define TARGET_LONG_BITS 32
  23
  24 #define ELF_MACHINE     EM_ARM
  25
  26 #define CPUState struct CPUARMState
  27
  28 #include "config.h"
  29 #include "qemu-common.h"
  30 #include "cpu-defs.h"
  31
  32 #include "softfloat.h"
  33
  34 #define TARGET_HAS_ICE 1
  35
  36 #define EXCP_UDEF            1   /* undefined instruction */
  37 #define EXCP_SWI             2   /* software interrupt */
  38 #define EXCP_PREFETCH_ABORT  3
  39 #define EXCP_DATA_ABORT      4
  40 #define EXCP_IRQ             5
  41 #define EXCP_FIQ             6
  42 #define EXCP_BKPT            7
  43 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  44 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  45 #define EXCP_STREX          10
  46
  47 #define ARMV7M_EXCP_RESET   1
  48 #define ARMV7M_EXCP_NMI     2
  49 #define ARMV7M_EXCP_HARD    3
  50 #define ARMV7M_EXCP_MEM     4
  51 #define ARMV7M_EXCP_BUS     5
  52 #define ARMV7M_EXCP_USAGE   6
  53 #define ARMV7M_EXCP_SVC     11
  54 #define ARMV7M_EXCP_DEBUG   12
  55 #define ARMV7M_EXCP_PENDSV  14
  56 #define ARMV7M_EXCP_SYSTICK 15
  57
  58 /* ARM-specific interrupt pending bits.  */
  59 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  60
  61
  62 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  63                             int srcreg, int operand, uint32_t value);
  64 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  65                                int dstreg, int operand);
  66
  67 struct arm_boot_info;
  68
  69 #define NB_MMU_MODES 2
  70
  71 /* We currently assume float and double are IEEE single and double
  72    precision respectively.
  73    Doing runtime conversions is tricky because VFP registers may contain
  74    integer values (eg. as the result of a FTOSI instruction).
  75    s<2n> maps to the least significant half of d<n>
  76    s<2n+1> maps to the most significant half of d<n>
  77  */
  78
  79 typedef struct CPUARMState {
  80     /* Regs for current mode.  */
  81     uint32_t regs[16];
  82     /* Frequently accessed CPSR bits are stored separately for efficiently.
  83        This contains all the other bits.  Use cpsr_{read,write} to access
  84        the whole CPSR.  */
  85     uint32_t uncached_cpsr;
  86     uint32_t spsr;
  87
  88     /* Banked registers.  */
  89     uint32_t banked_spsr[6];
  90     uint32_t banked_r13[6];
  91     uint32_t banked_r14[6];
  92
  93     /* These hold r8-r12.  */
  94     uint32_t usr_regs[5];
  95     uint32_t fiq_regs[5];
  96
  97     /* cpsr flag cache for faster execution */
  98     uint32_t CF; /* 0 or 1 */
  99     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 100     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 101     uint32_t ZF; /* Z set if zero.  */
 102     uint32_t QF; /* 0 or 1 */
 103     uint32_t GE; /* cpsr[19:16] */
 104     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 105     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 106
 107     /* System control coprocessor (cp15) */
 108     struct {
 109         uint32_t c0_cpuid;
 110         uint32_t c0_cachetype;
 111         uint32_t c0_ccsid[16]; /* Cache size.  */
 112         uint32_t c0_clid; /* Cache level.  */
 113         uint32_t c0_cssel; /* Cache size selection.  */
 114         uint32_t c0_c1[8]; /* Feature registers.  */
 115         uint32_t c0_c2[8]; /* Instruction set registers.  */
 116         uint32_t c1_sys; /* System control register.  */
 117         uint32_t c1_coproc; /* Coprocessor access register.  */
 118         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 119         uint32_t c2_base0; /* MMU translation table base 0.  */
 120         uint32_t c2_base1; /* MMU translation table base 1.  */
 121         uint32_t c2_control; /* MMU translation table base control.  */
 122         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 123         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 124         uint32_t c2_data; /* MPU data cachable bits.  */
 125         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 126         uint32_t c3; /* MMU domain access control register
 127                         MPU write buffer control.  */
 128         uint32_t c5_insn; /* Fault status registers.  */
 129         uint32_t c5_data;
 130         uint32_t c6_region[8]; /* MPU base/size registers.  */
 131         uint32_t c6_insn; /* Fault address registers.  */
 132         uint32_t c6_data;
 133         uint32_t c7_par;  /* Translation result. */
 134         uint32_t c9_insn; /* Cache lockdown registers.  */
 135         uint32_t c9_data;
 136         uint32_t c9_pmcr; /* performance monitor control register */
 137         uint32_t c9_pmcnten; /* perf monitor counter enables */
 138         uint32_t c9_pmovsr; /* perf monitor overflow status */
 139         uint32_t c9_pmxevtyper; /* perf monitor event type */
 140         uint32_t c9_pmuserenr; /* perf monitor user enable */
 141         uint32_t c9_pminten; /* perf monitor interrupt enables */
 142         uint32_t c13_fcse; /* FCSE PID.  */
 143         uint32_t c13_context; /* Context ID.  */
 144         uint32_t c13_tls1; /* User RW Thread register.  */
 145         uint32_t c13_tls2; /* User RO Thread register.  */
 146         uint32_t c13_tls3; /* Privileged Thread register.  */
 147         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 148         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 149         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 150         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 151         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 152     } cp15;
 153
 154     struct {
 155         uint32_t other_sp;
 156         uint32_t vecbase;
 157         uint32_t basepri;
 158         uint32_t control;
 159         int current_sp;
 160         int exception;
 161         int pending_exception;
 162     } v7m;
 163
 164     /* Thumb-2 EE state.  */
 165     uint32_t teecr;
 166     uint32_t teehbr;
 167
 168     /* Internal CPU feature flags.  */
 169     uint32_t features;
 170
 171     /* VFP coprocessor state.  */
 172     struct {
 173         float64 regs[32];
 174
 175         uint32_t xregs[16];
 176         /* We store these fpcsr fields separately for convenience.  */
 177         int vec_len;
 178         int vec_stride;
 179
 180         /* scratch space when Tn are not sufficient.  */
 181         uint32_t scratch[8];
 182
 183         /* fp_status is the "normal" fp status. standard_fp_status retains
 184          * values corresponding to the ARM "Standard FPSCR Value", ie
 185          * default-NaN, flush-to-zero, round-to-nearest and is used by
 186          * any operations (generally Neon) which the architecture defines
 187          * as controlled by the standard FPSCR value rather than the FPSCR.
 188          *
 189          * To avoid having to transfer exception bits around, we simply
 190          * say that the FPSCR cumulative exception flags are the logical
 191          * OR of the flags in the two fp statuses. This relies on the
 192          * only thing which needs to read the exception flags being
 193          * an explicit FPSCR read.
 194          */
 195         float_status fp_status;
 196         float_status standard_fp_status;
 197     } vfp;
 198     uint32_t exclusive_addr;
 199     uint32_t exclusive_val;
 200     uint32_t exclusive_high;
 201 #if defined(CONFIG_USER_ONLY)
 202     uint32_t exclusive_test;
 203     uint32_t exclusive_info;
 204 #endif
 205
 206     /* iwMMXt coprocessor state.  */
 207     struct {
 208         uint64_t regs[16];
 209         uint64_t val;
 210
 211         uint32_t cregs[16];
 212     } iwmmxt;
 213
 214 #if defined(CONFIG_USER_ONLY)
 215     /* For usermode syscall translation.  */
 216     int eabi;
 217 #endif
 218
 219     CPU_COMMON
 220
 221     /* These fields after the common ones so they are preserved on reset.  */
 222
 223     /* Coprocessor IO used by peripherals */
 224     struct {
 225         ARMReadCPFunc *cp_read;
 226         ARMWriteCPFunc *cp_write;
 227         void *opaque;
 228     } cp[15];
 229     void *nvic;
 230     const struct arm_boot_info *boot_info;
 231 } CPUARMState;
 232
 233 CPUARMState *cpu_arm_init(const char *cpu_model);
 234 void arm_translate_init(void);
 235 int cpu_arm_exec(CPUARMState *s);
 236 void cpu_arm_close(CPUARMState *s);
 237 void do_interrupt(CPUARMState *);
 238 void switch_mode(CPUARMState *, int);
 239 uint32_t do_arm_semihosting(CPUARMState *env);
 240
 241 /* you can call this signal handler from your SIGBUS and SIGSEGV
 242    signal handlers to inform the virtual CPU of exceptions. non zero
 243    is returned if the signal was handled by the virtual CPU.  */
 244 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 245                            void *puc);
 246 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 247                               int mmu_idx);
 248 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 249
 250 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 251 {
 252   env->cp15.c13_tls2 = newtls;
 253 }
 254
 255 #define CPSR_M (0x1f)
 256 #define CPSR_T (1 << 5)
 257 #define CPSR_F (1 << 6)
 258 #define CPSR_I (1 << 7)
 259 #define CPSR_A (1 << 8)
 260 #define CPSR_E (1 << 9)
 261 #define CPSR_IT_2_7 (0xfc00)
 262 #define CPSR_GE (0xf << 16)
 263 #define CPSR_RESERVED (0xf << 20)
 264 #define CPSR_J (1 << 24)
 265 #define CPSR_IT_0_1 (3 << 25)
 266 #define CPSR_Q (1 << 27)
 267 #define CPSR_V (1 << 28)
 268 #define CPSR_C (1 << 29)
 269 #define CPSR_Z (1 << 30)
 270 #define CPSR_N (1 << 31)
 271 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 272
 273 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 274 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 275 /* Bits writable in user mode.  */
 276 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 277 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 278 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 279
 280 /* Return the current CPSR value.  */
 281 uint32_t cpsr_read(CPUARMState *env);
 282 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 283 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 284
 285 /* Return the current xPSR value.  */
 286 static inline uint32_t xpsr_read(CPUARMState *env)
 287 {
 288     int ZF;
 289     ZF = (env->ZF == 0);
 290     return (env->NF & 0x80000000) | (ZF << 30)
 291         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 292         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 293         | ((env->condexec_bits & 0xfc) << 8)
 294         | env->v7m.exception;
 295 }
 296
 297 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 298 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 299 {
 300     if (mask & CPSR_NZCV) {
 301         env->ZF = (~val) & CPSR_Z;
 302         env->NF = val;
 303         env->CF = (val >> 29) & 1;
 304         env->VF = (val << 3) & 0x80000000;
 305     }
 306     if (mask & CPSR_Q)
 307         env->QF = ((val & CPSR_Q) != 0);
 308     if (mask & (1 << 24))
 309         env->thumb = ((val & (1 << 24)) != 0);
 310     if (mask & CPSR_IT_0_1) {
 311         env->condexec_bits &= ~3;
 312         env->condexec_bits |= (val >> 25) & 3;
 313     }
 314     if (mask & CPSR_IT_2_7) {
 315         env->condexec_bits &= 3;
 316         env->condexec_bits |= (val >> 8) & 0xfc;
 317     }
 318     if (mask & 0x1ff) {
 319         env->v7m.exception = val & 0x1ff;
 320     }
 321 }
 322
 323 /* Return the current FPSCR value.  */
 324 uint32_t vfp_get_fpscr(CPUARMState *env);
 325 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 326
 327 enum arm_cpu_mode {
 328   ARM_CPU_MODE_USR = 0x10,
 329   ARM_CPU_MODE_FIQ = 0x11,
 330   ARM_CPU_MODE_IRQ = 0x12,
 331   ARM_CPU_MODE_SVC = 0x13,
 332   ARM_CPU_MODE_ABT = 0x17,
 333   ARM_CPU_MODE_UND = 0x1b,
 334   ARM_CPU_MODE_SYS = 0x1f
 335 };
 336
 337 /* VFP system registers.  */
 338 #define ARM_VFP_FPSID   0
 339 #define ARM_VFP_FPSCR   1
 340 #define ARM_VFP_MVFR1   6
 341 #define ARM_VFP_MVFR0   7
 342 #define ARM_VFP_FPEXC   8
 343 #define ARM_VFP_FPINST  9
 344 #define ARM_VFP_FPINST2 10
 345
 346 /* iwMMXt coprocessor control registers.  */
 347 #define ARM_IWMMXT_wCID         0
 348 #define ARM_IWMMXT_wCon         1
 349 #define ARM_IWMMXT_wCSSF        2
 350 #define ARM_IWMMXT_wCASF        3
 351 #define ARM_IWMMXT_wCGR0        8
 352 #define ARM_IWMMXT_wCGR1        9
 353 #define ARM_IWMMXT_wCGR2        10
 354 #define ARM_IWMMXT_wCGR3        11
 355
 356 enum arm_features {
 357     ARM_FEATURE_VFP,
 358     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 359     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 360     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 361     ARM_FEATURE_V6,
 362     ARM_FEATURE_V6K,
 363     ARM_FEATURE_V7,
 364     ARM_FEATURE_THUMB2,
 365     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 366     ARM_FEATURE_VFP3,
 367     ARM_FEATURE_VFP_FP16,
 368     ARM_FEATURE_NEON,
 369     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 370     ARM_FEATURE_M, /* Microcontroller profile.  */
 371     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 372     ARM_FEATURE_THUMB2EE,
 373     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 374     ARM_FEATURE_V4T,
 375     ARM_FEATURE_V5,
 376     ARM_FEATURE_STRONGARM,
 377     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 378     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 379     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 380 };
 381
 382 static inline int arm_feature(CPUARMState *env, int feature)
 383 {
 384     return (env->features & (1u << feature)) != 0;
 385 }
 386
 387 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 388
 389 /* Interface between CPU and Interrupt controller.  */
 390 void armv7m_nvic_set_pending(void *opaque, int irq);
 391 int armv7m_nvic_acknowledge_irq(void *opaque);
 392 void armv7m_nvic_complete_irq(void *opaque, int irq);
 393
 394 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 395                        ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
 396                        void *opaque);
 397
 398 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 399    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 400    conventional cores (ie. Application or Realtime profile).  */
 401
 402 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 403 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
 404
 405 #define ARM_CPUID_ARM1026     0x4106a262
 406 #define ARM_CPUID_ARM926      0x41069265
 407 #define ARM_CPUID_ARM946      0x41059461
 408 #define ARM_CPUID_TI915T      0x54029152
 409 #define ARM_CPUID_TI925T      0x54029252
 410 #define ARM_CPUID_SA1100      0x4401A11B
 411 #define ARM_CPUID_SA1110      0x6901B119
 412 #define ARM_CPUID_PXA250      0x69052100
 413 #define ARM_CPUID_PXA255      0x69052d00
 414 #define ARM_CPUID_PXA260      0x69052903
 415 #define ARM_CPUID_PXA261      0x69052d05
 416 #define ARM_CPUID_PXA262      0x69052d06
 417 #define ARM_CPUID_PXA270      0x69054110
 418 #define ARM_CPUID_PXA270_A0   0x69054110
 419 #define ARM_CPUID_PXA270_A1   0x69054111
 420 #define ARM_CPUID_PXA270_B0   0x69054112
 421 #define ARM_CPUID_PXA270_B1   0x69054113
 422 #define ARM_CPUID_PXA270_C0   0x69054114
 423 #define ARM_CPUID_PXA270_C5   0x69054117
 424 #define ARM_CPUID_ARM1136     0x4117b363
 425 #define ARM_CPUID_ARM1136_R2  0x4107b362
 426 #define ARM_CPUID_ARM1176     0x410fb767
 427 #define ARM_CPUID_ARM11MPCORE 0x410fb022
 428 #define ARM_CPUID_CORTEXA8    0x410fc080
 429 #define ARM_CPUID_CORTEXA9    0x410fc090
 430 #define ARM_CPUID_CORTEXM3    0x410fc231
 431 #define ARM_CPUID_ANY         0xffffffff
 432
 433 #if defined(CONFIG_USER_ONLY)
 434 #define TARGET_PAGE_BITS 12
 435 #else
 436 /* The ARM MMU allows 1k pages.  */
 437 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 438    architecture revisions.  Maybe a configure option to disable them.  */
 439 #define TARGET_PAGE_BITS 10
 440 #endif
 441
 442 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 443 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 444
 445 #define cpu_init cpu_arm_init
 446 #define cpu_exec cpu_arm_exec
 447 #define cpu_gen_code cpu_arm_gen_code
 448 #define cpu_signal_handler cpu_arm_signal_handler
 449 #define cpu_list arm_cpu_list
 450
 451 #define CPU_SAVE_VERSION 4
 452
 453 /* MMU modes definitions */
 454 #define MMU_MODE0_SUFFIX _kernel
 455 #define MMU_MODE1_SUFFIX _user
 456 #define MMU_USER_IDX 1
 457 static inline int cpu_mmu_index (CPUState *env)
 458 {
 459     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 460 }
 461
 462 #if defined(CONFIG_USER_ONLY)
 463 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 464 {
 465     if (newsp)
 466         env->regs[13] = newsp;
 467     env->regs[0] = 0;
 468 }
 469 #endif
 470
 471 #include "cpu-all.h"
 472
 473 /* Bit usage in the TB flags field: */
 474 #define ARM_TBFLAG_THUMB_SHIFT      0
 475 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 476 #define ARM_TBFLAG_VECLEN_SHIFT     1
 477 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 478 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 479 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 480 #define ARM_TBFLAG_PRIV_SHIFT       6
 481 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 482 #define ARM_TBFLAG_VFPEN_SHIFT      7
 483 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 484 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 485 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 486 /* Bits 31..16 are currently unused. */
 487
 488 /* some convenience accessor macros */
 489 #define ARM_TBFLAG_THUMB(F) \
 490     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 491 #define ARM_TBFLAG_VECLEN(F) \
 492     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 493 #define ARM_TBFLAG_VECSTRIDE(F) \
 494     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 495 #define ARM_TBFLAG_PRIV(F) \
 496     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 497 #define ARM_TBFLAG_VFPEN(F) \
 498     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 499 #define ARM_TBFLAG_CONDEXEC(F) \
 500     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 501
 502 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 503                                         target_ulong *cs_base, int *flags)
 504 {
 505     int privmode;
 506     *pc = env->regs[15];
 507     *cs_base = 0;
 508     *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 509         | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 510         | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 511         | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
 512     if (arm_feature(env, ARM_FEATURE_M)) {
 513         privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 514     } else {
 515         privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 516     }
 517     if (privmode) {
 518         *flags |= ARM_TBFLAG_PRIV_MASK;
 519     }
 520     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 521         *flags |= ARM_TBFLAG_VFPEN_MASK;
 522     }
 523 }
 524
 525 static inline bool cpu_has_work(CPUState *env)
 526 {
 527     return env->interrupt_request &
 528         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 529 }
 530
 531 #include "exec-all.h"
 532
 533 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 534 {
 535     env->regs[15] = tb->pc;
 536 }
 537
 538 #endif