hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "pc.h"
  27 #include "fdc.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "isa.h"
  31 #include "pci.h"
  32 #include "prep_pci.h"
  33 #include "usb-ohci.h"
  34 #include "ppc.h"
  35 #include "boards.h"
  36 #include "qemu-log.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "mc146818rtc.h"
  40 #include "blockdev.h"
  41 #include "exec-memory.h"
  42
  43 //#define HARD_DEBUG_PPC_IO
  44 //#define DEBUG_PPC_IO
  45
  46 /* SMP is not enabled, for now */
  47 #define MAX_CPUS 1
  48
  49 #define MAX_IDE_BUS 2
  50
  51 #define BIOS_SIZE (1024 * 1024)
  52 #define BIOS_FILENAME "ppc_rom.bin"
  53 #define KERNEL_LOAD_ADDR 0x01000000
  54 #define INITRD_LOAD_ADDR 0x01800000
  55
  56 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  57 #define DEBUG_PPC_IO
  58 #endif
  59
  60 #if defined (HARD_DEBUG_PPC_IO)
  61 #define PPC_IO_DPRINTF(fmt, ...)                         \
  62 do {                                                     \
  63     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  64         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  65     } else {                                             \
  66         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  67     }                                                    \
  68 } while (0)
  69 #elif defined (DEBUG_PPC_IO)
  70 #define PPC_IO_DPRINTF(fmt, ...) \
  71 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
  72 #else
  73 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  74 #endif
  75
  76 /* Constants for devices init */
  77 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  78 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  79 static const int ide_irq[2] = { 13, 13 };
  80
  81 #define NE2000_NB_MAX 6
  82
  83 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  84 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  85
  86 //static ISADevice *pit;
  87
  88 /* ISA IO ports bridge */
  89 #define PPC_IO_BASE 0x80000000
  90
  91 #if 0
  92 /* Speaker port 0x61 */
  93 static int speaker_data_on;
  94 static int dummy_refresh_clock;
  95 #endif
  96
  97 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
  98 {
  99 #if 0
 100     speaker_data_on = (val >> 1) & 1;
 101     pit_set_gate(pit, 2, val & 1);
 102 #endif
 103 }
 104
 105 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
 106 {
 107 #if 0
 108     int out;
 109     out = pit_get_out(pit, 2, qemu_get_clock_ns(vm_clock));
 110     dummy_refresh_clock ^= 1;
 111     return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
 112         (dummy_refresh_clock << 4);
 113 #endif
 114     return 0;
 115 }
 116
 117 /* PCI intack register */
 118 /* Read-only register (?) */
 119 static void PPC_intack_write (void *opaque, target_phys_addr_t addr,
 120                               uint64_t value, unsigned size)
 121 {
 122 #if 0
 123     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx64 "\n", __func__, addr,
 124            value);
 125 #endif
 126 }
 127
 128 static uint64_t PPC_intack_read(void *opaque, target_phys_addr_t addr,
 129                                 unsigned size)
 130 {
 131     uint32_t retval = 0;
 132
 133     if ((addr & 0xf) == 0)
 134         retval = pic_read_irq(isa_pic);
 135 #if 0
 136     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 137            retval);
 138 #endif
 139
 140     return retval;
 141 }
 142
 143 static const MemoryRegionOps PPC_intack_ops = {
 144     .read = PPC_intack_read,
 145     .write = PPC_intack_write,
 146     .endianness = DEVICE_LITTLE_ENDIAN,
 147 };
 148
 149 /* PowerPC control and status registers */
 150 #if 0 // Not used
 151 static struct {
 152     /* IDs */
 153     uint32_t veni_devi;
 154     uint32_t revi;
 155     /* Control and status */
 156     uint32_t gcsr;
 157     uint32_t xcfr;
 158     uint32_t ct32;
 159     uint32_t mcsr;
 160     /* General purpose registers */
 161     uint32_t gprg[6];
 162     /* Exceptions */
 163     uint32_t feen;
 164     uint32_t fest;
 165     uint32_t fema;
 166     uint32_t fecl;
 167     uint32_t eeen;
 168     uint32_t eest;
 169     uint32_t eecl;
 170     uint32_t eeint;
 171     uint32_t eemck0;
 172     uint32_t eemck1;
 173     /* Error diagnostic */
 174 } XCSR;
 175
 176 static void PPC_XCSR_writeb (void *opaque,
 177                              target_phys_addr_t addr, uint32_t value)
 178 {
 179     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 180            value);
 181 }
 182
 183 static void PPC_XCSR_writew (void *opaque,
 184                              target_phys_addr_t addr, uint32_t value)
 185 {
 186     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 187            value);
 188 }
 189
 190 static void PPC_XCSR_writel (void *opaque,
 191                              target_phys_addr_t addr, uint32_t value)
 192 {
 193     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 194            value);
 195 }
 196
 197 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 198 {
 199     uint32_t retval = 0;
 200
 201     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 202            retval);
 203
 204     return retval;
 205 }
 206
 207 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 208 {
 209     uint32_t retval = 0;
 210
 211     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 212            retval);
 213
 214     return retval;
 215 }
 216
 217 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 218 {
 219     uint32_t retval = 0;
 220
 221     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 222            retval);
 223
 224     return retval;
 225 }
 226
 227 static const MemoryRegionOps PPC_XCSR_ops = {
 228     .old_mmio = {
 229         .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
 230         .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
 231     },
 232     .endianness = DEVICE_LITTLE_ENDIAN,
 233 };
 234
 235 #endif
 236
 237 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 238 typedef struct sysctrl_t {
 239     qemu_irq reset_irq;
 240     M48t59State *nvram;
 241     uint8_t state;
 242     uint8_t syscontrol;
 243     uint8_t fake_io[2];
 244     int contiguous_map;
 245     int endian;
 246 } sysctrl_t;
 247
 248 enum {
 249     STATE_HARDFILE = 0x01,
 250 };
 251
 252 static sysctrl_t *sysctrl;
 253
 254 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 255 {
 256     sysctrl_t *sysctrl = opaque;
 257
 258     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 259                    val);
 260     sysctrl->fake_io[addr - 0x0398] = val;
 261 }
 262
 263 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 264 {
 265     sysctrl_t *sysctrl = opaque;
 266
 267     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 268                    sysctrl->fake_io[addr - 0x0398]);
 269     return sysctrl->fake_io[addr - 0x0398];
 270 }
 271
 272 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 273 {
 274     sysctrl_t *sysctrl = opaque;
 275
 276     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 277                    addr - PPC_IO_BASE, val);
 278     switch (addr) {
 279     case 0x0092:
 280         /* Special port 92 */
 281         /* Check soft reset asked */
 282         if (val & 0x01) {
 283             qemu_irq_raise(sysctrl->reset_irq);
 284         } else {
 285             qemu_irq_lower(sysctrl->reset_irq);
 286         }
 287         /* Check LE mode */
 288         if (val & 0x02) {
 289             sysctrl->endian = 1;
 290         } else {
 291             sysctrl->endian = 0;
 292         }
 293         break;
 294     case 0x0800:
 295         /* Motorola CPU configuration register : read-only */
 296         break;
 297     case 0x0802:
 298         /* Motorola base module feature register : read-only */
 299         break;
 300     case 0x0803:
 301         /* Motorola base module status register : read-only */
 302         break;
 303     case 0x0808:
 304         /* Hardfile light register */
 305         if (val & 1)
 306             sysctrl->state |= STATE_HARDFILE;
 307         else
 308             sysctrl->state &= ~STATE_HARDFILE;
 309         break;
 310     case 0x0810:
 311         /* Password protect 1 register */
 312         if (sysctrl->nvram != NULL)
 313             m48t59_toggle_lock(sysctrl->nvram, 1);
 314         break;
 315     case 0x0812:
 316         /* Password protect 2 register */
 317         if (sysctrl->nvram != NULL)
 318             m48t59_toggle_lock(sysctrl->nvram, 2);
 319         break;
 320     case 0x0814:
 321         /* L2 invalidate register */
 322         //        tlb_flush(first_cpu, 1);
 323         break;
 324     case 0x081C:
 325         /* system control register */
 326         sysctrl->syscontrol = val & 0x0F;
 327         break;
 328     case 0x0850:
 329         /* I/O map type register */
 330         sysctrl->contiguous_map = val & 0x01;
 331         break;
 332     default:
 333         printf("ERROR: unaffected IO port write: %04" PRIx32
 334                " => %02" PRIx32"\n", addr, val);
 335         break;
 336     }
 337 }
 338
 339 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 340 {
 341     sysctrl_t *sysctrl = opaque;
 342     uint32_t retval = 0xFF;
 343
 344     switch (addr) {
 345     case 0x0092:
 346         /* Special port 92 */
 347         retval = 0x00;
 348         break;
 349     case 0x0800:
 350         /* Motorola CPU configuration register */
 351         retval = 0xEF; /* MPC750 */
 352         break;
 353     case 0x0802:
 354         /* Motorola Base module feature register */
 355         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 356         break;
 357     case 0x0803:
 358         /* Motorola base module status register */
 359         retval = 0xE0; /* Standard MPC750 */
 360         break;
 361     case 0x080C:
 362         /* Equipment present register:
 363          *  no L2 cache
 364          *  no upgrade processor
 365          *  no cards in PCI slots
 366          *  SCSI fuse is bad
 367          */
 368         retval = 0x3C;
 369         break;
 370     case 0x0810:
 371         /* Motorola base module extended feature register */
 372         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 373         break;
 374     case 0x0814:
 375         /* L2 invalidate: don't care */
 376         break;
 377     case 0x0818:
 378         /* Keylock */
 379         retval = 0x00;
 380         break;
 381     case 0x081C:
 382         /* system control register
 383          * 7 - 6 / 1 - 0: L2 cache enable
 384          */
 385         retval = sysctrl->syscontrol;
 386         break;
 387     case 0x0823:
 388         /* */
 389         retval = 0x03; /* no L2 cache */
 390         break;
 391     case 0x0850:
 392         /* I/O map type register */
 393         retval = sysctrl->contiguous_map;
 394         break;
 395     default:
 396         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 397         break;
 398     }
 399     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 400                    addr - PPC_IO_BASE, retval);
 401
 402     return retval;
 403 }
 404
 405 static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
 406                                                  target_phys_addr_t addr)
 407 {
 408     if (sysctrl->contiguous_map == 0) {
 409         /* 64 KB contiguous space for IOs */
 410         addr &= 0xFFFF;
 411     } else {
 412         /* 8 MB non-contiguous space for IOs */
 413         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 414     }
 415
 416     return addr;
 417 }
 418
 419 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 420                                 uint32_t value)
 421 {
 422     sysctrl_t *sysctrl = opaque;
 423
 424     addr = prep_IO_address(sysctrl, addr);
 425     cpu_outb(addr, value);
 426 }
 427
 428 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 429 {
 430     sysctrl_t *sysctrl = opaque;
 431     uint32_t ret;
 432
 433     addr = prep_IO_address(sysctrl, addr);
 434     ret = cpu_inb(addr);
 435
 436     return ret;
 437 }
 438
 439 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 440                                 uint32_t value)
 441 {
 442     sysctrl_t *sysctrl = opaque;
 443
 444     addr = prep_IO_address(sysctrl, addr);
 445     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 446     cpu_outw(addr, value);
 447 }
 448
 449 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 450 {
 451     sysctrl_t *sysctrl = opaque;
 452     uint32_t ret;
 453
 454     addr = prep_IO_address(sysctrl, addr);
 455     ret = cpu_inw(addr);
 456     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 457
 458     return ret;
 459 }
 460
 461 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 462                                 uint32_t value)
 463 {
 464     sysctrl_t *sysctrl = opaque;
 465
 466     addr = prep_IO_address(sysctrl, addr);
 467     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 468     cpu_outl(addr, value);
 469 }
 470
 471 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 472 {
 473     sysctrl_t *sysctrl = opaque;
 474     uint32_t ret;
 475
 476     addr = prep_IO_address(sysctrl, addr);
 477     ret = cpu_inl(addr);
 478     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 479
 480     return ret;
 481 }
 482
 483 static const MemoryRegionOps PPC_prep_io_ops = {
 484     .old_mmio = {
 485         .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },
 486         .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },
 487     },
 488     .endianness = DEVICE_LITTLE_ENDIAN,
 489 };
 490
 491 #define NVRAM_SIZE        0x2000
 492
 493 static void cpu_request_exit(void *opaque, int irq, int level)
 494 {
 495     CPUState *env = cpu_single_env;
 496
 497     if (env && level) {
 498         cpu_exit(env);
 499     }
 500 }
 501
 502 /* PowerPC PREP hardware initialisation */
 503 static void ppc_prep_init (ram_addr_t ram_size,
 504                            const char *boot_device,
 505                            const char *kernel_filename,
 506                            const char *kernel_cmdline,
 507                            const char *initrd_filename,
 508                            const char *cpu_model)
 509 {
 510     MemoryRegion *sysmem = get_system_memory();
 511     CPUState *env = NULL;
 512     char *filename;
 513     nvram_t nvram;
 514     M48t59State *m48t59;
 515     MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
 516     MemoryRegion *intack = g_new(MemoryRegion, 1);
 517 #if 0
 518     MemoryRegion *xcsr = g_new(MemoryRegion, 1);
 519 #endif
 520     int linux_boot, i, nb_nics1, bios_size;
 521     MemoryRegion *ram = g_new(MemoryRegion, 1);
 522     MemoryRegion *bios = g_new(MemoryRegion, 1);
 523     uint32_t kernel_base, initrd_base;
 524     long kernel_size, initrd_size;
 525     PCIBus *pci_bus;
 526     ISABus *isa_bus;
 527     qemu_irq *i8259;
 528     qemu_irq *cpu_exit_irq;
 529     int ppc_boot_device;
 530     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 531     DriveInfo *fd[MAX_FD];
 532
 533     sysctrl = g_malloc0(sizeof(sysctrl_t));
 534
 535     linux_boot = (kernel_filename != NULL);
 536
 537     /* init CPUs */
 538     if (cpu_model == NULL)
 539         cpu_model = "602";
 540     for (i = 0; i < smp_cpus; i++) {
 541         env = cpu_init(cpu_model);
 542         if (!env) {
 543             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 544             exit(1);
 545         }
 546         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 547             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 548             cpu_ppc_tb_init(env, 7812500UL);
 549         } else {
 550             /* Set time-base frequency to 100 Mhz */
 551             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 552         }
 553         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 554     }
 555
 556     /* allocate RAM */
 557     memory_region_init_ram(ram, NULL, "ppc_prep.ram", ram_size);
 558     memory_region_add_subregion(sysmem, 0, ram);
 559
 560     /* allocate and load BIOS */
 561     memory_region_init_ram(bios, NULL, "ppc_prep.bios", BIOS_SIZE);
 562     if (bios_name == NULL)
 563         bios_name = BIOS_FILENAME;
 564     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 565     if (filename) {
 566         bios_size = get_image_size(filename);
 567     } else {
 568         bios_size = -1;
 569     }
 570     if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 571         target_phys_addr_t bios_addr;
 572         bios_size = (bios_size + 0xfff) & ~0xfff;
 573         bios_addr = (uint32_t)(-bios_size);
 574         memory_region_set_readonly(bios, true);
 575         memory_region_add_subregion(sysmem, bios_addr, bios);
 576         bios_size = load_image_targphys(filename, bios_addr, bios_size);
 577     }
 578     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 579         hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
 580     }
 581     if (filename) {
 582         g_free(filename);
 583     }
 584
 585     if (linux_boot) {
 586         kernel_base = KERNEL_LOAD_ADDR;
 587         /* now we can load the kernel */
 588         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 589                                           ram_size - kernel_base);
 590         if (kernel_size < 0) {
 591             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 592             exit(1);
 593         }
 594         /* load initrd */
 595         if (initrd_filename) {
 596             initrd_base = INITRD_LOAD_ADDR;
 597             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 598                                               ram_size - initrd_base);
 599             if (initrd_size < 0) {
 600                 hw_error("qemu: could not load initial ram disk '%s'\n",
 601                           initrd_filename);
 602             }
 603         } else {
 604             initrd_base = 0;
 605             initrd_size = 0;
 606         }
 607         ppc_boot_device = 'm';
 608     } else {
 609         kernel_base = 0;
 610         kernel_size = 0;
 611         initrd_base = 0;
 612         initrd_size = 0;
 613         ppc_boot_device = '\0';
 614         /* For now, OHW cannot boot from the network. */
 615         for (i = 0; boot_device[i] != '\0'; i++) {
 616             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 617                 ppc_boot_device = boot_device[i];
 618                 break;
 619             }
 620         }
 621         if (ppc_boot_device == '\0') {
 622             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 623             exit(1);
 624         }
 625     }
 626
 627     isa_mem_base = 0xc0000000;
 628     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 629         hw_error("Only 6xx bus is supported on PREP machine\n");
 630     }
 631     /* Hmm, prep has no pci-isa bridge ??? */
 632     isa_bus = isa_bus_new(NULL, get_system_io());
 633     i8259 = i8259_init(isa_bus, first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 634     pci_bus = pci_prep_init(i8259, get_system_memory(), get_system_io());
 635     isa_bus_irqs(isa_bus, i8259);
 636     //    pci_bus = i440fx_init();
 637     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 638     memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl,
 639                           "ppc-io", 0x00800000);
 640     memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
 641
 642     /* init basic PC hardware */
 643     pci_vga_init(pci_bus);
 644     //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
 645     //    pit = pit_init(0x40, 0);
 646     rtc_init(isa_bus, 2000, NULL);
 647
 648     if (serial_hds[0])
 649         serial_isa_init(isa_bus, 0, serial_hds[0]);
 650     nb_nics1 = nb_nics;
 651     if (nb_nics1 > NE2000_NB_MAX)
 652         nb_nics1 = NE2000_NB_MAX;
 653     for(i = 0; i < nb_nics1; i++) {
 654         if (nd_table[i].model == NULL) {
 655             nd_table[i].model = g_strdup("ne2k_isa");
 656         }
 657         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 658             isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
 659                             &nd_table[i]);
 660         } else {
 661             pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 662         }
 663     }
 664
 665     ide_drive_get(hd, MAX_IDE_BUS);
 666     for(i = 0; i < MAX_IDE_BUS; i++) {
 667         isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
 668                      hd[2 * i],
 669                      hd[2 * i + 1]);
 670     }
 671     isa_create_simple(isa_bus, "i8042");
 672
 673     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 674     DMA_init(1, cpu_exit_irq);
 675
 676     //    SB16_init();
 677
 678     for(i = 0; i < MAX_FD; i++) {
 679         fd[i] = drive_get(IF_FLOPPY, 0, i);
 680     }
 681     fdctrl_init_isa(isa_bus, fd);
 682
 683     /* Register speaker port */
 684     register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
 685     register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
 686     /* Register fake IO ports for PREP */
 687     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 688     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 689     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 690     /* System control ports */
 691     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 692     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 693     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 694     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 695     /* PCI intack location */
 696     memory_region_init_io(intack, &PPC_intack_ops, NULL, "ppc-intack", 4);
 697     memory_region_add_subregion(sysmem, 0xBFFFFFF0, intack);
 698     /* PowerPC control and status register group */
 699 #if 0
 700     memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
 701     memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
 702 #endif
 703
 704     if (usb_enabled) {
 705         usb_ohci_init_pci(pci_bus, -1);
 706     }
 707
 708     m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
 709     if (m48t59 == NULL)
 710         return;
 711     sysctrl->nvram = m48t59;
 712
 713     /* Initialise NVRAM */
 714     nvram.opaque = m48t59;
 715     nvram.read_fn = &m48t59_read;
 716     nvram.write_fn = &m48t59_write;
 717     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 718                          kernel_base, kernel_size,
 719                          kernel_cmdline,
 720                          initrd_base, initrd_size,
 721                          /* XXX: need an option to load a NVRAM image */
 722                          0,
 723                          graphic_width, graphic_height, graphic_depth);
 724
 725     /* Special port to get debug messages from Open-Firmware */
 726     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 727 }
 728
 729 static QEMUMachine prep_machine = {
 730     .name = "prep",
 731     .desc = "PowerPC PREP platform",
 732     .init = ppc_prep_init,
 733     .max_cpus = MAX_CPUS,
 734 };
 735
 736 static void prep_machine_init(void)
 737 {
 738     qemu_register_machine(&prep_machine);
 739 }
 740
 741 machine_init(prep_machine_init);