hw/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc405.h"
  27 #include "nvram.h"
  28 #include "flash.h"
  29 #include "sysemu.h"
  30 #include "block.h"
  31 #include "boards.h"
  32 #include "qemu-log.h"
  33 #include "loader.h"
  34 #include "blockdev.h"
  35 #include "exec-memory.h"
  36
  37 #define BIOS_FILENAME "ppc405_rom.bin"
  38 #define BIOS_SIZE (2048 * 1024)
  39
  40 #define KERNEL_LOAD_ADDR 0x00000000
  41 #define INITRD_LOAD_ADDR 0x01800000
  42
  43 #define USE_FLASH_BIOS
  44
  45 #define DEBUG_BOARD_INIT
  46
  47 /*****************************************************************************/
  48 /* PPC405EP reference board (IBM) */
  49 /* Standalone board with:
  50  * - PowerPC 405EP CPU
  51  * - SDRAM (0x00000000)
  52  * - Flash (0xFFF80000)
  53  * - SRAM  (0xFFF00000)
  54  * - NVRAM (0xF0000000)
  55  * - FPGA  (0xF0300000)
  56  */
  57 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  58 struct ref405ep_fpga_t {
  59     uint8_t reg0;
  60     uint8_t reg1;
  61 };
  62
  63 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
  64 {
  65     ref405ep_fpga_t *fpga;
  66     uint32_t ret;
  67
  68     fpga = opaque;
  69     switch (addr) {
  70     case 0x0:
  71         ret = fpga->reg0;
  72         break;
  73     case 0x1:
  74         ret = fpga->reg1;
  75         break;
  76     default:
  77         ret = 0;
  78         break;
  79     }
  80
  81     return ret;
  82 }
  83
  84 static void ref405ep_fpga_writeb (void *opaque,
  85                                   target_phys_addr_t addr, uint32_t value)
  86 {
  87     ref405ep_fpga_t *fpga;
  88
  89     fpga = opaque;
  90     switch (addr) {
  91     case 0x0:
  92         /* Read only */
  93         break;
  94     case 0x1:
  95         fpga->reg1 = value;
  96         break;
  97     default:
  98         break;
  99     }
 100 }
 101
 102 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
 103 {
 104     uint32_t ret;
 105
 106     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 107     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 108
 109     return ret;
 110 }
 111
 112 static void ref405ep_fpga_writew (void *opaque,
 113                                   target_phys_addr_t addr, uint32_t value)
 114 {
 115     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 116     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 117 }
 118
 119 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
 120 {
 121     uint32_t ret;
 122
 123     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 124     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 125     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 126     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 127
 128     return ret;
 129 }
 130
 131 static void ref405ep_fpga_writel (void *opaque,
 132                                   target_phys_addr_t addr, uint32_t value)
 133 {
 134     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 135     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 136     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 137     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 138 }
 139
 140 static const MemoryRegionOps ref405ep_fpga_ops = {
 141     .old_mmio = {
 142         .read = {
 143             ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl,
 144         },
 145         .write = {
 146             ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel,
 147         },
 148     },
 149     .endianness = DEVICE_NATIVE_ENDIAN,
 150 };
 151
 152 static void ref405ep_fpga_reset (void *opaque)
 153 {
 154     ref405ep_fpga_t *fpga;
 155
 156     fpga = opaque;
 157     fpga->reg0 = 0x00;
 158     fpga->reg1 = 0x0F;
 159 }
 160
 161 static void ref405ep_fpga_init (MemoryRegion *sysmem, uint32_t base)
 162 {
 163     ref405ep_fpga_t *fpga;
 164     MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
 165
 166     fpga = g_malloc0(sizeof(ref405ep_fpga_t));
 167     memory_region_init_io(fpga_memory, &ref405ep_fpga_ops, fpga,
 168                           "fpga", 0x00000100);
 169     memory_region_add_subregion(sysmem, base, fpga_memory);
 170     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 171 }
 172
 173 static void ref405ep_init (ram_addr_t ram_size,
 174                            const char *boot_device,
 175                            const char *kernel_filename,
 176                            const char *kernel_cmdline,
 177                            const char *initrd_filename,
 178                            const char *cpu_model)
 179 {
 180     char *filename;
 181     ppc4xx_bd_info_t bd;
 182     CPUPPCState *env;
 183     qemu_irq *pic;
 184     MemoryRegion *bios;
 185     MemoryRegion *sram = g_new(MemoryRegion, 1);
 186     ram_addr_t bdloc;
 187     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 188     target_phys_addr_t ram_bases[2], ram_sizes[2];
 189     target_ulong sram_size;
 190     long bios_size;
 191     //int phy_addr = 0;
 192     //static int phy_addr = 1;
 193     target_ulong kernel_base, initrd_base;
 194     long kernel_size, initrd_size;
 195     int linux_boot;
 196     int fl_idx, fl_sectors, len;
 197     DriveInfo *dinfo;
 198     MemoryRegion *sysmem = get_system_memory();
 199
 200     /* XXX: fix this */
 201     memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000);
 202     ram_bases[0] = 0;
 203     ram_sizes[0] = 0x08000000;
 204     memory_region_init(&ram_memories[1], "ef405ep.ram1", 0);
 205     ram_bases[1] = 0x00000000;
 206     ram_sizes[1] = 0x00000000;
 207     ram_size = 128 * 1024 * 1024;
 208 #ifdef DEBUG_BOARD_INIT
 209     printf("%s: register cpu\n", __func__);
 210 #endif
 211     env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 212                         33333333, &pic, kernel_filename == NULL ? 0 : 1);
 213     /* allocate SRAM */
 214     sram_size = 512 * 1024;
 215     memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size);
 216     memory_region_add_subregion(sysmem, 0xFFF00000, sram);
 217     /* allocate and load BIOS */
 218 #ifdef DEBUG_BOARD_INIT
 219     printf("%s: register BIOS\n", __func__);
 220 #endif
 221     fl_idx = 0;
 222 #ifdef USE_FLASH_BIOS
 223     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 224     if (dinfo) {
 225         bios_size = bdrv_getlength(dinfo->bdrv);
 226         fl_sectors = (bios_size + 65535) >> 16;
 227 #ifdef DEBUG_BOARD_INIT
 228         printf("Register parallel flash %d size %lx"
 229                " at addr %lx '%s' %d\n",
 230                fl_idx, bios_size, -bios_size,
 231                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 232 #endif
 233         pflash_cfi02_register((uint32_t)(-bios_size),
 234                               NULL, "ef405ep.bios", bios_size,
 235                               dinfo->bdrv, 65536, fl_sectors, 1,
 236                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 237                               1);
 238         fl_idx++;
 239     } else
 240 #endif
 241     {
 242 #ifdef DEBUG_BOARD_INIT
 243         printf("Load BIOS from file\n");
 244 #endif
 245         bios = g_new(MemoryRegion, 1);
 246         memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE);
 247         if (bios_name == NULL)
 248             bios_name = BIOS_FILENAME;
 249         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 250         if (filename) {
 251             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 252             g_free(filename);
 253         } else {
 254             bios_size = -1;
 255         }
 256         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 257             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 258                     bios_name);
 259             exit(1);
 260         }
 261         bios_size = (bios_size + 0xfff) & ~0xfff;
 262         memory_region_set_readonly(bios, true);
 263         memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 264     }
 265     /* Register FPGA */
 266 #ifdef DEBUG_BOARD_INIT
 267     printf("%s: register FPGA\n", __func__);
 268 #endif
 269     ref405ep_fpga_init(sysmem, 0xF0300000);
 270     /* Register NVRAM */
 271 #ifdef DEBUG_BOARD_INIT
 272     printf("%s: register NVRAM\n", __func__);
 273 #endif
 274     m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
 275     /* Load kernel */
 276     linux_boot = (kernel_filename != NULL);
 277     if (linux_boot) {
 278 #ifdef DEBUG_BOARD_INIT
 279         printf("%s: load kernel\n", __func__);
 280 #endif
 281         memset(&bd, 0, sizeof(bd));
 282         bd.bi_memstart = 0x00000000;
 283         bd.bi_memsize = ram_size;
 284         bd.bi_flashstart = -bios_size;
 285         bd.bi_flashsize = -bios_size;
 286         bd.bi_flashoffset = 0;
 287         bd.bi_sramstart = 0xFFF00000;
 288         bd.bi_sramsize = sram_size;
 289         bd.bi_bootflags = 0;
 290         bd.bi_intfreq = 133333333;
 291         bd.bi_busfreq = 33333333;
 292         bd.bi_baudrate = 115200;
 293         bd.bi_s_version[0] = 'Q';
 294         bd.bi_s_version[1] = 'M';
 295         bd.bi_s_version[2] = 'U';
 296         bd.bi_s_version[3] = '\0';
 297         bd.bi_r_version[0] = 'Q';
 298         bd.bi_r_version[1] = 'E';
 299         bd.bi_r_version[2] = 'M';
 300         bd.bi_r_version[3] = 'U';
 301         bd.bi_r_version[4] = '\0';
 302         bd.bi_procfreq = 133333333;
 303         bd.bi_plb_busfreq = 33333333;
 304         bd.bi_pci_busfreq = 33333333;
 305         bd.bi_opbfreq = 33333333;
 306         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 307         env->gpr[3] = bdloc;
 308         kernel_base = KERNEL_LOAD_ADDR;
 309         /* now we can load the kernel */
 310         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 311                                           ram_size - kernel_base);
 312         if (kernel_size < 0) {
 313             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 314                     kernel_filename);
 315             exit(1);
 316         }
 317         printf("Load kernel size %ld at " TARGET_FMT_lx,
 318                kernel_size, kernel_base);
 319         /* load initrd */
 320         if (initrd_filename) {
 321             initrd_base = INITRD_LOAD_ADDR;
 322             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 323                                               ram_size - initrd_base);
 324             if (initrd_size < 0) {
 325                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 326                         initrd_filename);
 327                 exit(1);
 328             }
 329         } else {
 330             initrd_base = 0;
 331             initrd_size = 0;
 332         }
 333         env->gpr[4] = initrd_base;
 334         env->gpr[5] = initrd_size;
 335         if (kernel_cmdline != NULL) {
 336             len = strlen(kernel_cmdline);
 337             bdloc -= ((len + 255) & ~255);
 338             cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
 339             env->gpr[6] = bdloc;
 340             env->gpr[7] = bdloc + len;
 341         } else {
 342             env->gpr[6] = 0;
 343             env->gpr[7] = 0;
 344         }
 345         env->nip = KERNEL_LOAD_ADDR;
 346     } else {
 347         kernel_base = 0;
 348         kernel_size = 0;
 349         initrd_base = 0;
 350         initrd_size = 0;
 351         bdloc = 0;
 352     }
 353 #ifdef DEBUG_BOARD_INIT
 354     printf("%s: Done\n", __func__);
 355 #endif
 356     printf("bdloc " RAM_ADDR_FMT "\n", bdloc);
 357 }
 358
 359 static QEMUMachine ref405ep_machine = {
 360     .name = "ref405ep",
 361     .desc = "ref405ep",
 362     .init = ref405ep_init,
 363 };
 364
 365 /*****************************************************************************/
 366 /* AMCC Taihu evaluation board */
 367 /* - PowerPC 405EP processor
 368  * - SDRAM               128 MB at 0x00000000
 369  * - Boot flash          2 MB   at 0xFFE00000
 370  * - Application flash   32 MB  at 0xFC000000
 371  * - 2 serial ports
 372  * - 2 ethernet PHY
 373  * - 1 USB 1.1 device    0x50000000
 374  * - 1 LCD display       0x50100000
 375  * - 1 CPLD              0x50100000
 376  * - 1 I2C EEPROM
 377  * - 1 I2C thermal sensor
 378  * - a set of LEDs
 379  * - bit-bang SPI port using GPIOs
 380  * - 1 EBC interface connector 0 0x50200000
 381  * - 1 cardbus controller + expansion slot.
 382  * - 1 PCI expansion slot.
 383  */
 384 typedef struct taihu_cpld_t taihu_cpld_t;
 385 struct taihu_cpld_t {
 386     uint8_t reg0;
 387     uint8_t reg1;
 388 };
 389
 390 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
 391 {
 392     taihu_cpld_t *cpld;
 393     uint32_t ret;
 394
 395     cpld = opaque;
 396     switch (addr) {
 397     case 0x0:
 398         ret = cpld->reg0;
 399         break;
 400     case 0x1:
 401         ret = cpld->reg1;
 402         break;
 403     default:
 404         ret = 0;
 405         break;
 406     }
 407
 408     return ret;
 409 }
 410
 411 static void taihu_cpld_writeb (void *opaque,
 412                                target_phys_addr_t addr, uint32_t value)
 413 {
 414     taihu_cpld_t *cpld;
 415
 416     cpld = opaque;
 417     switch (addr) {
 418     case 0x0:
 419         /* Read only */
 420         break;
 421     case 0x1:
 422         cpld->reg1 = value;
 423         break;
 424     default:
 425         break;
 426     }
 427 }
 428
 429 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
 430 {
 431     uint32_t ret;
 432
 433     ret = taihu_cpld_readb(opaque, addr) << 8;
 434     ret |= taihu_cpld_readb(opaque, addr + 1);
 435
 436     return ret;
 437 }
 438
 439 static void taihu_cpld_writew (void *opaque,
 440                                target_phys_addr_t addr, uint32_t value)
 441 {
 442     taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
 443     taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
 444 }
 445
 446 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
 447 {
 448     uint32_t ret;
 449
 450     ret = taihu_cpld_readb(opaque, addr) << 24;
 451     ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
 452     ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
 453     ret |= taihu_cpld_readb(opaque, addr + 3);
 454
 455     return ret;
 456 }
 457
 458 static void taihu_cpld_writel (void *opaque,
 459                                target_phys_addr_t addr, uint32_t value)
 460 {
 461     taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
 462     taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 463     taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 464     taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
 465 }
 466
 467 static const MemoryRegionOps taihu_cpld_ops = {
 468     .old_mmio = {
 469         .read = { taihu_cpld_readb, taihu_cpld_readw, taihu_cpld_readl, },
 470         .write = { taihu_cpld_writeb, taihu_cpld_writew, taihu_cpld_writel, },
 471     },
 472     .endianness = DEVICE_NATIVE_ENDIAN,
 473 };
 474
 475 static void taihu_cpld_reset (void *opaque)
 476 {
 477     taihu_cpld_t *cpld;
 478
 479     cpld = opaque;
 480     cpld->reg0 = 0x01;
 481     cpld->reg1 = 0x80;
 482 }
 483
 484 static void taihu_cpld_init (MemoryRegion *sysmem, uint32_t base)
 485 {
 486     taihu_cpld_t *cpld;
 487     MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
 488
 489     cpld = g_malloc0(sizeof(taihu_cpld_t));
 490     memory_region_init_io(cpld_memory, &taihu_cpld_ops, cpld, "cpld", 0x100);
 491     memory_region_add_subregion(sysmem, base, cpld_memory);
 492     qemu_register_reset(&taihu_cpld_reset, cpld);
 493 }
 494
 495 static void taihu_405ep_init(ram_addr_t ram_size,
 496                              const char *boot_device,
 497                              const char *kernel_filename,
 498                              const char *kernel_cmdline,
 499                              const char *initrd_filename,
 500                              const char *cpu_model)
 501 {
 502     char *filename;
 503     qemu_irq *pic;
 504     MemoryRegion *sysmem = get_system_memory();
 505     MemoryRegion *bios;
 506     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 507     target_phys_addr_t ram_bases[2], ram_sizes[2];
 508     long bios_size;
 509     target_ulong kernel_base, initrd_base;
 510     long kernel_size, initrd_size;
 511     int linux_boot;
 512     int fl_idx, fl_sectors;
 513     DriveInfo *dinfo;
 514
 515     /* RAM is soldered to the board so the size cannot be changed */
 516     memory_region_init_ram(&ram_memories[0], NULL,
 517                            "taihu_405ep.ram-0", 0x04000000);
 518     ram_bases[0] = 0;
 519     ram_sizes[0] = 0x04000000;
 520     memory_region_init_ram(&ram_memories[1], NULL,
 521                            "taihu_405ep.ram-1", 0x04000000);
 522     ram_bases[1] = 0x04000000;
 523     ram_sizes[1] = 0x04000000;
 524     ram_size = 0x08000000;
 525 #ifdef DEBUG_BOARD_INIT
 526     printf("%s: register cpu\n", __func__);
 527 #endif
 528     ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 529                   33333333, &pic, kernel_filename == NULL ? 0 : 1);
 530     /* allocate and load BIOS */
 531 #ifdef DEBUG_BOARD_INIT
 532     printf("%s: register BIOS\n", __func__);
 533 #endif
 534     fl_idx = 0;
 535 #if defined(USE_FLASH_BIOS)
 536     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 537     if (dinfo) {
 538         bios_size = bdrv_getlength(dinfo->bdrv);
 539         /* XXX: should check that size is 2MB */
 540         //        bios_size = 2 * 1024 * 1024;
 541         fl_sectors = (bios_size + 65535) >> 16;
 542 #ifdef DEBUG_BOARD_INIT
 543         printf("Register parallel flash %d size %lx"
 544                " at addr %lx '%s' %d\n",
 545                fl_idx, bios_size, -bios_size,
 546                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 547 #endif
 548         pflash_cfi02_register((uint32_t)(-bios_size),
 549                               NULL, "taihu_405ep.bios", bios_size,
 550                               dinfo->bdrv, 65536, fl_sectors, 1,
 551                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 552                               1);
 553         fl_idx++;
 554     } else
 555 #endif
 556     {
 557 #ifdef DEBUG_BOARD_INIT
 558         printf("Load BIOS from file\n");
 559 #endif
 560         if (bios_name == NULL)
 561             bios_name = BIOS_FILENAME;
 562         bios = g_new(MemoryRegion, 1);
 563         memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE);
 564         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 565         if (filename) {
 566             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 567             g_free(filename);
 568         } else {
 569             bios_size = -1;
 570         }
 571         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 572             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 573                     bios_name);
 574             exit(1);
 575         }
 576         bios_size = (bios_size + 0xfff) & ~0xfff;
 577         memory_region_set_readonly(bios, true);
 578         memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 579     }
 580     /* Register Linux flash */
 581     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 582     if (dinfo) {
 583         bios_size = bdrv_getlength(dinfo->bdrv);
 584         /* XXX: should check that size is 32MB */
 585         bios_size = 32 * 1024 * 1024;
 586         fl_sectors = (bios_size + 65535) >> 16;
 587 #ifdef DEBUG_BOARD_INIT
 588         printf("Register parallel flash %d size %lx"
 589                " at addr " TARGET_FMT_lx " '%s'\n",
 590                fl_idx, bios_size, (target_ulong)0xfc000000,
 591                bdrv_get_device_name(dinfo->bdrv));
 592 #endif
 593         pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size,
 594                               dinfo->bdrv, 65536, fl_sectors, 1,
 595                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 596                               1);
 597         fl_idx++;
 598     }
 599     /* Register CLPD & LCD display */
 600 #ifdef DEBUG_BOARD_INIT
 601     printf("%s: register CPLD\n", __func__);
 602 #endif
 603     taihu_cpld_init(sysmem, 0x50100000);
 604     /* Load kernel */
 605     linux_boot = (kernel_filename != NULL);
 606     if (linux_boot) {
 607 #ifdef DEBUG_BOARD_INIT
 608         printf("%s: load kernel\n", __func__);
 609 #endif
 610         kernel_base = KERNEL_LOAD_ADDR;
 611         /* now we can load the kernel */
 612         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 613                                           ram_size - kernel_base);
 614         if (kernel_size < 0) {
 615             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 616                     kernel_filename);
 617             exit(1);
 618         }
 619         /* load initrd */
 620         if (initrd_filename) {
 621             initrd_base = INITRD_LOAD_ADDR;
 622             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 623                                               ram_size - initrd_base);
 624             if (initrd_size < 0) {
 625                 fprintf(stderr,
 626                         "qemu: could not load initial ram disk '%s'\n",
 627                         initrd_filename);
 628                 exit(1);
 629             }
 630         } else {
 631             initrd_base = 0;
 632             initrd_size = 0;
 633         }
 634     } else {
 635         kernel_base = 0;
 636         kernel_size = 0;
 637         initrd_base = 0;
 638         initrd_size = 0;
 639     }
 640 #ifdef DEBUG_BOARD_INIT
 641     printf("%s: Done\n", __func__);
 642 #endif
 643 }
 644
 645 static QEMUMachine taihu_machine = {
 646     .name = "taihu",
 647     .desc = "taihu",
 648     .init = taihu_405ep_init,
 649 };
 650
 651 static void ppc405_machine_init(void)
 652 {
 653     qemu_register_machine(&ref405ep_machine);
 654     qemu_register_machine(&taihu_machine);
 655 }
 656
 657 machine_init(ppc405_machine_init);