hw/pl061.c

   1 /*
   2  * Arm PrimeCell PL061 General Purpose IO with additional
   3  * Luminary Micro Stellaris bits.
   4  *
   5  * Copyright (c) 2007 CodeSourcery.
   6  * Written by Paul Brook
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "sysbus.h"
  12
  13 //#define DEBUG_PL061 1
  14
  15 #ifdef DEBUG_PL061
  16 #define DPRINTF(fmt, ...) \
  17 do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
  18 #define BADF(fmt, ...) \
  19 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
  20 #else
  21 #define DPRINTF(fmt, ...) do {} while(0)
  22 #define BADF(fmt, ...) \
  23 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
  24 #endif
  25
  26 static const uint8_t pl061_id[12] =
  27   { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  28 static const uint8_t pl061_id_luminary[12] =
  29   { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
  30
  31 typedef struct {
  32     SysBusDevice busdev;
  33     MemoryRegion iomem;
  34     uint32_t locked;
  35     uint32_t data;
  36     uint32_t old_data;
  37     uint32_t dir;
  38     uint32_t isense;
  39     uint32_t ibe;
  40     uint32_t iev;
  41     uint32_t im;
  42     uint32_t istate;
  43     uint32_t afsel;
  44     uint32_t dr2r;
  45     uint32_t dr4r;
  46     uint32_t dr8r;
  47     uint32_t odr;
  48     uint32_t pur;
  49     uint32_t pdr;
  50     uint32_t slr;
  51     uint32_t den;
  52     uint32_t cr;
  53     uint32_t float_high;
  54     uint32_t amsel;
  55     qemu_irq irq;
  56     qemu_irq out[8];
  57     const unsigned char *id;
  58 } pl061_state;
  59
  60 static const VMStateDescription vmstate_pl061 = {
  61     .name = "pl061",
  62     .version_id = 2,
  63     .minimum_version_id = 1,
  64     .fields = (VMStateField[]) {
  65         VMSTATE_UINT32(locked, pl061_state),
  66         VMSTATE_UINT32(data, pl061_state),
  67         VMSTATE_UINT32(old_data, pl061_state),
  68         VMSTATE_UINT32(dir, pl061_state),
  69         VMSTATE_UINT32(isense, pl061_state),
  70         VMSTATE_UINT32(ibe, pl061_state),
  71         VMSTATE_UINT32(iev, pl061_state),
  72         VMSTATE_UINT32(im, pl061_state),
  73         VMSTATE_UINT32(istate, pl061_state),
  74         VMSTATE_UINT32(afsel, pl061_state),
  75         VMSTATE_UINT32(dr2r, pl061_state),
  76         VMSTATE_UINT32(dr4r, pl061_state),
  77         VMSTATE_UINT32(dr8r, pl061_state),
  78         VMSTATE_UINT32(odr, pl061_state),
  79         VMSTATE_UINT32(pur, pl061_state),
  80         VMSTATE_UINT32(pdr, pl061_state),
  81         VMSTATE_UINT32(slr, pl061_state),
  82         VMSTATE_UINT32(den, pl061_state),
  83         VMSTATE_UINT32(cr, pl061_state),
  84         VMSTATE_UINT32(float_high, pl061_state),
  85         VMSTATE_UINT32_V(amsel, pl061_state, 2),
  86         VMSTATE_END_OF_LIST()
  87     }
  88 };
  89
  90 static void pl061_update(pl061_state *s)
  91 {
  92     uint8_t changed;
  93     uint8_t mask;
  94     uint8_t out;
  95     int i;
  96
  97     /* Outputs float high.  */
  98     /* FIXME: This is board dependent.  */
  99     out = (s->data & s->dir) | ~s->dir;
 100     changed = s->old_data ^ out;
 101     if (!changed)
 102         return;
 103
 104     s->old_data = out;
 105     for (i = 0; i < 8; i++) {
 106         mask = 1 << i;
 107         if (changed & mask) {
 108             DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
 109             qemu_set_irq(s->out[i], (out & mask) != 0);
 110         }
 111     }
 112
 113     /* FIXME: Implement input interrupts.  */
 114 }
 115
 116 static uint64_t pl061_read(void *opaque, target_phys_addr_t offset,
 117                            unsigned size)
 118 {
 119     pl061_state *s = (pl061_state *)opaque;
 120
 121     if (offset >= 0xfd0 && offset < 0x1000) {
 122         return s->id[(offset - 0xfd0) >> 2];
 123     }
 124     if (offset < 0x400) {
 125         return s->data & (offset >> 2);
 126     }
 127     switch (offset) {
 128     case 0x400: /* Direction */
 129         return s->dir;
 130     case 0x404: /* Interrupt sense */
 131         return s->isense;
 132     case 0x408: /* Interrupt both edges */
 133         return s->ibe;
 134     case 0x40c: /* Interrupt event */
 135         return s->iev;
 136     case 0x410: /* Interrupt mask */
 137         return s->im;
 138     case 0x414: /* Raw interrupt status */
 139         return s->istate;
 140     case 0x418: /* Masked interrupt status */
 141         return s->istate | s->im;
 142     case 0x420: /* Alternate function select */
 143         return s->afsel;
 144     case 0x500: /* 2mA drive */
 145         return s->dr2r;
 146     case 0x504: /* 4mA drive */
 147         return s->dr4r;
 148     case 0x508: /* 8mA drive */
 149         return s->dr8r;
 150     case 0x50c: /* Open drain */
 151         return s->odr;
 152     case 0x510: /* Pull-up */
 153         return s->pur;
 154     case 0x514: /* Pull-down */
 155         return s->pdr;
 156     case 0x518: /* Slew rate control */
 157         return s->slr;
 158     case 0x51c: /* Digital enable */
 159         return s->den;
 160     case 0x520: /* Lock */
 161         return s->locked;
 162     case 0x524: /* Commit */
 163         return s->cr;
 164     case 0x528: /* Analog mode select */
 165         return s->amsel;
 166     default:
 167         hw_error("pl061_read: Bad offset %x\n", (int)offset);
 168         return 0;
 169     }
 170 }
 171
 172 static void pl061_write(void *opaque, target_phys_addr_t offset,
 173                         uint64_t value, unsigned size)
 174 {
 175     pl061_state *s = (pl061_state *)opaque;
 176     uint8_t mask;
 177
 178     if (offset < 0x400) {
 179         mask = (offset >> 2) & s->dir;
 180         s->data = (s->data & ~mask) | (value & mask);
 181         pl061_update(s);
 182         return;
 183     }
 184     switch (offset) {
 185     case 0x400: /* Direction */
 186         s->dir = value & 0xff;
 187         break;
 188     case 0x404: /* Interrupt sense */
 189         s->isense = value & 0xff;
 190         break;
 191     case 0x408: /* Interrupt both edges */
 192         s->ibe = value & 0xff;
 193         break;
 194     case 0x40c: /* Interrupt event */
 195         s->iev = value & 0xff;
 196         break;
 197     case 0x410: /* Interrupt mask */
 198         s->im = value & 0xff;
 199         break;
 200     case 0x41c: /* Interrupt clear */
 201         s->istate &= ~value;
 202         break;
 203     case 0x420: /* Alternate function select */
 204         mask = s->cr;
 205         s->afsel = (s->afsel & ~mask) | (value & mask);
 206         break;
 207     case 0x500: /* 2mA drive */
 208         s->dr2r = value & 0xff;
 209         break;
 210     case 0x504: /* 4mA drive */
 211         s->dr4r = value & 0xff;
 212         break;
 213     case 0x508: /* 8mA drive */
 214         s->dr8r = value & 0xff;
 215         break;
 216     case 0x50c: /* Open drain */
 217         s->odr = value & 0xff;
 218         break;
 219     case 0x510: /* Pull-up */
 220         s->pur = value & 0xff;
 221         break;
 222     case 0x514: /* Pull-down */
 223         s->pdr = value & 0xff;
 224         break;
 225     case 0x518: /* Slew rate control */
 226         s->slr = value & 0xff;
 227         break;
 228     case 0x51c: /* Digital enable */
 229         s->den = value & 0xff;
 230         break;
 231     case 0x520: /* Lock */
 232         s->locked = (value != 0xacce551);
 233         break;
 234     case 0x524: /* Commit */
 235         if (!s->locked)
 236             s->cr = value & 0xff;
 237         break;
 238     case 0x528:
 239         s->amsel = value & 0xff;
 240         break;
 241     default:
 242         hw_error("pl061_write: Bad offset %x\n", (int)offset);
 243     }
 244     pl061_update(s);
 245 }
 246
 247 static void pl061_reset(pl061_state *s)
 248 {
 249   s->locked = 1;
 250   s->cr = 0xff;
 251 }
 252
 253 static void pl061_set_irq(void * opaque, int irq, int level)
 254 {
 255     pl061_state *s = (pl061_state *)opaque;
 256     uint8_t mask;
 257
 258     mask = 1 << irq;
 259     if ((s->dir & mask) == 0) {
 260         s->data &= ~mask;
 261         if (level)
 262             s->data |= mask;
 263         pl061_update(s);
 264     }
 265 }
 266
 267 static const MemoryRegionOps pl061_ops = {
 268     .read = pl061_read,
 269     .write = pl061_write,
 270     .endianness = DEVICE_NATIVE_ENDIAN,
 271 };
 272
 273 static int pl061_init(SysBusDevice *dev, const unsigned char *id)
 274 {
 275     pl061_state *s = FROM_SYSBUS(pl061_state, dev);
 276     s->id = id;
 277     memory_region_init_io(&s->iomem, &pl061_ops, s, "pl061", 0x1000);
 278     sysbus_init_mmio(dev, &s->iomem);
 279     sysbus_init_irq(dev, &s->irq);
 280     qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);
 281     qdev_init_gpio_out(&dev->qdev, s->out, 8);
 282     pl061_reset(s);
 283     return 0;
 284 }
 285
 286 static int pl061_init_luminary(SysBusDevice *dev)
 287 {
 288     return pl061_init(dev, pl061_id_luminary);
 289 }
 290
 291 static int pl061_init_arm(SysBusDevice *dev)
 292 {
 293     return pl061_init(dev, pl061_id);
 294 }
 295
 296 static SysBusDeviceInfo pl061_info = {
 297     .init = pl061_init_arm,
 298     .qdev.name = "pl061",
 299     .qdev.size = sizeof(pl061_state),
 300     .qdev.vmsd = &vmstate_pl061,
 301 };
 302
 303 static SysBusDeviceInfo pl061_luminary_info = {
 304     .init = pl061_init_luminary,
 305     .qdev.name = "pl061_luminary",
 306     .qdev.size = sizeof(pl061_state),
 307     .qdev.vmsd = &vmstate_pl061,
 308 };
 309
 310 static void pl061_register_devices(void)
 311 {
 312     sysbus_register_withprop(&pl061_info);
 313     sysbus_register_withprop(&pl061_luminary_info);
 314 }
 315
 316 device_init(pl061_register_devices)