hw/mst_fpga.c

   1 /*
   2  * PXA270-based Intel Mainstone platforms.
   3  * FPGA driver
   4  *
   5  * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
   6  *                                    <akuster@mvista.com>
   7  *
   8  * This code is licensed under the GNU GPL v2.
   9  */
  10 #include "hw.h"
  11 #include "sysbus.h"
  12
  13 /* Mainstone FPGA for extern irqs */
  14 #define FPGA_GPIO_PIN   0
  15 #define MST_NUM_IRQS    16
  16 #define MST_LEDDAT1             0x10
  17 #define MST_LEDDAT2             0x14
  18 #define MST_LEDCTRL             0x40
  19 #define MST_GPSWR               0x60
  20 #define MST_MSCWR1              0x80
  21 #define MST_MSCWR2              0x84
  22 #define MST_MSCWR3              0x88
  23 #define MST_MSCRD               0x90
  24 #define MST_INTMSKENA   0xc0
  25 #define MST_INTSETCLR   0xd0
  26 #define MST_PCMCIA0             0xe0
  27 #define MST_PCMCIA1             0xe4
  28
  29 #define MST_PCMCIAx_READY       (1 << 10)
  30 #define MST_PCMCIAx_nCD         (1 << 5)
  31
  32 #define MST_PCMCIA_CD0_IRQ      9
  33 #define MST_PCMCIA_CD1_IRQ      13
  34
  35 typedef struct mst_irq_state{
  36         SysBusDevice busdev;
  37         MemoryRegion iomem;
  38
  39         qemu_irq parent;
  40
  41         uint32_t prev_level;
  42         uint32_t leddat1;
  43         uint32_t leddat2;
  44         uint32_t ledctrl;
  45         uint32_t gpswr;
  46         uint32_t mscwr1;
  47         uint32_t mscwr2;
  48         uint32_t mscwr3;
  49         uint32_t mscrd;
  50         uint32_t intmskena;
  51         uint32_t intsetclr;
  52         uint32_t pcmcia0;
  53         uint32_t pcmcia1;
  54 }mst_irq_state;
  55
  56 static void
  57 mst_fpga_set_irq(void *opaque, int irq, int level)
  58 {
  59         mst_irq_state *s = (mst_irq_state *)opaque;
  60         uint32_t oldint = s->intsetclr & s->intmskena;
  61
  62         if (level)
  63                 s->prev_level |= 1u << irq;
  64         else
  65                 s->prev_level &= ~(1u << irq);
  66
  67         switch(irq) {
  68         case MST_PCMCIA_CD0_IRQ:
  69                 if (level)
  70                         s->pcmcia0 &= ~MST_PCMCIAx_nCD;
  71                 else
  72                         s->pcmcia0 |=  MST_PCMCIAx_nCD;
  73                 break;
  74         case MST_PCMCIA_CD1_IRQ:
  75                 if (level)
  76                         s->pcmcia1 &= ~MST_PCMCIAx_nCD;
  77                 else
  78                         s->pcmcia1 |=  MST_PCMCIAx_nCD;
  79                 break;
  80         }
  81
  82         if ((s->intmskena & (1u << irq)) && level)
  83                 s->intsetclr |= 1u << irq;
  84
  85         if (oldint != (s->intsetclr & s->intmskena))
  86                 qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
  87 }
  88
  89
  90 static uint64_t
  91 mst_fpga_readb(void *opaque, target_phys_addr_t addr, unsigned size)
  92 {
  93         mst_irq_state *s = (mst_irq_state *) opaque;
  94
  95         switch (addr) {
  96         case MST_LEDDAT1:
  97                 return s->leddat1;
  98         case MST_LEDDAT2:
  99                 return s->leddat2;
 100         case MST_LEDCTRL:
 101                 return s->ledctrl;
 102         case MST_GPSWR:
 103                 return s->gpswr;
 104         case MST_MSCWR1:
 105                 return s->mscwr1;
 106         case MST_MSCWR2:
 107                 return s->mscwr2;
 108         case MST_MSCWR3:
 109                 return s->mscwr3;
 110         case MST_MSCRD:
 111                 return s->mscrd;
 112         case MST_INTMSKENA:
 113                 return s->intmskena;
 114         case MST_INTSETCLR:
 115                 return s->intsetclr;
 116         case MST_PCMCIA0:
 117                 return s->pcmcia0;
 118         case MST_PCMCIA1:
 119                 return s->pcmcia1;
 120         default:
 121                 printf("Mainstone - mst_fpga_readb: Bad register offset "
 122                         "0x" TARGET_FMT_plx "\n", addr);
 123         }
 124         return 0;
 125 }
 126
 127 static void
 128 mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint64_t value,
 129                 unsigned size)
 130 {
 131         mst_irq_state *s = (mst_irq_state *) opaque;
 132         value &= 0xffffffff;
 133
 134         switch (addr) {
 135         case MST_LEDDAT1:
 136                 s->leddat1 = value;
 137                 break;
 138         case MST_LEDDAT2:
 139                 s->leddat2 = value;
 140                 break;
 141         case MST_LEDCTRL:
 142                 s->ledctrl = value;
 143                 break;
 144         case MST_GPSWR:
 145                 s->gpswr = value;
 146                 break;
 147         case MST_MSCWR1:
 148                 s->mscwr1 = value;
 149                 break;
 150         case MST_MSCWR2:
 151                 s->mscwr2 = value;
 152                 break;
 153         case MST_MSCWR3:
 154                 s->mscwr3 = value;
 155                 break;
 156         case MST_MSCRD:
 157                 s->mscrd =  value;
 158                 break;
 159         case MST_INTMSKENA:     /* Mask interrupt */
 160                 s->intmskena = (value & 0xFEEFF);
 161                 qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
 162                 break;
 163         case MST_INTSETCLR:     /* clear or set interrupt */
 164                 s->intsetclr = (value & 0xFEEFF);
 165                 qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
 166                 break;
 167                 /* For PCMCIAx allow the to change only power and reset */
 168         case MST_PCMCIA0:
 169                 s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f);
 170                 break;
 171         case MST_PCMCIA1:
 172                 s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f);
 173                 break;
 174         default:
 175                 printf("Mainstone - mst_fpga_writeb: Bad register offset "
 176                         "0x" TARGET_FMT_plx "\n", addr);
 177         }
 178 }
 179
 180 static const MemoryRegionOps mst_fpga_ops = {
 181         .read = mst_fpga_readb,
 182         .write = mst_fpga_writeb,
 183         .endianness = DEVICE_NATIVE_ENDIAN,
 184 };
 185
 186 static int mst_fpga_post_load(void *opaque, int version_id)
 187 {
 188         mst_irq_state *s = (mst_irq_state *) opaque;
 189
 190         qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
 191         return 0;
 192 }
 193
 194 static int mst_fpga_init(SysBusDevice *dev)
 195 {
 196         mst_irq_state *s;
 197
 198         s = FROM_SYSBUS(mst_irq_state, dev);
 199
 200         s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
 201         s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
 202
 203         sysbus_init_irq(dev, &s->parent);
 204
 205         /* alloc the external 16 irqs */
 206         qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
 207
 208         memory_region_init_io(&s->iomem, &mst_fpga_ops, s,
 209                             "fpga", 0x00100000);
 210         sysbus_init_mmio(dev, &s->iomem);
 211         return 0;
 212 }
 213
 214 static VMStateDescription vmstate_mst_fpga_regs = {
 215         .name = "mainstone_fpga",
 216         .version_id = 0,
 217         .minimum_version_id = 0,
 218         .minimum_version_id_old = 0,
 219         .post_load = mst_fpga_post_load,
 220         .fields = (VMStateField []) {
 221                 VMSTATE_UINT32(prev_level, mst_irq_state),
 222                 VMSTATE_UINT32(leddat1, mst_irq_state),
 223                 VMSTATE_UINT32(leddat2, mst_irq_state),
 224                 VMSTATE_UINT32(ledctrl, mst_irq_state),
 225                 VMSTATE_UINT32(gpswr, mst_irq_state),
 226                 VMSTATE_UINT32(mscwr1, mst_irq_state),
 227                 VMSTATE_UINT32(mscwr2, mst_irq_state),
 228                 VMSTATE_UINT32(mscwr3, mst_irq_state),
 229                 VMSTATE_UINT32(mscrd, mst_irq_state),
 230                 VMSTATE_UINT32(intmskena, mst_irq_state),
 231                 VMSTATE_UINT32(intsetclr, mst_irq_state),
 232                 VMSTATE_UINT32(pcmcia0, mst_irq_state),
 233                 VMSTATE_UINT32(pcmcia1, mst_irq_state),
 234                 VMSTATE_END_OF_LIST(),
 235         },
 236 };
 237
 238 static SysBusDeviceInfo mst_fpga_info = {
 239         .init = mst_fpga_init,
 240         .qdev.name = "mainstone-fpga",
 241         .qdev.desc = "Mainstone II FPGA",
 242         .qdev.size = sizeof(mst_irq_state),
 243         .qdev.vmsd = &vmstate_mst_fpga_regs,
 244 };
 245
 246 static void mst_fpga_register(void)
 247 {
 248         sysbus_register_withprop(&mst_fpga_info);
 249 }
 250 device_init(mst_fpga_register);