2 * QEMU Sun4u/Sun4v System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
29 #include "hw/pci/pci.h"
30 #include "hw/pci/pci_bus.h"
31 #include "hw/pci-host/apb.h"
32 #include "hw/i386/pc.h"
33 #include "hw/char/serial.h"
34 #include "hw/timer/m48t59.h"
35 #include "hw/block/fdc.h"
37 #include "qemu/timer.h"
38 #include "sysemu/sysemu.h"
39 #include "hw/boards.h"
40 #include "hw/nvram/sun_nvram.h"
41 #include "hw/nvram/chrp_nvram.h"
42 #include "hw/sparc/sparc64.h"
43 #include "hw/nvram/fw_cfg.h"
44 #include "hw/sysbus.h"
46 #include "hw/ide/pci.h"
47 #include "hw/loader.h"
49 #include "qemu/cutils.h"
54 #define EBUS_DPRINTF(fmt, ...) \
55 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
57 #define EBUS_DPRINTF(fmt, ...)
60 #define KERNEL_LOAD_ADDR 0x00404000
61 #define CMDLINE_ADDR 0x003ff000
62 #define PROM_SIZE_MAX (4 * 1024 * 1024)
63 #define PROM_VADDR 0x000ffd00000ULL
64 #define APB_SPECIAL_BASE 0x1fe00000000ULL
65 #define APB_MEM_BASE 0x1ff00000000ULL
66 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
67 #define PROM_FILENAME "openbios-sparc64"
68 #define NVRAM_SIZE 0x2000
70 #define BIOS_CFG_IOPORT 0x510
71 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
72 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
73 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
80 uint64_t console_serial_base
;
83 typedef struct EbusState
{
89 void DMA_init(ISABus
*bus
, int high_page_enable
)
93 static void fw_cfg_boot_set(void *opaque
, const char *boot_device
,
96 fw_cfg_modify_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
99 static int sun4u_NVRAM_set_params(Nvram
*nvram
, uint16_t NVRAM_size
,
100 const char *arch
, ram_addr_t RAM_size
,
101 const char *boot_devices
,
102 uint32_t kernel_image
, uint32_t kernel_size
,
104 uint32_t initrd_image
, uint32_t initrd_size
,
105 uint32_t NVRAM_image
,
106 int width
, int height
, int depth
,
107 const uint8_t *macaddr
)
111 uint8_t image
[0x1ff0];
112 NvramClass
*k
= NVRAM_GET_CLASS(nvram
);
114 memset(image
, '\0', sizeof(image
));
116 /* OpenBIOS nvram variables partition */
117 sysp_end
= chrp_nvram_create_system_partition(image
, 0);
119 /* Free space partition */
120 chrp_nvram_create_free_partition(&image
[sysp_end
], 0x1fd0 - sysp_end
);
122 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
, 0x80);
124 for (i
= 0; i
< sizeof(image
); i
++) {
125 (k
->write
)(nvram
, i
, image
[i
]);
131 static uint64_t sun4u_load_kernel(const char *kernel_filename
,
132 const char *initrd_filename
,
133 ram_addr_t RAM_size
, uint64_t *initrd_size
,
134 uint64_t *initrd_addr
, uint64_t *kernel_addr
,
135 uint64_t *kernel_entry
)
143 linux_boot
= (kernel_filename
!= NULL
);
154 kernel_size
= load_elf(kernel_filename
, NULL
, NULL
, kernel_entry
,
155 kernel_addr
, &kernel_top
, 1, EM_SPARCV9
, 0, 0);
156 if (kernel_size
< 0) {
157 *kernel_addr
= KERNEL_LOAD_ADDR
;
158 *kernel_entry
= KERNEL_LOAD_ADDR
;
159 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
160 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
163 if (kernel_size
< 0) {
164 kernel_size
= load_image_targphys(kernel_filename
,
166 RAM_size
- KERNEL_LOAD_ADDR
);
168 if (kernel_size
< 0) {
169 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
173 /* load initrd above kernel */
175 if (initrd_filename
) {
176 *initrd_addr
= TARGET_PAGE_ALIGN(kernel_top
);
178 *initrd_size
= load_image_targphys(initrd_filename
,
180 RAM_size
- *initrd_addr
);
181 if ((int)*initrd_size
< 0) {
182 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
187 if (*initrd_size
> 0) {
188 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
189 ptr
= rom_ptr(*kernel_addr
+ i
);
190 if (ldl_p(ptr
+ 8) == 0x48647253) { /* HdrS */
191 stl_p(ptr
+ 24, *initrd_addr
+ *kernel_addr
);
192 stl_p(ptr
+ 28, *initrd_size
);
201 typedef struct ResetData
{
206 static void isa_irq_handler(void *opaque
, int n
, int level
)
208 static const int isa_irq_to_ivec
[16] = {
209 [1] = 0x29, /* keyboard */
210 [4] = 0x2b, /* serial */
211 [6] = 0x27, /* floppy */
212 [7] = 0x22, /* parallel */
213 [12] = 0x2a, /* mouse */
215 qemu_irq
*irqs
= opaque
;
218 assert(n
< ARRAY_SIZE(isa_irq_to_ivec
));
219 ivec
= isa_irq_to_ivec
[n
];
220 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n
, level
, ivec
);
222 qemu_set_irq(irqs
[ivec
], level
);
226 /* EBUS (Eight bit bus) bridge */
228 pci_ebus_init(PCIDevice
*pci_dev
, qemu_irq
*irqs
)
233 isa_bus
= ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev
), "isa.0"));
234 isa_irq
= qemu_allocate_irqs(isa_irq_handler
, irqs
, 16);
235 isa_bus_irqs(isa_bus
, isa_irq
);
239 static void pci_ebus_realize(PCIDevice
*pci_dev
, Error
**errp
)
241 EbusState
*s
= DO_UPCAST(EbusState
, pci_dev
, pci_dev
);
243 if (!isa_bus_new(DEVICE(pci_dev
), get_system_memory(),
244 pci_address_space_io(pci_dev
), errp
)) {
248 pci_dev
->config
[0x04] = 0x06; // command = bus master, pci mem
249 pci_dev
->config
[0x05] = 0x00;
250 pci_dev
->config
[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
251 pci_dev
->config
[0x07] = 0x03; // status = medium devsel
252 pci_dev
->config
[0x09] = 0x00; // programming i/f
253 pci_dev
->config
[0x0D] = 0x0a; // latency_timer
255 memory_region_init_alias(&s
->bar0
, OBJECT(s
), "bar0", get_system_io(),
257 pci_register_bar(pci_dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar0
);
258 memory_region_init_alias(&s
->bar1
, OBJECT(s
), "bar1", get_system_io(),
260 pci_register_bar(pci_dev
, 1, PCI_BASE_ADDRESS_SPACE_IO
, &s
->bar1
);
263 static void ebus_class_init(ObjectClass
*klass
, void *data
)
265 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
267 k
->realize
= pci_ebus_realize
;
268 k
->vendor_id
= PCI_VENDOR_ID_SUN
;
269 k
->device_id
= PCI_DEVICE_ID_SUN_EBUS
;
271 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
274 static const TypeInfo ebus_info
= {
276 .parent
= TYPE_PCI_DEVICE
,
277 .instance_size
= sizeof(EbusState
),
278 .class_init
= ebus_class_init
,
279 .interfaces
= (InterfaceInfo
[]) {
280 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
285 #define TYPE_OPENPROM "openprom"
286 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
288 typedef struct PROMState
{
289 SysBusDevice parent_obj
;
294 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
296 hwaddr
*base_addr
= (hwaddr
*)opaque
;
297 return addr
+ *base_addr
- PROM_VADDR
;
300 /* Boot PROM (OpenBIOS) */
301 static void prom_init(hwaddr addr
, const char *bios_name
)
308 dev
= qdev_create(NULL
, TYPE_OPENPROM
);
309 qdev_init_nofail(dev
);
310 s
= SYS_BUS_DEVICE(dev
);
312 sysbus_mmio_map(s
, 0, addr
);
315 if (bios_name
== NULL
) {
316 bios_name
= PROM_FILENAME
;
318 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
320 ret
= load_elf(filename
, translate_prom_address
, &addr
,
321 NULL
, NULL
, NULL
, 1, EM_SPARCV9
, 0, 0);
322 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
323 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
329 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
330 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
335 static void prom_init1(Object
*obj
)
337 PROMState
*s
= OPENPROM(obj
);
338 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
340 memory_region_init_ram_nomigrate(&s
->prom
, obj
, "sun4u.prom", PROM_SIZE_MAX
,
342 vmstate_register_ram_global(&s
->prom
);
343 memory_region_set_readonly(&s
->prom
, true);
344 sysbus_init_mmio(dev
, &s
->prom
);
347 static Property prom_properties
[] = {
348 {/* end of property list */},
351 static void prom_class_init(ObjectClass
*klass
, void *data
)
353 DeviceClass
*dc
= DEVICE_CLASS(klass
);
355 dc
->props
= prom_properties
;
358 static const TypeInfo prom_info
= {
359 .name
= TYPE_OPENPROM
,
360 .parent
= TYPE_SYS_BUS_DEVICE
,
361 .instance_size
= sizeof(PROMState
),
362 .class_init
= prom_class_init
,
363 .instance_init
= prom_init1
,
367 #define TYPE_SUN4U_MEMORY "memory"
368 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
370 typedef struct RamDevice
{
371 SysBusDevice parent_obj
;
378 static void ram_realize(DeviceState
*dev
, Error
**errp
)
380 RamDevice
*d
= SUN4U_RAM(dev
);
381 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
383 memory_region_init_ram_nomigrate(&d
->ram
, OBJECT(d
), "sun4u.ram", d
->size
,
385 vmstate_register_ram_global(&d
->ram
);
386 sysbus_init_mmio(sbd
, &d
->ram
);
389 static void ram_init(hwaddr addr
, ram_addr_t RAM_size
)
396 dev
= qdev_create(NULL
, TYPE_SUN4U_MEMORY
);
397 s
= SYS_BUS_DEVICE(dev
);
401 qdev_init_nofail(dev
);
403 sysbus_mmio_map(s
, 0, addr
);
406 static Property ram_properties
[] = {
407 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
408 DEFINE_PROP_END_OF_LIST(),
411 static void ram_class_init(ObjectClass
*klass
, void *data
)
413 DeviceClass
*dc
= DEVICE_CLASS(klass
);
415 dc
->realize
= ram_realize
;
416 dc
->props
= ram_properties
;
419 static const TypeInfo ram_info
= {
420 .name
= TYPE_SUN4U_MEMORY
,
421 .parent
= TYPE_SYS_BUS_DEVICE
,
422 .instance_size
= sizeof(RamDevice
),
423 .class_init
= ram_class_init
,
426 static void sun4uv_init(MemoryRegion
*address_space_mem
,
427 MachineState
*machine
,
428 const struct hwdef
*hwdef
)
433 uint64_t initrd_addr
, initrd_size
, kernel_addr
, kernel_size
, kernel_entry
;
434 PCIBus
*pci_bus
, *pci_busA
, *pci_busB
;
435 PCIDevice
*ebus
, *pci_dev
;
438 qemu_irq
*ivec_irqs
, *pbm_irqs
;
439 DriveInfo
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
440 DriveInfo
*fd
[MAX_FD
];
448 cpu
= sparc64_cpu_devinit(machine
->cpu_type
, hwdef
->prom_addr
);
451 ram_init(0, machine
->ram_size
);
453 prom_init(hwdef
->prom_addr
, bios_name
);
455 ivec_irqs
= qemu_allocate_irqs(sparc64_cpu_set_ivec_irq
, cpu
, IVEC_MAX
);
456 pci_bus
= pci_apb_init(APB_SPECIAL_BASE
, APB_MEM_BASE
, ivec_irqs
, &pci_busA
,
457 &pci_busB
, &pbm_irqs
);
459 /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is
460 reserved (leaving no slots free after on-board devices) however slots
461 0-3 are free on busB */
462 pci_bus
->slot_reserved_mask
= 0xfffffffc;
463 pci_busA
->slot_reserved_mask
= 0xfffffff1;
464 pci_busB
->slot_reserved_mask
= 0xfffffff0;
466 ebus
= pci_create_multifunction(pci_busA
, PCI_DEVFN(1, 0), true, "ebus");
467 qdev_init_nofail(DEVICE(ebus
));
469 isa_bus
= pci_ebus_init(ebus
, pbm_irqs
);
472 if (hwdef
->console_serial_base
) {
473 serial_mm_init(address_space_mem
, hwdef
->console_serial_base
, 0,
474 NULL
, 115200, serial_hds
[i
], DEVICE_BIG_ENDIAN
);
478 serial_hds_isa_init(isa_bus
, i
, MAX_SERIAL_PORTS
);
479 parallel_hds_isa_init(isa_bus
, MAX_PARALLEL_PORTS
);
481 pci_dev
= pci_create_simple(pci_busA
, PCI_DEVFN(2, 0), "VGA");
483 memset(&macaddr
, 0, sizeof(MACAddr
));
485 for (i
= 0; i
< nb_nics
; i
++) {
488 if (!nd
->model
|| strcmp(nd
->model
, "sunhme") == 0) {
490 pci_dev
= pci_create_multifunction(pci_busA
, PCI_DEVFN(1, 1),
492 memcpy(&macaddr
, &nd
->macaddr
.a
, sizeof(MACAddr
));
495 pci_dev
= pci_create(pci_busB
, -1, "sunhme");
498 pci_dev
= pci_create(pci_busB
, -1, nd
->model
);
501 dev
= &pci_dev
->qdev
;
502 qdev_set_nic_properties(dev
, nd
);
503 qdev_init_nofail(dev
);
506 /* If we don't have an onboard NIC, grab a default MAC address so that
507 * we have a valid machine id */
509 qemu_macaddr_default_if_unset(&macaddr
);
512 ide_drive_get(hd
, ARRAY_SIZE(hd
));
514 pci_dev
= pci_create(pci_busA
, PCI_DEVFN(3, 0), "cmd646-ide");
515 qdev_prop_set_uint32(&pci_dev
->qdev
, "secondary", 1);
516 qdev_init_nofail(&pci_dev
->qdev
);
517 pci_ide_create_devs(pci_dev
, hd
);
519 isa_create_simple(isa_bus
, "i8042");
522 for(i
= 0; i
< MAX_FD
; i
++) {
523 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
525 dev
= DEVICE(isa_create(isa_bus
, TYPE_ISA_FDC
));
527 qdev_prop_set_drive(dev
, "driveA", blk_by_legacy_dinfo(fd
[0]),
531 qdev_prop_set_drive(dev
, "driveB", blk_by_legacy_dinfo(fd
[1]),
534 qdev_prop_set_uint32(dev
, "dma", -1);
535 qdev_init_nofail(dev
);
537 /* Map NVRAM into I/O (ebus) space */
538 nvram
= m48t59_init(NULL
, 0, 0, NVRAM_SIZE
, 1968, 59);
539 s
= SYS_BUS_DEVICE(nvram
);
540 memory_region_add_subregion(pci_address_space_io(ebus
), 0x2000,
541 sysbus_mmio_get_region(s
, 0));
545 kernel_size
= sun4u_load_kernel(machine
->kernel_filename
,
546 machine
->initrd_filename
,
547 ram_size
, &initrd_size
, &initrd_addr
,
548 &kernel_addr
, &kernel_entry
);
550 sun4u_NVRAM_set_params(nvram
, NVRAM_SIZE
, "Sun4u", machine
->ram_size
,
552 kernel_addr
, kernel_size
,
553 machine
->kernel_cmdline
,
554 initrd_addr
, initrd_size
,
555 /* XXX: need an option to load a NVRAM image */
557 graphic_width
, graphic_height
, graphic_depth
,
558 (uint8_t *)&macaddr
);
560 dev
= qdev_create(NULL
, TYPE_FW_CFG_IO
);
561 qdev_prop_set_bit(dev
, "dma_enabled", false);
562 object_property_add_child(OBJECT(ebus
), TYPE_FW_CFG
, OBJECT(dev
), NULL
);
563 qdev_init_nofail(dev
);
564 memory_region_add_subregion(pci_address_space_io(ebus
), BIOS_CFG_IOPORT
,
565 &FW_CFG_IO(dev
)->comb_iomem
);
567 fw_cfg
= FW_CFG(dev
);
568 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)smp_cpus
);
569 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)max_cpus
);
570 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
571 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
572 fw_cfg_add_i64(fw_cfg
, FW_CFG_KERNEL_ADDR
, kernel_entry
);
573 fw_cfg_add_i64(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
574 if (machine
->kernel_cmdline
) {
575 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
576 strlen(machine
->kernel_cmdline
) + 1);
577 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, machine
->kernel_cmdline
);
579 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
581 fw_cfg_add_i64(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
582 fw_cfg_add_i64(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
583 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, machine
->boot_order
[0]);
585 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_WIDTH
, graphic_width
);
586 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_HEIGHT
, graphic_height
);
587 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_DEPTH
, graphic_depth
);
589 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
597 static const struct hwdef hwdefs
[] = {
598 /* Sun4u generic PC-like machine */
600 .machine_id
= sun4u_id
,
601 .prom_addr
= 0x1fff0000000ULL
,
602 .console_serial_base
= 0,
604 /* Sun4v generic PC-like machine */
606 .machine_id
= sun4v_id
,
607 .prom_addr
= 0x1fff0000000ULL
,
608 .console_serial_base
= 0,
612 /* Sun4u hardware initialisation */
613 static void sun4u_init(MachineState
*machine
)
615 sun4uv_init(get_system_memory(), machine
, &hwdefs
[0]);
618 /* Sun4v hardware initialisation */
619 static void sun4v_init(MachineState
*machine
)
621 sun4uv_init(get_system_memory(), machine
, &hwdefs
[1]);
624 static void sun4u_class_init(ObjectClass
*oc
, void *data
)
626 MachineClass
*mc
= MACHINE_CLASS(oc
);
628 mc
->desc
= "Sun4u platform";
629 mc
->init
= sun4u_init
;
630 mc
->block_default_type
= IF_IDE
;
631 mc
->max_cpus
= 1; /* XXX for now */
633 mc
->default_boot_order
= "c";
634 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
637 static const TypeInfo sun4u_type
= {
638 .name
= MACHINE_TYPE_NAME("sun4u"),
639 .parent
= TYPE_MACHINE
,
640 .class_init
= sun4u_class_init
,
643 static void sun4v_class_init(ObjectClass
*oc
, void *data
)
645 MachineClass
*mc
= MACHINE_CLASS(oc
);
647 mc
->desc
= "Sun4v platform";
648 mc
->init
= sun4v_init
;
649 mc
->block_default_type
= IF_IDE
;
650 mc
->max_cpus
= 1; /* XXX for now */
651 mc
->default_boot_order
= "c";
652 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
655 static const TypeInfo sun4v_type
= {
656 .name
= MACHINE_TYPE_NAME("sun4v"),
657 .parent
= TYPE_MACHINE
,
658 .class_init
= sun4v_class_init
,
661 static void sun4u_register_types(void)
663 type_register_static(&ebus_info
);
664 type_register_static(&prom_info
);
665 type_register_static(&ram_info
);
667 type_register_static(&sun4u_type
);
668 type_register_static(&sun4v_type
);
671 type_init(sun4u_register_types
)