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qcow2: don't permit changing encryption parameters
[qemu/ar7.git] / hw / net / eepro100.c
bloba63ed2ca3b9173693fda7cd83a6106ac232d5bf8
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2011 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * Windows networking
28 *
29 * References:
30 *
31 * Intel 8255x 10/100 Mbps Ethernet Controller Family
32 * Open Source Software Developer Manual
33 *
34 * TODO:
35 * * PHY emulation should be separated from nic emulation.
36 * Most nic emulations could share the same phy code.
37 * * i82550 is untested. It is programmed like the i82559.
38 * * i82562 is untested. It is programmed like the i82559.
39 * * Power management (i82558 and later) is not implemented.
40 * * Wake-on-LAN is not implemented.
41 */
42
43 #include "qemu/osdep.h"
44 #include "hw/hw.h"
45 #include "hw/pci/pci.h"
46 #include "net/net.h"
47 #include "hw/nvram/eeprom93xx.h"
48 #include "sysemu/sysemu.h"
49 #include "sysemu/dma.h"
50 #include "qemu/bitops.h"
51 #include "qapi/error.h"
52
53 /* QEMU sends frames smaller than 60 bytes to ethernet nics.
54 * Such frames are rejected by real nics and their emulations.
55 * To avoid this behaviour, other nic emulations pad received
56 * frames. The following definition enables this padding for
57 * eepro100, too. We keep the define around in case it might
58 * become useful the future if the core networking is ever
59 * changed to pad short packets itself. */
60 #define CONFIG_PAD_RECEIVED_FRAMES
61
62 #define KiB 1024
63
64 /* Debug EEPRO100 card. */
65 #if 0
66 # define DEBUG_EEPRO100
67 #endif
68
69 #ifdef DEBUG_EEPRO100
70 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
71 #else
72 #define logout(fmt, ...) ((void)0)
73 #endif
74
75 /* Set flags to 0 to disable debug output. */
76 #define INT 1 /* interrupt related actions */
77 #define MDI 1 /* mdi related actions */
78 #define OTHER 1
79 #define RXTX 1
80 #define EEPROM 1 /* eeprom related actions */
81
82 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
83
84 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
85
86 #define MAX_ETH_FRAME_SIZE 1514
87
88 /* This driver supports several different devices which are declared here. */
89 #define i82550 0x82550
90 #define i82551 0x82551
91 #define i82557A 0x82557a
92 #define i82557B 0x82557b
93 #define i82557C 0x82557c
94 #define i82558A 0x82558a
95 #define i82558B 0x82558b
96 #define i82559A 0x82559a
97 #define i82559B 0x82559b
98 #define i82559C 0x82559c
99 #define i82559ER 0x82559e
100 #define i82562 0x82562
101 #define i82801 0x82801
102
103 /* Use 64 word EEPROM. TODO: could be a runtime option. */
104 #define EEPROM_SIZE 64
105
106 #define PCI_MEM_SIZE (4 * KiB)
107 #define PCI_IO_SIZE 64
108 #define PCI_FLASH_SIZE (128 * KiB)
109
110 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
111
112 /* The SCB accepts the following controls for the Tx and Rx units: */
113 #define CU_NOP 0x0000 /* No operation. */
114 #define CU_START 0x0010 /* CU start. */
115 #define CU_RESUME 0x0020 /* CU resume. */
116 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
117 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
118 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
119 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
120 #define CU_SRESUME 0x00a0 /* CU static resume. */
121
122 #define RU_NOP 0x0000
123 #define RX_START 0x0001
124 #define RX_RESUME 0x0002
125 #define RU_ABORT 0x0004
126 #define RX_ADDR_LOAD 0x0006
127 #define RX_RESUMENR 0x0007
128 #define INT_MASK 0x0100
129 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
130
131 typedef struct {
132 const char *name;
133 const char *desc;
134 uint16_t device_id;
135 uint16_t alt_device_id;
136 uint8_t revision;
137 uint16_t subsystem_vendor_id;
138 uint16_t subsystem_id;
139
140 uint32_t device;
141 uint8_t stats_size;
142 bool has_extended_tcb_support;
143 bool power_management;
144 } E100PCIDeviceInfo;
145
146 /* Offsets to the various registers.
147 All accesses need not be longword aligned. */
148 typedef enum {
149 SCBStatus = 0, /* Status Word. */
150 SCBAck = 1,
151 SCBCmd = 2, /* Rx/Command Unit command and status. */
152 SCBIntmask = 3,
153 SCBPointer = 4, /* General purpose pointer. */
154 SCBPort = 8, /* Misc. commands and operands. */
155 SCBflash = 12, /* Flash memory control. */
156 SCBeeprom = 14, /* EEPROM control. */
157 SCBCtrlMDI = 16, /* MDI interface control. */
158 SCBEarlyRx = 20, /* Early receive byte count. */
159 SCBFlow = 24, /* Flow Control. */
160 SCBpmdr = 27, /* Power Management Driver. */
161 SCBgctrl = 28, /* General Control. */
162 SCBgstat = 29, /* General Status. */
163 } E100RegisterOffset;
164
165 /* A speedo3 transmit buffer descriptor with two buffers... */
166 typedef struct {
167 uint16_t status;
168 uint16_t command;
169 uint32_t link; /* void * */
170 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
171 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
172 uint8_t tx_threshold; /* transmit threshold */
173 uint8_t tbd_count; /* TBD number */
174 #if 0
175 /* This constitutes two "TBD" entries: hdr and data */
176 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
177 int32_t tx_buf_size0; /* Length of Tx hdr. */
178 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
179 int32_t tx_buf_size1; /* Length of Tx data. */
180 #endif
181 } eepro100_tx_t;
182
183 /* Receive frame descriptor. */
184 typedef struct {
185 int16_t status;
186 uint16_t command;
187 uint32_t link; /* struct RxFD * */
188 uint32_t rx_buf_addr; /* void * */
189 uint16_t count;
190 uint16_t size;
191 /* Ethernet frame data follows. */
192 } eepro100_rx_t;
193
194 typedef enum {
195 COMMAND_EL = BIT(15),
196 COMMAND_S = BIT(14),
197 COMMAND_I = BIT(13),
198 COMMAND_NC = BIT(4),
199 COMMAND_SF = BIT(3),
200 COMMAND_CMD = BITS(2, 0),
201 } scb_command_bit;
202
203 typedef enum {
204 STATUS_C = BIT(15),
205 STATUS_OK = BIT(13),
206 } scb_status_bit;
207
208 typedef struct {
209 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
210 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
211 tx_multiple_collisions, tx_total_collisions;
212 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
213 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
214 rx_short_frame_errors;
215 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
216 uint16_t xmt_tco_frames, rcv_tco_frames;
217 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
218 uint32_t reserved[4];
219 } eepro100_stats_t;
220
221 typedef enum {
222 cu_idle = 0,
223 cu_suspended = 1,
224 cu_active = 2,
225 cu_lpq_active = 2,
226 cu_hqp_active = 3
227 } cu_state_t;
228
229 typedef enum {
230 ru_idle = 0,
231 ru_suspended = 1,
232 ru_no_resources = 2,
233 ru_ready = 4
234 } ru_state_t;
235
236 typedef struct {
237 PCIDevice dev;
238 /* Hash register (multicast mask array, multiple individual addresses). */
239 uint8_t mult[8];
240 MemoryRegion mmio_bar;
241 MemoryRegion io_bar;
242 MemoryRegion flash_bar;
243 NICState *nic;
244 NICConf conf;
245 uint8_t scb_stat; /* SCB stat/ack byte */
246 uint8_t int_stat; /* PCI interrupt status */
247 /* region must not be saved by nic_save. */
248 uint16_t mdimem[32];
249 eeprom_t *eeprom;
250 uint32_t device; /* device variant */
251 /* (cu_base + cu_offset) address the next command block in the command block list. */
252 uint32_t cu_base; /* CU base address */
253 uint32_t cu_offset; /* CU address offset */
254 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
255 uint32_t ru_base; /* RU base address */
256 uint32_t ru_offset; /* RU address offset */
257 uint32_t statsaddr; /* pointer to eepro100_stats_t */
258
259 /* Temporary status information (no need to save these values),
260 * used while processing CU commands. */
261 eepro100_tx_t tx; /* transmit buffer descriptor */
262 uint32_t cb_address; /* = cu_base + cu_offset */
263
264 /* Statistical counters. Also used for wake-up packet (i82559). */
265 eepro100_stats_t statistics;
266
267 /* Data in mem is always in the byte order of the controller (le).
268 * It must be dword aligned to allow direct access to 32 bit values. */
269 uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));
270
271 /* Configuration bytes. */
272 uint8_t configuration[22];
273
274 /* vmstate for each particular nic */
275 VMStateDescription *vmstate;
276
277 /* Quasi static device properties (no need to save them). */
278 uint16_t stats_size;
279 bool has_extended_tcb_support;
280 bool use_alt_device_id;
281 } EEPRO100State;
282
283 /* Word indices in EEPROM. */
284 typedef enum {
285 EEPROM_CNFG_MDIX = 0x03,
286 EEPROM_ID = 0x05,
287 EEPROM_PHY_ID = 0x06,
288 EEPROM_VENDOR_ID = 0x0c,
289 EEPROM_CONFIG_ASF = 0x0d,
290 EEPROM_DEVICE_ID = 0x23,
291 EEPROM_SMBUS_ADDR = 0x90,
292 } EEPROMOffset;
293
294 /* Bit values for EEPROM ID word. */
295 typedef enum {
296 EEPROM_ID_MDM = BIT(0), /* Modem */
297 EEPROM_ID_STB = BIT(1), /* Standby Enable */
298 EEPROM_ID_WMR = BIT(2), /* ??? */
299 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
300 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
301 EEPROM_ID_ALT = BIT(7), /* */
302 /* BITS(10, 8) device revision */
303 EEPROM_ID_BD = BIT(11), /* boot disable */
304 EEPROM_ID_ID = BIT(13), /* id bit */
305 /* BITS(15, 14) signature */
306 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
307 } eeprom_id_bit;
308
309 /* Default values for MDI (PHY) registers */
310 static const uint16_t eepro100_mdi_default[] = {
311 /* MDI Registers 0 - 6, 7 */
312 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
313 /* MDI Registers 8 - 15 */
314 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
315 /* MDI Registers 16 - 31 */
316 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
317 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
318 };
319
320 /* Readonly mask for MDI (PHY) registers */
321 static const uint16_t eepro100_mdi_mask[] = {
322 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
323 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
324 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
325 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
326 };
327
328 #define POLYNOMIAL 0x04c11db6
329
330 static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s);
331
332 /* From FreeBSD (locally modified). */
333 static unsigned e100_compute_mcast_idx(const uint8_t *ep)
334 {
335 uint32_t crc;
336 int carry, i, j;
337 uint8_t b;
338
339 crc = 0xffffffff;
340 for (i = 0; i < 6; i++) {
341 b = *ep++;
342 for (j = 0; j < 8; j++) {
343 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
344 crc <<= 1;
345 b >>= 1;
346 if (carry) {
347 crc = ((crc ^ POLYNOMIAL) | carry);
348 }
349 }
350 }
351 return (crc & BITS(7, 2)) >> 2;
352 }
353
354 /* Read a 16 bit control/status (CSR) register. */
355 static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
356 {
357 assert(!((uintptr_t)&s->mem[addr] & 1));
358 return lduw_le_p(&s->mem[addr]);
359 }
360
361 /* Read a 32 bit control/status (CSR) register. */
362 static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
363 {
364 assert(!((uintptr_t)&s->mem[addr] & 3));
365 return ldl_le_p(&s->mem[addr]);
366 }
367
368 /* Write a 16 bit control/status (CSR) register. */
369 static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
370 uint16_t val)
371 {
372 assert(!((uintptr_t)&s->mem[addr] & 1));
373 stw_le_p(&s->mem[addr], val);
374 }
375
376 /* Read a 32 bit control/status (CSR) register. */
377 static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
378 uint32_t val)
379 {
380 assert(!((uintptr_t)&s->mem[addr] & 3));
381 stl_le_p(&s->mem[addr], val);
382 }
383
384 #if defined(DEBUG_EEPRO100)
385 static const char *nic_dump(const uint8_t * buf, unsigned size)
386 {
387 static char dump[3 * 16 + 1];
388 char *p = &dump[0];
389 if (size > 16) {
390 size = 16;
391 }
392 while (size-- > 0) {
393 p += sprintf(p, " %02x", *buf++);
394 }
395 return dump;
396 }
397 #endif /* DEBUG_EEPRO100 */
398
399 enum scb_stat_ack {
400 stat_ack_not_ours = 0x00,
401 stat_ack_sw_gen = 0x04,
402 stat_ack_rnr = 0x10,
403 stat_ack_cu_idle = 0x20,
404 stat_ack_frame_rx = 0x40,
405 stat_ack_cu_cmd_done = 0x80,
406 stat_ack_not_present = 0xFF,
407 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
408 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
409 };
410
411 static void disable_interrupt(EEPRO100State * s)
412 {
413 if (s->int_stat) {
414 TRACE(INT, logout("interrupt disabled\n"));
415 pci_irq_deassert(&s->dev);
416 s->int_stat = 0;
417 }
418 }
419
420 static void enable_interrupt(EEPRO100State * s)
421 {
422 if (!s->int_stat) {
423 TRACE(INT, logout("interrupt enabled\n"));
424 pci_irq_assert(&s->dev);
425 s->int_stat = 1;
426 }
427 }
428
429 static void eepro100_acknowledge(EEPRO100State * s)
430 {
431 s->scb_stat &= ~s->mem[SCBAck];
432 s->mem[SCBAck] = s->scb_stat;
433 if (s->scb_stat == 0) {
434 disable_interrupt(s);
435 }
436 }
437
438 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
439 {
440 uint8_t mask = ~s->mem[SCBIntmask];
441 s->mem[SCBAck] |= status;
442 status = s->scb_stat = s->mem[SCBAck];
443 status &= (mask | 0x0f);
444 #if 0
445 status &= (~s->mem[SCBIntmask] | 0x0xf);
446 #endif
447 if (status && (mask & 0x01)) {
448 /* SCB mask and SCB Bit M do not disable interrupt. */
449 enable_interrupt(s);
450 } else if (s->int_stat) {
451 disable_interrupt(s);
452 }
453 }
454
455 static void eepro100_cx_interrupt(EEPRO100State * s)
456 {
457 /* CU completed action command. */
458 /* Transmit not ok (82557 only, not in emulation). */
459 eepro100_interrupt(s, 0x80);
460 }
461
462 static void eepro100_cna_interrupt(EEPRO100State * s)
463 {
464 /* CU left the active state. */
465 eepro100_interrupt(s, 0x20);
466 }
467
468 static void eepro100_fr_interrupt(EEPRO100State * s)
469 {
470 /* RU received a complete frame. */
471 eepro100_interrupt(s, 0x40);
472 }
473
474 static void eepro100_rnr_interrupt(EEPRO100State * s)
475 {
476 /* RU is not ready. */
477 eepro100_interrupt(s, 0x10);
478 }
479
480 static void eepro100_mdi_interrupt(EEPRO100State * s)
481 {
482 /* MDI completed read or write cycle. */
483 eepro100_interrupt(s, 0x08);
484 }
485
486 static void eepro100_swi_interrupt(EEPRO100State * s)
487 {
488 /* Software has requested an interrupt. */
489 eepro100_interrupt(s, 0x04);
490 }
491
492 #if 0
493 static void eepro100_fcp_interrupt(EEPRO100State * s)
494 {
495 /* Flow control pause interrupt (82558 and later). */
496 eepro100_interrupt(s, 0x01);
497 }
498 #endif
499
500 static void e100_pci_reset(EEPRO100State *s, Error **errp)
501 {
502 E100PCIDeviceInfo *info = eepro100_get_class(s);
503 uint32_t device = s->device;
504 uint8_t *pci_conf = s->dev.config;
505
506 TRACE(OTHER, logout("%p\n", s));
507
508 /* PCI Status */
509 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
510 PCI_STATUS_FAST_BACK);
511 /* PCI Latency Timer */
512 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
513 /* Capability Pointer is set by PCI framework. */
514 /* Interrupt Line */
515 /* Interrupt Pin */
516 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
517 /* Minimum Grant */
518 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
519 /* Maximum Latency */
520 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
521
522 s->stats_size = info->stats_size;
523 s->has_extended_tcb_support = info->has_extended_tcb_support;
524
525 switch (device) {
526 case i82550:
527 case i82551:
528 case i82557A:
529 case i82557B:
530 case i82557C:
531 case i82558A:
532 case i82558B:
533 case i82559A:
534 case i82559B:
535 case i82559ER:
536 case i82562:
537 case i82801:
538 case i82559C:
539 break;
540 default:
541 logout("Device %X is undefined!\n", device);
542 }
543
544 /* Standard TxCB. */
545 s->configuration[6] |= BIT(4);
546
547 /* Standard statistical counters. */
548 s->configuration[6] |= BIT(5);
549
550 if (s->stats_size == 80) {
551 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
552 if (s->configuration[6] & BIT(2)) {
553 /* TCO statistical counters. */
554 assert(s->configuration[6] & BIT(5));
555 } else {
556 if (s->configuration[6] & BIT(5)) {
557 /* No extended statistical counters, i82557 compatible. */
558 s->stats_size = 64;
559 } else {
560 /* i82558 compatible. */
561 s->stats_size = 76;
562 }
563 }
564 } else {
565 if (s->configuration[6] & BIT(5)) {
566 /* No extended statistical counters. */
567 s->stats_size = 64;
568 }
569 }
570 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
571
572 if (info->power_management) {
573 /* Power Management Capabilities */
574 int cfg_offset = 0xdc;
575 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
576 cfg_offset, PCI_PM_SIZEOF,
577 errp);
578 if (r < 0) {
579 return;
580 }
581
582 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
583 #if 0 /* TODO: replace dummy code for power management emulation. */
584 /* TODO: Power Management Control / Status. */
585 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
586 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
587 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
588 #endif
589 }
590
591 #if EEPROM_SIZE > 0
592 if (device == i82557C || device == i82558B || device == i82559C) {
593 /*
594 TODO: get vendor id from EEPROM for i82557C or later.
595 TODO: get device id from EEPROM for i82557C or later.
596 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
597 TODO: header type is determined by EEPROM for i82559.
598 TODO: get subsystem id from EEPROM for i82557C or later.
599 TODO: get subsystem vendor id from EEPROM for i82557C or later.
600 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
601 TODO: capability pointer depends on EEPROM for i82558.
602 */
603 logout("Get device id and revision from EEPROM!!!\n");
604 }
605 #endif /* EEPROM_SIZE > 0 */
606 }
607
608 static void nic_selective_reset(EEPRO100State * s)
609 {
610 size_t i;
611 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
612 #if 0
613 eeprom93xx_reset(s->eeprom);
614 #endif
615 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
616 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
617 if (s->device == i82557B || s->device == i82557C)
618 eeprom_contents[5] = 0x0100;
619 eeprom_contents[EEPROM_PHY_ID] = 1;
620 uint16_t sum = 0;
621 for (i = 0; i < EEPROM_SIZE - 1; i++) {
622 sum += eeprom_contents[i];
623 }
624 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
625 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
626
627 memset(s->mem, 0, sizeof(s->mem));
628 e100_write_reg4(s, SCBCtrlMDI, BIT(21));
629
630 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
631 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
632 }
633
634 static void nic_reset(void *opaque)
635 {
636 EEPRO100State *s = opaque;
637 TRACE(OTHER, logout("%p\n", s));
638 /* TODO: Clearing of hash register for selective reset, too? */
639 memset(&s->mult[0], 0, sizeof(s->mult));
640 nic_selective_reset(s);
641 }
642
643 #if defined(DEBUG_EEPRO100)
644 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
645 "Command/Status",
646 "General Pointer",
647 "Port",
648 "EEPROM/Flash Control",
649 "MDI Control",
650 "Receive DMA Byte Count",
651 "Flow Control",
652 "General Status/Control"
653 };
654
655 static char *regname(uint32_t addr)
656 {
657 static char buf[32];
658 if (addr < PCI_IO_SIZE) {
659 const char *r = e100_reg[addr / 4];
660 if (r != 0) {
661 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
662 } else {
663 snprintf(buf, sizeof(buf), "0x%02x", addr);
664 }
665 } else {
666 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
667 }
668 return buf;
669 }
670 #endif /* DEBUG_EEPRO100 */
671
672 /*****************************************************************************
673 *
674 * Command emulation.
675 *
676 ****************************************************************************/
677
678 #if 0
679 static uint16_t eepro100_read_command(EEPRO100State * s)
680 {
681 uint16_t val = 0xffff;
682 TRACE(OTHER, logout("val=0x%04x\n", val));
683 return val;
684 }
685 #endif
686
687 /* Commands that can be put in a command list entry. */
688 enum commands {
689 CmdNOp = 0,
690 CmdIASetup = 1,
691 CmdConfigure = 2,
692 CmdMulticastList = 3,
693 CmdTx = 4,
694 CmdTDR = 5, /* load microcode */
695 CmdDump = 6,
696 CmdDiagnose = 7,
697
698 /* And some extra flags: */
699 CmdSuspend = 0x4000, /* Suspend after completion. */
700 CmdIntr = 0x2000, /* Interrupt after completion. */
701 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
702 };
703
704 static cu_state_t get_cu_state(EEPRO100State * s)
705 {
706 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
707 }
708
709 static void set_cu_state(EEPRO100State * s, cu_state_t state)
710 {
711 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
712 }
713
714 static ru_state_t get_ru_state(EEPRO100State * s)
715 {
716 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
717 }
718
719 static void set_ru_state(EEPRO100State * s, ru_state_t state)
720 {
721 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
722 }
723
724 static void dump_statistics(EEPRO100State * s)
725 {
726 /* Dump statistical data. Most data is never changed by the emulation
727 * and always 0, so we first just copy the whole block and then those
728 * values which really matter.
729 * Number of data should check configuration!!!
730 */
731 pci_dma_write(&s->dev, s->statsaddr, &s->statistics, s->stats_size);
732 stl_le_pci_dma(&s->dev, s->statsaddr + 0,
733 s->statistics.tx_good_frames);
734 stl_le_pci_dma(&s->dev, s->statsaddr + 36,
735 s->statistics.rx_good_frames);
736 stl_le_pci_dma(&s->dev, s->statsaddr + 48,
737 s->statistics.rx_resource_errors);
738 stl_le_pci_dma(&s->dev, s->statsaddr + 60,
739 s->statistics.rx_short_frame_errors);
740 #if 0
741 stw_le_pci_dma(&s->dev, s->statsaddr + 76, s->statistics.xmt_tco_frames);
742 stw_le_pci_dma(&s->dev, s->statsaddr + 78, s->statistics.rcv_tco_frames);
743 missing("CU dump statistical counters");
744 #endif
745 }
746
747 static void read_cb(EEPRO100State *s)
748 {
749 pci_dma_read(&s->dev, s->cb_address, &s->tx, sizeof(s->tx));
750 s->tx.status = le16_to_cpu(s->tx.status);
751 s->tx.command = le16_to_cpu(s->tx.command);
752 s->tx.link = le32_to_cpu(s->tx.link);
753 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
754 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
755 }
756
757 static void tx_command(EEPRO100State *s)
758 {
759 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
760 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
761 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
762 uint8_t buf[2600];
763 uint16_t size = 0;
764 uint32_t tbd_address = s->cb_address + 0x10;
765 TRACE(RXTX, logout
766 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
767 tbd_array, tcb_bytes, s->tx.tbd_count));
768
769 if (tcb_bytes > 2600) {
770 logout("TCB byte count too large, using 2600\n");
771 tcb_bytes = 2600;
772 }
773 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
774 logout
775 ("illegal values of TBD array address and TCB byte count!\n");
776 }
777 assert(tcb_bytes <= sizeof(buf));
778 while (size < tcb_bytes) {
779 TRACE(RXTX, logout
780 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
781 tbd_address, tcb_bytes));
782 pci_dma_read(&s->dev, tbd_address, &buf[size], tcb_bytes);
783 size += tcb_bytes;
784 }
785 if (tbd_array == 0xffffffff) {
786 /* Simplified mode. Was already handled by code above. */
787 } else {
788 /* Flexible mode. */
789 uint8_t tbd_count = 0;
790 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
791 /* Extended Flexible TCB. */
792 for (; tbd_count < 2; tbd_count++) {
793 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev,
794 tbd_address);
795 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev,
796 tbd_address + 4);
797 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev,
798 tbd_address + 6);
799 tbd_address += 8;
800 TRACE(RXTX, logout
801 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
802 tx_buffer_address, tx_buffer_size));
803 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
804 pci_dma_read(&s->dev, tx_buffer_address,
805 &buf[size], tx_buffer_size);
806 size += tx_buffer_size;
807 if (tx_buffer_el & 1) {
808 break;
809 }
810 }
811 }
812 tbd_address = tbd_array;
813 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
814 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
815 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
816 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
817 tbd_address += 8;
818 TRACE(RXTX, logout
819 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
820 tx_buffer_address, tx_buffer_size));
821 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
822 pci_dma_read(&s->dev, tx_buffer_address,
823 &buf[size], tx_buffer_size);
824 size += tx_buffer_size;
825 if (tx_buffer_el & 1) {
826 break;
827 }
828 }
829 }
830 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
831 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
832 s->statistics.tx_good_frames++;
833 /* Transmit with bad status would raise an CX/TNO interrupt.
834 * (82557 only). Emulation never has bad status. */
835 #if 0
836 eepro100_cx_interrupt(s);
837 #endif
838 }
839
840 static void set_multicast_list(EEPRO100State *s)
841 {
842 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
843 uint16_t i;
844 memset(&s->mult[0], 0, sizeof(s->mult));
845 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
846 for (i = 0; i < multicast_count; i += 6) {
847 uint8_t multicast_addr[6];
848 pci_dma_read(&s->dev, s->cb_address + 10 + i, multicast_addr, 6);
849 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
850 unsigned mcast_idx = e100_compute_mcast_idx(multicast_addr);
851 assert(mcast_idx < 64);
852 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
853 }
854 }
855
856 static void action_command(EEPRO100State *s)
857 {
858 /* The loop below won't stop if it gets special handcrafted data.
859 Therefore we limit the number of iterations. */
860 unsigned max_loop_count = 16;
861
862 for (;;) {
863 bool bit_el;
864 bool bit_s;
865 bool bit_i;
866 bool bit_nc;
867 uint16_t ok_status = STATUS_OK;
868 s->cb_address = s->cu_base + s->cu_offset;
869 read_cb(s);
870 bit_el = ((s->tx.command & COMMAND_EL) != 0);
871 bit_s = ((s->tx.command & COMMAND_S) != 0);
872 bit_i = ((s->tx.command & COMMAND_I) != 0);
873 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
874 #if 0
875 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
876 #endif
877
878 if (max_loop_count-- == 0) {
879 /* Prevent an endless loop. */
880 logout("loop in %s:%u\n", __FILE__, __LINE__);
881 break;
882 }
883
884 s->cu_offset = s->tx.link;
885 TRACE(OTHER,
886 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
887 s->tx.status, s->tx.command, s->tx.link));
888 switch (s->tx.command & COMMAND_CMD) {
889 case CmdNOp:
890 /* Do nothing. */
891 break;
892 case CmdIASetup:
893 pci_dma_read(&s->dev, s->cb_address + 8, &s->conf.macaddr.a[0], 6);
894 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
895 break;
896 case CmdConfigure:
897 pci_dma_read(&s->dev, s->cb_address + 8,
898 &s->configuration[0], sizeof(s->configuration));
899 TRACE(OTHER, logout("configuration: %s\n",
900 nic_dump(&s->configuration[0], 16)));
901 TRACE(OTHER, logout("configuration: %s\n",
902 nic_dump(&s->configuration[16],
903 ARRAY_SIZE(s->configuration) - 16)));
904 if (s->configuration[20] & BIT(6)) {
905 TRACE(OTHER, logout("Multiple IA bit\n"));
906 }
907 break;
908 case CmdMulticastList:
909 set_multicast_list(s);
910 break;
911 case CmdTx:
912 if (bit_nc) {
913 missing("CmdTx: NC = 0");
914 ok_status = 0;
915 break;
916 }
917 tx_command(s);
918 break;
919 case CmdTDR:
920 TRACE(OTHER, logout("load microcode\n"));
921 /* Starting with offset 8, the command contains
922 * 64 dwords microcode which we just ignore here. */
923 break;
924 case CmdDiagnose:
925 TRACE(OTHER, logout("diagnose\n"));
926 /* Make sure error flag is not set. */
927 s->tx.status = 0;
928 break;
929 default:
930 missing("undefined command");
931 ok_status = 0;
932 break;
933 }
934 /* Write new status. */
935 stw_le_pci_dma(&s->dev, s->cb_address,
936 s->tx.status | ok_status | STATUS_C);
937 if (bit_i) {
938 /* CU completed action. */
939 eepro100_cx_interrupt(s);
940 }
941 if (bit_el) {
942 /* CU becomes idle. Terminate command loop. */
943 set_cu_state(s, cu_idle);
944 eepro100_cna_interrupt(s);
945 break;
946 } else if (bit_s) {
947 /* CU becomes suspended. Terminate command loop. */
948 set_cu_state(s, cu_suspended);
949 eepro100_cna_interrupt(s);
950 break;
951 } else {
952 /* More entries in list. */
953 TRACE(OTHER, logout("CU list with at least one more entry\n"));
954 }
955 }
956 TRACE(OTHER, logout("CU list empty\n"));
957 /* List is empty. Now CU is idle or suspended. */
958 }
959
960 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
961 {
962 cu_state_t cu_state;
963 switch (val) {
964 case CU_NOP:
965 /* No operation. */
966 break;
967 case CU_START:
968 cu_state = get_cu_state(s);
969 if (cu_state != cu_idle && cu_state != cu_suspended) {
970 /* Intel documentation says that CU must be idle or suspended
971 * for the CU start command. */
972 logout("unexpected CU state is %u\n", cu_state);
973 }
974 set_cu_state(s, cu_active);
975 s->cu_offset = e100_read_reg4(s, SCBPointer);
976 action_command(s);
977 break;
978 case CU_RESUME:
979 if (get_cu_state(s) != cu_suspended) {
980 logout("bad CU resume from CU state %u\n", get_cu_state(s));
981 /* Workaround for bad Linux eepro100 driver which resumes
982 * from idle state. */
983 #if 0
984 missing("cu resume");
985 #endif
986 set_cu_state(s, cu_suspended);
987 }
988 if (get_cu_state(s) == cu_suspended) {
989 TRACE(OTHER, logout("CU resuming\n"));
990 set_cu_state(s, cu_active);
991 action_command(s);
992 }
993 break;
994 case CU_STATSADDR:
995 /* Load dump counters address. */
996 s->statsaddr = e100_read_reg4(s, SCBPointer);
997 TRACE(OTHER, logout("val=0x%02x (dump counters address)\n", val));
998 if (s->statsaddr & 3) {
999 /* Memory must be Dword aligned. */
1000 logout("unaligned dump counters address\n");
1001 /* Handling of misaligned addresses is undefined.
1002 * Here we align the address by ignoring the lower bits. */
1003 /* TODO: Test unaligned dump counter address on real hardware. */
1004 s->statsaddr &= ~3;
1005 }
1006 break;
1007 case CU_SHOWSTATS:
1008 /* Dump statistical counters. */
1009 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
1010 dump_statistics(s);
1011 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa005);
1012 break;
1013 case CU_CMD_BASE:
1014 /* Load CU base. */
1015 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
1016 s->cu_base = e100_read_reg4(s, SCBPointer);
1017 break;
1018 case CU_DUMPSTATS:
1019 /* Dump and reset statistical counters. */
1020 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1021 dump_statistics(s);
1022 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa007);
1023 memset(&s->statistics, 0, sizeof(s->statistics));
1024 break;
1025 case CU_SRESUME:
1026 /* CU static resume. */
1027 missing("CU static resume");
1028 break;
1029 default:
1030 missing("Undefined CU command");
1031 }
1032 }
1033
1034 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1035 {
1036 switch (val) {
1037 case RU_NOP:
1038 /* No operation. */
1039 break;
1040 case RX_START:
1041 /* RU start. */
1042 if (get_ru_state(s) != ru_idle) {
1043 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1044 #if 0
1045 assert(!"wrong RU state");
1046 #endif
1047 }
1048 set_ru_state(s, ru_ready);
1049 s->ru_offset = e100_read_reg4(s, SCBPointer);
1050 qemu_flush_queued_packets(qemu_get_queue(s->nic));
1051 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1052 break;
1053 case RX_RESUME:
1054 /* Restart RU. */
1055 if (get_ru_state(s) != ru_suspended) {
1056 logout("RU state is %u, should be %u\n", get_ru_state(s),
1057 ru_suspended);
1058 #if 0
1059 assert(!"wrong RU state");
1060 #endif
1061 }
1062 set_ru_state(s, ru_ready);
1063 break;
1064 case RU_ABORT:
1065 /* RU abort. */
1066 if (get_ru_state(s) == ru_ready) {
1067 eepro100_rnr_interrupt(s);
1068 }
1069 set_ru_state(s, ru_idle);
1070 break;
1071 case RX_ADDR_LOAD:
1072 /* Load RU base. */
1073 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1074 s->ru_base = e100_read_reg4(s, SCBPointer);
1075 break;
1076 default:
1077 logout("val=0x%02x (undefined RU command)\n", val);
1078 missing("Undefined SU command");
1079 }
1080 }
1081
1082 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1083 {
1084 eepro100_ru_command(s, val & 0x0f);
1085 eepro100_cu_command(s, val & 0xf0);
1086 if ((val) == 0) {
1087 TRACE(OTHER, logout("val=0x%02x\n", val));
1088 }
1089 /* Clear command byte after command was accepted. */
1090 s->mem[SCBCmd] = 0;
1091 }
1092
1093 /*****************************************************************************
1094 *
1095 * EEPROM emulation.
1096 *
1097 ****************************************************************************/
1098
1099 #define EEPROM_CS 0x02
1100 #define EEPROM_SK 0x01
1101 #define EEPROM_DI 0x04
1102 #define EEPROM_DO 0x08
1103
1104 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1105 {
1106 uint16_t val = e100_read_reg2(s, SCBeeprom);
1107 if (eeprom93xx_read(s->eeprom)) {
1108 val |= EEPROM_DO;
1109 } else {
1110 val &= ~EEPROM_DO;
1111 }
1112 TRACE(EEPROM, logout("val=0x%04x\n", val));
1113 return val;
1114 }
1115
1116 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1117 {
1118 TRACE(EEPROM, logout("val=0x%02x\n", val));
1119
1120 /* mask unwritable bits */
1121 #if 0
1122 val = SET_MASKED(val, 0x31, eeprom->value);
1123 #endif
1124
1125 int eecs = ((val & EEPROM_CS) != 0);
1126 int eesk = ((val & EEPROM_SK) != 0);
1127 int eedi = ((val & EEPROM_DI) != 0);
1128 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1129 }
1130
1131 /*****************************************************************************
1132 *
1133 * MDI emulation.
1134 *
1135 ****************************************************************************/
1136
1137 #if defined(DEBUG_EEPRO100)
1138 static const char * const mdi_op_name[] = {
1139 "opcode 0",
1140 "write",
1141 "read",
1142 "opcode 3"
1143 };
1144
1145 static const char * const mdi_reg_name[] = {
1146 "Control",
1147 "Status",
1148 "PHY Identification (Word 1)",
1149 "PHY Identification (Word 2)",
1150 "Auto-Negotiation Advertisement",
1151 "Auto-Negotiation Link Partner Ability",
1152 "Auto-Negotiation Expansion"
1153 };
1154
1155 static const char *reg2name(uint8_t reg)
1156 {
1157 static char buffer[10];
1158 const char *p = buffer;
1159 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1160 p = mdi_reg_name[reg];
1161 } else {
1162 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1163 }
1164 return p;
1165 }
1166 #endif /* DEBUG_EEPRO100 */
1167
1168 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1169 {
1170 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1171
1172 #ifdef DEBUG_EEPRO100
1173 uint8_t raiseint = (val & BIT(29)) >> 29;
1174 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1175 uint8_t phy = (val & BITS(25, 21)) >> 21;
1176 uint8_t reg = (val & BITS(20, 16)) >> 16;
1177 uint16_t data = (val & BITS(15, 0));
1178 #endif
1179 /* Emulation takes no time to finish MDI transaction. */
1180 val |= BIT(28);
1181 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1182 val, raiseint, mdi_op_name[opcode], phy,
1183 reg2name(reg), data));
1184 return val;
1185 }
1186
1187 static void eepro100_write_mdi(EEPRO100State *s)
1188 {
1189 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1190 uint8_t raiseint = (val & BIT(29)) >> 29;
1191 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1192 uint8_t phy = (val & BITS(25, 21)) >> 21;
1193 uint8_t reg = (val & BITS(20, 16)) >> 16;
1194 uint16_t data = (val & BITS(15, 0));
1195 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1196 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1197 if (phy != 1) {
1198 /* Unsupported PHY address. */
1199 #if 0
1200 logout("phy must be 1 but is %u\n", phy);
1201 #endif
1202 data = 0;
1203 } else if (opcode != 1 && opcode != 2) {
1204 /* Unsupported opcode. */
1205 logout("opcode must be 1 or 2 but is %u\n", opcode);
1206 data = 0;
1207 } else if (reg > 6) {
1208 /* Unsupported register. */
1209 logout("register must be 0...6 but is %u\n", reg);
1210 data = 0;
1211 } else {
1212 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1213 val, raiseint, mdi_op_name[opcode], phy,
1214 reg2name(reg), data));
1215 if (opcode == 1) {
1216 /* MDI write */
1217 switch (reg) {
1218 case 0: /* Control Register */
1219 if (data & 0x8000) {
1220 /* Reset status and control registers to default. */
1221 s->mdimem[0] = eepro100_mdi_default[0];
1222 s->mdimem[1] = eepro100_mdi_default[1];
1223 data = s->mdimem[reg];
1224 } else {
1225 /* Restart Auto Configuration = Normal Operation */
1226 data &= ~0x0200;
1227 }
1228 break;
1229 case 1: /* Status Register */
1230 missing("not writable");
1231 break;
1232 case 2: /* PHY Identification Register (Word 1) */
1233 case 3: /* PHY Identification Register (Word 2) */
1234 missing("not implemented");
1235 break;
1236 case 4: /* Auto-Negotiation Advertisement Register */
1237 case 5: /* Auto-Negotiation Link Partner Ability Register */
1238 break;
1239 case 6: /* Auto-Negotiation Expansion Register */
1240 default:
1241 missing("not implemented");
1242 }
1243 s->mdimem[reg] &= eepro100_mdi_mask[reg];
1244 s->mdimem[reg] |= data & ~eepro100_mdi_mask[reg];
1245 } else if (opcode == 2) {
1246 /* MDI read */
1247 switch (reg) {
1248 case 0: /* Control Register */
1249 if (data & 0x8000) {
1250 /* Reset status and control registers to default. */
1251 s->mdimem[0] = eepro100_mdi_default[0];
1252 s->mdimem[1] = eepro100_mdi_default[1];
1253 }
1254 break;
1255 case 1: /* Status Register */
1256 s->mdimem[reg] |= 0x0020;
1257 break;
1258 case 2: /* PHY Identification Register (Word 1) */
1259 case 3: /* PHY Identification Register (Word 2) */
1260 case 4: /* Auto-Negotiation Advertisement Register */
1261 break;
1262 case 5: /* Auto-Negotiation Link Partner Ability Register */
1263 s->mdimem[reg] = 0x41fe;
1264 break;
1265 case 6: /* Auto-Negotiation Expansion Register */
1266 s->mdimem[reg] = 0x0001;
1267 break;
1268 }
1269 data = s->mdimem[reg];
1270 }
1271 /* Emulation takes no time to finish MDI transaction.
1272 * Set MDI bit in SCB status register. */
1273 s->mem[SCBAck] |= 0x08;
1274 val |= BIT(28);
1275 if (raiseint) {
1276 eepro100_mdi_interrupt(s);
1277 }
1278 }
1279 val = (val & 0xffff0000) + data;
1280 e100_write_reg4(s, SCBCtrlMDI, val);
1281 }
1282
1283 /*****************************************************************************
1284 *
1285 * Port emulation.
1286 *
1287 ****************************************************************************/
1288
1289 #define PORT_SOFTWARE_RESET 0
1290 #define PORT_SELFTEST 1
1291 #define PORT_SELECTIVE_RESET 2
1292 #define PORT_DUMP 3
1293 #define PORT_SELECTION_MASK 3
1294
1295 typedef struct {
1296 uint32_t st_sign; /* Self Test Signature */
1297 uint32_t st_result; /* Self Test Results */
1298 } eepro100_selftest_t;
1299
1300 static uint32_t eepro100_read_port(EEPRO100State * s)
1301 {
1302 return 0;
1303 }
1304
1305 static void eepro100_write_port(EEPRO100State *s)
1306 {
1307 uint32_t val = e100_read_reg4(s, SCBPort);
1308 uint32_t address = (val & ~PORT_SELECTION_MASK);
1309 uint8_t selection = (val & PORT_SELECTION_MASK);
1310 switch (selection) {
1311 case PORT_SOFTWARE_RESET:
1312 nic_reset(s);
1313 break;
1314 case PORT_SELFTEST:
1315 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1316 eepro100_selftest_t data;
1317 pci_dma_read(&s->dev, address, (uint8_t *) &data, sizeof(data));
1318 data.st_sign = 0xffffffff;
1319 data.st_result = 0;
1320 pci_dma_write(&s->dev, address, (uint8_t *) &data, sizeof(data));
1321 break;
1322 case PORT_SELECTIVE_RESET:
1323 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1324 nic_selective_reset(s);
1325 break;
1326 default:
1327 logout("val=0x%08x\n", val);
1328 missing("unknown port selection");
1329 }
1330 }
1331
1332 /*****************************************************************************
1333 *
1334 * General hardware emulation.
1335 *
1336 ****************************************************************************/
1337
1338 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1339 {
1340 uint8_t val = 0;
1341 if (addr <= sizeof(s->mem) - sizeof(val)) {
1342 val = s->mem[addr];
1343 }
1344
1345 switch (addr) {
1346 case SCBStatus:
1347 case SCBAck:
1348 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1349 break;
1350 case SCBCmd:
1351 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1352 #if 0
1353 val = eepro100_read_command(s);
1354 #endif
1355 break;
1356 case SCBIntmask:
1357 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1358 break;
1359 case SCBPort + 3:
1360 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1361 break;
1362 case SCBeeprom:
1363 val = eepro100_read_eeprom(s);
1364 break;
1365 case SCBCtrlMDI:
1366 case SCBCtrlMDI + 1:
1367 case SCBCtrlMDI + 2:
1368 case SCBCtrlMDI + 3:
1369 val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1370 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1371 break;
1372 case SCBpmdr: /* Power Management Driver Register */
1373 val = 0;
1374 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1375 break;
1376 case SCBgctrl: /* General Control Register */
1377 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1378 break;
1379 case SCBgstat: /* General Status Register */
1380 /* 100 Mbps full duplex, valid link */
1381 val = 0x07;
1382 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1383 break;
1384 default:
1385 logout("addr=%s val=0x%02x\n", regname(addr), val);
1386 missing("unknown byte read");
1387 }
1388 return val;
1389 }
1390
1391 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1392 {
1393 uint16_t val = 0;
1394 if (addr <= sizeof(s->mem) - sizeof(val)) {
1395 val = e100_read_reg2(s, addr);
1396 }
1397
1398 switch (addr) {
1399 case SCBStatus:
1400 case SCBCmd:
1401 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1402 break;
1403 case SCBeeprom:
1404 val = eepro100_read_eeprom(s);
1405 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1406 break;
1407 case SCBCtrlMDI:
1408 case SCBCtrlMDI + 2:
1409 val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1410 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1411 break;
1412 default:
1413 logout("addr=%s val=0x%04x\n", regname(addr), val);
1414 missing("unknown word read");
1415 }
1416 return val;
1417 }
1418
1419 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1420 {
1421 uint32_t val = 0;
1422 if (addr <= sizeof(s->mem) - sizeof(val)) {
1423 val = e100_read_reg4(s, addr);
1424 }
1425
1426 switch (addr) {
1427 case SCBStatus:
1428 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1429 break;
1430 case SCBPointer:
1431 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1432 break;
1433 case SCBPort:
1434 val = eepro100_read_port(s);
1435 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1436 break;
1437 case SCBflash:
1438 val = eepro100_read_eeprom(s);
1439 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1440 break;
1441 case SCBCtrlMDI:
1442 val = eepro100_read_mdi(s);
1443 break;
1444 default:
1445 logout("addr=%s val=0x%08x\n", regname(addr), val);
1446 missing("unknown longword read");
1447 }
1448 return val;
1449 }
1450
1451 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1452 {
1453 /* SCBStatus is readonly. */
1454 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1455 s->mem[addr] = val;
1456 }
1457
1458 switch (addr) {
1459 case SCBStatus:
1460 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1461 break;
1462 case SCBAck:
1463 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1464 eepro100_acknowledge(s);
1465 break;
1466 case SCBCmd:
1467 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1468 eepro100_write_command(s, val);
1469 break;
1470 case SCBIntmask:
1471 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1472 if (val & BIT(1)) {
1473 eepro100_swi_interrupt(s);
1474 }
1475 eepro100_interrupt(s, 0);
1476 break;
1477 case SCBPointer:
1478 case SCBPointer + 1:
1479 case SCBPointer + 2:
1480 case SCBPointer + 3:
1481 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1482 break;
1483 case SCBPort:
1484 case SCBPort + 1:
1485 case SCBPort + 2:
1486 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1487 break;
1488 case SCBPort + 3:
1489 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1490 eepro100_write_port(s);
1491 break;
1492 case SCBFlow: /* does not exist on 82557 */
1493 case SCBFlow + 1:
1494 case SCBFlow + 2:
1495 case SCBpmdr: /* does not exist on 82557 */
1496 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1497 break;
1498 case SCBeeprom:
1499 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1500 eepro100_write_eeprom(s->eeprom, val);
1501 break;
1502 case SCBCtrlMDI:
1503 case SCBCtrlMDI + 1:
1504 case SCBCtrlMDI + 2:
1505 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1506 break;
1507 case SCBCtrlMDI + 3:
1508 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1509 eepro100_write_mdi(s);
1510 break;
1511 default:
1512 logout("addr=%s val=0x%02x\n", regname(addr), val);
1513 missing("unknown byte write");
1514 }
1515 }
1516
1517 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1518 {
1519 /* SCBStatus is readonly. */
1520 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1521 e100_write_reg2(s, addr, val);
1522 }
1523
1524 switch (addr) {
1525 case SCBStatus:
1526 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1527 s->mem[SCBAck] = (val >> 8);
1528 eepro100_acknowledge(s);
1529 break;
1530 case SCBCmd:
1531 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1532 eepro100_write_command(s, val);
1533 eepro100_write1(s, SCBIntmask, val >> 8);
1534 break;
1535 case SCBPointer:
1536 case SCBPointer + 2:
1537 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1538 break;
1539 case SCBPort:
1540 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1541 break;
1542 case SCBPort + 2:
1543 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1544 eepro100_write_port(s);
1545 break;
1546 case SCBeeprom:
1547 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1548 eepro100_write_eeprom(s->eeprom, val);
1549 break;
1550 case SCBCtrlMDI:
1551 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1552 break;
1553 case SCBCtrlMDI + 2:
1554 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1555 eepro100_write_mdi(s);
1556 break;
1557 default:
1558 logout("addr=%s val=0x%04x\n", regname(addr), val);
1559 missing("unknown word write");
1560 }
1561 }
1562
1563 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1564 {
1565 if (addr <= sizeof(s->mem) - sizeof(val)) {
1566 e100_write_reg4(s, addr, val);
1567 }
1568
1569 switch (addr) {
1570 case SCBPointer:
1571 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1572 break;
1573 case SCBPort:
1574 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1575 eepro100_write_port(s);
1576 break;
1577 case SCBflash:
1578 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1579 val = val >> 16;
1580 eepro100_write_eeprom(s->eeprom, val);
1581 break;
1582 case SCBCtrlMDI:
1583 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1584 eepro100_write_mdi(s);
1585 break;
1586 default:
1587 logout("addr=%s val=0x%08x\n", regname(addr), val);
1588 missing("unknown longword write");
1589 }
1590 }
1591
1592 static uint64_t eepro100_read(void *opaque, hwaddr addr,
1593 unsigned size)
1594 {
1595 EEPRO100State *s = opaque;
1596
1597 switch (size) {
1598 case 1: return eepro100_read1(s, addr);
1599 case 2: return eepro100_read2(s, addr);
1600 case 4: return eepro100_read4(s, addr);
1601 default: abort();
1602 }
1603 }
1604
1605 static void eepro100_write(void *opaque, hwaddr addr,
1606 uint64_t data, unsigned size)
1607 {
1608 EEPRO100State *s = opaque;
1609
1610 switch (size) {
1611 case 1:
1612 eepro100_write1(s, addr, data);
1613 break;
1614 case 2:
1615 eepro100_write2(s, addr, data);
1616 break;
1617 case 4:
1618 eepro100_write4(s, addr, data);
1619 break;
1620 default:
1621 abort();
1622 }
1623 }
1624
1625 static const MemoryRegionOps eepro100_ops = {
1626 .read = eepro100_read,
1627 .write = eepro100_write,
1628 .endianness = DEVICE_LITTLE_ENDIAN,
1629 };
1630
1631 static ssize_t nic_receive(NetClientState *nc, const uint8_t * buf, size_t size)
1632 {
1633 /* TODO:
1634 * - Magic packets should set bit 30 in power management driver register.
1635 * - Interesting packets should set bit 29 in power management driver register.
1636 */
1637 EEPRO100State *s = qemu_get_nic_opaque(nc);
1638 uint16_t rfd_status = 0xa000;
1639 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1640 uint8_t min_buf[60];
1641 #endif
1642 static const uint8_t broadcast_macaddr[6] =
1643 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1644
1645 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1646 /* Pad to minimum Ethernet frame length */
1647 if (size < sizeof(min_buf)) {
1648 memcpy(min_buf, buf, size);
1649 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1650 buf = min_buf;
1651 size = sizeof(min_buf);
1652 }
1653 #endif
1654
1655 if (s->configuration[8] & 0x80) {
1656 /* CSMA is disabled. */
1657 logout("%p received while CSMA is disabled\n", s);
1658 return -1;
1659 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1660 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1661 /* Short frame and configuration byte 7/0 (discard short receive) set:
1662 * Short frame is discarded */
1663 logout("%p received short frame (%zu byte)\n", s, size);
1664 s->statistics.rx_short_frame_errors++;
1665 return -1;
1666 #endif
1667 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1668 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1669 * Long frames are discarded. */
1670 logout("%p received long frame (%zu byte), ignored\n", s, size);
1671 return -1;
1672 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1673 /* Frame matches individual address. */
1674 /* TODO: check configuration byte 15/4 (ignore U/L). */
1675 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1676 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1677 /* Broadcast frame. */
1678 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1679 rfd_status |= 0x0002;
1680 } else if (buf[0] & 0x01) {
1681 /* Multicast frame. */
1682 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1683 if (s->configuration[21] & BIT(3)) {
1684 /* Multicast all bit is set, receive all multicast frames. */
1685 } else {
1686 unsigned mcast_idx = e100_compute_mcast_idx(buf);
1687 assert(mcast_idx < 64);
1688 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1689 /* Multicast frame is allowed in hash table. */
1690 } else if (s->configuration[15] & BIT(0)) {
1691 /* Promiscuous: receive all. */
1692 rfd_status |= 0x0004;
1693 } else {
1694 TRACE(RXTX, logout("%p multicast ignored\n", s));
1695 return -1;
1696 }
1697 }
1698 /* TODO: Next not for promiscuous mode? */
1699 rfd_status |= 0x0002;
1700 } else if (s->configuration[15] & BIT(0)) {
1701 /* Promiscuous: receive all. */
1702 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1703 rfd_status |= 0x0004;
1704 } else if (s->configuration[20] & BIT(6)) {
1705 /* Multiple IA bit set. */
1706 unsigned mcast_idx = compute_mcast_idx(buf);
1707 assert(mcast_idx < 64);
1708 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1709 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1710 } else {
1711 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1712 return -1;
1713 }
1714 } else {
1715 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1716 nic_dump(buf, size)));
1717 return size;
1718 }
1719
1720 if (get_ru_state(s) != ru_ready) {
1721 /* No resources available. */
1722 logout("no resources, state=%u\n", get_ru_state(s));
1723 /* TODO: RNR interrupt only at first failed frame? */
1724 eepro100_rnr_interrupt(s);
1725 s->statistics.rx_resource_errors++;
1726 #if 0
1727 assert(!"no resources");
1728 #endif
1729 return -1;
1730 }
1731 /* !!! */
1732 eepro100_rx_t rx;
1733 pci_dma_read(&s->dev, s->ru_base + s->ru_offset,
1734 &rx, sizeof(eepro100_rx_t));
1735 uint16_t rfd_command = le16_to_cpu(rx.command);
1736 uint16_t rfd_size = le16_to_cpu(rx.size);
1737
1738 if (size > rfd_size) {
1739 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1740 "(%zu bytes); data truncated\n", rfd_size, size);
1741 size = rfd_size;
1742 }
1743 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1744 if (size < 64) {
1745 rfd_status |= 0x0080;
1746 }
1747 #endif
1748 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1749 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1750 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1751 offsetof(eepro100_rx_t, status), rfd_status);
1752 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1753 offsetof(eepro100_rx_t, count), size);
1754 /* Early receive interrupt not supported. */
1755 #if 0
1756 eepro100_er_interrupt(s);
1757 #endif
1758 /* Receive CRC Transfer not supported. */
1759 if (s->configuration[18] & BIT(2)) {
1760 missing("Receive CRC Transfer");
1761 return -1;
1762 }
1763 /* TODO: check stripping enable bit. */
1764 #if 0
1765 assert(!(s->configuration[17] & BIT(0)));
1766 #endif
1767 pci_dma_write(&s->dev, s->ru_base + s->ru_offset +
1768 sizeof(eepro100_rx_t), buf, size);
1769 s->statistics.rx_good_frames++;
1770 eepro100_fr_interrupt(s);
1771 s->ru_offset = le32_to_cpu(rx.link);
1772 if (rfd_command & COMMAND_EL) {
1773 /* EL bit is set, so this was the last frame. */
1774 logout("receive: Running out of frames\n");
1775 set_ru_state(s, ru_no_resources);
1776 eepro100_rnr_interrupt(s);
1777 }
1778 if (rfd_command & COMMAND_S) {
1779 /* S bit is set. */
1780 set_ru_state(s, ru_suspended);
1781 }
1782 return size;
1783 }
1784
1785 static const VMStateDescription vmstate_eepro100 = {
1786 .version_id = 3,
1787 .minimum_version_id = 2,
1788 .fields = (VMStateField[]) {
1789 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1790 VMSTATE_UNUSED(32),
1791 VMSTATE_BUFFER(mult, EEPRO100State),
1792 VMSTATE_BUFFER(mem, EEPRO100State),
1793 /* Save all members of struct between scb_stat and mem. */
1794 VMSTATE_UINT8(scb_stat, EEPRO100State),
1795 VMSTATE_UINT8(int_stat, EEPRO100State),
1796 VMSTATE_UNUSED(3*4),
1797 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1798 VMSTATE_UNUSED(19*4),
1799 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1800 /* The eeprom should be saved and restored by its own routines. */
1801 VMSTATE_UINT32(device, EEPRO100State),
1802 /* TODO check device. */
1803 VMSTATE_UINT32(cu_base, EEPRO100State),
1804 VMSTATE_UINT32(cu_offset, EEPRO100State),
1805 VMSTATE_UINT32(ru_base, EEPRO100State),
1806 VMSTATE_UINT32(ru_offset, EEPRO100State),
1807 VMSTATE_UINT32(statsaddr, EEPRO100State),
1808 /* Save eepro100_stats_t statistics. */
1809 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1810 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1811 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1812 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1813 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1814 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1815 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1816 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1817 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1818 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1819 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1820 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1821 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1822 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1823 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1824 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1825 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1826 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1827 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1828 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1829 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1830 /* Configuration bytes. */
1831 VMSTATE_BUFFER(configuration, EEPRO100State),
1832 VMSTATE_END_OF_LIST()
1833 }
1834 };
1835
1836 static void pci_nic_uninit(PCIDevice *pci_dev)
1837 {
1838 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1839
1840 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
1841 g_free(s->vmstate);
1842 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
1843 qemu_del_nic(s->nic);
1844 }
1845
1846 static NetClientInfo net_eepro100_info = {
1847 .type = NET_CLIENT_DRIVER_NIC,
1848 .size = sizeof(NICState),
1849 .receive = nic_receive,
1850 };
1851
1852 static void e100_nic_realize(PCIDevice *pci_dev, Error **errp)
1853 {
1854 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1855 E100PCIDeviceInfo *info = eepro100_get_class(s);
1856 Error *local_err = NULL;
1857
1858 TRACE(OTHER, logout("\n"));
1859
1860 /* By default, the i82559a adapter uses the legacy PCI ID (for the
1861 * i82557). This allows the PCI ID to be changed to the alternate
1862 * i82559 ID if needed.
1863 */
1864 if (s->use_alt_device_id && strcmp(info->name, "i82559a") == 0) {
1865 pci_config_set_device_id(s->dev.config, info->alt_device_id);
1866 }
1867
1868 s->device = info->device;
1869
1870 e100_pci_reset(s, &local_err);
1871 if (local_err) {
1872 error_propagate(errp, local_err);
1873 return;
1874 }
1875
1876 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1877 * i82559 and later support 64 or 256 word EEPROM. */
1878 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
1879
1880 /* Handler for memory-mapped I/O */
1881 memory_region_init_io(&s->mmio_bar, OBJECT(s), &eepro100_ops, s,
1882 "eepro100-mmio", PCI_MEM_SIZE);
1883 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar);
1884 memory_region_init_io(&s->io_bar, OBJECT(s), &eepro100_ops, s,
1885 "eepro100-io", PCI_IO_SIZE);
1886 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1887 /* FIXME: flash aliases to mmio?! */
1888 memory_region_init_io(&s->flash_bar, OBJECT(s), &eepro100_ops, s,
1889 "eepro100-flash", PCI_FLASH_SIZE);
1890 pci_register_bar(&s->dev, 2, 0, &s->flash_bar);
1891
1892 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1893 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1894
1895 nic_reset(s);
1896
1897 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1898 object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
1899
1900 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1901 TRACE(OTHER, logout("%s\n", qemu_get_queue(s->nic)->info_str));
1902
1903 qemu_register_reset(nic_reset, s);
1904
1905 s->vmstate = g_memdup(&vmstate_eepro100, sizeof(vmstate_eepro100));
1906 s->vmstate->name = qemu_get_queue(s->nic)->model;
1907 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
1908 }
1909
1910 static void eepro100_instance_init(Object *obj)
1911 {
1912 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, PCI_DEVICE(obj));
1913 device_add_bootindex_property(obj, &s->conf.bootindex,
1914 "bootindex", "/ethernet-phy@0",
1915 DEVICE(s), NULL);
1916 }
1917
1918 static E100PCIDeviceInfo e100_devices[] = {
1919 {
1920 .name = "i82550",
1921 .desc = "Intel i82550 Ethernet",
1922 .device = i82550,
1923 /* TODO: check device id. */
1924 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1925 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1926 .revision = 0x0e,
1927 /* TODO: check size of statistical counters. */
1928 .stats_size = 80,
1929 /* TODO: check extended tcb support. */
1930 .has_extended_tcb_support = true,
1931 .power_management = true,
1932 },{
1933 .name = "i82551",
1934 .desc = "Intel i82551 Ethernet",
1935 .device = i82551,
1936 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1937 /* Revision ID: 0x0f, 0x10. */
1938 .revision = 0x0f,
1939 /* TODO: check size of statistical counters. */
1940 .stats_size = 80,
1941 .has_extended_tcb_support = true,
1942 .power_management = true,
1943 },{
1944 .name = "i82557a",
1945 .desc = "Intel i82557A Ethernet",
1946 .device = i82557A,
1947 .device_id = PCI_DEVICE_ID_INTEL_82557,
1948 .revision = 0x01,
1949 .power_management = false,
1950 },{
1951 .name = "i82557b",
1952 .desc = "Intel i82557B Ethernet",
1953 .device = i82557B,
1954 .device_id = PCI_DEVICE_ID_INTEL_82557,
1955 .revision = 0x02,
1956 .power_management = false,
1957 },{
1958 .name = "i82557c",
1959 .desc = "Intel i82557C Ethernet",
1960 .device = i82557C,
1961 .device_id = PCI_DEVICE_ID_INTEL_82557,
1962 .revision = 0x03,
1963 .power_management = false,
1964 },{
1965 .name = "i82558a",
1966 .desc = "Intel i82558A Ethernet",
1967 .device = i82558A,
1968 .device_id = PCI_DEVICE_ID_INTEL_82557,
1969 .revision = 0x04,
1970 .stats_size = 76,
1971 .has_extended_tcb_support = true,
1972 .power_management = true,
1973 },{
1974 .name = "i82558b",
1975 .desc = "Intel i82558B Ethernet",
1976 .device = i82558B,
1977 .device_id = PCI_DEVICE_ID_INTEL_82557,
1978 .revision = 0x05,
1979 .stats_size = 76,
1980 .has_extended_tcb_support = true,
1981 .power_management = true,
1982 },{
1983 .name = "i82559a",
1984 .desc = "Intel i82559A Ethernet",
1985 .device = i82559A,
1986 .device_id = PCI_DEVICE_ID_INTEL_82557,
1987 .alt_device_id = PCI_DEVICE_ID_INTEL_82559,
1988 .revision = 0x06,
1989 .stats_size = 80,
1990 .has_extended_tcb_support = true,
1991 .power_management = true,
1992 },{
1993 .name = "i82559b",
1994 .desc = "Intel i82559B Ethernet",
1995 .device = i82559B,
1996 .device_id = PCI_DEVICE_ID_INTEL_82557,
1997 .revision = 0x07,
1998 .stats_size = 80,
1999 .has_extended_tcb_support = true,
2000 .power_management = true,
2001 },{
2002 .name = "i82559c",
2003 .desc = "Intel i82559C Ethernet",
2004 .device = i82559C,
2005 .device_id = PCI_DEVICE_ID_INTEL_82557,
2006 #if 0
2007 .revision = 0x08,
2008 #endif
2009 /* TODO: Windows wants revision id 0x0c. */
2010 .revision = 0x0c,
2011 #if EEPROM_SIZE > 0
2012 .subsystem_vendor_id = PCI_VENDOR_ID_INTEL,
2013 .subsystem_id = 0x0040,
2014 #endif
2015 .stats_size = 80,
2016 .has_extended_tcb_support = true,
2017 .power_management = true,
2018 },{
2019 .name = "i82559er",
2020 .desc = "Intel i82559ER Ethernet",
2021 .device = i82559ER,
2022 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2023 .revision = 0x09,
2024 .stats_size = 80,
2025 .has_extended_tcb_support = true,
2026 .power_management = true,
2027 },{
2028 .name = "i82562",
2029 .desc = "Intel i82562 Ethernet",
2030 .device = i82562,
2031 /* TODO: check device id. */
2032 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2033 /* TODO: wrong revision id. */
2034 .revision = 0x0e,
2035 .stats_size = 80,
2036 .has_extended_tcb_support = true,
2037 .power_management = true,
2038 },{
2039 /* Toshiba Tecra 8200. */
2040 .name = "i82801",
2041 .desc = "Intel i82801 Ethernet",
2042 .device = i82801,
2043 .device_id = 0x2449,
2044 .revision = 0x03,
2045 .stats_size = 80,
2046 .has_extended_tcb_support = true,
2047 .power_management = true,
2048 }
2049 };
2050
2051 static E100PCIDeviceInfo *eepro100_get_class_by_name(const char *typename)
2052 {
2053 E100PCIDeviceInfo *info = NULL;
2054 int i;
2055
2056 /* This is admittedly awkward but also temporary. QOM allows for
2057 * parameterized typing and for subclassing both of which would suitable
2058 * handle what's going on here. But class_data is already being used as
2059 * a stop-gap hack to allow incremental qdev conversion so we cannot use it
2060 * right now. Once we merge the final QOM series, we can come back here and
2061 * do this in a much more elegant fashion.
2062 */
2063 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2064 if (strcmp(e100_devices[i].name, typename) == 0) {
2065 info = &e100_devices[i];
2066 break;
2067 }
2068 }
2069 assert(info != NULL);
2070
2071 return info;
2072 }
2073
2074 static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s)
2075 {
2076 return eepro100_get_class_by_name(object_get_typename(OBJECT(s)));
2077 }
2078
2079 static Property e100_properties[] = {
2080 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2081 DEFINE_PROP_BOOL("x-use-alt-device-id", EEPRO100State, use_alt_device_id,
2082 true),
2083 DEFINE_PROP_END_OF_LIST(),
2084 };
2085
2086 static void eepro100_class_init(ObjectClass *klass, void *data)
2087 {
2088 DeviceClass *dc = DEVICE_CLASS(klass);
2089 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2090 E100PCIDeviceInfo *info;
2091
2092 info = eepro100_get_class_by_name(object_class_get_name(klass));
2093
2094 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
2095 dc->props = e100_properties;
2096 dc->desc = info->desc;
2097 k->vendor_id = PCI_VENDOR_ID_INTEL;
2098 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
2099 k->romfile = "pxe-eepro100.rom";
2100 k->realize = e100_nic_realize;
2101 k->exit = pci_nic_uninit;
2102 k->device_id = info->device_id;
2103 k->revision = info->revision;
2104 k->subsystem_vendor_id = info->subsystem_vendor_id;
2105 k->subsystem_id = info->subsystem_id;
2106 }
2107
2108 static void eepro100_register_types(void)
2109 {
2110 size_t i;
2111 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2112 TypeInfo type_info = {};
2113 E100PCIDeviceInfo *info = &e100_devices[i];
2114
2115 type_info.name = info->name;
2116 type_info.parent = TYPE_PCI_DEVICE;
2117 type_info.class_init = eepro100_class_init;
2118 type_info.instance_size = sizeof(EEPRO100State);
2119 type_info.instance_init = eepro100_instance_init;
2120 type_info.interfaces = (InterfaceInfo[]) {
2121 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2122 { },
2123 };
2124
2125 type_register(&type_info);
2126 }
2127 }
2128
2129 type_init(eepro100_register_types)
AR7 emulation for QEMU