hw/arm/msf2-soc.c

   1 /*
   2  * SmartFusion2 SoC emulation.
   3  *
   4  * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "qapi/error.h"
  28 #include "exec/address-spaces.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/irq.h"
  31 #include "hw/arm/msf2-soc.h"
  32 #include "hw/misc/unimp.h"
  33 #include "sysemu/runstate.h"
  34 #include "sysemu/sysemu.h"
  35
  36 #define MSF2_TIMER_BASE       0x40004000
  37 #define MSF2_SYSREG_BASE      0x40038000
  38
  39 #define ENVM_BASE_ADDRESS     0x60000000
  40
  41 #define SRAM_BASE_ADDRESS     0x20000000
  42
  43 #define MSF2_ENVM_MAX_SIZE    (512 * KiB)
  44
  45 /*
  46  * eSRAM max size is 80k without SECDED(Single error correction and
  47  * dual error detection) feature and 64k with SECDED.
  48  * We do not support SECDED now.
  49  */
  50 #define MSF2_ESRAM_MAX_SIZE       (80 * KiB)
  51
  52 static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
  53 static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
  54
  55 static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
  56 static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
  57 static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
  58
  59 static void do_sys_reset(void *opaque, int n, int level)
  60 {
  61     if (level) {
  62         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
  63     }
  64 }
  65
  66 static void m2sxxx_soc_initfn(Object *obj)
  67 {
  68     MSF2State *s = MSF2_SOC(obj);
  69     int i;
  70
  71     sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
  72                           TYPE_ARMV7M);
  73
  74     sysbus_init_child_obj(obj, "sysreg", &s->sysreg, sizeof(s->sysreg),
  75                           TYPE_MSF2_SYSREG);
  76
  77     sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
  78                           TYPE_MSS_TIMER);
  79
  80     for (i = 0; i < MSF2_NUM_SPIS; i++) {
  81         sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
  82                           TYPE_MSS_SPI);
  83     }
  84 }
  85
  86 static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
  87 {
  88     MSF2State *s = MSF2_SOC(dev_soc);
  89     DeviceState *dev, *armv7m;
  90     SysBusDevice *busdev;
  91     Error *err = NULL;
  92     int i;
  93
  94     MemoryRegion *system_memory = get_system_memory();
  95     MemoryRegion *nvm = g_new(MemoryRegion, 1);
  96     MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
  97     MemoryRegion *sram = g_new(MemoryRegion, 1);
  98
  99     memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
 100                            &error_fatal);
 101     /*
 102      * On power-on, the eNVM region 0x60000000 is automatically
 103      * remapped to the Cortex-M3 processor executable region
 104      * start address (0x0). We do not support remapping other eNVM,
 105      * eSRAM and DDR regions by guest(via Sysreg) currently.
 106      */
 107     memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM",
 108                              nvm, 0, s->envm_size);
 109
 110     memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
 111     memory_region_add_subregion(system_memory, 0, nvm_alias);
 112
 113     memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
 114                            &error_fatal);
 115     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
 116
 117     armv7m = DEVICE(&s->armv7m);
 118     qdev_prop_set_uint32(armv7m, "num-irq", 81);
 119     qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
 120     qdev_prop_set_bit(armv7m, "enable-bitband", true);
 121     object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
 122                                      "memory", &error_abort);
 123     object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
 124     if (err != NULL) {
 125         error_propagate(errp, err);
 126         return;
 127     }
 128
 129     if (!s->m3clk) {
 130         error_setg(errp, "Invalid m3clk value");
 131         error_append_hint(errp, "m3clk can not be zero\n");
 132         return;
 133     }
 134
 135     qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
 136                                 qemu_allocate_irq(&do_sys_reset, NULL, 0));
 137
 138     system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
 139
 140     for (i = 0; i < MSF2_NUM_UARTS; i++) {
 141         if (serial_hd(i)) {
 142             serial_mm_init(get_system_memory(), uart_addr[i], 2,
 143                            qdev_get_gpio_in(armv7m, uart_irq[i]),
 144                            115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
 145         }
 146     }
 147
 148     dev = DEVICE(&s->timer);
 149     /* APB0 clock is the timer input clock */
 150     qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
 151     object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
 152     if (err != NULL) {
 153         error_propagate(errp, err);
 154         return;
 155     }
 156     busdev = SYS_BUS_DEVICE(dev);
 157     sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
 158     sysbus_connect_irq(busdev, 0,
 159                            qdev_get_gpio_in(armv7m, timer_irq[0]));
 160     sysbus_connect_irq(busdev, 1,
 161                            qdev_get_gpio_in(armv7m, timer_irq[1]));
 162
 163     dev = DEVICE(&s->sysreg);
 164     qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
 165     qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
 166     object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
 167     if (err != NULL) {
 168         error_propagate(errp, err);
 169         return;
 170     }
 171     busdev = SYS_BUS_DEVICE(dev);
 172     sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
 173
 174     for (i = 0; i < MSF2_NUM_SPIS; i++) {
 175         gchar *bus_name;
 176
 177         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 178         if (err != NULL) {
 179             error_propagate(errp, err);
 180             return;
 181         }
 182
 183         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
 184         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 185                            qdev_get_gpio_in(armv7m, spi_irq[i]));
 186
 187         /* Alias controller SPI bus to the SoC itself */
 188         bus_name = g_strdup_printf("spi%d", i);
 189         object_property_add_alias(OBJECT(s), bus_name,
 190                                   OBJECT(&s->spi[i]), "spi",
 191                                   &error_abort);
 192         g_free(bus_name);
 193     }
 194
 195     /* Below devices are not modelled yet. */
 196     create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
 197     create_unimplemented_device("dma", 0x40003000, 0x1000);
 198     create_unimplemented_device("watchdog", 0x40005000, 0x1000);
 199     create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
 200     create_unimplemented_device("gpio", 0x40013000, 0x1000);
 201     create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
 202     create_unimplemented_device("can", 0x40015000, 0x1000);
 203     create_unimplemented_device("rtc", 0x40017000, 0x1000);
 204     create_unimplemented_device("apb_config", 0x40020000, 0x10000);
 205     create_unimplemented_device("emac", 0x40041000, 0x1000);
 206     create_unimplemented_device("usb", 0x40043000, 0x1000);
 207 }
 208
 209 static Property m2sxxx_soc_properties[] = {
 210     /*
 211      * part name specifies the type of SmartFusion2 device variant(this
 212      * property is for information purpose only.
 213      */
 214     DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
 215     DEFINE_PROP_STRING("part-name", MSF2State, part_name),
 216     DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
 217     DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
 218                         MSF2_ESRAM_MAX_SIZE),
 219     /* Libero GUI shows 100Mhz as default for clocks */
 220     DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
 221     /* default divisors in Libero GUI */
 222     DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
 223     DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
 224     DEFINE_PROP_END_OF_LIST(),
 225 };
 226
 227 static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
 228 {
 229     DeviceClass *dc = DEVICE_CLASS(klass);
 230
 231     dc->realize = m2sxxx_soc_realize;
 232     device_class_set_props(dc, m2sxxx_soc_properties);
 233 }
 234
 235 static const TypeInfo m2sxxx_soc_info = {
 236     .name          = TYPE_MSF2_SOC,
 237     .parent        = TYPE_SYS_BUS_DEVICE,
 238     .instance_size = sizeof(MSF2State),
 239     .instance_init = m2sxxx_soc_initfn,
 240     .class_init    = m2sxxx_soc_class_init,
 241 };
 242
 243 static void m2sxxx_soc_types(void)
 244 {
 245     type_register_static(&m2sxxx_soc_info);
 246 }
 247
 248 type_init(m2sxxx_soc_types)