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libqos: move useful qos-test funcs to qos_external
[qemu/ar7.git] / hw / arm / fsl-imx6.c
blobecc62855f2b0b3fcd1971a63ae5f9f3e38689cb5
1 /*
2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX6 SOC emulation.
5 *
6 * Based on hw/arm/fsl-imx31.c
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "hw/arm/fsl-imx6.h"
25 #include "hw/boards.h"
26 #include "hw/qdev-properties.h"
27 #include "sysemu/sysemu.h"
28 #include "chardev/char.h"
29 #include "qemu/error-report.h"
30 #include "qemu/module.h"
31
32 #define IMX6_ESDHC_CAPABILITIES 0x057834b4
33
34 #define NAME_SIZE 20
35
36 static void fsl_imx6_init(Object *obj)
37 {
38 MachineState *ms = MACHINE(qdev_get_machine());
39 FslIMX6State *s = FSL_IMX6(obj);
40 char name[NAME_SIZE];
41 int i;
42
43 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
44 snprintf(name, NAME_SIZE, "cpu%d", i);
45 object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
46 ARM_CPU_TYPE_NAME("cortex-a9"),
47 &error_abort, NULL);
48 }
49
50 sysbus_init_child_obj(obj, "a9mpcore", &s->a9mpcore, sizeof(s->a9mpcore),
51 TYPE_A9MPCORE_PRIV);
52
53 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM);
54
55 sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC);
56
57 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
58 snprintf(name, NAME_SIZE, "uart%d", i + 1);
59 sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
60 TYPE_IMX_SERIAL);
61 }
62
63 sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT);
64
65 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
66 snprintf(name, NAME_SIZE, "epit%d", i + 1);
67 sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]),
68 TYPE_IMX_EPIT);
69 }
70
71 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
72 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
73 sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
74 TYPE_IMX_I2C);
75 }
76
77 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
78 snprintf(name, NAME_SIZE, "gpio%d", i + 1);
79 sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
80 TYPE_IMX_GPIO);
81 }
82
83 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
84 snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
85 sysbus_init_child_obj(obj, name, &s->esdhc[i], sizeof(s->esdhc[i]),
86 TYPE_IMX_USDHC);
87 }
88
89 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
90 snprintf(name, NAME_SIZE, "spi%d", i + 1);
91 sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
92 TYPE_IMX_SPI);
93 }
94 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
95 snprintf(name, NAME_SIZE, "wdt%d", i);
96 sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
97 TYPE_IMX2_WDT);
98 }
99
100
101 sysbus_init_child_obj(obj, "eth", &s->eth, sizeof(s->eth), TYPE_IMX_ENET);
102 }
103
104 static void fsl_imx6_realize(DeviceState *dev, Error **errp)
105 {
106 MachineState *ms = MACHINE(qdev_get_machine());
107 FslIMX6State *s = FSL_IMX6(dev);
108 uint16_t i;
109 Error *err = NULL;
110 unsigned int smp_cpus = ms->smp.cpus;
111
112 if (smp_cpus > FSL_IMX6_NUM_CPUS) {
113 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
114 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
115 return;
116 }
117
118 for (i = 0; i < smp_cpus; i++) {
119
120 /* On uniprocessor, the CBAR is set to 0 */
121 if (smp_cpus > 1) {
122 object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR,
123 "reset-cbar", &error_abort);
124 }
125
126 /* All CPU but CPU 0 start in power off mode */
127 if (i) {
128 object_property_set_bool(OBJECT(&s->cpu[i]), true,
129 "start-powered-off", &error_abort);
130 }
131
132 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
133 if (err) {
134 error_propagate(errp, err);
135 return;
136 }
137 }
138
139 object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu",
140 &error_abort);
141
142 object_property_set_int(OBJECT(&s->a9mpcore),
143 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq",
144 &error_abort);
145
146 object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err);
147 if (err) {
148 error_propagate(errp, err);
149 return;
150 }
151 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
152
153 for (i = 0; i < smp_cpus; i++) {
154 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
155 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
156 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
157 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
158 }
159
160 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
161 if (err) {
162 error_propagate(errp, err);
163 return;
164 }
165 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
166
167 object_property_set_bool(OBJECT(&s->src), true, "realized", &err);
168 if (err) {
169 error_propagate(errp, err);
170 return;
171 }
172 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);
173
174 /* Initialize all UARTs */
175 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
176 static const struct {
177 hwaddr addr;
178 unsigned int irq;
179 } serial_table[FSL_IMX6_NUM_UARTS] = {
180 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ },
181 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ },
182 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ },
183 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ },
184 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
185 };
186
187 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
188
189 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
190 if (err) {
191 error_propagate(errp, err);
192 return;
193 }
194
195 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
196 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
197 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
198 serial_table[i].irq));
199 }
200
201 s->gpt.ccm = IMX_CCM(&s->ccm);
202
203 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
204 if (err) {
205 error_propagate(errp, err);
206 return;
207 }
208
209 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
210 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
211 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
212 FSL_IMX6_GPT_IRQ));
213
214 /* Initialize all EPIT timers */
215 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
216 static const struct {
217 hwaddr addr;
218 unsigned int irq;
219 } epit_table[FSL_IMX6_NUM_EPITS] = {
220 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ },
221 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ },
222 };
223
224 s->epit[i].ccm = IMX_CCM(&s->ccm);
225
226 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
227 if (err) {
228 error_propagate(errp, err);
229 return;
230 }
231
232 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
233 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
234 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
235 epit_table[i].irq));
236 }
237
238 /* Initialize all I2C */
239 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
240 static const struct {
241 hwaddr addr;
242 unsigned int irq;
243 } i2c_table[FSL_IMX6_NUM_I2CS] = {
244 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ },
245 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ },
246 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
247 };
248
249 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
250 if (err) {
251 error_propagate(errp, err);
252 return;
253 }
254
255 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
256 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
257 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
258 i2c_table[i].irq));
259 }
260
261 /* Initialize all GPIOs */
262 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
263 static const struct {
264 hwaddr addr;
265 unsigned int irq_low;
266 unsigned int irq_high;
267 } gpio_table[FSL_IMX6_NUM_GPIOS] = {
268 {
269 FSL_IMX6_GPIO1_ADDR,
270 FSL_IMX6_GPIO1_LOW_IRQ,
271 FSL_IMX6_GPIO1_HIGH_IRQ
272 },
273 {
274 FSL_IMX6_GPIO2_ADDR,
275 FSL_IMX6_GPIO2_LOW_IRQ,
276 FSL_IMX6_GPIO2_HIGH_IRQ
277 },
278 {
279 FSL_IMX6_GPIO3_ADDR,
280 FSL_IMX6_GPIO3_LOW_IRQ,
281 FSL_IMX6_GPIO3_HIGH_IRQ
282 },
283 {
284 FSL_IMX6_GPIO4_ADDR,
285 FSL_IMX6_GPIO4_LOW_IRQ,
286 FSL_IMX6_GPIO4_HIGH_IRQ
287 },
288 {
289 FSL_IMX6_GPIO5_ADDR,
290 FSL_IMX6_GPIO5_LOW_IRQ,
291 FSL_IMX6_GPIO5_HIGH_IRQ
292 },
293 {
294 FSL_IMX6_GPIO6_ADDR,
295 FSL_IMX6_GPIO6_LOW_IRQ,
296 FSL_IMX6_GPIO6_HIGH_IRQ
297 },
298 {
299 FSL_IMX6_GPIO7_ADDR,
300 FSL_IMX6_GPIO7_LOW_IRQ,
301 FSL_IMX6_GPIO7_HIGH_IRQ
302 },
303 };
304
305 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel",
306 &error_abort);
307 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq",
308 &error_abort);
309 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
310 if (err) {
311 error_propagate(errp, err);
312 return;
313 }
314
315 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
316 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
317 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
318 gpio_table[i].irq_low));
319 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
320 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
321 gpio_table[i].irq_high));
322 }
323
324 /* Initialize all SDHC */
325 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
326 static const struct {
327 hwaddr addr;
328 unsigned int irq;
329 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = {
330 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ },
331 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ },
332 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ },
333 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
334 };
335
336 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
337 object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version",
338 &err);
339 object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES,
340 "capareg", &err);
341 object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
342 if (err) {
343 error_propagate(errp, err);
344 return;
345 }
346 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
347 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
348 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
349 esdhc_table[i].irq));
350 }
351
352 /* Initialize all ECSPI */
353 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
354 static const struct {
355 hwaddr addr;
356 unsigned int irq;
357 } spi_table[FSL_IMX6_NUM_ECSPIS] = {
358 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ },
359 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ },
360 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ },
361 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ },
362 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ },
363 };
364
365 /* Initialize the SPI */
366 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
367 if (err) {
368 error_propagate(errp, err);
369 return;
370 }
371
372 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
373 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
374 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
375 spi_table[i].irq));
376 }
377
378 qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
379 object_property_set_bool(OBJECT(&s->eth), true, "realized", &err);
380 if (err) {
381 error_propagate(errp, err);
382 return;
383 }
384 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
385 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
386 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
387 FSL_IMX6_ENET_MAC_IRQ));
388 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
389 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
390 FSL_IMX6_ENET_MAC_1588_IRQ));
391
392 /*
393 * Watchdog
394 */
395 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
396 static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = {
397 FSL_IMX6_WDOG1_ADDR,
398 FSL_IMX6_WDOG2_ADDR,
399 };
400
401 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
402 &error_abort);
403
404 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
405 }
406
407 /* ROM memory */
408 memory_region_init_rom(&s->rom, NULL, "imx6.rom",
409 FSL_IMX6_ROM_SIZE, &err);
410 if (err) {
411 error_propagate(errp, err);
412 return;
413 }
414 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
415 &s->rom);
416
417 /* CAAM memory */
418 memory_region_init_rom(&s->caam, NULL, "imx6.caam",
419 FSL_IMX6_CAAM_MEM_SIZE, &err);
420 if (err) {
421 error_propagate(errp, err);
422 return;
423 }
424 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
425 &s->caam);
426
427 /* OCRAM memory */
428 memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE,
429 &err);
430 if (err) {
431 error_propagate(errp, err);
432 return;
433 }
434 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
435 &s->ocram);
436
437 /* internal OCRAM (256 KB) is aliased over 1 MB */
438 memory_region_init_alias(&s->ocram_alias, NULL, "imx6.ocram_alias",
439 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
440 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
441 &s->ocram_alias);
442 }
443
444 static void fsl_imx6_class_init(ObjectClass *oc, void *data)
445 {
446 DeviceClass *dc = DEVICE_CLASS(oc);
447
448 dc->realize = fsl_imx6_realize;
449 dc->desc = "i.MX6 SOC";
450 /* Reason: Uses serial_hd() in the realize() function */
451 dc->user_creatable = false;
452 }
453
454 static const TypeInfo fsl_imx6_type_info = {
455 .name = TYPE_FSL_IMX6,
456 .parent = TYPE_DEVICE,
457 .instance_size = sizeof(FslIMX6State),
458 .instance_init = fsl_imx6_init,
459 .class_init = fsl_imx6_class_init,
460 };
461
462 static void fsl_imx6_register_types(void)
463 {
464 type_register_static(&fsl_imx6_type_info);
465 }
466
467 type_init(fsl_imx6_register_types)
AR7 emulation for QEMU