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exec: remove ram_addr argument from qemu_ram_block_from_host
[qemu/ar7.git] / target-ppc / translate.c
blobf5ceae59002413396348eb51daa978b0f7eb8ba2
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91
92 p = cpu_reg_names;
93 cpu_reg_names_size = sizeof(cpu_reg_names);
94
95 for (i = 0; i < 8; i++) {
96 snprintf(p, cpu_reg_names_size, "crf%d", i);
97 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
98 offsetof(CPUPPCState, crf[i]), p);
99 p += 5;
100 cpu_reg_names_size -= 5;
101 }
102
103 for (i = 0; i < 32; i++) {
104 snprintf(p, cpu_reg_names_size, "r%d", i);
105 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
106 offsetof(CPUPPCState, gpr[i]), p);
107 p += (i < 10) ? 3 : 4;
108 cpu_reg_names_size -= (i < 10) ? 3 : 4;
109 snprintf(p, cpu_reg_names_size, "r%dH", i);
110 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
111 offsetof(CPUPPCState, gprh[i]), p);
112 p += (i < 10) ? 4 : 5;
113 cpu_reg_names_size -= (i < 10) ? 4 : 5;
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(cpu_env,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(cpu_env,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(cpu_env,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(cpu_env,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(cpu_env,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(cpu_env,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(cpu_env,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(cpu_env,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(cpu_env,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 bool pr, hv;
196 int mem_idx;
197 int access_type;
198 /* Translation flags */
199 int le_mode;
200 TCGMemOp default_tcg_memop_mask;
201 #if defined(TARGET_PPC64)
202 int sf_mode;
203 int has_cfar;
204 #endif
205 int fpu_enabled;
206 int altivec_enabled;
207 int vsx_enabled;
208 int spe_enabled;
209 int tm_enabled;
210 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
211 int singlestep_enabled;
212 uint64_t insns_flags;
213 uint64_t insns_flags2;
214 };
215
216 /* Return true iff byteswap is needed in a scalar memop */
217 static inline bool need_byteswap(const DisasContext *ctx)
218 {
219 #if defined(TARGET_WORDS_BIGENDIAN)
220 return ctx->le_mode;
221 #else
222 return !ctx->le_mode;
223 #endif
224 }
225
226 /* True when active word size < size of target_long. */
227 #ifdef TARGET_PPC64
228 # define NARROW_MODE(C) (!(C)->sf_mode)
229 #else
230 # define NARROW_MODE(C) 0
231 #endif
232
233 struct opc_handler_t {
234 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
235 uint32_t inval1;
236 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
237 uint32_t inval2;
238 /* instruction type */
239 uint64_t type;
240 /* extended instruction type */
241 uint64_t type2;
242 /* handler */
243 void (*handler)(DisasContext *ctx);
244 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
245 const char *oname;
246 #endif
247 #if defined(DO_PPC_STATISTICS)
248 uint64_t count;
249 #endif
250 };
251
252 static inline void gen_reset_fpstatus(void)
253 {
254 gen_helper_reset_fpstatus(cpu_env);
255 }
256
257 static inline void gen_compute_fprf(TCGv_i64 arg)
258 {
259 gen_helper_compute_fprf(cpu_env, arg);
260 gen_helper_float_check_status(cpu_env);
261 }
262
263 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
264 {
265 if (ctx->access_type != access_type) {
266 tcg_gen_movi_i32(cpu_access_type, access_type);
267 ctx->access_type = access_type;
268 }
269 }
270
271 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
272 {
273 if (NARROW_MODE(ctx)) {
274 nip = (uint32_t)nip;
275 }
276 tcg_gen_movi_tl(cpu_nip, nip);
277 }
278
279 void gen_update_current_nip(void *opaque)
280 {
281 DisasContext *ctx = opaque;
282
283 tcg_gen_movi_tl(cpu_nip, ctx->nip);
284 }
285
286 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
287 {
288 TCGv_i32 t0, t1;
289 if (ctx->exception == POWERPC_EXCP_NONE) {
290 gen_update_nip(ctx, ctx->nip);
291 }
292 t0 = tcg_const_i32(excp);
293 t1 = tcg_const_i32(error);
294 gen_helper_raise_exception_err(cpu_env, t0, t1);
295 tcg_temp_free_i32(t0);
296 tcg_temp_free_i32(t1);
297 ctx->exception = (excp);
298 }
299
300 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
301 {
302 TCGv_i32 t0;
303 if (ctx->exception == POWERPC_EXCP_NONE) {
304 gen_update_nip(ctx, ctx->nip);
305 }
306 t0 = tcg_const_i32(excp);
307 gen_helper_raise_exception(cpu_env, t0);
308 tcg_temp_free_i32(t0);
309 ctx->exception = (excp);
310 }
311
312 static inline void gen_debug_exception(DisasContext *ctx)
313 {
314 TCGv_i32 t0;
315
316 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
317 (ctx->exception != POWERPC_EXCP_SYNC)) {
318 gen_update_nip(ctx, ctx->nip);
319 }
320 t0 = tcg_const_i32(EXCP_DEBUG);
321 gen_helper_raise_exception(cpu_env, t0);
322 tcg_temp_free_i32(t0);
323 }
324
325 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
326 {
327 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
328 }
329
330 /* Stop translation */
331 static inline void gen_stop_exception(DisasContext *ctx)
332 {
333 gen_update_nip(ctx, ctx->nip);
334 ctx->exception = POWERPC_EXCP_STOP;
335 }
336
337 #ifndef CONFIG_USER_ONLY
338 /* No need to update nip here, as execution flow will change */
339 static inline void gen_sync_exception(DisasContext *ctx)
340 {
341 ctx->exception = POWERPC_EXCP_SYNC;
342 }
343 #endif
344
345 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
346 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
349 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
350
351 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
352 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
353
354 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
355 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
356
357 typedef struct opcode_t {
358 unsigned char opc1, opc2, opc3;
359 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
360 unsigned char pad[5];
361 #else
362 unsigned char pad[1];
363 #endif
364 opc_handler_t handler;
365 const char *oname;
366 } opcode_t;
367
368 /*****************************************************************************/
369 /*** Instruction decoding ***/
370 #define EXTRACT_HELPER(name, shift, nb) \
371 static inline uint32_t name(uint32_t opcode) \
372 { \
373 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
374 }
375
376 #define EXTRACT_SHELPER(name, shift, nb) \
377 static inline int32_t name(uint32_t opcode) \
378 { \
379 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
380 }
381
382 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
383 static inline uint32_t name(uint32_t opcode) \
384 { \
385 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
386 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
387 }
388 /* Opcode part 1 */
389 EXTRACT_HELPER(opc1, 26, 6);
390 /* Opcode part 2 */
391 EXTRACT_HELPER(opc2, 1, 5);
392 /* Opcode part 3 */
393 EXTRACT_HELPER(opc3, 6, 5);
394 /* Update Cr0 flags */
395 EXTRACT_HELPER(Rc, 0, 1);
396 /* Update Cr6 flags (Altivec) */
397 EXTRACT_HELPER(Rc21, 10, 1);
398 /* Destination */
399 EXTRACT_HELPER(rD, 21, 5);
400 /* Source */
401 EXTRACT_HELPER(rS, 21, 5);
402 /* First operand */
403 EXTRACT_HELPER(rA, 16, 5);
404 /* Second operand */
405 EXTRACT_HELPER(rB, 11, 5);
406 /* Third operand */
407 EXTRACT_HELPER(rC, 6, 5);
408 /*** Get CRn ***/
409 EXTRACT_HELPER(crfD, 23, 3);
410 EXTRACT_HELPER(crfS, 18, 3);
411 EXTRACT_HELPER(crbD, 21, 5);
412 EXTRACT_HELPER(crbA, 16, 5);
413 EXTRACT_HELPER(crbB, 11, 5);
414 /* SPR / TBL */
415 EXTRACT_HELPER(_SPR, 11, 10);
416 static inline uint32_t SPR(uint32_t opcode)
417 {
418 uint32_t sprn = _SPR(opcode);
419
420 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
421 }
422 /*** Get constants ***/
423 /* 16 bits signed immediate value */
424 EXTRACT_SHELPER(SIMM, 0, 16);
425 /* 16 bits unsigned immediate value */
426 EXTRACT_HELPER(UIMM, 0, 16);
427 /* 5 bits signed immediate value */
428 EXTRACT_HELPER(SIMM5, 16, 5);
429 /* 5 bits signed immediate value */
430 EXTRACT_HELPER(UIMM5, 16, 5);
431 /* Bit count */
432 EXTRACT_HELPER(NB, 11, 5);
433 /* Shift count */
434 EXTRACT_HELPER(SH, 11, 5);
435 /* Vector shift count */
436 EXTRACT_HELPER(VSH, 6, 4);
437 /* Mask start */
438 EXTRACT_HELPER(MB, 6, 5);
439 /* Mask end */
440 EXTRACT_HELPER(ME, 1, 5);
441 /* Trap operand */
442 EXTRACT_HELPER(TO, 21, 5);
443
444 EXTRACT_HELPER(CRM, 12, 8);
445
446 #ifndef CONFIG_USER_ONLY
447 EXTRACT_HELPER(SR, 16, 4);
448 #endif
449
450 /* mtfsf/mtfsfi */
451 EXTRACT_HELPER(FPBF, 23, 3);
452 EXTRACT_HELPER(FPIMM, 12, 4);
453 EXTRACT_HELPER(FPL, 25, 1);
454 EXTRACT_HELPER(FPFLM, 17, 8);
455 EXTRACT_HELPER(FPW, 16, 1);
456
457 /*** Jump target decoding ***/
458 /* Immediate address */
459 static inline target_ulong LI(uint32_t opcode)
460 {
461 return (opcode >> 0) & 0x03FFFFFC;
462 }
463
464 static inline uint32_t BD(uint32_t opcode)
465 {
466 return (opcode >> 0) & 0xFFFC;
467 }
468
469 EXTRACT_HELPER(BO, 21, 5);
470 EXTRACT_HELPER(BI, 16, 5);
471 /* Absolute/relative address */
472 EXTRACT_HELPER(AA, 1, 1);
473 /* Link */
474 EXTRACT_HELPER(LK, 0, 1);
475
476 /* DFP Z22-form */
477 EXTRACT_HELPER(DCM, 10, 6)
478
479 /* DFP Z23-form */
480 EXTRACT_HELPER(RMC, 9, 2)
481
482 /* Create a mask between <start> and <end> bits */
483 static inline target_ulong MASK(uint32_t start, uint32_t end)
484 {
485 target_ulong ret;
486
487 #if defined(TARGET_PPC64)
488 if (likely(start == 0)) {
489 ret = UINT64_MAX << (63 - end);
490 } else if (likely(end == 63)) {
491 ret = UINT64_MAX >> start;
492 }
493 #else
494 if (likely(start == 0)) {
495 ret = UINT32_MAX << (31 - end);
496 } else if (likely(end == 31)) {
497 ret = UINT32_MAX >> start;
498 }
499 #endif
500 else {
501 ret = (((target_ulong)(-1ULL)) >> (start)) ^
502 (((target_ulong)(-1ULL) >> (end)) >> 1);
503 if (unlikely(start > end))
504 return ~ret;
505 }
506
507 return ret;
508 }
509
510 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
511 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
512 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
513 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
514 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
515 EXTRACT_HELPER(DM, 8, 2);
516 EXTRACT_HELPER(UIM, 16, 2);
517 EXTRACT_HELPER(SHW, 8, 2);
518 EXTRACT_HELPER(SP, 19, 2);
519 /*****************************************************************************/
520 /* PowerPC instructions table */
521
522 #if defined(DO_PPC_STATISTICS)
523 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
524 { \
525 .opc1 = op1, \
526 .opc2 = op2, \
527 .opc3 = op3, \
528 .pad = { 0, }, \
529 .handler = { \
530 .inval1 = invl, \
531 .type = _typ, \
532 .type2 = _typ2, \
533 .handler = &gen_##name, \
534 .oname = stringify(name), \
535 }, \
536 .oname = stringify(name), \
537 }
538 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
539 { \
540 .opc1 = op1, \
541 .opc2 = op2, \
542 .opc3 = op3, \
543 .pad = { 0, }, \
544 .handler = { \
545 .inval1 = invl1, \
546 .inval2 = invl2, \
547 .type = _typ, \
548 .type2 = _typ2, \
549 .handler = &gen_##name, \
550 .oname = stringify(name), \
551 }, \
552 .oname = stringify(name), \
553 }
554 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
555 { \
556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
561 .inval1 = invl, \
562 .type = _typ, \
563 .type2 = _typ2, \
564 .handler = &gen_##name, \
565 .oname = onam, \
566 }, \
567 .oname = onam, \
568 }
569 #else
570 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
571 { \
572 .opc1 = op1, \
573 .opc2 = op2, \
574 .opc3 = op3, \
575 .pad = { 0, }, \
576 .handler = { \
577 .inval1 = invl, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 }, \
582 .oname = stringify(name), \
583 }
584 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
585 { \
586 .opc1 = op1, \
587 .opc2 = op2, \
588 .opc3 = op3, \
589 .pad = { 0, }, \
590 .handler = { \
591 .inval1 = invl1, \
592 .inval2 = invl2, \
593 .type = _typ, \
594 .type2 = _typ2, \
595 .handler = &gen_##name, \
596 }, \
597 .oname = stringify(name), \
598 }
599 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
600 { \
601 .opc1 = op1, \
602 .opc2 = op2, \
603 .opc3 = op3, \
604 .pad = { 0, }, \
605 .handler = { \
606 .inval1 = invl, \
607 .type = _typ, \
608 .type2 = _typ2, \
609 .handler = &gen_##name, \
610 }, \
611 .oname = onam, \
612 }
613 #endif
614
615 /* SPR load/store helpers */
616 static inline void gen_load_spr(TCGv t, int reg)
617 {
618 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
619 }
620
621 static inline void gen_store_spr(int reg, TCGv t)
622 {
623 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
624 }
625
626 /* Invalid instruction */
627 static void gen_invalid(DisasContext *ctx)
628 {
629 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
630 }
631
632 static opc_handler_t invalid_handler = {
633 .inval1 = 0xFFFFFFFF,
634 .inval2 = 0xFFFFFFFF,
635 .type = PPC_NONE,
636 .type2 = PPC_NONE,
637 .handler = gen_invalid,
638 };
639
640 /*** Integer comparison ***/
641
642 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
643 {
644 TCGv t0 = tcg_temp_new();
645 TCGv_i32 t1 = tcg_temp_new_i32();
646
647 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
648
649 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
650 tcg_gen_trunc_tl_i32(t1, t0);
651 tcg_gen_shli_i32(t1, t1, CRF_LT);
652 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
653
654 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
655 tcg_gen_trunc_tl_i32(t1, t0);
656 tcg_gen_shli_i32(t1, t1, CRF_GT);
657 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
658
659 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
660 tcg_gen_trunc_tl_i32(t1, t0);
661 tcg_gen_shli_i32(t1, t1, CRF_EQ);
662 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
663
664 tcg_temp_free(t0);
665 tcg_temp_free_i32(t1);
666 }
667
668 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
669 {
670 TCGv t0 = tcg_const_tl(arg1);
671 gen_op_cmp(arg0, t0, s, crf);
672 tcg_temp_free(t0);
673 }
674
675 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
676 {
677 TCGv t0, t1;
678 t0 = tcg_temp_new();
679 t1 = tcg_temp_new();
680 if (s) {
681 tcg_gen_ext32s_tl(t0, arg0);
682 tcg_gen_ext32s_tl(t1, arg1);
683 } else {
684 tcg_gen_ext32u_tl(t0, arg0);
685 tcg_gen_ext32u_tl(t1, arg1);
686 }
687 gen_op_cmp(t0, t1, s, crf);
688 tcg_temp_free(t1);
689 tcg_temp_free(t0);
690 }
691
692 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
693 {
694 TCGv t0 = tcg_const_tl(arg1);
695 gen_op_cmp32(arg0, t0, s, crf);
696 tcg_temp_free(t0);
697 }
698
699 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
700 {
701 if (NARROW_MODE(ctx)) {
702 gen_op_cmpi32(reg, 0, 1, 0);
703 } else {
704 gen_op_cmpi(reg, 0, 1, 0);
705 }
706 }
707
708 /* cmp */
709 static void gen_cmp(DisasContext *ctx)
710 {
711 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
712 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
713 1, crfD(ctx->opcode));
714 } else {
715 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
716 1, crfD(ctx->opcode));
717 }
718 }
719
720 /* cmpi */
721 static void gen_cmpi(DisasContext *ctx)
722 {
723 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
724 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
725 1, crfD(ctx->opcode));
726 } else {
727 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
728 1, crfD(ctx->opcode));
729 }
730 }
731
732 /* cmpl */
733 static void gen_cmpl(DisasContext *ctx)
734 {
735 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
736 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
737 0, crfD(ctx->opcode));
738 } else {
739 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
740 0, crfD(ctx->opcode));
741 }
742 }
743
744 /* cmpli */
745 static void gen_cmpli(DisasContext *ctx)
746 {
747 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
748 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
749 0, crfD(ctx->opcode));
750 } else {
751 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
752 0, crfD(ctx->opcode));
753 }
754 }
755
756 /* isel (PowerPC 2.03 specification) */
757 static void gen_isel(DisasContext *ctx)
758 {
759 uint32_t bi = rC(ctx->opcode);
760 uint32_t mask = 0x08 >> (bi & 0x03);
761 TCGv t0 = tcg_temp_new();
762 TCGv zr;
763
764 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
765 tcg_gen_andi_tl(t0, t0, mask);
766
767 zr = tcg_const_tl(0);
768 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
769 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
770 cpu_gpr[rB(ctx->opcode)]);
771 tcg_temp_free(zr);
772 tcg_temp_free(t0);
773 }
774
775 /* cmpb: PowerPC 2.05 specification */
776 static void gen_cmpb(DisasContext *ctx)
777 {
778 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
779 cpu_gpr[rB(ctx->opcode)]);
780 }
781
782 /*** Integer arithmetic ***/
783
784 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
785 TCGv arg1, TCGv arg2, int sub)
786 {
787 TCGv t0 = tcg_temp_new();
788
789 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
790 tcg_gen_xor_tl(t0, arg1, arg2);
791 if (sub) {
792 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
793 } else {
794 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
795 }
796 tcg_temp_free(t0);
797 if (NARROW_MODE(ctx)) {
798 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
799 }
800 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
801 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
802 }
803
804 /* Common add function */
805 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
806 TCGv arg2, bool add_ca, bool compute_ca,
807 bool compute_ov, bool compute_rc0)
808 {
809 TCGv t0 = ret;
810
811 if (compute_ca || compute_ov) {
812 t0 = tcg_temp_new();
813 }
814
815 if (compute_ca) {
816 if (NARROW_MODE(ctx)) {
817 /* Caution: a non-obvious corner case of the spec is that we
818 must produce the *entire* 64-bit addition, but produce the
819 carry into bit 32. */
820 TCGv t1 = tcg_temp_new();
821 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
822 tcg_gen_add_tl(t0, arg1, arg2);
823 if (add_ca) {
824 tcg_gen_add_tl(t0, t0, cpu_ca);
825 }
826 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
827 tcg_temp_free(t1);
828 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
829 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
830 } else {
831 TCGv zero = tcg_const_tl(0);
832 if (add_ca) {
833 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
834 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
835 } else {
836 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
837 }
838 tcg_temp_free(zero);
839 }
840 } else {
841 tcg_gen_add_tl(t0, arg1, arg2);
842 if (add_ca) {
843 tcg_gen_add_tl(t0, t0, cpu_ca);
844 }
845 }
846
847 if (compute_ov) {
848 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
849 }
850 if (unlikely(compute_rc0)) {
851 gen_set_Rc0(ctx, t0);
852 }
853
854 if (!TCGV_EQUAL(t0, ret)) {
855 tcg_gen_mov_tl(ret, t0);
856 tcg_temp_free(t0);
857 }
858 }
859 /* Add functions with two operands */
860 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
861 static void glue(gen_, name)(DisasContext *ctx) \
862 { \
863 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
864 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
865 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
866 }
867 /* Add functions with one operand and one immediate */
868 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
869 add_ca, compute_ca, compute_ov) \
870 static void glue(gen_, name)(DisasContext *ctx) \
871 { \
872 TCGv t0 = tcg_const_tl(const_val); \
873 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
874 cpu_gpr[rA(ctx->opcode)], t0, \
875 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
876 tcg_temp_free(t0); \
877 }
878
879 /* add add. addo addo. */
880 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
881 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
882 /* addc addc. addco addco. */
883 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
884 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
885 /* adde adde. addeo addeo. */
886 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
887 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
888 /* addme addme. addmeo addmeo. */
889 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
890 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
891 /* addze addze. addzeo addzeo.*/
892 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
893 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
894 /* addi */
895 static void gen_addi(DisasContext *ctx)
896 {
897 target_long simm = SIMM(ctx->opcode);
898
899 if (rA(ctx->opcode) == 0) {
900 /* li case */
901 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
902 } else {
903 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
904 cpu_gpr[rA(ctx->opcode)], simm);
905 }
906 }
907 /* addic addic.*/
908 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
909 {
910 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
911 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
912 c, 0, 1, 0, compute_rc0);
913 tcg_temp_free(c);
914 }
915
916 static void gen_addic(DisasContext *ctx)
917 {
918 gen_op_addic(ctx, 0);
919 }
920
921 static void gen_addic_(DisasContext *ctx)
922 {
923 gen_op_addic(ctx, 1);
924 }
925
926 /* addis */
927 static void gen_addis(DisasContext *ctx)
928 {
929 target_long simm = SIMM(ctx->opcode);
930
931 if (rA(ctx->opcode) == 0) {
932 /* lis case */
933 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
934 } else {
935 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
936 cpu_gpr[rA(ctx->opcode)], simm << 16);
937 }
938 }
939
940 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
941 TCGv arg2, int sign, int compute_ov)
942 {
943 TCGLabel *l1 = gen_new_label();
944 TCGLabel *l2 = gen_new_label();
945 TCGv_i32 t0 = tcg_temp_local_new_i32();
946 TCGv_i32 t1 = tcg_temp_local_new_i32();
947
948 tcg_gen_trunc_tl_i32(t0, arg1);
949 tcg_gen_trunc_tl_i32(t1, arg2);
950 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
951 if (sign) {
952 TCGLabel *l3 = gen_new_label();
953 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
954 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
955 gen_set_label(l3);
956 tcg_gen_div_i32(t0, t0, t1);
957 } else {
958 tcg_gen_divu_i32(t0, t0, t1);
959 }
960 if (compute_ov) {
961 tcg_gen_movi_tl(cpu_ov, 0);
962 }
963 tcg_gen_br(l2);
964 gen_set_label(l1);
965 if (sign) {
966 tcg_gen_sari_i32(t0, t0, 31);
967 } else {
968 tcg_gen_movi_i32(t0, 0);
969 }
970 if (compute_ov) {
971 tcg_gen_movi_tl(cpu_ov, 1);
972 tcg_gen_movi_tl(cpu_so, 1);
973 }
974 gen_set_label(l2);
975 tcg_gen_extu_i32_tl(ret, t0);
976 tcg_temp_free_i32(t0);
977 tcg_temp_free_i32(t1);
978 if (unlikely(Rc(ctx->opcode) != 0))
979 gen_set_Rc0(ctx, ret);
980 }
981 /* Div functions */
982 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
983 static void glue(gen_, name)(DisasContext *ctx) \
984 { \
985 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
986 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
987 sign, compute_ov); \
988 }
989 /* divwu divwu. divwuo divwuo. */
990 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
991 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
992 /* divw divw. divwo divwo. */
993 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
994 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
995
996 /* div[wd]eu[o][.] */
997 #define GEN_DIVE(name, hlpr, compute_ov) \
998 static void gen_##name(DisasContext *ctx) \
999 { \
1000 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1001 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1002 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1003 tcg_temp_free_i32(t0); \
1004 if (unlikely(Rc(ctx->opcode) != 0)) { \
1005 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1006 } \
1007 }
1008
1009 GEN_DIVE(divweu, divweu, 0);
1010 GEN_DIVE(divweuo, divweu, 1);
1011 GEN_DIVE(divwe, divwe, 0);
1012 GEN_DIVE(divweo, divwe, 1);
1013
1014 #if defined(TARGET_PPC64)
1015 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1016 TCGv arg2, int sign, int compute_ov)
1017 {
1018 TCGLabel *l1 = gen_new_label();
1019 TCGLabel *l2 = gen_new_label();
1020
1021 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1022 if (sign) {
1023 TCGLabel *l3 = gen_new_label();
1024 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1025 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1026 gen_set_label(l3);
1027 tcg_gen_div_i64(ret, arg1, arg2);
1028 } else {
1029 tcg_gen_divu_i64(ret, arg1, arg2);
1030 }
1031 if (compute_ov) {
1032 tcg_gen_movi_tl(cpu_ov, 0);
1033 }
1034 tcg_gen_br(l2);
1035 gen_set_label(l1);
1036 if (sign) {
1037 tcg_gen_sari_i64(ret, arg1, 63);
1038 } else {
1039 tcg_gen_movi_i64(ret, 0);
1040 }
1041 if (compute_ov) {
1042 tcg_gen_movi_tl(cpu_ov, 1);
1043 tcg_gen_movi_tl(cpu_so, 1);
1044 }
1045 gen_set_label(l2);
1046 if (unlikely(Rc(ctx->opcode) != 0))
1047 gen_set_Rc0(ctx, ret);
1048 }
1049 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1050 static void glue(gen_, name)(DisasContext *ctx) \
1051 { \
1052 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1053 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1054 sign, compute_ov); \
1055 }
1056 /* divwu divwu. divwuo divwuo. */
1057 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1058 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1059 /* divw divw. divwo divwo. */
1060 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1061 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1062
1063 GEN_DIVE(divdeu, divdeu, 0);
1064 GEN_DIVE(divdeuo, divdeu, 1);
1065 GEN_DIVE(divde, divde, 0);
1066 GEN_DIVE(divdeo, divde, 1);
1067 #endif
1068
1069 /* mulhw mulhw. */
1070 static void gen_mulhw(DisasContext *ctx)
1071 {
1072 TCGv_i32 t0 = tcg_temp_new_i32();
1073 TCGv_i32 t1 = tcg_temp_new_i32();
1074
1075 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1076 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1077 tcg_gen_muls2_i32(t0, t1, t0, t1);
1078 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1079 tcg_temp_free_i32(t0);
1080 tcg_temp_free_i32(t1);
1081 if (unlikely(Rc(ctx->opcode) != 0))
1082 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1083 }
1084
1085 /* mulhwu mulhwu. */
1086 static void gen_mulhwu(DisasContext *ctx)
1087 {
1088 TCGv_i32 t0 = tcg_temp_new_i32();
1089 TCGv_i32 t1 = tcg_temp_new_i32();
1090
1091 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1092 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1093 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1094 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1095 tcg_temp_free_i32(t0);
1096 tcg_temp_free_i32(t1);
1097 if (unlikely(Rc(ctx->opcode) != 0))
1098 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1099 }
1100
1101 /* mullw mullw. */
1102 static void gen_mullw(DisasContext *ctx)
1103 {
1104 #if defined(TARGET_PPC64)
1105 TCGv_i64 t0, t1;
1106 t0 = tcg_temp_new_i64();
1107 t1 = tcg_temp_new_i64();
1108 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1109 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1110 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1111 tcg_temp_free(t0);
1112 tcg_temp_free(t1);
1113 #else
1114 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1115 cpu_gpr[rB(ctx->opcode)]);
1116 #endif
1117 if (unlikely(Rc(ctx->opcode) != 0))
1118 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1119 }
1120
1121 /* mullwo mullwo. */
1122 static void gen_mullwo(DisasContext *ctx)
1123 {
1124 TCGv_i32 t0 = tcg_temp_new_i32();
1125 TCGv_i32 t1 = tcg_temp_new_i32();
1126
1127 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1128 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1129 tcg_gen_muls2_i32(t0, t1, t0, t1);
1130 #if defined(TARGET_PPC64)
1131 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1132 #else
1133 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1134 #endif
1135
1136 tcg_gen_sari_i32(t0, t0, 31);
1137 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1138 tcg_gen_extu_i32_tl(cpu_ov, t0);
1139 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1140
1141 tcg_temp_free_i32(t0);
1142 tcg_temp_free_i32(t1);
1143 if (unlikely(Rc(ctx->opcode) != 0))
1144 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1145 }
1146
1147 /* mulli */
1148 static void gen_mulli(DisasContext *ctx)
1149 {
1150 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1151 SIMM(ctx->opcode));
1152 }
1153
1154 #if defined(TARGET_PPC64)
1155 /* mulhd mulhd. */
1156 static void gen_mulhd(DisasContext *ctx)
1157 {
1158 TCGv lo = tcg_temp_new();
1159 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1161 tcg_temp_free(lo);
1162 if (unlikely(Rc(ctx->opcode) != 0)) {
1163 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1164 }
1165 }
1166
1167 /* mulhdu mulhdu. */
1168 static void gen_mulhdu(DisasContext *ctx)
1169 {
1170 TCGv lo = tcg_temp_new();
1171 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1172 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1173 tcg_temp_free(lo);
1174 if (unlikely(Rc(ctx->opcode) != 0)) {
1175 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1176 }
1177 }
1178
1179 /* mulld mulld. */
1180 static void gen_mulld(DisasContext *ctx)
1181 {
1182 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1183 cpu_gpr[rB(ctx->opcode)]);
1184 if (unlikely(Rc(ctx->opcode) != 0))
1185 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1186 }
1187
1188 /* mulldo mulldo. */
1189 static void gen_mulldo(DisasContext *ctx)
1190 {
1191 TCGv_i64 t0 = tcg_temp_new_i64();
1192 TCGv_i64 t1 = tcg_temp_new_i64();
1193
1194 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1195 cpu_gpr[rB(ctx->opcode)]);
1196 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1197
1198 tcg_gen_sari_i64(t0, t0, 63);
1199 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1200 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1201
1202 tcg_temp_free_i64(t0);
1203 tcg_temp_free_i64(t1);
1204
1205 if (unlikely(Rc(ctx->opcode) != 0)) {
1206 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1207 }
1208 }
1209 #endif
1210
1211 /* Common subf function */
1212 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1213 TCGv arg2, bool add_ca, bool compute_ca,
1214 bool compute_ov, bool compute_rc0)
1215 {
1216 TCGv t0 = ret;
1217
1218 if (compute_ca || compute_ov) {
1219 t0 = tcg_temp_new();
1220 }
1221
1222 if (compute_ca) {
1223 /* dest = ~arg1 + arg2 [+ ca]. */
1224 if (NARROW_MODE(ctx)) {
1225 /* Caution: a non-obvious corner case of the spec is that we
1226 must produce the *entire* 64-bit addition, but produce the
1227 carry into bit 32. */
1228 TCGv inv1 = tcg_temp_new();
1229 TCGv t1 = tcg_temp_new();
1230 tcg_gen_not_tl(inv1, arg1);
1231 if (add_ca) {
1232 tcg_gen_add_tl(t0, arg2, cpu_ca);
1233 } else {
1234 tcg_gen_addi_tl(t0, arg2, 1);
1235 }
1236 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1237 tcg_gen_add_tl(t0, t0, inv1);
1238 tcg_temp_free(inv1);
1239 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1240 tcg_temp_free(t1);
1241 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1242 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1243 } else if (add_ca) {
1244 TCGv zero, inv1 = tcg_temp_new();
1245 tcg_gen_not_tl(inv1, arg1);
1246 zero = tcg_const_tl(0);
1247 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1248 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1249 tcg_temp_free(zero);
1250 tcg_temp_free(inv1);
1251 } else {
1252 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1253 tcg_gen_sub_tl(t0, arg2, arg1);
1254 }
1255 } else if (add_ca) {
1256 /* Since we're ignoring carry-out, we can simplify the
1257 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1258 tcg_gen_sub_tl(t0, arg2, arg1);
1259 tcg_gen_add_tl(t0, t0, cpu_ca);
1260 tcg_gen_subi_tl(t0, t0, 1);
1261 } else {
1262 tcg_gen_sub_tl(t0, arg2, arg1);
1263 }
1264
1265 if (compute_ov) {
1266 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1267 }
1268 if (unlikely(compute_rc0)) {
1269 gen_set_Rc0(ctx, t0);
1270 }
1271
1272 if (!TCGV_EQUAL(t0, ret)) {
1273 tcg_gen_mov_tl(ret, t0);
1274 tcg_temp_free(t0);
1275 }
1276 }
1277 /* Sub functions with Two operands functions */
1278 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1279 static void glue(gen_, name)(DisasContext *ctx) \
1280 { \
1281 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1282 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1283 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1284 }
1285 /* Sub functions with one operand and one immediate */
1286 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1287 add_ca, compute_ca, compute_ov) \
1288 static void glue(gen_, name)(DisasContext *ctx) \
1289 { \
1290 TCGv t0 = tcg_const_tl(const_val); \
1291 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1292 cpu_gpr[rA(ctx->opcode)], t0, \
1293 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1294 tcg_temp_free(t0); \
1295 }
1296 /* subf subf. subfo subfo. */
1297 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1298 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1299 /* subfc subfc. subfco subfco. */
1300 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1301 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1302 /* subfe subfe. subfeo subfo. */
1303 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1304 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1305 /* subfme subfme. subfmeo subfmeo. */
1306 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1307 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1308 /* subfze subfze. subfzeo subfzeo.*/
1309 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1310 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1311
1312 /* subfic */
1313 static void gen_subfic(DisasContext *ctx)
1314 {
1315 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1316 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1317 c, 0, 1, 0, 0);
1318 tcg_temp_free(c);
1319 }
1320
1321 /* neg neg. nego nego. */
1322 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1323 {
1324 TCGv zero = tcg_const_tl(0);
1325 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1326 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1327 tcg_temp_free(zero);
1328 }
1329
1330 static void gen_neg(DisasContext *ctx)
1331 {
1332 gen_op_arith_neg(ctx, 0);
1333 }
1334
1335 static void gen_nego(DisasContext *ctx)
1336 {
1337 gen_op_arith_neg(ctx, 1);
1338 }
1339
1340 /*** Integer logical ***/
1341 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1342 static void glue(gen_, name)(DisasContext *ctx) \
1343 { \
1344 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1345 cpu_gpr[rB(ctx->opcode)]); \
1346 if (unlikely(Rc(ctx->opcode) != 0)) \
1347 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1348 }
1349
1350 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1351 static void glue(gen_, name)(DisasContext *ctx) \
1352 { \
1353 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1354 if (unlikely(Rc(ctx->opcode) != 0)) \
1355 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1356 }
1357
1358 /* and & and. */
1359 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1360 /* andc & andc. */
1361 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1362
1363 /* andi. */
1364 static void gen_andi_(DisasContext *ctx)
1365 {
1366 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1367 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1368 }
1369
1370 /* andis. */
1371 static void gen_andis_(DisasContext *ctx)
1372 {
1373 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1374 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1375 }
1376
1377 /* cntlzw */
1378 static void gen_cntlzw(DisasContext *ctx)
1379 {
1380 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1381 if (unlikely(Rc(ctx->opcode) != 0))
1382 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1383 }
1384 /* eqv & eqv. */
1385 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1386 /* extsb & extsb. */
1387 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1388 /* extsh & extsh. */
1389 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1390 /* nand & nand. */
1391 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1392 /* nor & nor. */
1393 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1394
1395 /* or & or. */
1396 static void gen_or(DisasContext *ctx)
1397 {
1398 int rs, ra, rb;
1399
1400 rs = rS(ctx->opcode);
1401 ra = rA(ctx->opcode);
1402 rb = rB(ctx->opcode);
1403 /* Optimisation for mr. ri case */
1404 if (rs != ra || rs != rb) {
1405 if (rs != rb)
1406 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1407 else
1408 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1409 if (unlikely(Rc(ctx->opcode) != 0))
1410 gen_set_Rc0(ctx, cpu_gpr[ra]);
1411 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1412 gen_set_Rc0(ctx, cpu_gpr[rs]);
1413 #if defined(TARGET_PPC64)
1414 } else {
1415 int prio = 0;
1416
1417 switch (rs) {
1418 case 1:
1419 /* Set process priority to low */
1420 prio = 2;
1421 break;
1422 case 6:
1423 /* Set process priority to medium-low */
1424 prio = 3;
1425 break;
1426 case 2:
1427 /* Set process priority to normal */
1428 prio = 4;
1429 break;
1430 #if !defined(CONFIG_USER_ONLY)
1431 case 31:
1432 if (!ctx->pr) {
1433 /* Set process priority to very low */
1434 prio = 1;
1435 }
1436 break;
1437 case 5:
1438 if (!ctx->pr) {
1439 /* Set process priority to medium-hight */
1440 prio = 5;
1441 }
1442 break;
1443 case 3:
1444 if (!ctx->pr) {
1445 /* Set process priority to high */
1446 prio = 6;
1447 }
1448 break;
1449 case 7:
1450 if (ctx->hv) {
1451 /* Set process priority to very high */
1452 prio = 7;
1453 }
1454 break;
1455 #endif
1456 default:
1457 /* nop */
1458 break;
1459 }
1460 if (prio) {
1461 TCGv t0 = tcg_temp_new();
1462 gen_load_spr(t0, SPR_PPR);
1463 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1464 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1465 gen_store_spr(SPR_PPR, t0);
1466 tcg_temp_free(t0);
1467 }
1468 #endif
1469 }
1470 }
1471 /* orc & orc. */
1472 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1473
1474 /* xor & xor. */
1475 static void gen_xor(DisasContext *ctx)
1476 {
1477 /* Optimisation for "set to zero" case */
1478 if (rS(ctx->opcode) != rB(ctx->opcode))
1479 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1480 else
1481 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1482 if (unlikely(Rc(ctx->opcode) != 0))
1483 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1484 }
1485
1486 /* ori */
1487 static void gen_ori(DisasContext *ctx)
1488 {
1489 target_ulong uimm = UIMM(ctx->opcode);
1490
1491 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1492 /* NOP */
1493 /* XXX: should handle special NOPs for POWER series */
1494 return;
1495 }
1496 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1497 }
1498
1499 /* oris */
1500 static void gen_oris(DisasContext *ctx)
1501 {
1502 target_ulong uimm = UIMM(ctx->opcode);
1503
1504 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1505 /* NOP */
1506 return;
1507 }
1508 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1509 }
1510
1511 /* xori */
1512 static void gen_xori(DisasContext *ctx)
1513 {
1514 target_ulong uimm = UIMM(ctx->opcode);
1515
1516 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1517 /* NOP */
1518 return;
1519 }
1520 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1521 }
1522
1523 /* xoris */
1524 static void gen_xoris(DisasContext *ctx)
1525 {
1526 target_ulong uimm = UIMM(ctx->opcode);
1527
1528 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1529 /* NOP */
1530 return;
1531 }
1532 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1533 }
1534
1535 /* popcntb : PowerPC 2.03 specification */
1536 static void gen_popcntb(DisasContext *ctx)
1537 {
1538 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1539 }
1540
1541 static void gen_popcntw(DisasContext *ctx)
1542 {
1543 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1544 }
1545
1546 #if defined(TARGET_PPC64)
1547 /* popcntd: PowerPC 2.06 specification */
1548 static void gen_popcntd(DisasContext *ctx)
1549 {
1550 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1551 }
1552 #endif
1553
1554 /* prtyw: PowerPC 2.05 specification */
1555 static void gen_prtyw(DisasContext *ctx)
1556 {
1557 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1558 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1559 TCGv t0 = tcg_temp_new();
1560 tcg_gen_shri_tl(t0, rs, 16);
1561 tcg_gen_xor_tl(ra, rs, t0);
1562 tcg_gen_shri_tl(t0, ra, 8);
1563 tcg_gen_xor_tl(ra, ra, t0);
1564 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1565 tcg_temp_free(t0);
1566 }
1567
1568 #if defined(TARGET_PPC64)
1569 /* prtyd: PowerPC 2.05 specification */
1570 static void gen_prtyd(DisasContext *ctx)
1571 {
1572 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1573 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1574 TCGv t0 = tcg_temp_new();
1575 tcg_gen_shri_tl(t0, rs, 32);
1576 tcg_gen_xor_tl(ra, rs, t0);
1577 tcg_gen_shri_tl(t0, ra, 16);
1578 tcg_gen_xor_tl(ra, ra, t0);
1579 tcg_gen_shri_tl(t0, ra, 8);
1580 tcg_gen_xor_tl(ra, ra, t0);
1581 tcg_gen_andi_tl(ra, ra, 1);
1582 tcg_temp_free(t0);
1583 }
1584 #endif
1585
1586 #if defined(TARGET_PPC64)
1587 /* bpermd */
1588 static void gen_bpermd(DisasContext *ctx)
1589 {
1590 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1591 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1592 }
1593 #endif
1594
1595 #if defined(TARGET_PPC64)
1596 /* extsw & extsw. */
1597 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1598
1599 /* cntlzd */
1600 static void gen_cntlzd(DisasContext *ctx)
1601 {
1602 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1603 if (unlikely(Rc(ctx->opcode) != 0))
1604 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1605 }
1606 #endif
1607
1608 /*** Integer rotate ***/
1609
1610 /* rlwimi & rlwimi. */
1611 static void gen_rlwimi(DisasContext *ctx)
1612 {
1613 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1614 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1615 uint32_t sh = SH(ctx->opcode);
1616 uint32_t mb = MB(ctx->opcode);
1617 uint32_t me = ME(ctx->opcode);
1618
1619 if (sh == (31-me) && mb <= me) {
1620 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1621 } else {
1622 target_ulong mask;
1623 TCGv_i32 t0;
1624 TCGv t1;
1625
1626 #if defined(TARGET_PPC64)
1627 mb += 32;
1628 me += 32;
1629 #endif
1630 mask = MASK(mb, me);
1631
1632 t0 = tcg_temp_new_i32();
1633 t1 = tcg_temp_new();
1634 tcg_gen_trunc_tl_i32(t0, t_rs);
1635 tcg_gen_rotli_i32(t0, t0, sh);
1636 tcg_gen_extu_i32_tl(t1, t0);
1637 tcg_temp_free_i32(t0);
1638
1639 tcg_gen_andi_tl(t1, t1, mask);
1640 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1641 tcg_gen_or_tl(t_ra, t_ra, t1);
1642 tcg_temp_free(t1);
1643 }
1644 if (unlikely(Rc(ctx->opcode) != 0)) {
1645 gen_set_Rc0(ctx, t_ra);
1646 }
1647 }
1648
1649 /* rlwinm & rlwinm. */
1650 static void gen_rlwinm(DisasContext *ctx)
1651 {
1652 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1653 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1654 uint32_t sh = SH(ctx->opcode);
1655 uint32_t mb = MB(ctx->opcode);
1656 uint32_t me = ME(ctx->opcode);
1657
1658 if (mb == 0 && me == (31 - sh)) {
1659 tcg_gen_shli_tl(t_ra, t_rs, sh);
1660 tcg_gen_ext32u_tl(t_ra, t_ra);
1661 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1662 tcg_gen_ext32u_tl(t_ra, t_rs);
1663 tcg_gen_shri_tl(t_ra, t_ra, mb);
1664 } else {
1665 #if defined(TARGET_PPC64)
1666 mb += 32;
1667 me += 32;
1668 #endif
1669 if (sh == 0) {
1670 tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me));
1671 } else {
1672 TCGv_i32 t0 = tcg_temp_new_i32();
1673
1674 tcg_gen_trunc_tl_i32(t0, t_rs);
1675 tcg_gen_rotli_i32(t0, t0, sh);
1676 tcg_gen_andi_i32(t0, t0, MASK(mb, me));
1677 tcg_gen_extu_i32_tl(t_ra, t0);
1678 tcg_temp_free_i32(t0);
1679 }
1680 }
1681 if (unlikely(Rc(ctx->opcode) != 0)) {
1682 gen_set_Rc0(ctx, t_ra);
1683 }
1684 }
1685
1686 /* rlwnm & rlwnm. */
1687 static void gen_rlwnm(DisasContext *ctx)
1688 {
1689 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1690 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1691 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1692 uint32_t mb = MB(ctx->opcode);
1693 uint32_t me = ME(ctx->opcode);
1694 TCGv_i32 t0, t1;
1695
1696 #if defined(TARGET_PPC64)
1697 mb += 32;
1698 me += 32;
1699 #endif
1700
1701 t0 = tcg_temp_new_i32();
1702 t1 = tcg_temp_new_i32();
1703 tcg_gen_trunc_tl_i32(t0, t_rb);
1704 tcg_gen_trunc_tl_i32(t1, t_rs);
1705 tcg_gen_andi_i32(t0, t0, 0x1f);
1706 tcg_gen_rotl_i32(t1, t1, t0);
1707 tcg_temp_free_i32(t0);
1708
1709 tcg_gen_andi_i32(t1, t1, MASK(mb, me));
1710 tcg_gen_extu_i32_tl(t_ra, t1);
1711 tcg_temp_free_i32(t1);
1712
1713 if (unlikely(Rc(ctx->opcode) != 0)) {
1714 gen_set_Rc0(ctx, t_ra);
1715 }
1716 }
1717
1718 #if defined(TARGET_PPC64)
1719 #define GEN_PPC64_R2(name, opc1, opc2) \
1720 static void glue(gen_, name##0)(DisasContext *ctx) \
1721 { \
1722 gen_##name(ctx, 0); \
1723 } \
1724 \
1725 static void glue(gen_, name##1)(DisasContext *ctx) \
1726 { \
1727 gen_##name(ctx, 1); \
1728 }
1729 #define GEN_PPC64_R4(name, opc1, opc2) \
1730 static void glue(gen_, name##0)(DisasContext *ctx) \
1731 { \
1732 gen_##name(ctx, 0, 0); \
1733 } \
1734 \
1735 static void glue(gen_, name##1)(DisasContext *ctx) \
1736 { \
1737 gen_##name(ctx, 0, 1); \
1738 } \
1739 \
1740 static void glue(gen_, name##2)(DisasContext *ctx) \
1741 { \
1742 gen_##name(ctx, 1, 0); \
1743 } \
1744 \
1745 static void glue(gen_, name##3)(DisasContext *ctx) \
1746 { \
1747 gen_##name(ctx, 1, 1); \
1748 }
1749
1750 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
1751 {
1752 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1753 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1754
1755 if (sh != 0 && mb == 0 && me == (63 - sh)) {
1756 tcg_gen_shli_tl(t_ra, t_rs, sh);
1757 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
1758 tcg_gen_shri_tl(t_ra, t_rs, mb);
1759 } else {
1760 tcg_gen_rotli_tl(t_ra, t_rs, sh);
1761 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1762 }
1763 if (unlikely(Rc(ctx->opcode) != 0)) {
1764 gen_set_Rc0(ctx, t_ra);
1765 }
1766 }
1767
1768 /* rldicl - rldicl. */
1769 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1770 {
1771 uint32_t sh, mb;
1772
1773 sh = SH(ctx->opcode) | (shn << 5);
1774 mb = MB(ctx->opcode) | (mbn << 5);
1775 gen_rldinm(ctx, mb, 63, sh);
1776 }
1777 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1778
1779 /* rldicr - rldicr. */
1780 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1781 {
1782 uint32_t sh, me;
1783
1784 sh = SH(ctx->opcode) | (shn << 5);
1785 me = MB(ctx->opcode) | (men << 5);
1786 gen_rldinm(ctx, 0, me, sh);
1787 }
1788 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1789
1790 /* rldic - rldic. */
1791 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1792 {
1793 uint32_t sh, mb;
1794
1795 sh = SH(ctx->opcode) | (shn << 5);
1796 mb = MB(ctx->opcode) | (mbn << 5);
1797 gen_rldinm(ctx, mb, 63 - sh, sh);
1798 }
1799 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1800
1801 static void gen_rldnm(DisasContext *ctx, int mb, int me)
1802 {
1803 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1804 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1805 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1806 TCGv t0;
1807
1808 t0 = tcg_temp_new();
1809 tcg_gen_andi_tl(t0, t_rb, 0x3f);
1810 tcg_gen_rotl_tl(t_ra, t_rs, t0);
1811 tcg_temp_free(t0);
1812
1813 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1814 if (unlikely(Rc(ctx->opcode) != 0)) {
1815 gen_set_Rc0(ctx, t_ra);
1816 }
1817 }
1818
1819 /* rldcl - rldcl. */
1820 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1821 {
1822 uint32_t mb;
1823
1824 mb = MB(ctx->opcode) | (mbn << 5);
1825 gen_rldnm(ctx, mb, 63);
1826 }
1827 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1828
1829 /* rldcr - rldcr. */
1830 static inline void gen_rldcr(DisasContext *ctx, int men)
1831 {
1832 uint32_t me;
1833
1834 me = MB(ctx->opcode) | (men << 5);
1835 gen_rldnm(ctx, 0, me);
1836 }
1837 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1838
1839 /* rldimi - rldimi. */
1840 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1841 {
1842 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1843 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1844 uint32_t sh = SH(ctx->opcode) | (shn << 5);
1845 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
1846 uint32_t me = 63 - sh;
1847
1848 if (mb <= me) {
1849 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1850 } else {
1851 target_ulong mask = MASK(mb, me);
1852 TCGv t1 = tcg_temp_new();
1853
1854 tcg_gen_rotli_tl(t1, t_rs, sh);
1855 tcg_gen_andi_tl(t1, t1, mask);
1856 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1857 tcg_gen_or_tl(t_ra, t_ra, t1);
1858 tcg_temp_free(t1);
1859 }
1860 if (unlikely(Rc(ctx->opcode) != 0)) {
1861 gen_set_Rc0(ctx, t_ra);
1862 }
1863 }
1864 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1865 #endif
1866
1867 /*** Integer shift ***/
1868
1869 /* slw & slw. */
1870 static void gen_slw(DisasContext *ctx)
1871 {
1872 TCGv t0, t1;
1873
1874 t0 = tcg_temp_new();
1875 /* AND rS with a mask that is 0 when rB >= 0x20 */
1876 #if defined(TARGET_PPC64)
1877 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1878 tcg_gen_sari_tl(t0, t0, 0x3f);
1879 #else
1880 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1881 tcg_gen_sari_tl(t0, t0, 0x1f);
1882 #endif
1883 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1884 t1 = tcg_temp_new();
1885 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1886 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1887 tcg_temp_free(t1);
1888 tcg_temp_free(t0);
1889 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1890 if (unlikely(Rc(ctx->opcode) != 0))
1891 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1892 }
1893
1894 /* sraw & sraw. */
1895 static void gen_sraw(DisasContext *ctx)
1896 {
1897 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1898 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1899 if (unlikely(Rc(ctx->opcode) != 0))
1900 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1901 }
1902
1903 /* srawi & srawi. */
1904 static void gen_srawi(DisasContext *ctx)
1905 {
1906 int sh = SH(ctx->opcode);
1907 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1908 TCGv src = cpu_gpr[rS(ctx->opcode)];
1909 if (sh == 0) {
1910 tcg_gen_ext32s_tl(dst, src);
1911 tcg_gen_movi_tl(cpu_ca, 0);
1912 } else {
1913 TCGv t0;
1914 tcg_gen_ext32s_tl(dst, src);
1915 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1916 t0 = tcg_temp_new();
1917 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1918 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1919 tcg_temp_free(t0);
1920 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1921 tcg_gen_sari_tl(dst, dst, sh);
1922 }
1923 if (unlikely(Rc(ctx->opcode) != 0)) {
1924 gen_set_Rc0(ctx, dst);
1925 }
1926 }
1927
1928 /* srw & srw. */
1929 static void gen_srw(DisasContext *ctx)
1930 {
1931 TCGv t0, t1;
1932
1933 t0 = tcg_temp_new();
1934 /* AND rS with a mask that is 0 when rB >= 0x20 */
1935 #if defined(TARGET_PPC64)
1936 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1937 tcg_gen_sari_tl(t0, t0, 0x3f);
1938 #else
1939 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1940 tcg_gen_sari_tl(t0, t0, 0x1f);
1941 #endif
1942 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1943 tcg_gen_ext32u_tl(t0, t0);
1944 t1 = tcg_temp_new();
1945 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1946 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1947 tcg_temp_free(t1);
1948 tcg_temp_free(t0);
1949 if (unlikely(Rc(ctx->opcode) != 0))
1950 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1951 }
1952
1953 #if defined(TARGET_PPC64)
1954 /* sld & sld. */
1955 static void gen_sld(DisasContext *ctx)
1956 {
1957 TCGv t0, t1;
1958
1959 t0 = tcg_temp_new();
1960 /* AND rS with a mask that is 0 when rB >= 0x40 */
1961 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1962 tcg_gen_sari_tl(t0, t0, 0x3f);
1963 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1964 t1 = tcg_temp_new();
1965 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1966 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1967 tcg_temp_free(t1);
1968 tcg_temp_free(t0);
1969 if (unlikely(Rc(ctx->opcode) != 0))
1970 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1971 }
1972
1973 /* srad & srad. */
1974 static void gen_srad(DisasContext *ctx)
1975 {
1976 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1977 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1978 if (unlikely(Rc(ctx->opcode) != 0))
1979 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1980 }
1981 /* sradi & sradi. */
1982 static inline void gen_sradi(DisasContext *ctx, int n)
1983 {
1984 int sh = SH(ctx->opcode) + (n << 5);
1985 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1986 TCGv src = cpu_gpr[rS(ctx->opcode)];
1987 if (sh == 0) {
1988 tcg_gen_mov_tl(dst, src);
1989 tcg_gen_movi_tl(cpu_ca, 0);
1990 } else {
1991 TCGv t0;
1992 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1993 t0 = tcg_temp_new();
1994 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1995 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1996 tcg_temp_free(t0);
1997 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1998 tcg_gen_sari_tl(dst, src, sh);
1999 }
2000 if (unlikely(Rc(ctx->opcode) != 0)) {
2001 gen_set_Rc0(ctx, dst);
2002 }
2003 }
2004
2005 static void gen_sradi0(DisasContext *ctx)
2006 {
2007 gen_sradi(ctx, 0);
2008 }
2009
2010 static void gen_sradi1(DisasContext *ctx)
2011 {
2012 gen_sradi(ctx, 1);
2013 }
2014
2015 /* srd & srd. */
2016 static void gen_srd(DisasContext *ctx)
2017 {
2018 TCGv t0, t1;
2019
2020 t0 = tcg_temp_new();
2021 /* AND rS with a mask that is 0 when rB >= 0x40 */
2022 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2023 tcg_gen_sari_tl(t0, t0, 0x3f);
2024 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2025 t1 = tcg_temp_new();
2026 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2027 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2028 tcg_temp_free(t1);
2029 tcg_temp_free(t0);
2030 if (unlikely(Rc(ctx->opcode) != 0))
2031 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2032 }
2033 #endif
2034
2035 #if defined(TARGET_PPC64)
2036 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2037 {
2038 TCGv_i32 tmp = tcg_temp_new_i32();
2039 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2040 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2041 tcg_temp_free_i32(tmp);
2042 }
2043 #else
2044 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2045 {
2046 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2047 }
2048 #endif
2049
2050 /*** Floating-Point arithmetic ***/
2051 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2052 static void gen_f##name(DisasContext *ctx) \
2053 { \
2054 if (unlikely(!ctx->fpu_enabled)) { \
2055 gen_exception(ctx, POWERPC_EXCP_FPU); \
2056 return; \
2057 } \
2058 /* NIP cannot be restored if the memory exception comes from an helper */ \
2059 gen_update_nip(ctx, ctx->nip - 4); \
2060 gen_reset_fpstatus(); \
2061 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2062 cpu_fpr[rA(ctx->opcode)], \
2063 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2064 if (isfloat) { \
2065 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2066 cpu_fpr[rD(ctx->opcode)]); \
2067 } \
2068 if (set_fprf) { \
2069 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2070 } \
2071 if (unlikely(Rc(ctx->opcode) != 0)) { \
2072 gen_set_cr1_from_fpscr(ctx); \
2073 } \
2074 }
2075
2076 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2077 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2078 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2079
2080 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2081 static void gen_f##name(DisasContext *ctx) \
2082 { \
2083 if (unlikely(!ctx->fpu_enabled)) { \
2084 gen_exception(ctx, POWERPC_EXCP_FPU); \
2085 return; \
2086 } \
2087 /* NIP cannot be restored if the memory exception comes from an helper */ \
2088 gen_update_nip(ctx, ctx->nip - 4); \
2089 gen_reset_fpstatus(); \
2090 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2091 cpu_fpr[rA(ctx->opcode)], \
2092 cpu_fpr[rB(ctx->opcode)]); \
2093 if (isfloat) { \
2094 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2095 cpu_fpr[rD(ctx->opcode)]); \
2096 } \
2097 if (set_fprf) { \
2098 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2099 } \
2100 if (unlikely(Rc(ctx->opcode) != 0)) { \
2101 gen_set_cr1_from_fpscr(ctx); \
2102 } \
2103 }
2104 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2105 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2106 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2107
2108 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2109 static void gen_f##name(DisasContext *ctx) \
2110 { \
2111 if (unlikely(!ctx->fpu_enabled)) { \
2112 gen_exception(ctx, POWERPC_EXCP_FPU); \
2113 return; \
2114 } \
2115 /* NIP cannot be restored if the memory exception comes from an helper */ \
2116 gen_update_nip(ctx, ctx->nip - 4); \
2117 gen_reset_fpstatus(); \
2118 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2119 cpu_fpr[rA(ctx->opcode)], \
2120 cpu_fpr[rC(ctx->opcode)]); \
2121 if (isfloat) { \
2122 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2123 cpu_fpr[rD(ctx->opcode)]); \
2124 } \
2125 if (set_fprf) { \
2126 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2127 } \
2128 if (unlikely(Rc(ctx->opcode) != 0)) { \
2129 gen_set_cr1_from_fpscr(ctx); \
2130 } \
2131 }
2132 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2133 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2134 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2135
2136 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2137 static void gen_f##name(DisasContext *ctx) \
2138 { \
2139 if (unlikely(!ctx->fpu_enabled)) { \
2140 gen_exception(ctx, POWERPC_EXCP_FPU); \
2141 return; \
2142 } \
2143 /* NIP cannot be restored if the memory exception comes from an helper */ \
2144 gen_update_nip(ctx, ctx->nip - 4); \
2145 gen_reset_fpstatus(); \
2146 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2147 cpu_fpr[rB(ctx->opcode)]); \
2148 if (set_fprf) { \
2149 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2150 } \
2151 if (unlikely(Rc(ctx->opcode) != 0)) { \
2152 gen_set_cr1_from_fpscr(ctx); \
2153 } \
2154 }
2155
2156 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2157 static void gen_f##name(DisasContext *ctx) \
2158 { \
2159 if (unlikely(!ctx->fpu_enabled)) { \
2160 gen_exception(ctx, POWERPC_EXCP_FPU); \
2161 return; \
2162 } \
2163 /* NIP cannot be restored if the memory exception comes from an helper */ \
2164 gen_update_nip(ctx, ctx->nip - 4); \
2165 gen_reset_fpstatus(); \
2166 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2167 cpu_fpr[rB(ctx->opcode)]); \
2168 if (set_fprf) { \
2169 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2170 } \
2171 if (unlikely(Rc(ctx->opcode) != 0)) { \
2172 gen_set_cr1_from_fpscr(ctx); \
2173 } \
2174 }
2175
2176 /* fadd - fadds */
2177 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2178 /* fdiv - fdivs */
2179 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2180 /* fmul - fmuls */
2181 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2182
2183 /* fre */
2184 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2185
2186 /* fres */
2187 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2188
2189 /* frsqrte */
2190 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2191
2192 /* frsqrtes */
2193 static void gen_frsqrtes(DisasContext *ctx)
2194 {
2195 if (unlikely(!ctx->fpu_enabled)) {
2196 gen_exception(ctx, POWERPC_EXCP_FPU);
2197 return;
2198 }
2199 /* NIP cannot be restored if the memory exception comes from an helper */
2200 gen_update_nip(ctx, ctx->nip - 4);
2201 gen_reset_fpstatus();
2202 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2203 cpu_fpr[rB(ctx->opcode)]);
2204 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2205 cpu_fpr[rD(ctx->opcode)]);
2206 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2207 if (unlikely(Rc(ctx->opcode) != 0)) {
2208 gen_set_cr1_from_fpscr(ctx);
2209 }
2210 }
2211
2212 /* fsel */
2213 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2214 /* fsub - fsubs */
2215 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2216 /* Optional: */
2217
2218 /* fsqrt */
2219 static void gen_fsqrt(DisasContext *ctx)
2220 {
2221 if (unlikely(!ctx->fpu_enabled)) {
2222 gen_exception(ctx, POWERPC_EXCP_FPU);
2223 return;
2224 }
2225 /* NIP cannot be restored if the memory exception comes from an helper */
2226 gen_update_nip(ctx, ctx->nip - 4);
2227 gen_reset_fpstatus();
2228 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2229 cpu_fpr[rB(ctx->opcode)]);
2230 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2231 if (unlikely(Rc(ctx->opcode) != 0)) {
2232 gen_set_cr1_from_fpscr(ctx);
2233 }
2234 }
2235
2236 static void gen_fsqrts(DisasContext *ctx)
2237 {
2238 if (unlikely(!ctx->fpu_enabled)) {
2239 gen_exception(ctx, POWERPC_EXCP_FPU);
2240 return;
2241 }
2242 /* NIP cannot be restored if the memory exception comes from an helper */
2243 gen_update_nip(ctx, ctx->nip - 4);
2244 gen_reset_fpstatus();
2245 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2246 cpu_fpr[rB(ctx->opcode)]);
2247 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2248 cpu_fpr[rD(ctx->opcode)]);
2249 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2250 if (unlikely(Rc(ctx->opcode) != 0)) {
2251 gen_set_cr1_from_fpscr(ctx);
2252 }
2253 }
2254
2255 /*** Floating-Point multiply-and-add ***/
2256 /* fmadd - fmadds */
2257 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2258 /* fmsub - fmsubs */
2259 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2260 /* fnmadd - fnmadds */
2261 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2262 /* fnmsub - fnmsubs */
2263 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2264
2265 /*** Floating-Point round & convert ***/
2266 /* fctiw */
2267 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2268 /* fctiwu */
2269 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2270 /* fctiwz */
2271 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2272 /* fctiwuz */
2273 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2274 /* frsp */
2275 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2276 /* fcfid */
2277 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2278 /* fcfids */
2279 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2280 /* fcfidu */
2281 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2282 /* fcfidus */
2283 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2284 /* fctid */
2285 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2286 /* fctidu */
2287 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2288 /* fctidz */
2289 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2290 /* fctidu */
2291 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2292
2293 /* frin */
2294 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2295 /* friz */
2296 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2297 /* frip */
2298 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2299 /* frim */
2300 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2301
2302 static void gen_ftdiv(DisasContext *ctx)
2303 {
2304 if (unlikely(!ctx->fpu_enabled)) {
2305 gen_exception(ctx, POWERPC_EXCP_FPU);
2306 return;
2307 }
2308 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2309 cpu_fpr[rB(ctx->opcode)]);
2310 }
2311
2312 static void gen_ftsqrt(DisasContext *ctx)
2313 {
2314 if (unlikely(!ctx->fpu_enabled)) {
2315 gen_exception(ctx, POWERPC_EXCP_FPU);
2316 return;
2317 }
2318 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2319 }
2320
2321
2322
2323 /*** Floating-Point compare ***/
2324
2325 /* fcmpo */
2326 static void gen_fcmpo(DisasContext *ctx)
2327 {
2328 TCGv_i32 crf;
2329 if (unlikely(!ctx->fpu_enabled)) {
2330 gen_exception(ctx, POWERPC_EXCP_FPU);
2331 return;
2332 }
2333 /* NIP cannot be restored if the memory exception comes from an helper */
2334 gen_update_nip(ctx, ctx->nip - 4);
2335 gen_reset_fpstatus();
2336 crf = tcg_const_i32(crfD(ctx->opcode));
2337 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2338 cpu_fpr[rB(ctx->opcode)], crf);
2339 tcg_temp_free_i32(crf);
2340 gen_helper_float_check_status(cpu_env);
2341 }
2342
2343 /* fcmpu */
2344 static void gen_fcmpu(DisasContext *ctx)
2345 {
2346 TCGv_i32 crf;
2347 if (unlikely(!ctx->fpu_enabled)) {
2348 gen_exception(ctx, POWERPC_EXCP_FPU);
2349 return;
2350 }
2351 /* NIP cannot be restored if the memory exception comes from an helper */
2352 gen_update_nip(ctx, ctx->nip - 4);
2353 gen_reset_fpstatus();
2354 crf = tcg_const_i32(crfD(ctx->opcode));
2355 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2356 cpu_fpr[rB(ctx->opcode)], crf);
2357 tcg_temp_free_i32(crf);
2358 gen_helper_float_check_status(cpu_env);
2359 }
2360
2361 /*** Floating-point move ***/
2362 /* fabs */
2363 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2364 static void gen_fabs(DisasContext *ctx)
2365 {
2366 if (unlikely(!ctx->fpu_enabled)) {
2367 gen_exception(ctx, POWERPC_EXCP_FPU);
2368 return;
2369 }
2370 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2371 ~(1ULL << 63));
2372 if (unlikely(Rc(ctx->opcode))) {
2373 gen_set_cr1_from_fpscr(ctx);
2374 }
2375 }
2376
2377 /* fmr - fmr. */
2378 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2379 static void gen_fmr(DisasContext *ctx)
2380 {
2381 if (unlikely(!ctx->fpu_enabled)) {
2382 gen_exception(ctx, POWERPC_EXCP_FPU);
2383 return;
2384 }
2385 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2386 if (unlikely(Rc(ctx->opcode))) {
2387 gen_set_cr1_from_fpscr(ctx);
2388 }
2389 }
2390
2391 /* fnabs */
2392 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2393 static void gen_fnabs(DisasContext *ctx)
2394 {
2395 if (unlikely(!ctx->fpu_enabled)) {
2396 gen_exception(ctx, POWERPC_EXCP_FPU);
2397 return;
2398 }
2399 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2400 1ULL << 63);
2401 if (unlikely(Rc(ctx->opcode))) {
2402 gen_set_cr1_from_fpscr(ctx);
2403 }
2404 }
2405
2406 /* fneg */
2407 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2408 static void gen_fneg(DisasContext *ctx)
2409 {
2410 if (unlikely(!ctx->fpu_enabled)) {
2411 gen_exception(ctx, POWERPC_EXCP_FPU);
2412 return;
2413 }
2414 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2415 1ULL << 63);
2416 if (unlikely(Rc(ctx->opcode))) {
2417 gen_set_cr1_from_fpscr(ctx);
2418 }
2419 }
2420
2421 /* fcpsgn: PowerPC 2.05 specification */
2422 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2423 static void gen_fcpsgn(DisasContext *ctx)
2424 {
2425 if (unlikely(!ctx->fpu_enabled)) {
2426 gen_exception(ctx, POWERPC_EXCP_FPU);
2427 return;
2428 }
2429 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2430 cpu_fpr[rB(ctx->opcode)], 0, 63);
2431 if (unlikely(Rc(ctx->opcode))) {
2432 gen_set_cr1_from_fpscr(ctx);
2433 }
2434 }
2435
2436 static void gen_fmrgew(DisasContext *ctx)
2437 {
2438 TCGv_i64 b0;
2439 if (unlikely(!ctx->fpu_enabled)) {
2440 gen_exception(ctx, POWERPC_EXCP_FPU);
2441 return;
2442 }
2443 b0 = tcg_temp_new_i64();
2444 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2445 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2446 b0, 0, 32);
2447 tcg_temp_free_i64(b0);
2448 }
2449
2450 static void gen_fmrgow(DisasContext *ctx)
2451 {
2452 if (unlikely(!ctx->fpu_enabled)) {
2453 gen_exception(ctx, POWERPC_EXCP_FPU);
2454 return;
2455 }
2456 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2457 cpu_fpr[rB(ctx->opcode)],
2458 cpu_fpr[rA(ctx->opcode)],
2459 32, 32);
2460 }
2461
2462 /*** Floating-Point status & ctrl register ***/
2463
2464 /* mcrfs */
2465 static void gen_mcrfs(DisasContext *ctx)
2466 {
2467 TCGv tmp = tcg_temp_new();
2468 TCGv_i32 tmask;
2469 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2470 int bfa;
2471 int nibble;
2472 int shift;
2473
2474 if (unlikely(!ctx->fpu_enabled)) {
2475 gen_exception(ctx, POWERPC_EXCP_FPU);
2476 return;
2477 }
2478 bfa = crfS(ctx->opcode);
2479 nibble = 7 - bfa;
2480 shift = 4 * nibble;
2481 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2482 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2483 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2484 tcg_temp_free(tmp);
2485 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2486 /* Only the exception bits (including FX) should be cleared if read */
2487 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2488 /* FEX and VX need to be updated, so don't set fpscr directly */
2489 tmask = tcg_const_i32(1 << nibble);
2490 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2491 tcg_temp_free_i32(tmask);
2492 tcg_temp_free_i64(tnew_fpscr);
2493 }
2494
2495 /* mffs */
2496 static void gen_mffs(DisasContext *ctx)
2497 {
2498 if (unlikely(!ctx->fpu_enabled)) {
2499 gen_exception(ctx, POWERPC_EXCP_FPU);
2500 return;
2501 }
2502 gen_reset_fpstatus();
2503 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2504 if (unlikely(Rc(ctx->opcode))) {
2505 gen_set_cr1_from_fpscr(ctx);
2506 }
2507 }
2508
2509 /* mtfsb0 */
2510 static void gen_mtfsb0(DisasContext *ctx)
2511 {
2512 uint8_t crb;
2513
2514 if (unlikely(!ctx->fpu_enabled)) {
2515 gen_exception(ctx, POWERPC_EXCP_FPU);
2516 return;
2517 }
2518 crb = 31 - crbD(ctx->opcode);
2519 gen_reset_fpstatus();
2520 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2521 TCGv_i32 t0;
2522 /* NIP cannot be restored if the memory exception comes from an helper */
2523 gen_update_nip(ctx, ctx->nip - 4);
2524 t0 = tcg_const_i32(crb);
2525 gen_helper_fpscr_clrbit(cpu_env, t0);
2526 tcg_temp_free_i32(t0);
2527 }
2528 if (unlikely(Rc(ctx->opcode) != 0)) {
2529 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2530 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2531 }
2532 }
2533
2534 /* mtfsb1 */
2535 static void gen_mtfsb1(DisasContext *ctx)
2536 {
2537 uint8_t crb;
2538
2539 if (unlikely(!ctx->fpu_enabled)) {
2540 gen_exception(ctx, POWERPC_EXCP_FPU);
2541 return;
2542 }
2543 crb = 31 - crbD(ctx->opcode);
2544 gen_reset_fpstatus();
2545 /* XXX: we pretend we can only do IEEE floating-point computations */
2546 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2547 TCGv_i32 t0;
2548 /* NIP cannot be restored if the memory exception comes from an helper */
2549 gen_update_nip(ctx, ctx->nip - 4);
2550 t0 = tcg_const_i32(crb);
2551 gen_helper_fpscr_setbit(cpu_env, t0);
2552 tcg_temp_free_i32(t0);
2553 }
2554 if (unlikely(Rc(ctx->opcode) != 0)) {
2555 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2556 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2557 }
2558 /* We can raise a differed exception */
2559 gen_helper_float_check_status(cpu_env);
2560 }
2561
2562 /* mtfsf */
2563 static void gen_mtfsf(DisasContext *ctx)
2564 {
2565 TCGv_i32 t0;
2566 int flm, l, w;
2567
2568 if (unlikely(!ctx->fpu_enabled)) {
2569 gen_exception(ctx, POWERPC_EXCP_FPU);
2570 return;
2571 }
2572 flm = FPFLM(ctx->opcode);
2573 l = FPL(ctx->opcode);
2574 w = FPW(ctx->opcode);
2575 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2576 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2577 return;
2578 }
2579 /* NIP cannot be restored if the memory exception comes from an helper */
2580 gen_update_nip(ctx, ctx->nip - 4);
2581 gen_reset_fpstatus();
2582 if (l) {
2583 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2584 } else {
2585 t0 = tcg_const_i32(flm << (w * 8));
2586 }
2587 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2588 tcg_temp_free_i32(t0);
2589 if (unlikely(Rc(ctx->opcode) != 0)) {
2590 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2591 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2592 }
2593 /* We can raise a differed exception */
2594 gen_helper_float_check_status(cpu_env);
2595 }
2596
2597 /* mtfsfi */
2598 static void gen_mtfsfi(DisasContext *ctx)
2599 {
2600 int bf, sh, w;
2601 TCGv_i64 t0;
2602 TCGv_i32 t1;
2603
2604 if (unlikely(!ctx->fpu_enabled)) {
2605 gen_exception(ctx, POWERPC_EXCP_FPU);
2606 return;
2607 }
2608 w = FPW(ctx->opcode);
2609 bf = FPBF(ctx->opcode);
2610 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2611 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2612 return;
2613 }
2614 sh = (8 * w) + 7 - bf;
2615 /* NIP cannot be restored if the memory exception comes from an helper */
2616 gen_update_nip(ctx, ctx->nip - 4);
2617 gen_reset_fpstatus();
2618 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2619 t1 = tcg_const_i32(1 << sh);
2620 gen_helper_store_fpscr(cpu_env, t0, t1);
2621 tcg_temp_free_i64(t0);
2622 tcg_temp_free_i32(t1);
2623 if (unlikely(Rc(ctx->opcode) != 0)) {
2624 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2625 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2626 }
2627 /* We can raise a differed exception */
2628 gen_helper_float_check_status(cpu_env);
2629 }
2630
2631 /*** Addressing modes ***/
2632 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2633 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2634 target_long maskl)
2635 {
2636 target_long simm = SIMM(ctx->opcode);
2637
2638 simm &= ~maskl;
2639 if (rA(ctx->opcode) == 0) {
2640 if (NARROW_MODE(ctx)) {
2641 simm = (uint32_t)simm;
2642 }
2643 tcg_gen_movi_tl(EA, simm);
2644 } else if (likely(simm != 0)) {
2645 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2646 if (NARROW_MODE(ctx)) {
2647 tcg_gen_ext32u_tl(EA, EA);
2648 }
2649 } else {
2650 if (NARROW_MODE(ctx)) {
2651 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2652 } else {
2653 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2654 }
2655 }
2656 }
2657
2658 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2659 {
2660 if (rA(ctx->opcode) == 0) {
2661 if (NARROW_MODE(ctx)) {
2662 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2663 } else {
2664 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2665 }
2666 } else {
2667 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2668 if (NARROW_MODE(ctx)) {
2669 tcg_gen_ext32u_tl(EA, EA);
2670 }
2671 }
2672 }
2673
2674 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2675 {
2676 if (rA(ctx->opcode) == 0) {
2677 tcg_gen_movi_tl(EA, 0);
2678 } else if (NARROW_MODE(ctx)) {
2679 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2680 } else {
2681 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2682 }
2683 }
2684
2685 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2686 target_long val)
2687 {
2688 tcg_gen_addi_tl(ret, arg1, val);
2689 if (NARROW_MODE(ctx)) {
2690 tcg_gen_ext32u_tl(ret, ret);
2691 }
2692 }
2693
2694 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2695 {
2696 TCGLabel *l1 = gen_new_label();
2697 TCGv t0 = tcg_temp_new();
2698 TCGv_i32 t1, t2;
2699 /* NIP cannot be restored if the memory exception comes from an helper */
2700 gen_update_nip(ctx, ctx->nip - 4);
2701 tcg_gen_andi_tl(t0, EA, mask);
2702 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2703 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2704 t2 = tcg_const_i32(0);
2705 gen_helper_raise_exception_err(cpu_env, t1, t2);
2706 tcg_temp_free_i32(t1);
2707 tcg_temp_free_i32(t2);
2708 gen_set_label(l1);
2709 tcg_temp_free(t0);
2710 }
2711
2712 /*** Integer load ***/
2713 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2714 {
2715 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2716 }
2717
2718 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2719 {
2720 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2721 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2722 }
2723
2724 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2725 {
2726 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2727 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2728 }
2729
2730 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2731 {
2732 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2733 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2734 }
2735
2736 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2737 {
2738 TCGv tmp = tcg_temp_new();
2739 gen_qemu_ld32u(ctx, tmp, addr);
2740 tcg_gen_extu_tl_i64(val, tmp);
2741 tcg_temp_free(tmp);
2742 }
2743
2744 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2745 {
2746 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2747 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2748 }
2749
2750 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2751 {
2752 TCGv tmp = tcg_temp_new();
2753 gen_qemu_ld32s(ctx, tmp, addr);
2754 tcg_gen_ext_tl_i64(val, tmp);
2755 tcg_temp_free(tmp);
2756 }
2757
2758 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2759 {
2760 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2761 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2762 }
2763
2764 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2765 {
2766 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2767 }
2768
2769 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2770 {
2771 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2772 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2773 }
2774
2775 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2776 {
2777 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2778 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2779 }
2780
2781 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2782 {
2783 TCGv tmp = tcg_temp_new();
2784 tcg_gen_trunc_i64_tl(tmp, val);
2785 gen_qemu_st32(ctx, tmp, addr);
2786 tcg_temp_free(tmp);
2787 }
2788
2789 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2790 {
2791 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2792 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2793 }
2794
2795 #define GEN_LD(name, ldop, opc, type) \
2796 static void glue(gen_, name)(DisasContext *ctx) \
2797 { \
2798 TCGv EA; \
2799 gen_set_access_type(ctx, ACCESS_INT); \
2800 EA = tcg_temp_new(); \
2801 gen_addr_imm_index(ctx, EA, 0); \
2802 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2803 tcg_temp_free(EA); \
2804 }
2805
2806 #define GEN_LDU(name, ldop, opc, type) \
2807 static void glue(gen_, name##u)(DisasContext *ctx) \
2808 { \
2809 TCGv EA; \
2810 if (unlikely(rA(ctx->opcode) == 0 || \
2811 rA(ctx->opcode) == rD(ctx->opcode))) { \
2812 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2813 return; \
2814 } \
2815 gen_set_access_type(ctx, ACCESS_INT); \
2816 EA = tcg_temp_new(); \
2817 if (type == PPC_64B) \
2818 gen_addr_imm_index(ctx, EA, 0x03); \
2819 else \
2820 gen_addr_imm_index(ctx, EA, 0); \
2821 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2822 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2823 tcg_temp_free(EA); \
2824 }
2825
2826 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2827 static void glue(gen_, name##ux)(DisasContext *ctx) \
2828 { \
2829 TCGv EA; \
2830 if (unlikely(rA(ctx->opcode) == 0 || \
2831 rA(ctx->opcode) == rD(ctx->opcode))) { \
2832 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2833 return; \
2834 } \
2835 gen_set_access_type(ctx, ACCESS_INT); \
2836 EA = tcg_temp_new(); \
2837 gen_addr_reg_index(ctx, EA); \
2838 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2839 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2840 tcg_temp_free(EA); \
2841 }
2842
2843 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2844 static void glue(gen_, name##x)(DisasContext *ctx) \
2845 { \
2846 TCGv EA; \
2847 gen_set_access_type(ctx, ACCESS_INT); \
2848 EA = tcg_temp_new(); \
2849 gen_addr_reg_index(ctx, EA); \
2850 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2851 tcg_temp_free(EA); \
2852 }
2853 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2854 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2855
2856 #define GEN_LDS(name, ldop, op, type) \
2857 GEN_LD(name, ldop, op | 0x20, type); \
2858 GEN_LDU(name, ldop, op | 0x21, type); \
2859 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2860 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2861
2862 /* lbz lbzu lbzux lbzx */
2863 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2864 /* lha lhau lhaux lhax */
2865 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2866 /* lhz lhzu lhzux lhzx */
2867 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2868 /* lwz lwzu lwzux lwzx */
2869 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2870 #if defined(TARGET_PPC64)
2871 /* lwaux */
2872 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2873 /* lwax */
2874 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2875 /* ldux */
2876 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2877 /* ldx */
2878 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2879
2880 static void gen_ld(DisasContext *ctx)
2881 {
2882 TCGv EA;
2883 if (Rc(ctx->opcode)) {
2884 if (unlikely(rA(ctx->opcode) == 0 ||
2885 rA(ctx->opcode) == rD(ctx->opcode))) {
2886 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2887 return;
2888 }
2889 }
2890 gen_set_access_type(ctx, ACCESS_INT);
2891 EA = tcg_temp_new();
2892 gen_addr_imm_index(ctx, EA, 0x03);
2893 if (ctx->opcode & 0x02) {
2894 /* lwa (lwau is undefined) */
2895 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2896 } else {
2897 /* ld - ldu */
2898 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2899 }
2900 if (Rc(ctx->opcode))
2901 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2902 tcg_temp_free(EA);
2903 }
2904
2905 /* lq */
2906 static void gen_lq(DisasContext *ctx)
2907 {
2908 int ra, rd;
2909 TCGv EA;
2910
2911 /* lq is a legal user mode instruction starting in ISA 2.07 */
2912 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2913 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2914
2915 if (!legal_in_user_mode && ctx->pr) {
2916 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2917 return;
2918 }
2919
2920 if (!le_is_supported && ctx->le_mode) {
2921 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2922 return;
2923 }
2924
2925 ra = rA(ctx->opcode);
2926 rd = rD(ctx->opcode);
2927 if (unlikely((rd & 1) || rd == ra)) {
2928 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2929 return;
2930 }
2931
2932 gen_set_access_type(ctx, ACCESS_INT);
2933 EA = tcg_temp_new();
2934 gen_addr_imm_index(ctx, EA, 0x0F);
2935
2936 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2937 64-bit byteswap already. */
2938 if (unlikely(ctx->le_mode)) {
2939 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2940 gen_addr_add(ctx, EA, EA, 8);
2941 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2942 } else {
2943 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2944 gen_addr_add(ctx, EA, EA, 8);
2945 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2946 }
2947 tcg_temp_free(EA);
2948 }
2949 #endif
2950
2951 /*** Integer store ***/
2952 #define GEN_ST(name, stop, opc, type) \
2953 static void glue(gen_, name)(DisasContext *ctx) \
2954 { \
2955 TCGv EA; \
2956 gen_set_access_type(ctx, ACCESS_INT); \
2957 EA = tcg_temp_new(); \
2958 gen_addr_imm_index(ctx, EA, 0); \
2959 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2960 tcg_temp_free(EA); \
2961 }
2962
2963 #define GEN_STU(name, stop, opc, type) \
2964 static void glue(gen_, stop##u)(DisasContext *ctx) \
2965 { \
2966 TCGv EA; \
2967 if (unlikely(rA(ctx->opcode) == 0)) { \
2968 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2969 return; \
2970 } \
2971 gen_set_access_type(ctx, ACCESS_INT); \
2972 EA = tcg_temp_new(); \
2973 if (type == PPC_64B) \
2974 gen_addr_imm_index(ctx, EA, 0x03); \
2975 else \
2976 gen_addr_imm_index(ctx, EA, 0); \
2977 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2978 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2979 tcg_temp_free(EA); \
2980 }
2981
2982 #define GEN_STUX(name, stop, opc2, opc3, type) \
2983 static void glue(gen_, name##ux)(DisasContext *ctx) \
2984 { \
2985 TCGv EA; \
2986 if (unlikely(rA(ctx->opcode) == 0)) { \
2987 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2988 return; \
2989 } \
2990 gen_set_access_type(ctx, ACCESS_INT); \
2991 EA = tcg_temp_new(); \
2992 gen_addr_reg_index(ctx, EA); \
2993 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2994 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2995 tcg_temp_free(EA); \
2996 }
2997
2998 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2999 static void glue(gen_, name##x)(DisasContext *ctx) \
3000 { \
3001 TCGv EA; \
3002 gen_set_access_type(ctx, ACCESS_INT); \
3003 EA = tcg_temp_new(); \
3004 gen_addr_reg_index(ctx, EA); \
3005 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3006 tcg_temp_free(EA); \
3007 }
3008 #define GEN_STX(name, stop, opc2, opc3, type) \
3009 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3010
3011 #define GEN_STS(name, stop, op, type) \
3012 GEN_ST(name, stop, op | 0x20, type); \
3013 GEN_STU(name, stop, op | 0x21, type); \
3014 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3015 GEN_STX(name, stop, 0x17, op | 0x00, type)
3016
3017 /* stb stbu stbux stbx */
3018 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3019 /* sth sthu sthux sthx */
3020 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3021 /* stw stwu stwux stwx */
3022 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3023 #if defined(TARGET_PPC64)
3024 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3025 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3026
3027 static void gen_std(DisasContext *ctx)
3028 {
3029 int rs;
3030 TCGv EA;
3031
3032 rs = rS(ctx->opcode);
3033 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3034
3035 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3036 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3037
3038 if (!legal_in_user_mode && ctx->pr) {
3039 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3040 return;
3041 }
3042
3043 if (!le_is_supported && ctx->le_mode) {
3044 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3045 return;
3046 }
3047
3048 if (unlikely(rs & 1)) {
3049 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3050 return;
3051 }
3052 gen_set_access_type(ctx, ACCESS_INT);
3053 EA = tcg_temp_new();
3054 gen_addr_imm_index(ctx, EA, 0x03);
3055
3056 /* We only need to swap high and low halves. gen_qemu_st64 does
3057 necessary 64-bit byteswap already. */
3058 if (unlikely(ctx->le_mode)) {
3059 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3060 gen_addr_add(ctx, EA, EA, 8);
3061 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3062 } else {
3063 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3064 gen_addr_add(ctx, EA, EA, 8);
3065 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3066 }
3067 tcg_temp_free(EA);
3068 } else {
3069 /* std / stdu*/
3070 if (Rc(ctx->opcode)) {
3071 if (unlikely(rA(ctx->opcode) == 0)) {
3072 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3073 return;
3074 }
3075 }
3076 gen_set_access_type(ctx, ACCESS_INT);
3077 EA = tcg_temp_new();
3078 gen_addr_imm_index(ctx, EA, 0x03);
3079 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3080 if (Rc(ctx->opcode))
3081 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3082 tcg_temp_free(EA);
3083 }
3084 }
3085 #endif
3086 /*** Integer load and store with byte reverse ***/
3087
3088 /* lhbrx */
3089 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3090 {
3091 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3092 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3093 }
3094 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3095
3096 /* lwbrx */
3097 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3098 {
3099 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3100 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3101 }
3102 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3103
3104 #if defined(TARGET_PPC64)
3105 /* ldbrx */
3106 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3107 {
3108 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3109 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3110 }
3111 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3112 #endif /* TARGET_PPC64 */
3113
3114 /* sthbrx */
3115 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3116 {
3117 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3118 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3119 }
3120 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3121
3122 /* stwbrx */
3123 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3124 {
3125 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3126 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3127 }
3128 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3129
3130 #if defined(TARGET_PPC64)
3131 /* stdbrx */
3132 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3133 {
3134 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3135 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3136 }
3137 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3138 #endif /* TARGET_PPC64 */
3139
3140 /*** Integer load and store multiple ***/
3141
3142 /* lmw */
3143 static void gen_lmw(DisasContext *ctx)
3144 {
3145 TCGv t0;
3146 TCGv_i32 t1;
3147 gen_set_access_type(ctx, ACCESS_INT);
3148 /* NIP cannot be restored if the memory exception comes from an helper */
3149 gen_update_nip(ctx, ctx->nip - 4);
3150 t0 = tcg_temp_new();
3151 t1 = tcg_const_i32(rD(ctx->opcode));
3152 gen_addr_imm_index(ctx, t0, 0);
3153 gen_helper_lmw(cpu_env, t0, t1);
3154 tcg_temp_free(t0);
3155 tcg_temp_free_i32(t1);
3156 }
3157
3158 /* stmw */
3159 static void gen_stmw(DisasContext *ctx)
3160 {
3161 TCGv t0;
3162 TCGv_i32 t1;
3163 gen_set_access_type(ctx, ACCESS_INT);
3164 /* NIP cannot be restored if the memory exception comes from an helper */
3165 gen_update_nip(ctx, ctx->nip - 4);
3166 t0 = tcg_temp_new();
3167 t1 = tcg_const_i32(rS(ctx->opcode));
3168 gen_addr_imm_index(ctx, t0, 0);
3169 gen_helper_stmw(cpu_env, t0, t1);
3170 tcg_temp_free(t0);
3171 tcg_temp_free_i32(t1);
3172 }
3173
3174 /*** Integer load and store strings ***/
3175
3176 /* lswi */
3177 /* PowerPC32 specification says we must generate an exception if
3178 * rA is in the range of registers to be loaded.
3179 * In an other hand, IBM says this is valid, but rA won't be loaded.
3180 * For now, I'll follow the spec...
3181 */
3182 static void gen_lswi(DisasContext *ctx)
3183 {
3184 TCGv t0;
3185 TCGv_i32 t1, t2;
3186 int nb = NB(ctx->opcode);
3187 int start = rD(ctx->opcode);
3188 int ra = rA(ctx->opcode);
3189 int nr;
3190
3191 if (nb == 0)
3192 nb = 32;
3193 nr = (nb + 3) / 4;
3194 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3195 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3196 return;
3197 }
3198 gen_set_access_type(ctx, ACCESS_INT);
3199 /* NIP cannot be restored if the memory exception comes from an helper */
3200 gen_update_nip(ctx, ctx->nip - 4);
3201 t0 = tcg_temp_new();
3202 gen_addr_register(ctx, t0);
3203 t1 = tcg_const_i32(nb);
3204 t2 = tcg_const_i32(start);
3205 gen_helper_lsw(cpu_env, t0, t1, t2);
3206 tcg_temp_free(t0);
3207 tcg_temp_free_i32(t1);
3208 tcg_temp_free_i32(t2);
3209 }
3210
3211 /* lswx */
3212 static void gen_lswx(DisasContext *ctx)
3213 {
3214 TCGv t0;
3215 TCGv_i32 t1, t2, t3;
3216 gen_set_access_type(ctx, ACCESS_INT);
3217 /* NIP cannot be restored if the memory exception comes from an helper */
3218 gen_update_nip(ctx, ctx->nip - 4);
3219 t0 = tcg_temp_new();
3220 gen_addr_reg_index(ctx, t0);
3221 t1 = tcg_const_i32(rD(ctx->opcode));
3222 t2 = tcg_const_i32(rA(ctx->opcode));
3223 t3 = tcg_const_i32(rB(ctx->opcode));
3224 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3225 tcg_temp_free(t0);
3226 tcg_temp_free_i32(t1);
3227 tcg_temp_free_i32(t2);
3228 tcg_temp_free_i32(t3);
3229 }
3230
3231 /* stswi */
3232 static void gen_stswi(DisasContext *ctx)
3233 {
3234 TCGv t0;
3235 TCGv_i32 t1, t2;
3236 int nb = NB(ctx->opcode);
3237 gen_set_access_type(ctx, ACCESS_INT);
3238 /* NIP cannot be restored if the memory exception comes from an helper */
3239 gen_update_nip(ctx, ctx->nip - 4);
3240 t0 = tcg_temp_new();
3241 gen_addr_register(ctx, t0);
3242 if (nb == 0)
3243 nb = 32;
3244 t1 = tcg_const_i32(nb);
3245 t2 = tcg_const_i32(rS(ctx->opcode));
3246 gen_helper_stsw(cpu_env, t0, t1, t2);
3247 tcg_temp_free(t0);
3248 tcg_temp_free_i32(t1);
3249 tcg_temp_free_i32(t2);
3250 }
3251
3252 /* stswx */
3253 static void gen_stswx(DisasContext *ctx)
3254 {
3255 TCGv t0;
3256 TCGv_i32 t1, t2;
3257 gen_set_access_type(ctx, ACCESS_INT);
3258 /* NIP cannot be restored if the memory exception comes from an helper */
3259 gen_update_nip(ctx, ctx->nip - 4);
3260 t0 = tcg_temp_new();
3261 gen_addr_reg_index(ctx, t0);
3262 t1 = tcg_temp_new_i32();
3263 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3264 tcg_gen_andi_i32(t1, t1, 0x7F);
3265 t2 = tcg_const_i32(rS(ctx->opcode));
3266 gen_helper_stsw(cpu_env, t0, t1, t2);
3267 tcg_temp_free(t0);
3268 tcg_temp_free_i32(t1);
3269 tcg_temp_free_i32(t2);
3270 }
3271
3272 /*** Memory synchronisation ***/
3273 /* eieio */
3274 static void gen_eieio(DisasContext *ctx)
3275 {
3276 }
3277
3278 /* isync */
3279 static void gen_isync(DisasContext *ctx)
3280 {
3281 gen_stop_exception(ctx);
3282 }
3283
3284 #define LARX(name, len, loadop) \
3285 static void gen_##name(DisasContext *ctx) \
3286 { \
3287 TCGv t0; \
3288 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3289 gen_set_access_type(ctx, ACCESS_RES); \
3290 t0 = tcg_temp_local_new(); \
3291 gen_addr_reg_index(ctx, t0); \
3292 if ((len) > 1) { \
3293 gen_check_align(ctx, t0, (len)-1); \
3294 } \
3295 gen_qemu_##loadop(ctx, gpr, t0); \
3296 tcg_gen_mov_tl(cpu_reserve, t0); \
3297 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3298 tcg_temp_free(t0); \
3299 }
3300
3301 /* lwarx */
3302 LARX(lbarx, 1, ld8u);
3303 LARX(lharx, 2, ld16u);
3304 LARX(lwarx, 4, ld32u);
3305
3306
3307 #if defined(CONFIG_USER_ONLY)
3308 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3309 int reg, int size)
3310 {
3311 TCGv t0 = tcg_temp_new();
3312 uint32_t save_exception = ctx->exception;
3313
3314 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3315 tcg_gen_movi_tl(t0, (size << 5) | reg);
3316 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3317 tcg_temp_free(t0);
3318 gen_update_nip(ctx, ctx->nip-4);
3319 ctx->exception = POWERPC_EXCP_BRANCH;
3320 gen_exception(ctx, POWERPC_EXCP_STCX);
3321 ctx->exception = save_exception;
3322 }
3323 #else
3324 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3325 int reg, int size)
3326 {
3327 TCGLabel *l1;
3328
3329 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3330 l1 = gen_new_label();
3331 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3332 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3333 #if defined(TARGET_PPC64)
3334 if (size == 8) {
3335 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3336 } else
3337 #endif
3338 if (size == 4) {
3339 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3340 } else if (size == 2) {
3341 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3342 #if defined(TARGET_PPC64)
3343 } else if (size == 16) {
3344 TCGv gpr1, gpr2 , EA8;
3345 if (unlikely(ctx->le_mode)) {
3346 gpr1 = cpu_gpr[reg+1];
3347 gpr2 = cpu_gpr[reg];
3348 } else {
3349 gpr1 = cpu_gpr[reg];
3350 gpr2 = cpu_gpr[reg+1];
3351 }
3352 gen_qemu_st64(ctx, gpr1, EA);
3353 EA8 = tcg_temp_local_new();
3354 gen_addr_add(ctx, EA8, EA, 8);
3355 gen_qemu_st64(ctx, gpr2, EA8);
3356 tcg_temp_free(EA8);
3357 #endif
3358 } else {
3359 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3360 }
3361 gen_set_label(l1);
3362 tcg_gen_movi_tl(cpu_reserve, -1);
3363 }
3364 #endif
3365
3366 #define STCX(name, len) \
3367 static void gen_##name(DisasContext *ctx) \
3368 { \
3369 TCGv t0; \
3370 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3371 gen_inval_exception(ctx, \
3372 POWERPC_EXCP_INVAL_INVAL); \
3373 return; \
3374 } \
3375 gen_set_access_type(ctx, ACCESS_RES); \
3376 t0 = tcg_temp_local_new(); \
3377 gen_addr_reg_index(ctx, t0); \
3378 if (len > 1) { \
3379 gen_check_align(ctx, t0, (len)-1); \
3380 } \
3381 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3382 tcg_temp_free(t0); \
3383 }
3384
3385 STCX(stbcx_, 1);
3386 STCX(sthcx_, 2);
3387 STCX(stwcx_, 4);
3388
3389 #if defined(TARGET_PPC64)
3390 /* ldarx */
3391 LARX(ldarx, 8, ld64);
3392
3393 /* lqarx */
3394 static void gen_lqarx(DisasContext *ctx)
3395 {
3396 TCGv EA;
3397 int rd = rD(ctx->opcode);
3398 TCGv gpr1, gpr2;
3399
3400 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3401 (rd == rB(ctx->opcode)))) {
3402 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3403 return;
3404 }
3405
3406 gen_set_access_type(ctx, ACCESS_RES);
3407 EA = tcg_temp_local_new();
3408 gen_addr_reg_index(ctx, EA);
3409 gen_check_align(ctx, EA, 15);
3410 if (unlikely(ctx->le_mode)) {
3411 gpr1 = cpu_gpr[rd+1];
3412 gpr2 = cpu_gpr[rd];
3413 } else {
3414 gpr1 = cpu_gpr[rd];
3415 gpr2 = cpu_gpr[rd+1];
3416 }
3417 gen_qemu_ld64(ctx, gpr1, EA);
3418 tcg_gen_mov_tl(cpu_reserve, EA);
3419
3420 gen_addr_add(ctx, EA, EA, 8);
3421 gen_qemu_ld64(ctx, gpr2, EA);
3422
3423 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3424 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3425
3426 tcg_temp_free(EA);
3427 }
3428
3429 /* stdcx. */
3430 STCX(stdcx_, 8);
3431 STCX(stqcx_, 16);
3432 #endif /* defined(TARGET_PPC64) */
3433
3434 /* sync */
3435 static void gen_sync(DisasContext *ctx)
3436 {
3437 }
3438
3439 /* wait */
3440 static void gen_wait(DisasContext *ctx)
3441 {
3442 TCGv_i32 t0 = tcg_temp_new_i32();
3443 tcg_gen_st_i32(t0, cpu_env,
3444 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3445 tcg_temp_free_i32(t0);
3446 /* Stop translation, as the CPU is supposed to sleep from now */
3447 gen_exception_err(ctx, EXCP_HLT, 1);
3448 }
3449
3450 /*** Floating-point load ***/
3451 #define GEN_LDF(name, ldop, opc, type) \
3452 static void glue(gen_, name)(DisasContext *ctx) \
3453 { \
3454 TCGv EA; \
3455 if (unlikely(!ctx->fpu_enabled)) { \
3456 gen_exception(ctx, POWERPC_EXCP_FPU); \
3457 return; \
3458 } \
3459 gen_set_access_type(ctx, ACCESS_FLOAT); \
3460 EA = tcg_temp_new(); \
3461 gen_addr_imm_index(ctx, EA, 0); \
3462 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3463 tcg_temp_free(EA); \
3464 }
3465
3466 #define GEN_LDUF(name, ldop, opc, type) \
3467 static void glue(gen_, name##u)(DisasContext *ctx) \
3468 { \
3469 TCGv EA; \
3470 if (unlikely(!ctx->fpu_enabled)) { \
3471 gen_exception(ctx, POWERPC_EXCP_FPU); \
3472 return; \
3473 } \
3474 if (unlikely(rA(ctx->opcode) == 0)) { \
3475 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3476 return; \
3477 } \
3478 gen_set_access_type(ctx, ACCESS_FLOAT); \
3479 EA = tcg_temp_new(); \
3480 gen_addr_imm_index(ctx, EA, 0); \
3481 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3482 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3483 tcg_temp_free(EA); \
3484 }
3485
3486 #define GEN_LDUXF(name, ldop, opc, type) \
3487 static void glue(gen_, name##ux)(DisasContext *ctx) \
3488 { \
3489 TCGv EA; \
3490 if (unlikely(!ctx->fpu_enabled)) { \
3491 gen_exception(ctx, POWERPC_EXCP_FPU); \
3492 return; \
3493 } \
3494 if (unlikely(rA(ctx->opcode) == 0)) { \
3495 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3496 return; \
3497 } \
3498 gen_set_access_type(ctx, ACCESS_FLOAT); \
3499 EA = tcg_temp_new(); \
3500 gen_addr_reg_index(ctx, EA); \
3501 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3502 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3503 tcg_temp_free(EA); \
3504 }
3505
3506 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3507 static void glue(gen_, name##x)(DisasContext *ctx) \
3508 { \
3509 TCGv EA; \
3510 if (unlikely(!ctx->fpu_enabled)) { \
3511 gen_exception(ctx, POWERPC_EXCP_FPU); \
3512 return; \
3513 } \
3514 gen_set_access_type(ctx, ACCESS_FLOAT); \
3515 EA = tcg_temp_new(); \
3516 gen_addr_reg_index(ctx, EA); \
3517 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3518 tcg_temp_free(EA); \
3519 }
3520
3521 #define GEN_LDFS(name, ldop, op, type) \
3522 GEN_LDF(name, ldop, op | 0x20, type); \
3523 GEN_LDUF(name, ldop, op | 0x21, type); \
3524 GEN_LDUXF(name, ldop, op | 0x01, type); \
3525 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3526
3527 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3528 {
3529 TCGv t0 = tcg_temp_new();
3530 TCGv_i32 t1 = tcg_temp_new_i32();
3531 gen_qemu_ld32u(ctx, t0, arg2);
3532 tcg_gen_trunc_tl_i32(t1, t0);
3533 tcg_temp_free(t0);
3534 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3535 tcg_temp_free_i32(t1);
3536 }
3537
3538 /* lfd lfdu lfdux lfdx */
3539 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3540 /* lfs lfsu lfsux lfsx */
3541 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3542
3543 /* lfdp */
3544 static void gen_lfdp(DisasContext *ctx)
3545 {
3546 TCGv EA;
3547 if (unlikely(!ctx->fpu_enabled)) {
3548 gen_exception(ctx, POWERPC_EXCP_FPU);
3549 return;
3550 }
3551 gen_set_access_type(ctx, ACCESS_FLOAT);
3552 EA = tcg_temp_new();
3553 gen_addr_imm_index(ctx, EA, 0);
3554 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3555 64-bit byteswap already. */
3556 if (unlikely(ctx->le_mode)) {
3557 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3558 tcg_gen_addi_tl(EA, EA, 8);
3559 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3560 } else {
3561 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3562 tcg_gen_addi_tl(EA, EA, 8);
3563 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3564 }
3565 tcg_temp_free(EA);
3566 }
3567
3568 /* lfdpx */
3569 static void gen_lfdpx(DisasContext *ctx)
3570 {
3571 TCGv EA;
3572 if (unlikely(!ctx->fpu_enabled)) {
3573 gen_exception(ctx, POWERPC_EXCP_FPU);
3574 return;
3575 }
3576 gen_set_access_type(ctx, ACCESS_FLOAT);
3577 EA = tcg_temp_new();
3578 gen_addr_reg_index(ctx, EA);
3579 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3580 64-bit byteswap already. */
3581 if (unlikely(ctx->le_mode)) {
3582 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3583 tcg_gen_addi_tl(EA, EA, 8);
3584 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3585 } else {
3586 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3587 tcg_gen_addi_tl(EA, EA, 8);
3588 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3589 }
3590 tcg_temp_free(EA);
3591 }
3592
3593 /* lfiwax */
3594 static void gen_lfiwax(DisasContext *ctx)
3595 {
3596 TCGv EA;
3597 TCGv t0;
3598 if (unlikely(!ctx->fpu_enabled)) {
3599 gen_exception(ctx, POWERPC_EXCP_FPU);
3600 return;
3601 }
3602 gen_set_access_type(ctx, ACCESS_FLOAT);
3603 EA = tcg_temp_new();
3604 t0 = tcg_temp_new();
3605 gen_addr_reg_index(ctx, EA);
3606 gen_qemu_ld32s(ctx, t0, EA);
3607 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3608 tcg_temp_free(EA);
3609 tcg_temp_free(t0);
3610 }
3611
3612 /* lfiwzx */
3613 static void gen_lfiwzx(DisasContext *ctx)
3614 {
3615 TCGv EA;
3616 if (unlikely(!ctx->fpu_enabled)) {
3617 gen_exception(ctx, POWERPC_EXCP_FPU);
3618 return;
3619 }
3620 gen_set_access_type(ctx, ACCESS_FLOAT);
3621 EA = tcg_temp_new();
3622 gen_addr_reg_index(ctx, EA);
3623 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3624 tcg_temp_free(EA);
3625 }
3626 /*** Floating-point store ***/
3627 #define GEN_STF(name, stop, opc, type) \
3628 static void glue(gen_, name)(DisasContext *ctx) \
3629 { \
3630 TCGv EA; \
3631 if (unlikely(!ctx->fpu_enabled)) { \
3632 gen_exception(ctx, POWERPC_EXCP_FPU); \
3633 return; \
3634 } \
3635 gen_set_access_type(ctx, ACCESS_FLOAT); \
3636 EA = tcg_temp_new(); \
3637 gen_addr_imm_index(ctx, EA, 0); \
3638 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3639 tcg_temp_free(EA); \
3640 }
3641
3642 #define GEN_STUF(name, stop, opc, type) \
3643 static void glue(gen_, name##u)(DisasContext *ctx) \
3644 { \
3645 TCGv EA; \
3646 if (unlikely(!ctx->fpu_enabled)) { \
3647 gen_exception(ctx, POWERPC_EXCP_FPU); \
3648 return; \
3649 } \
3650 if (unlikely(rA(ctx->opcode) == 0)) { \
3651 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3652 return; \
3653 } \
3654 gen_set_access_type(ctx, ACCESS_FLOAT); \
3655 EA = tcg_temp_new(); \
3656 gen_addr_imm_index(ctx, EA, 0); \
3657 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3658 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3659 tcg_temp_free(EA); \
3660 }
3661
3662 #define GEN_STUXF(name, stop, opc, type) \
3663 static void glue(gen_, name##ux)(DisasContext *ctx) \
3664 { \
3665 TCGv EA; \
3666 if (unlikely(!ctx->fpu_enabled)) { \
3667 gen_exception(ctx, POWERPC_EXCP_FPU); \
3668 return; \
3669 } \
3670 if (unlikely(rA(ctx->opcode) == 0)) { \
3671 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3672 return; \
3673 } \
3674 gen_set_access_type(ctx, ACCESS_FLOAT); \
3675 EA = tcg_temp_new(); \
3676 gen_addr_reg_index(ctx, EA); \
3677 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3678 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3679 tcg_temp_free(EA); \
3680 }
3681
3682 #define GEN_STXF(name, stop, opc2, opc3, type) \
3683 static void glue(gen_, name##x)(DisasContext *ctx) \
3684 { \
3685 TCGv EA; \
3686 if (unlikely(!ctx->fpu_enabled)) { \
3687 gen_exception(ctx, POWERPC_EXCP_FPU); \
3688 return; \
3689 } \
3690 gen_set_access_type(ctx, ACCESS_FLOAT); \
3691 EA = tcg_temp_new(); \
3692 gen_addr_reg_index(ctx, EA); \
3693 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3694 tcg_temp_free(EA); \
3695 }
3696
3697 #define GEN_STFS(name, stop, op, type) \
3698 GEN_STF(name, stop, op | 0x20, type); \
3699 GEN_STUF(name, stop, op | 0x21, type); \
3700 GEN_STUXF(name, stop, op | 0x01, type); \
3701 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3702
3703 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3704 {
3705 TCGv_i32 t0 = tcg_temp_new_i32();
3706 TCGv t1 = tcg_temp_new();
3707 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3708 tcg_gen_extu_i32_tl(t1, t0);
3709 tcg_temp_free_i32(t0);
3710 gen_qemu_st32(ctx, t1, arg2);
3711 tcg_temp_free(t1);
3712 }
3713
3714 /* stfd stfdu stfdux stfdx */
3715 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3716 /* stfs stfsu stfsux stfsx */
3717 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3718
3719 /* stfdp */
3720 static void gen_stfdp(DisasContext *ctx)
3721 {
3722 TCGv EA;
3723 if (unlikely(!ctx->fpu_enabled)) {
3724 gen_exception(ctx, POWERPC_EXCP_FPU);
3725 return;
3726 }
3727 gen_set_access_type(ctx, ACCESS_FLOAT);
3728 EA = tcg_temp_new();
3729 gen_addr_imm_index(ctx, EA, 0);
3730 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3731 64-bit byteswap already. */
3732 if (unlikely(ctx->le_mode)) {
3733 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3734 tcg_gen_addi_tl(EA, EA, 8);
3735 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3736 } else {
3737 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3738 tcg_gen_addi_tl(EA, EA, 8);
3739 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3740 }
3741 tcg_temp_free(EA);
3742 }
3743
3744 /* stfdpx */
3745 static void gen_stfdpx(DisasContext *ctx)
3746 {
3747 TCGv EA;
3748 if (unlikely(!ctx->fpu_enabled)) {
3749 gen_exception(ctx, POWERPC_EXCP_FPU);
3750 return;
3751 }
3752 gen_set_access_type(ctx, ACCESS_FLOAT);
3753 EA = tcg_temp_new();
3754 gen_addr_reg_index(ctx, EA);
3755 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3756 64-bit byteswap already. */
3757 if (unlikely(ctx->le_mode)) {
3758 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3759 tcg_gen_addi_tl(EA, EA, 8);
3760 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3761 } else {
3762 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3763 tcg_gen_addi_tl(EA, EA, 8);
3764 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3765 }
3766 tcg_temp_free(EA);
3767 }
3768
3769 /* Optional: */
3770 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3771 {
3772 TCGv t0 = tcg_temp_new();
3773 tcg_gen_trunc_i64_tl(t0, arg1),
3774 gen_qemu_st32(ctx, t0, arg2);
3775 tcg_temp_free(t0);
3776 }
3777 /* stfiwx */
3778 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3779
3780 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3781 {
3782 #if defined(TARGET_PPC64)
3783 if (ctx->has_cfar)
3784 tcg_gen_movi_tl(cpu_cfar, nip);
3785 #endif
3786 }
3787
3788 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3789 {
3790 if (unlikely(ctx->singlestep_enabled)) {
3791 return false;
3792 }
3793
3794 #ifndef CONFIG_USER_ONLY
3795 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3796 #else
3797 return true;
3798 #endif
3799 }
3800
3801 /*** Branch ***/
3802 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3803 {
3804 if (NARROW_MODE(ctx)) {
3805 dest = (uint32_t) dest;
3806 }
3807 if (use_goto_tb(ctx, dest)) {
3808 tcg_gen_goto_tb(n);
3809 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3810 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3811 } else {
3812 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3813 if (unlikely(ctx->singlestep_enabled)) {
3814 if ((ctx->singlestep_enabled &
3815 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3816 (ctx->exception == POWERPC_EXCP_BRANCH ||
3817 ctx->exception == POWERPC_EXCP_TRACE)) {
3818 target_ulong tmp = ctx->nip;
3819 ctx->nip = dest;
3820 gen_exception(ctx, POWERPC_EXCP_TRACE);
3821 ctx->nip = tmp;
3822 }
3823 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3824 gen_debug_exception(ctx);
3825 }
3826 }
3827 tcg_gen_exit_tb(0);
3828 }
3829 }
3830
3831 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3832 {
3833 if (NARROW_MODE(ctx)) {
3834 nip = (uint32_t)nip;
3835 }
3836 tcg_gen_movi_tl(cpu_lr, nip);
3837 }
3838
3839 /* b ba bl bla */
3840 static void gen_b(DisasContext *ctx)
3841 {
3842 target_ulong li, target;
3843
3844 ctx->exception = POWERPC_EXCP_BRANCH;
3845 /* sign extend LI */
3846 li = LI(ctx->opcode);
3847 li = (li ^ 0x02000000) - 0x02000000;
3848 if (likely(AA(ctx->opcode) == 0)) {
3849 target = ctx->nip + li - 4;
3850 } else {
3851 target = li;
3852 }
3853 if (LK(ctx->opcode)) {
3854 gen_setlr(ctx, ctx->nip);
3855 }
3856 gen_update_cfar(ctx, ctx->nip);
3857 gen_goto_tb(ctx, 0, target);
3858 }
3859
3860 #define BCOND_IM 0
3861 #define BCOND_LR 1
3862 #define BCOND_CTR 2
3863 #define BCOND_TAR 3
3864
3865 static inline void gen_bcond(DisasContext *ctx, int type)
3866 {
3867 uint32_t bo = BO(ctx->opcode);
3868 TCGLabel *l1;
3869 TCGv target;
3870
3871 ctx->exception = POWERPC_EXCP_BRANCH;
3872 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3873 target = tcg_temp_local_new();
3874 if (type == BCOND_CTR)
3875 tcg_gen_mov_tl(target, cpu_ctr);
3876 else if (type == BCOND_TAR)
3877 gen_load_spr(target, SPR_TAR);
3878 else
3879 tcg_gen_mov_tl(target, cpu_lr);
3880 } else {
3881 TCGV_UNUSED(target);
3882 }
3883 if (LK(ctx->opcode))
3884 gen_setlr(ctx, ctx->nip);
3885 l1 = gen_new_label();
3886 if ((bo & 0x4) == 0) {
3887 /* Decrement and test CTR */
3888 TCGv temp = tcg_temp_new();
3889 if (unlikely(type == BCOND_CTR)) {
3890 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3891 return;
3892 }
3893 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3894 if (NARROW_MODE(ctx)) {
3895 tcg_gen_ext32u_tl(temp, cpu_ctr);
3896 } else {
3897 tcg_gen_mov_tl(temp, cpu_ctr);
3898 }
3899 if (bo & 0x2) {
3900 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3901 } else {
3902 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3903 }
3904 tcg_temp_free(temp);
3905 }
3906 if ((bo & 0x10) == 0) {
3907 /* Test CR */
3908 uint32_t bi = BI(ctx->opcode);
3909 uint32_t mask = 0x08 >> (bi & 0x03);
3910 TCGv_i32 temp = tcg_temp_new_i32();
3911
3912 if (bo & 0x8) {
3913 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3914 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3915 } else {
3916 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3917 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3918 }
3919 tcg_temp_free_i32(temp);
3920 }
3921 gen_update_cfar(ctx, ctx->nip);
3922 if (type == BCOND_IM) {
3923 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3924 if (likely(AA(ctx->opcode) == 0)) {
3925 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3926 } else {
3927 gen_goto_tb(ctx, 0, li);
3928 }
3929 gen_set_label(l1);
3930 gen_goto_tb(ctx, 1, ctx->nip);
3931 } else {
3932 if (NARROW_MODE(ctx)) {
3933 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3934 } else {
3935 tcg_gen_andi_tl(cpu_nip, target, ~3);
3936 }
3937 tcg_gen_exit_tb(0);
3938 gen_set_label(l1);
3939 gen_update_nip(ctx, ctx->nip);
3940 tcg_gen_exit_tb(0);
3941 }
3942 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3943 tcg_temp_free(target);
3944 }
3945 }
3946
3947 static void gen_bc(DisasContext *ctx)
3948 {
3949 gen_bcond(ctx, BCOND_IM);
3950 }
3951
3952 static void gen_bcctr(DisasContext *ctx)
3953 {
3954 gen_bcond(ctx, BCOND_CTR);
3955 }
3956
3957 static void gen_bclr(DisasContext *ctx)
3958 {
3959 gen_bcond(ctx, BCOND_LR);
3960 }
3961
3962 static void gen_bctar(DisasContext *ctx)
3963 {
3964 gen_bcond(ctx, BCOND_TAR);
3965 }
3966
3967 /*** Condition register logical ***/
3968 #define GEN_CRLOGIC(name, tcg_op, opc) \
3969 static void glue(gen_, name)(DisasContext *ctx) \
3970 { \
3971 uint8_t bitmask; \
3972 int sh; \
3973 TCGv_i32 t0, t1; \
3974 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3975 t0 = tcg_temp_new_i32(); \
3976 if (sh > 0) \
3977 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3978 else if (sh < 0) \
3979 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3980 else \
3981 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3982 t1 = tcg_temp_new_i32(); \
3983 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3984 if (sh > 0) \
3985 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3986 else if (sh < 0) \
3987 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3988 else \
3989 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3990 tcg_op(t0, t0, t1); \
3991 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3992 tcg_gen_andi_i32(t0, t0, bitmask); \
3993 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3994 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3995 tcg_temp_free_i32(t0); \
3996 tcg_temp_free_i32(t1); \
3997 }
3998
3999 /* crand */
4000 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4001 /* crandc */
4002 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4003 /* creqv */
4004 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4005 /* crnand */
4006 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4007 /* crnor */
4008 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4009 /* cror */
4010 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4011 /* crorc */
4012 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4013 /* crxor */
4014 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4015
4016 /* mcrf */
4017 static void gen_mcrf(DisasContext *ctx)
4018 {
4019 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4020 }
4021
4022 /*** System linkage ***/
4023
4024 /* rfi (supervisor only) */
4025 static void gen_rfi(DisasContext *ctx)
4026 {
4027 #if defined(CONFIG_USER_ONLY)
4028 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4029 #else
4030 /* Restore CPU state */
4031 if (unlikely(ctx->pr)) {
4032 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4033 return;
4034 }
4035 gen_update_cfar(ctx, ctx->nip);
4036 gen_helper_rfi(cpu_env);
4037 gen_sync_exception(ctx);
4038 #endif
4039 }
4040
4041 #if defined(TARGET_PPC64)
4042 static void gen_rfid(DisasContext *ctx)
4043 {
4044 #if defined(CONFIG_USER_ONLY)
4045 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4046 #else
4047 /* Restore CPU state */
4048 if (unlikely(ctx->pr)) {
4049 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4050 return;
4051 }
4052 gen_update_cfar(ctx, ctx->nip);
4053 gen_helper_rfid(cpu_env);
4054 gen_sync_exception(ctx);
4055 #endif
4056 }
4057
4058 static void gen_hrfid(DisasContext *ctx)
4059 {
4060 #if defined(CONFIG_USER_ONLY)
4061 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4062 #else
4063 /* Restore CPU state */
4064 if (unlikely(!ctx->hv)) {
4065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4066 return;
4067 }
4068 gen_helper_hrfid(cpu_env);
4069 gen_sync_exception(ctx);
4070 #endif
4071 }
4072 #endif
4073
4074 /* sc */
4075 #if defined(CONFIG_USER_ONLY)
4076 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4077 #else
4078 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4079 #endif
4080 static void gen_sc(DisasContext *ctx)
4081 {
4082 uint32_t lev;
4083
4084 lev = (ctx->opcode >> 5) & 0x7F;
4085 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4086 }
4087
4088 /*** Trap ***/
4089
4090 /* tw */
4091 static void gen_tw(DisasContext *ctx)
4092 {
4093 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4094 /* Update the nip since this might generate a trap exception */
4095 gen_update_nip(ctx, ctx->nip);
4096 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4097 t0);
4098 tcg_temp_free_i32(t0);
4099 }
4100
4101 /* twi */
4102 static void gen_twi(DisasContext *ctx)
4103 {
4104 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4105 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4106 /* Update the nip since this might generate a trap exception */
4107 gen_update_nip(ctx, ctx->nip);
4108 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4109 tcg_temp_free(t0);
4110 tcg_temp_free_i32(t1);
4111 }
4112
4113 #if defined(TARGET_PPC64)
4114 /* td */
4115 static void gen_td(DisasContext *ctx)
4116 {
4117 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4118 /* Update the nip since this might generate a trap exception */
4119 gen_update_nip(ctx, ctx->nip);
4120 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4121 t0);
4122 tcg_temp_free_i32(t0);
4123 }
4124
4125 /* tdi */
4126 static void gen_tdi(DisasContext *ctx)
4127 {
4128 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4129 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4130 /* Update the nip since this might generate a trap exception */
4131 gen_update_nip(ctx, ctx->nip);
4132 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4133 tcg_temp_free(t0);
4134 tcg_temp_free_i32(t1);
4135 }
4136 #endif
4137
4138 /*** Processor control ***/
4139
4140 static void gen_read_xer(TCGv dst)
4141 {
4142 TCGv t0 = tcg_temp_new();
4143 TCGv t1 = tcg_temp_new();
4144 TCGv t2 = tcg_temp_new();
4145 tcg_gen_mov_tl(dst, cpu_xer);
4146 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4147 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4148 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4149 tcg_gen_or_tl(t0, t0, t1);
4150 tcg_gen_or_tl(dst, dst, t2);
4151 tcg_gen_or_tl(dst, dst, t0);
4152 tcg_temp_free(t0);
4153 tcg_temp_free(t1);
4154 tcg_temp_free(t2);
4155 }
4156
4157 static void gen_write_xer(TCGv src)
4158 {
4159 tcg_gen_andi_tl(cpu_xer, src,
4160 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4161 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4162 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4163 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4164 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4165 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4166 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4167 }
4168
4169 /* mcrxr */
4170 static void gen_mcrxr(DisasContext *ctx)
4171 {
4172 TCGv_i32 t0 = tcg_temp_new_i32();
4173 TCGv_i32 t1 = tcg_temp_new_i32();
4174 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4175
4176 tcg_gen_trunc_tl_i32(t0, cpu_so);
4177 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4178 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4179 tcg_gen_shli_i32(t0, t0, 3);
4180 tcg_gen_shli_i32(t1, t1, 2);
4181 tcg_gen_shli_i32(dst, dst, 1);
4182 tcg_gen_or_i32(dst, dst, t0);
4183 tcg_gen_or_i32(dst, dst, t1);
4184 tcg_temp_free_i32(t0);
4185 tcg_temp_free_i32(t1);
4186
4187 tcg_gen_movi_tl(cpu_so, 0);
4188 tcg_gen_movi_tl(cpu_ov, 0);
4189 tcg_gen_movi_tl(cpu_ca, 0);
4190 }
4191
4192 /* mfcr mfocrf */
4193 static void gen_mfcr(DisasContext *ctx)
4194 {
4195 uint32_t crm, crn;
4196
4197 if (likely(ctx->opcode & 0x00100000)) {
4198 crm = CRM(ctx->opcode);
4199 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4200 crn = ctz32 (crm);
4201 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4202 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4203 cpu_gpr[rD(ctx->opcode)], crn * 4);
4204 }
4205 } else {
4206 TCGv_i32 t0 = tcg_temp_new_i32();
4207 tcg_gen_mov_i32(t0, cpu_crf[0]);
4208 tcg_gen_shli_i32(t0, t0, 4);
4209 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4210 tcg_gen_shli_i32(t0, t0, 4);
4211 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4212 tcg_gen_shli_i32(t0, t0, 4);
4213 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4214 tcg_gen_shli_i32(t0, t0, 4);
4215 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4216 tcg_gen_shli_i32(t0, t0, 4);
4217 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4218 tcg_gen_shli_i32(t0, t0, 4);
4219 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4220 tcg_gen_shli_i32(t0, t0, 4);
4221 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4222 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4223 tcg_temp_free_i32(t0);
4224 }
4225 }
4226
4227 /* mfmsr */
4228 static void gen_mfmsr(DisasContext *ctx)
4229 {
4230 #if defined(CONFIG_USER_ONLY)
4231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4232 #else
4233 if (unlikely(ctx->pr)) {
4234 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4235 return;
4236 }
4237 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4238 #endif
4239 }
4240
4241 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4242 {
4243 #if 0
4244 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4245 printf("ERROR: try to access SPR %d !\n", sprn);
4246 #endif
4247 }
4248 #define SPR_NOACCESS (&spr_noaccess)
4249
4250 /* mfspr */
4251 static inline void gen_op_mfspr(DisasContext *ctx)
4252 {
4253 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4254 uint32_t sprn = SPR(ctx->opcode);
4255
4256 #if defined(CONFIG_USER_ONLY)
4257 read_cb = ctx->spr_cb[sprn].uea_read;
4258 #else
4259 if (ctx->pr) {
4260 read_cb = ctx->spr_cb[sprn].uea_read;
4261 } else if (ctx->hv) {
4262 read_cb = ctx->spr_cb[sprn].hea_read;
4263 } else {
4264 read_cb = ctx->spr_cb[sprn].oea_read;
4265 }
4266 #endif
4267 if (likely(read_cb != NULL)) {
4268 if (likely(read_cb != SPR_NOACCESS)) {
4269 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4270 } else {
4271 /* Privilege exception */
4272 /* This is a hack to avoid warnings when running Linux:
4273 * this OS breaks the PowerPC virtualisation model,
4274 * allowing userland application to read the PVR
4275 */
4276 if (sprn != SPR_PVR) {
4277 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4278 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4279 if (qemu_log_separate()) {
4280 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4281 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4282 }
4283 }
4284 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4285 }
4286 } else {
4287 /* Not defined */
4288 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4289 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4290 if (qemu_log_separate()) {
4291 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4292 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4293 }
4294 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4295 }
4296 }
4297
4298 static void gen_mfspr(DisasContext *ctx)
4299 {
4300 gen_op_mfspr(ctx);
4301 }
4302
4303 /* mftb */
4304 static void gen_mftb(DisasContext *ctx)
4305 {
4306 gen_op_mfspr(ctx);
4307 }
4308
4309 /* mtcrf mtocrf*/
4310 static void gen_mtcrf(DisasContext *ctx)
4311 {
4312 uint32_t crm, crn;
4313
4314 crm = CRM(ctx->opcode);
4315 if (likely((ctx->opcode & 0x00100000))) {
4316 if (crm && ((crm & (crm - 1)) == 0)) {
4317 TCGv_i32 temp = tcg_temp_new_i32();
4318 crn = ctz32 (crm);
4319 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4320 tcg_gen_shri_i32(temp, temp, crn * 4);
4321 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4322 tcg_temp_free_i32(temp);
4323 }
4324 } else {
4325 TCGv_i32 temp = tcg_temp_new_i32();
4326 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4327 for (crn = 0 ; crn < 8 ; crn++) {
4328 if (crm & (1 << crn)) {
4329 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4330 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4331 }
4332 }
4333 tcg_temp_free_i32(temp);
4334 }
4335 }
4336
4337 /* mtmsr */
4338 #if defined(TARGET_PPC64)
4339 static void gen_mtmsrd(DisasContext *ctx)
4340 {
4341 #if defined(CONFIG_USER_ONLY)
4342 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4343 #else
4344 if (unlikely(ctx->pr)) {
4345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4346 return;
4347 }
4348 if (ctx->opcode & 0x00010000) {
4349 /* Special form that does not need any synchronisation */
4350 TCGv t0 = tcg_temp_new();
4351 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4352 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4353 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4354 tcg_temp_free(t0);
4355 } else {
4356 /* XXX: we need to update nip before the store
4357 * if we enter power saving mode, we will exit the loop
4358 * directly from ppc_store_msr
4359 */
4360 gen_update_nip(ctx, ctx->nip);
4361 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4362 /* Must stop the translation as machine state (may have) changed */
4363 /* Note that mtmsr is not always defined as context-synchronizing */
4364 gen_stop_exception(ctx);
4365 }
4366 #endif
4367 }
4368 #endif
4369
4370 static void gen_mtmsr(DisasContext *ctx)
4371 {
4372 #if defined(CONFIG_USER_ONLY)
4373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4374 #else
4375 if (unlikely(ctx->pr)) {
4376 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4377 return;
4378 }
4379 if (ctx->opcode & 0x00010000) {
4380 /* Special form that does not need any synchronisation */
4381 TCGv t0 = tcg_temp_new();
4382 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4383 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4384 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4385 tcg_temp_free(t0);
4386 } else {
4387 TCGv msr = tcg_temp_new();
4388
4389 /* XXX: we need to update nip before the store
4390 * if we enter power saving mode, we will exit the loop
4391 * directly from ppc_store_msr
4392 */
4393 gen_update_nip(ctx, ctx->nip);
4394 #if defined(TARGET_PPC64)
4395 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4396 #else
4397 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4398 #endif
4399 gen_helper_store_msr(cpu_env, msr);
4400 tcg_temp_free(msr);
4401 /* Must stop the translation as machine state (may have) changed */
4402 /* Note that mtmsr is not always defined as context-synchronizing */
4403 gen_stop_exception(ctx);
4404 }
4405 #endif
4406 }
4407
4408 /* mtspr */
4409 static void gen_mtspr(DisasContext *ctx)
4410 {
4411 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4412 uint32_t sprn = SPR(ctx->opcode);
4413
4414 #if defined(CONFIG_USER_ONLY)
4415 write_cb = ctx->spr_cb[sprn].uea_write;
4416 #else
4417 if (ctx->pr) {
4418 write_cb = ctx->spr_cb[sprn].uea_write;
4419 } else if (ctx->hv) {
4420 write_cb = ctx->spr_cb[sprn].hea_write;
4421 } else {
4422 write_cb = ctx->spr_cb[sprn].oea_write;
4423 }
4424 #endif
4425 if (likely(write_cb != NULL)) {
4426 if (likely(write_cb != SPR_NOACCESS)) {
4427 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4428 } else {
4429 /* Privilege exception */
4430 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4431 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4432 if (qemu_log_separate()) {
4433 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4434 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4435 }
4436 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4437 }
4438 } else {
4439 /* Not defined */
4440 if (qemu_log_separate()) {
4441 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4442 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4443 }
4444 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4445 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4446 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4447 }
4448 }
4449
4450 /*** Cache management ***/
4451
4452 /* dcbf */
4453 static void gen_dcbf(DisasContext *ctx)
4454 {
4455 /* XXX: specification says this is treated as a load by the MMU */
4456 TCGv t0;
4457 gen_set_access_type(ctx, ACCESS_CACHE);
4458 t0 = tcg_temp_new();
4459 gen_addr_reg_index(ctx, t0);
4460 gen_qemu_ld8u(ctx, t0, t0);
4461 tcg_temp_free(t0);
4462 }
4463
4464 /* dcbi (Supervisor only) */
4465 static void gen_dcbi(DisasContext *ctx)
4466 {
4467 #if defined(CONFIG_USER_ONLY)
4468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4469 #else
4470 TCGv EA, val;
4471 if (unlikely(ctx->pr)) {
4472 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4473 return;
4474 }
4475 EA = tcg_temp_new();
4476 gen_set_access_type(ctx, ACCESS_CACHE);
4477 gen_addr_reg_index(ctx, EA);
4478 val = tcg_temp_new();
4479 /* XXX: specification says this should be treated as a store by the MMU */
4480 gen_qemu_ld8u(ctx, val, EA);
4481 gen_qemu_st8(ctx, val, EA);
4482 tcg_temp_free(val);
4483 tcg_temp_free(EA);
4484 #endif
4485 }
4486
4487 /* dcdst */
4488 static void gen_dcbst(DisasContext *ctx)
4489 {
4490 /* XXX: specification say this is treated as a load by the MMU */
4491 TCGv t0;
4492 gen_set_access_type(ctx, ACCESS_CACHE);
4493 t0 = tcg_temp_new();
4494 gen_addr_reg_index(ctx, t0);
4495 gen_qemu_ld8u(ctx, t0, t0);
4496 tcg_temp_free(t0);
4497 }
4498
4499 /* dcbt */
4500 static void gen_dcbt(DisasContext *ctx)
4501 {
4502 /* interpreted as no-op */
4503 /* XXX: specification say this is treated as a load by the MMU
4504 * but does not generate any exception
4505 */
4506 }
4507
4508 /* dcbtst */
4509 static void gen_dcbtst(DisasContext *ctx)
4510 {
4511 /* interpreted as no-op */
4512 /* XXX: specification say this is treated as a load by the MMU
4513 * but does not generate any exception
4514 */
4515 }
4516
4517 /* dcbtls */
4518 static void gen_dcbtls(DisasContext *ctx)
4519 {
4520 /* Always fails locking the cache */
4521 TCGv t0 = tcg_temp_new();
4522 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4523 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4524 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4525 tcg_temp_free(t0);
4526 }
4527
4528 /* dcbz */
4529 static void gen_dcbz(DisasContext *ctx)
4530 {
4531 TCGv tcgv_addr;
4532 TCGv_i32 tcgv_is_dcbzl;
4533 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4534
4535 gen_set_access_type(ctx, ACCESS_CACHE);
4536 /* NIP cannot be restored if the memory exception comes from an helper */
4537 gen_update_nip(ctx, ctx->nip - 4);
4538 tcgv_addr = tcg_temp_new();
4539 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4540
4541 gen_addr_reg_index(ctx, tcgv_addr);
4542 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4543
4544 tcg_temp_free(tcgv_addr);
4545 tcg_temp_free_i32(tcgv_is_dcbzl);
4546 }
4547
4548 /* dst / dstt */
4549 static void gen_dst(DisasContext *ctx)
4550 {
4551 if (rA(ctx->opcode) == 0) {
4552 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4553 } else {
4554 /* interpreted as no-op */
4555 }
4556 }
4557
4558 /* dstst /dststt */
4559 static void gen_dstst(DisasContext *ctx)
4560 {
4561 if (rA(ctx->opcode) == 0) {
4562 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4563 } else {
4564 /* interpreted as no-op */
4565 }
4566
4567 }
4568
4569 /* dss / dssall */
4570 static void gen_dss(DisasContext *ctx)
4571 {
4572 /* interpreted as no-op */
4573 }
4574
4575 /* icbi */
4576 static void gen_icbi(DisasContext *ctx)
4577 {
4578 TCGv t0;
4579 gen_set_access_type(ctx, ACCESS_CACHE);
4580 /* NIP cannot be restored if the memory exception comes from an helper */
4581 gen_update_nip(ctx, ctx->nip - 4);
4582 t0 = tcg_temp_new();
4583 gen_addr_reg_index(ctx, t0);
4584 gen_helper_icbi(cpu_env, t0);
4585 tcg_temp_free(t0);
4586 }
4587
4588 /* Optional: */
4589 /* dcba */
4590 static void gen_dcba(DisasContext *ctx)
4591 {
4592 /* interpreted as no-op */
4593 /* XXX: specification say this is treated as a store by the MMU
4594 * but does not generate any exception
4595 */
4596 }
4597
4598 /*** Segment register manipulation ***/
4599 /* Supervisor only: */
4600
4601 /* mfsr */
4602 static void gen_mfsr(DisasContext *ctx)
4603 {
4604 #if defined(CONFIG_USER_ONLY)
4605 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4606 #else
4607 TCGv t0;
4608 if (unlikely(ctx->pr)) {
4609 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4610 return;
4611 }
4612 t0 = tcg_const_tl(SR(ctx->opcode));
4613 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4614 tcg_temp_free(t0);
4615 #endif
4616 }
4617
4618 /* mfsrin */
4619 static void gen_mfsrin(DisasContext *ctx)
4620 {
4621 #if defined(CONFIG_USER_ONLY)
4622 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4623 #else
4624 TCGv t0;
4625 if (unlikely(ctx->pr)) {
4626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4627 return;
4628 }
4629 t0 = tcg_temp_new();
4630 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4631 tcg_gen_andi_tl(t0, t0, 0xF);
4632 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4633 tcg_temp_free(t0);
4634 #endif
4635 }
4636
4637 /* mtsr */
4638 static void gen_mtsr(DisasContext *ctx)
4639 {
4640 #if defined(CONFIG_USER_ONLY)
4641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4642 #else
4643 TCGv t0;
4644 if (unlikely(ctx->pr)) {
4645 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4646 return;
4647 }
4648 t0 = tcg_const_tl(SR(ctx->opcode));
4649 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4650 tcg_temp_free(t0);
4651 #endif
4652 }
4653
4654 /* mtsrin */
4655 static void gen_mtsrin(DisasContext *ctx)
4656 {
4657 #if defined(CONFIG_USER_ONLY)
4658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4659 #else
4660 TCGv t0;
4661 if (unlikely(ctx->pr)) {
4662 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4663 return;
4664 }
4665 t0 = tcg_temp_new();
4666 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4667 tcg_gen_andi_tl(t0, t0, 0xF);
4668 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4669 tcg_temp_free(t0);
4670 #endif
4671 }
4672
4673 #if defined(TARGET_PPC64)
4674 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4675
4676 /* mfsr */
4677 static void gen_mfsr_64b(DisasContext *ctx)
4678 {
4679 #if defined(CONFIG_USER_ONLY)
4680 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4681 #else
4682 TCGv t0;
4683 if (unlikely(ctx->pr)) {
4684 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4685 return;
4686 }
4687 t0 = tcg_const_tl(SR(ctx->opcode));
4688 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4689 tcg_temp_free(t0);
4690 #endif
4691 }
4692
4693 /* mfsrin */
4694 static void gen_mfsrin_64b(DisasContext *ctx)
4695 {
4696 #if defined(CONFIG_USER_ONLY)
4697 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4698 #else
4699 TCGv t0;
4700 if (unlikely(ctx->pr)) {
4701 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4702 return;
4703 }
4704 t0 = tcg_temp_new();
4705 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4706 tcg_gen_andi_tl(t0, t0, 0xF);
4707 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4708 tcg_temp_free(t0);
4709 #endif
4710 }
4711
4712 /* mtsr */
4713 static void gen_mtsr_64b(DisasContext *ctx)
4714 {
4715 #if defined(CONFIG_USER_ONLY)
4716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4717 #else
4718 TCGv t0;
4719 if (unlikely(ctx->pr)) {
4720 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4721 return;
4722 }
4723 t0 = tcg_const_tl(SR(ctx->opcode));
4724 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4725 tcg_temp_free(t0);
4726 #endif
4727 }
4728
4729 /* mtsrin */
4730 static void gen_mtsrin_64b(DisasContext *ctx)
4731 {
4732 #if defined(CONFIG_USER_ONLY)
4733 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4734 #else
4735 TCGv t0;
4736 if (unlikely(ctx->pr)) {
4737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4738 return;
4739 }
4740 t0 = tcg_temp_new();
4741 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4742 tcg_gen_andi_tl(t0, t0, 0xF);
4743 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4744 tcg_temp_free(t0);
4745 #endif
4746 }
4747
4748 /* slbmte */
4749 static void gen_slbmte(DisasContext *ctx)
4750 {
4751 #if defined(CONFIG_USER_ONLY)
4752 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4753 #else
4754 if (unlikely(ctx->pr)) {
4755 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4756 return;
4757 }
4758 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4759 cpu_gpr[rS(ctx->opcode)]);
4760 #endif
4761 }
4762
4763 static void gen_slbmfee(DisasContext *ctx)
4764 {
4765 #if defined(CONFIG_USER_ONLY)
4766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4767 #else
4768 if (unlikely(ctx->pr)) {
4769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4770 return;
4771 }
4772 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4773 cpu_gpr[rB(ctx->opcode)]);
4774 #endif
4775 }
4776
4777 static void gen_slbmfev(DisasContext *ctx)
4778 {
4779 #if defined(CONFIG_USER_ONLY)
4780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4781 #else
4782 if (unlikely(ctx->pr)) {
4783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4784 return;
4785 }
4786 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4787 cpu_gpr[rB(ctx->opcode)]);
4788 #endif
4789 }
4790 #endif /* defined(TARGET_PPC64) */
4791
4792 /*** Lookaside buffer management ***/
4793 /* Optional & supervisor only: */
4794
4795 /* tlbia */
4796 static void gen_tlbia(DisasContext *ctx)
4797 {
4798 #if defined(CONFIG_USER_ONLY)
4799 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4800 #else
4801 if (unlikely(ctx->pr)) {
4802 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4803 return;
4804 }
4805 gen_helper_tlbia(cpu_env);
4806 #endif
4807 }
4808
4809 /* tlbiel */
4810 static void gen_tlbiel(DisasContext *ctx)
4811 {
4812 #if defined(CONFIG_USER_ONLY)
4813 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4814 #else
4815 if (unlikely(ctx->pr)) {
4816 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4817 return;
4818 }
4819 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4820 #endif
4821 }
4822
4823 /* tlbie */
4824 static void gen_tlbie(DisasContext *ctx)
4825 {
4826 #if defined(CONFIG_USER_ONLY)
4827 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4828 #else
4829 if (unlikely(ctx->pr)) {
4830 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4831 return;
4832 }
4833 if (NARROW_MODE(ctx)) {
4834 TCGv t0 = tcg_temp_new();
4835 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4836 gen_helper_tlbie(cpu_env, t0);
4837 tcg_temp_free(t0);
4838 } else {
4839 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4840 }
4841 #endif
4842 }
4843
4844 /* tlbsync */
4845 static void gen_tlbsync(DisasContext *ctx)
4846 {
4847 #if defined(CONFIG_USER_ONLY)
4848 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4849 #else
4850 if (unlikely(ctx->pr)) {
4851 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4852 return;
4853 }
4854 /* This has no effect: it should ensure that all previous
4855 * tlbie have completed
4856 */
4857 gen_stop_exception(ctx);
4858 #endif
4859 }
4860
4861 #if defined(TARGET_PPC64)
4862 /* slbia */
4863 static void gen_slbia(DisasContext *ctx)
4864 {
4865 #if defined(CONFIG_USER_ONLY)
4866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4867 #else
4868 if (unlikely(ctx->pr)) {
4869 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4870 return;
4871 }
4872 gen_helper_slbia(cpu_env);
4873 #endif
4874 }
4875
4876 /* slbie */
4877 static void gen_slbie(DisasContext *ctx)
4878 {
4879 #if defined(CONFIG_USER_ONLY)
4880 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4881 #else
4882 if (unlikely(ctx->pr)) {
4883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4884 return;
4885 }
4886 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4887 #endif
4888 }
4889 #endif
4890
4891 /*** External control ***/
4892 /* Optional: */
4893
4894 /* eciwx */
4895 static void gen_eciwx(DisasContext *ctx)
4896 {
4897 TCGv t0;
4898 /* Should check EAR[E] ! */
4899 gen_set_access_type(ctx, ACCESS_EXT);
4900 t0 = tcg_temp_new();
4901 gen_addr_reg_index(ctx, t0);
4902 gen_check_align(ctx, t0, 0x03);
4903 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4904 tcg_temp_free(t0);
4905 }
4906
4907 /* ecowx */
4908 static void gen_ecowx(DisasContext *ctx)
4909 {
4910 TCGv t0;
4911 /* Should check EAR[E] ! */
4912 gen_set_access_type(ctx, ACCESS_EXT);
4913 t0 = tcg_temp_new();
4914 gen_addr_reg_index(ctx, t0);
4915 gen_check_align(ctx, t0, 0x03);
4916 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4917 tcg_temp_free(t0);
4918 }
4919
4920 /* PowerPC 601 specific instructions */
4921
4922 /* abs - abs. */
4923 static void gen_abs(DisasContext *ctx)
4924 {
4925 TCGLabel *l1 = gen_new_label();
4926 TCGLabel *l2 = gen_new_label();
4927 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4928 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4929 tcg_gen_br(l2);
4930 gen_set_label(l1);
4931 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4932 gen_set_label(l2);
4933 if (unlikely(Rc(ctx->opcode) != 0))
4934 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4935 }
4936
4937 /* abso - abso. */
4938 static void gen_abso(DisasContext *ctx)
4939 {
4940 TCGLabel *l1 = gen_new_label();
4941 TCGLabel *l2 = gen_new_label();
4942 TCGLabel *l3 = gen_new_label();
4943 /* Start with XER OV disabled, the most likely case */
4944 tcg_gen_movi_tl(cpu_ov, 0);
4945 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4946 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4947 tcg_gen_movi_tl(cpu_ov, 1);
4948 tcg_gen_movi_tl(cpu_so, 1);
4949 tcg_gen_br(l2);
4950 gen_set_label(l1);
4951 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4952 tcg_gen_br(l3);
4953 gen_set_label(l2);
4954 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4955 gen_set_label(l3);
4956 if (unlikely(Rc(ctx->opcode) != 0))
4957 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4958 }
4959
4960 /* clcs */
4961 static void gen_clcs(DisasContext *ctx)
4962 {
4963 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4964 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4965 tcg_temp_free_i32(t0);
4966 /* Rc=1 sets CR0 to an undefined state */
4967 }
4968
4969 /* div - div. */
4970 static void gen_div(DisasContext *ctx)
4971 {
4972 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4973 cpu_gpr[rB(ctx->opcode)]);
4974 if (unlikely(Rc(ctx->opcode) != 0))
4975 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4976 }
4977
4978 /* divo - divo. */
4979 static void gen_divo(DisasContext *ctx)
4980 {
4981 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4982 cpu_gpr[rB(ctx->opcode)]);
4983 if (unlikely(Rc(ctx->opcode) != 0))
4984 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4985 }
4986
4987 /* divs - divs. */
4988 static void gen_divs(DisasContext *ctx)
4989 {
4990 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4991 cpu_gpr[rB(ctx->opcode)]);
4992 if (unlikely(Rc(ctx->opcode) != 0))
4993 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4994 }
4995
4996 /* divso - divso. */
4997 static void gen_divso(DisasContext *ctx)
4998 {
4999 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5000 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5001 if (unlikely(Rc(ctx->opcode) != 0))
5002 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5003 }
5004
5005 /* doz - doz. */
5006 static void gen_doz(DisasContext *ctx)
5007 {
5008 TCGLabel *l1 = gen_new_label();
5009 TCGLabel *l2 = gen_new_label();
5010 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5011 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5012 tcg_gen_br(l2);
5013 gen_set_label(l1);
5014 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5015 gen_set_label(l2);
5016 if (unlikely(Rc(ctx->opcode) != 0))
5017 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5018 }
5019
5020 /* dozo - dozo. */
5021 static void gen_dozo(DisasContext *ctx)
5022 {
5023 TCGLabel *l1 = gen_new_label();
5024 TCGLabel *l2 = gen_new_label();
5025 TCGv t0 = tcg_temp_new();
5026 TCGv t1 = tcg_temp_new();
5027 TCGv t2 = tcg_temp_new();
5028 /* Start with XER OV disabled, the most likely case */
5029 tcg_gen_movi_tl(cpu_ov, 0);
5030 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5031 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5032 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5033 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5034 tcg_gen_andc_tl(t1, t1, t2);
5035 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5036 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5037 tcg_gen_movi_tl(cpu_ov, 1);
5038 tcg_gen_movi_tl(cpu_so, 1);
5039 tcg_gen_br(l2);
5040 gen_set_label(l1);
5041 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5042 gen_set_label(l2);
5043 tcg_temp_free(t0);
5044 tcg_temp_free(t1);
5045 tcg_temp_free(t2);
5046 if (unlikely(Rc(ctx->opcode) != 0))
5047 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5048 }
5049
5050 /* dozi */
5051 static void gen_dozi(DisasContext *ctx)
5052 {
5053 target_long simm = SIMM(ctx->opcode);
5054 TCGLabel *l1 = gen_new_label();
5055 TCGLabel *l2 = gen_new_label();
5056 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5057 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5058 tcg_gen_br(l2);
5059 gen_set_label(l1);
5060 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5061 gen_set_label(l2);
5062 if (unlikely(Rc(ctx->opcode) != 0))
5063 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5064 }
5065
5066 /* lscbx - lscbx. */
5067 static void gen_lscbx(DisasContext *ctx)
5068 {
5069 TCGv t0 = tcg_temp_new();
5070 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5071 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5072 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5073
5074 gen_addr_reg_index(ctx, t0);
5075 /* NIP cannot be restored if the memory exception comes from an helper */
5076 gen_update_nip(ctx, ctx->nip - 4);
5077 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5078 tcg_temp_free_i32(t1);
5079 tcg_temp_free_i32(t2);
5080 tcg_temp_free_i32(t3);
5081 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5082 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5083 if (unlikely(Rc(ctx->opcode) != 0))
5084 gen_set_Rc0(ctx, t0);
5085 tcg_temp_free(t0);
5086 }
5087
5088 /* maskg - maskg. */
5089 static void gen_maskg(DisasContext *ctx)
5090 {
5091 TCGLabel *l1 = gen_new_label();
5092 TCGv t0 = tcg_temp_new();
5093 TCGv t1 = tcg_temp_new();
5094 TCGv t2 = tcg_temp_new();
5095 TCGv t3 = tcg_temp_new();
5096 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5097 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5098 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5099 tcg_gen_addi_tl(t2, t0, 1);
5100 tcg_gen_shr_tl(t2, t3, t2);
5101 tcg_gen_shr_tl(t3, t3, t1);
5102 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5103 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5104 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5105 gen_set_label(l1);
5106 tcg_temp_free(t0);
5107 tcg_temp_free(t1);
5108 tcg_temp_free(t2);
5109 tcg_temp_free(t3);
5110 if (unlikely(Rc(ctx->opcode) != 0))
5111 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5112 }
5113
5114 /* maskir - maskir. */
5115 static void gen_maskir(DisasContext *ctx)
5116 {
5117 TCGv t0 = tcg_temp_new();
5118 TCGv t1 = tcg_temp_new();
5119 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5120 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5121 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5122 tcg_temp_free(t0);
5123 tcg_temp_free(t1);
5124 if (unlikely(Rc(ctx->opcode) != 0))
5125 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5126 }
5127
5128 /* mul - mul. */
5129 static void gen_mul(DisasContext *ctx)
5130 {
5131 TCGv_i64 t0 = tcg_temp_new_i64();
5132 TCGv_i64 t1 = tcg_temp_new_i64();
5133 TCGv t2 = tcg_temp_new();
5134 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5135 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5136 tcg_gen_mul_i64(t0, t0, t1);
5137 tcg_gen_trunc_i64_tl(t2, t0);
5138 gen_store_spr(SPR_MQ, t2);
5139 tcg_gen_shri_i64(t1, t0, 32);
5140 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5141 tcg_temp_free_i64(t0);
5142 tcg_temp_free_i64(t1);
5143 tcg_temp_free(t2);
5144 if (unlikely(Rc(ctx->opcode) != 0))
5145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5146 }
5147
5148 /* mulo - mulo. */
5149 static void gen_mulo(DisasContext *ctx)
5150 {
5151 TCGLabel *l1 = gen_new_label();
5152 TCGv_i64 t0 = tcg_temp_new_i64();
5153 TCGv_i64 t1 = tcg_temp_new_i64();
5154 TCGv t2 = tcg_temp_new();
5155 /* Start with XER OV disabled, the most likely case */
5156 tcg_gen_movi_tl(cpu_ov, 0);
5157 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5158 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5159 tcg_gen_mul_i64(t0, t0, t1);
5160 tcg_gen_trunc_i64_tl(t2, t0);
5161 gen_store_spr(SPR_MQ, t2);
5162 tcg_gen_shri_i64(t1, t0, 32);
5163 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5164 tcg_gen_ext32s_i64(t1, t0);
5165 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5166 tcg_gen_movi_tl(cpu_ov, 1);
5167 tcg_gen_movi_tl(cpu_so, 1);
5168 gen_set_label(l1);
5169 tcg_temp_free_i64(t0);
5170 tcg_temp_free_i64(t1);
5171 tcg_temp_free(t2);
5172 if (unlikely(Rc(ctx->opcode) != 0))
5173 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5174 }
5175
5176 /* nabs - nabs. */
5177 static void gen_nabs(DisasContext *ctx)
5178 {
5179 TCGLabel *l1 = gen_new_label();
5180 TCGLabel *l2 = gen_new_label();
5181 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5182 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5183 tcg_gen_br(l2);
5184 gen_set_label(l1);
5185 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5186 gen_set_label(l2);
5187 if (unlikely(Rc(ctx->opcode) != 0))
5188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5189 }
5190
5191 /* nabso - nabso. */
5192 static void gen_nabso(DisasContext *ctx)
5193 {
5194 TCGLabel *l1 = gen_new_label();
5195 TCGLabel *l2 = gen_new_label();
5196 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5197 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5198 tcg_gen_br(l2);
5199 gen_set_label(l1);
5200 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5201 gen_set_label(l2);
5202 /* nabs never overflows */
5203 tcg_gen_movi_tl(cpu_ov, 0);
5204 if (unlikely(Rc(ctx->opcode) != 0))
5205 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5206 }
5207
5208 /* rlmi - rlmi. */
5209 static void gen_rlmi(DisasContext *ctx)
5210 {
5211 uint32_t mb = MB(ctx->opcode);
5212 uint32_t me = ME(ctx->opcode);
5213 TCGv t0 = tcg_temp_new();
5214 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5215 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5216 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5217 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5218 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5219 tcg_temp_free(t0);
5220 if (unlikely(Rc(ctx->opcode) != 0))
5221 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5222 }
5223
5224 /* rrib - rrib. */
5225 static void gen_rrib(DisasContext *ctx)
5226 {
5227 TCGv t0 = tcg_temp_new();
5228 TCGv t1 = tcg_temp_new();
5229 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5230 tcg_gen_movi_tl(t1, 0x80000000);
5231 tcg_gen_shr_tl(t1, t1, t0);
5232 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5233 tcg_gen_and_tl(t0, t0, t1);
5234 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5235 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5236 tcg_temp_free(t0);
5237 tcg_temp_free(t1);
5238 if (unlikely(Rc(ctx->opcode) != 0))
5239 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5240 }
5241
5242 /* sle - sle. */
5243 static void gen_sle(DisasContext *ctx)
5244 {
5245 TCGv t0 = tcg_temp_new();
5246 TCGv t1 = tcg_temp_new();
5247 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5248 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5249 tcg_gen_subfi_tl(t1, 32, t1);
5250 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5251 tcg_gen_or_tl(t1, t0, t1);
5252 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5253 gen_store_spr(SPR_MQ, t1);
5254 tcg_temp_free(t0);
5255 tcg_temp_free(t1);
5256 if (unlikely(Rc(ctx->opcode) != 0))
5257 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5258 }
5259
5260 /* sleq - sleq. */
5261 static void gen_sleq(DisasContext *ctx)
5262 {
5263 TCGv t0 = tcg_temp_new();
5264 TCGv t1 = tcg_temp_new();
5265 TCGv t2 = tcg_temp_new();
5266 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5267 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5268 tcg_gen_shl_tl(t2, t2, t0);
5269 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5270 gen_load_spr(t1, SPR_MQ);
5271 gen_store_spr(SPR_MQ, t0);
5272 tcg_gen_and_tl(t0, t0, t2);
5273 tcg_gen_andc_tl(t1, t1, t2);
5274 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5275 tcg_temp_free(t0);
5276 tcg_temp_free(t1);
5277 tcg_temp_free(t2);
5278 if (unlikely(Rc(ctx->opcode) != 0))
5279 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5280 }
5281
5282 /* sliq - sliq. */
5283 static void gen_sliq(DisasContext *ctx)
5284 {
5285 int sh = SH(ctx->opcode);
5286 TCGv t0 = tcg_temp_new();
5287 TCGv t1 = tcg_temp_new();
5288 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5289 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5290 tcg_gen_or_tl(t1, t0, t1);
5291 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5292 gen_store_spr(SPR_MQ, t1);
5293 tcg_temp_free(t0);
5294 tcg_temp_free(t1);
5295 if (unlikely(Rc(ctx->opcode) != 0))
5296 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5297 }
5298
5299 /* slliq - slliq. */
5300 static void gen_slliq(DisasContext *ctx)
5301 {
5302 int sh = SH(ctx->opcode);
5303 TCGv t0 = tcg_temp_new();
5304 TCGv t1 = tcg_temp_new();
5305 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5306 gen_load_spr(t1, SPR_MQ);
5307 gen_store_spr(SPR_MQ, t0);
5308 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5309 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5310 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5311 tcg_temp_free(t0);
5312 tcg_temp_free(t1);
5313 if (unlikely(Rc(ctx->opcode) != 0))
5314 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5315 }
5316
5317 /* sllq - sllq. */
5318 static void gen_sllq(DisasContext *ctx)
5319 {
5320 TCGLabel *l1 = gen_new_label();
5321 TCGLabel *l2 = gen_new_label();
5322 TCGv t0 = tcg_temp_local_new();
5323 TCGv t1 = tcg_temp_local_new();
5324 TCGv t2 = tcg_temp_local_new();
5325 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5326 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5327 tcg_gen_shl_tl(t1, t1, t2);
5328 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5329 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5330 gen_load_spr(t0, SPR_MQ);
5331 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5332 tcg_gen_br(l2);
5333 gen_set_label(l1);
5334 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5335 gen_load_spr(t2, SPR_MQ);
5336 tcg_gen_andc_tl(t1, t2, t1);
5337 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5338 gen_set_label(l2);
5339 tcg_temp_free(t0);
5340 tcg_temp_free(t1);
5341 tcg_temp_free(t2);
5342 if (unlikely(Rc(ctx->opcode) != 0))
5343 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5344 }
5345
5346 /* slq - slq. */
5347 static void gen_slq(DisasContext *ctx)
5348 {
5349 TCGLabel *l1 = gen_new_label();
5350 TCGv t0 = tcg_temp_new();
5351 TCGv t1 = tcg_temp_new();
5352 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5353 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5354 tcg_gen_subfi_tl(t1, 32, t1);
5355 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5356 tcg_gen_or_tl(t1, t0, t1);
5357 gen_store_spr(SPR_MQ, t1);
5358 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5359 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5360 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5361 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5362 gen_set_label(l1);
5363 tcg_temp_free(t0);
5364 tcg_temp_free(t1);
5365 if (unlikely(Rc(ctx->opcode) != 0))
5366 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5367 }
5368
5369 /* sraiq - sraiq. */
5370 static void gen_sraiq(DisasContext *ctx)
5371 {
5372 int sh = SH(ctx->opcode);
5373 TCGLabel *l1 = gen_new_label();
5374 TCGv t0 = tcg_temp_new();
5375 TCGv t1 = tcg_temp_new();
5376 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5377 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5378 tcg_gen_or_tl(t0, t0, t1);
5379 gen_store_spr(SPR_MQ, t0);
5380 tcg_gen_movi_tl(cpu_ca, 0);
5381 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5382 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5383 tcg_gen_movi_tl(cpu_ca, 1);
5384 gen_set_label(l1);
5385 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5386 tcg_temp_free(t0);
5387 tcg_temp_free(t1);
5388 if (unlikely(Rc(ctx->opcode) != 0))
5389 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5390 }
5391
5392 /* sraq - sraq. */
5393 static void gen_sraq(DisasContext *ctx)
5394 {
5395 TCGLabel *l1 = gen_new_label();
5396 TCGLabel *l2 = gen_new_label();
5397 TCGv t0 = tcg_temp_new();
5398 TCGv t1 = tcg_temp_local_new();
5399 TCGv t2 = tcg_temp_local_new();
5400 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5401 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5402 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5403 tcg_gen_subfi_tl(t2, 32, t2);
5404 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5405 tcg_gen_or_tl(t0, t0, t2);
5406 gen_store_spr(SPR_MQ, t0);
5407 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5408 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5409 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5410 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5411 gen_set_label(l1);
5412 tcg_temp_free(t0);
5413 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5414 tcg_gen_movi_tl(cpu_ca, 0);
5415 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5416 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5417 tcg_gen_movi_tl(cpu_ca, 1);
5418 gen_set_label(l2);
5419 tcg_temp_free(t1);
5420 tcg_temp_free(t2);
5421 if (unlikely(Rc(ctx->opcode) != 0))
5422 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5423 }
5424
5425 /* sre - sre. */
5426 static void gen_sre(DisasContext *ctx)
5427 {
5428 TCGv t0 = tcg_temp_new();
5429 TCGv t1 = tcg_temp_new();
5430 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5431 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5432 tcg_gen_subfi_tl(t1, 32, t1);
5433 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5434 tcg_gen_or_tl(t1, t0, t1);
5435 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5436 gen_store_spr(SPR_MQ, t1);
5437 tcg_temp_free(t0);
5438 tcg_temp_free(t1);
5439 if (unlikely(Rc(ctx->opcode) != 0))
5440 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5441 }
5442
5443 /* srea - srea. */
5444 static void gen_srea(DisasContext *ctx)
5445 {
5446 TCGv t0 = tcg_temp_new();
5447 TCGv t1 = tcg_temp_new();
5448 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5449 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5450 gen_store_spr(SPR_MQ, t0);
5451 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5452 tcg_temp_free(t0);
5453 tcg_temp_free(t1);
5454 if (unlikely(Rc(ctx->opcode) != 0))
5455 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5456 }
5457
5458 /* sreq */
5459 static void gen_sreq(DisasContext *ctx)
5460 {
5461 TCGv t0 = tcg_temp_new();
5462 TCGv t1 = tcg_temp_new();
5463 TCGv t2 = tcg_temp_new();
5464 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5465 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5466 tcg_gen_shr_tl(t1, t1, t0);
5467 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5468 gen_load_spr(t2, SPR_MQ);
5469 gen_store_spr(SPR_MQ, t0);
5470 tcg_gen_and_tl(t0, t0, t1);
5471 tcg_gen_andc_tl(t2, t2, t1);
5472 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5473 tcg_temp_free(t0);
5474 tcg_temp_free(t1);
5475 tcg_temp_free(t2);
5476 if (unlikely(Rc(ctx->opcode) != 0))
5477 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5478 }
5479
5480 /* sriq */
5481 static void gen_sriq(DisasContext *ctx)
5482 {
5483 int sh = SH(ctx->opcode);
5484 TCGv t0 = tcg_temp_new();
5485 TCGv t1 = tcg_temp_new();
5486 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5487 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5488 tcg_gen_or_tl(t1, t0, t1);
5489 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5490 gen_store_spr(SPR_MQ, t1);
5491 tcg_temp_free(t0);
5492 tcg_temp_free(t1);
5493 if (unlikely(Rc(ctx->opcode) != 0))
5494 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5495 }
5496
5497 /* srliq */
5498 static void gen_srliq(DisasContext *ctx)
5499 {
5500 int sh = SH(ctx->opcode);
5501 TCGv t0 = tcg_temp_new();
5502 TCGv t1 = tcg_temp_new();
5503 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5504 gen_load_spr(t1, SPR_MQ);
5505 gen_store_spr(SPR_MQ, t0);
5506 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5507 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5508 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5509 tcg_temp_free(t0);
5510 tcg_temp_free(t1);
5511 if (unlikely(Rc(ctx->opcode) != 0))
5512 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5513 }
5514
5515 /* srlq */
5516 static void gen_srlq(DisasContext *ctx)
5517 {
5518 TCGLabel *l1 = gen_new_label();
5519 TCGLabel *l2 = gen_new_label();
5520 TCGv t0 = tcg_temp_local_new();
5521 TCGv t1 = tcg_temp_local_new();
5522 TCGv t2 = tcg_temp_local_new();
5523 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5524 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5525 tcg_gen_shr_tl(t2, t1, t2);
5526 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5527 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5528 gen_load_spr(t0, SPR_MQ);
5529 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5530 tcg_gen_br(l2);
5531 gen_set_label(l1);
5532 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5533 tcg_gen_and_tl(t0, t0, t2);
5534 gen_load_spr(t1, SPR_MQ);
5535 tcg_gen_andc_tl(t1, t1, t2);
5536 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5537 gen_set_label(l2);
5538 tcg_temp_free(t0);
5539 tcg_temp_free(t1);
5540 tcg_temp_free(t2);
5541 if (unlikely(Rc(ctx->opcode) != 0))
5542 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5543 }
5544
5545 /* srq */
5546 static void gen_srq(DisasContext *ctx)
5547 {
5548 TCGLabel *l1 = gen_new_label();
5549 TCGv t0 = tcg_temp_new();
5550 TCGv t1 = tcg_temp_new();
5551 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5552 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5553 tcg_gen_subfi_tl(t1, 32, t1);
5554 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5555 tcg_gen_or_tl(t1, t0, t1);
5556 gen_store_spr(SPR_MQ, t1);
5557 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5558 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5559 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5560 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5561 gen_set_label(l1);
5562 tcg_temp_free(t0);
5563 tcg_temp_free(t1);
5564 if (unlikely(Rc(ctx->opcode) != 0))
5565 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5566 }
5567
5568 /* PowerPC 602 specific instructions */
5569
5570 /* dsa */
5571 static void gen_dsa(DisasContext *ctx)
5572 {
5573 /* XXX: TODO */
5574 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5575 }
5576
5577 /* esa */
5578 static void gen_esa(DisasContext *ctx)
5579 {
5580 /* XXX: TODO */
5581 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5582 }
5583
5584 /* mfrom */
5585 static void gen_mfrom(DisasContext *ctx)
5586 {
5587 #if defined(CONFIG_USER_ONLY)
5588 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5589 #else
5590 if (unlikely(ctx->pr)) {
5591 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5592 return;
5593 }
5594 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5595 #endif
5596 }
5597
5598 /* 602 - 603 - G2 TLB management */
5599
5600 /* tlbld */
5601 static void gen_tlbld_6xx(DisasContext *ctx)
5602 {
5603 #if defined(CONFIG_USER_ONLY)
5604 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5605 #else
5606 if (unlikely(ctx->pr)) {
5607 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5608 return;
5609 }
5610 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5611 #endif
5612 }
5613
5614 /* tlbli */
5615 static void gen_tlbli_6xx(DisasContext *ctx)
5616 {
5617 #if defined(CONFIG_USER_ONLY)
5618 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5619 #else
5620 if (unlikely(ctx->pr)) {
5621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5622 return;
5623 }
5624 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5625 #endif
5626 }
5627
5628 /* 74xx TLB management */
5629
5630 /* tlbld */
5631 static void gen_tlbld_74xx(DisasContext *ctx)
5632 {
5633 #if defined(CONFIG_USER_ONLY)
5634 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5635 #else
5636 if (unlikely(ctx->pr)) {
5637 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5638 return;
5639 }
5640 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5641 #endif
5642 }
5643
5644 /* tlbli */
5645 static void gen_tlbli_74xx(DisasContext *ctx)
5646 {
5647 #if defined(CONFIG_USER_ONLY)
5648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5649 #else
5650 if (unlikely(ctx->pr)) {
5651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5652 return;
5653 }
5654 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5655 #endif
5656 }
5657
5658 /* POWER instructions not in PowerPC 601 */
5659
5660 /* clf */
5661 static void gen_clf(DisasContext *ctx)
5662 {
5663 /* Cache line flush: implemented as no-op */
5664 }
5665
5666 /* cli */
5667 static void gen_cli(DisasContext *ctx)
5668 {
5669 /* Cache line invalidate: privileged and treated as no-op */
5670 #if defined(CONFIG_USER_ONLY)
5671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5672 #else
5673 if (unlikely(ctx->pr)) {
5674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5675 return;
5676 }
5677 #endif
5678 }
5679
5680 /* dclst */
5681 static void gen_dclst(DisasContext *ctx)
5682 {
5683 /* Data cache line store: treated as no-op */
5684 }
5685
5686 static void gen_mfsri(DisasContext *ctx)
5687 {
5688 #if defined(CONFIG_USER_ONLY)
5689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5690 #else
5691 int ra = rA(ctx->opcode);
5692 int rd = rD(ctx->opcode);
5693 TCGv t0;
5694 if (unlikely(ctx->pr)) {
5695 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5696 return;
5697 }
5698 t0 = tcg_temp_new();
5699 gen_addr_reg_index(ctx, t0);
5700 tcg_gen_shri_tl(t0, t0, 28);
5701 tcg_gen_andi_tl(t0, t0, 0xF);
5702 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5703 tcg_temp_free(t0);
5704 if (ra != 0 && ra != rd)
5705 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5706 #endif
5707 }
5708
5709 static void gen_rac(DisasContext *ctx)
5710 {
5711 #if defined(CONFIG_USER_ONLY)
5712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5713 #else
5714 TCGv t0;
5715 if (unlikely(ctx->pr)) {
5716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5717 return;
5718 }
5719 t0 = tcg_temp_new();
5720 gen_addr_reg_index(ctx, t0);
5721 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5722 tcg_temp_free(t0);
5723 #endif
5724 }
5725
5726 static void gen_rfsvc(DisasContext *ctx)
5727 {
5728 #if defined(CONFIG_USER_ONLY)
5729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5730 #else
5731 if (unlikely(ctx->pr)) {
5732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5733 return;
5734 }
5735 gen_helper_rfsvc(cpu_env);
5736 gen_sync_exception(ctx);
5737 #endif
5738 }
5739
5740 /* svc is not implemented for now */
5741
5742 /* POWER2 specific instructions */
5743 /* Quad manipulation (load/store two floats at a time) */
5744
5745 /* lfq */
5746 static void gen_lfq(DisasContext *ctx)
5747 {
5748 int rd = rD(ctx->opcode);
5749 TCGv t0;
5750 gen_set_access_type(ctx, ACCESS_FLOAT);
5751 t0 = tcg_temp_new();
5752 gen_addr_imm_index(ctx, t0, 0);
5753 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5754 gen_addr_add(ctx, t0, t0, 8);
5755 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5756 tcg_temp_free(t0);
5757 }
5758
5759 /* lfqu */
5760 static void gen_lfqu(DisasContext *ctx)
5761 {
5762 int ra = rA(ctx->opcode);
5763 int rd = rD(ctx->opcode);
5764 TCGv t0, t1;
5765 gen_set_access_type(ctx, ACCESS_FLOAT);
5766 t0 = tcg_temp_new();
5767 t1 = tcg_temp_new();
5768 gen_addr_imm_index(ctx, t0, 0);
5769 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5770 gen_addr_add(ctx, t1, t0, 8);
5771 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5772 if (ra != 0)
5773 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5774 tcg_temp_free(t0);
5775 tcg_temp_free(t1);
5776 }
5777
5778 /* lfqux */
5779 static void gen_lfqux(DisasContext *ctx)
5780 {
5781 int ra = rA(ctx->opcode);
5782 int rd = rD(ctx->opcode);
5783 gen_set_access_type(ctx, ACCESS_FLOAT);
5784 TCGv t0, t1;
5785 t0 = tcg_temp_new();
5786 gen_addr_reg_index(ctx, t0);
5787 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5788 t1 = tcg_temp_new();
5789 gen_addr_add(ctx, t1, t0, 8);
5790 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5791 tcg_temp_free(t1);
5792 if (ra != 0)
5793 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5794 tcg_temp_free(t0);
5795 }
5796
5797 /* lfqx */
5798 static void gen_lfqx(DisasContext *ctx)
5799 {
5800 int rd = rD(ctx->opcode);
5801 TCGv t0;
5802 gen_set_access_type(ctx, ACCESS_FLOAT);
5803 t0 = tcg_temp_new();
5804 gen_addr_reg_index(ctx, t0);
5805 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5806 gen_addr_add(ctx, t0, t0, 8);
5807 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5808 tcg_temp_free(t0);
5809 }
5810
5811 /* stfq */
5812 static void gen_stfq(DisasContext *ctx)
5813 {
5814 int rd = rD(ctx->opcode);
5815 TCGv t0;
5816 gen_set_access_type(ctx, ACCESS_FLOAT);
5817 t0 = tcg_temp_new();
5818 gen_addr_imm_index(ctx, t0, 0);
5819 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5820 gen_addr_add(ctx, t0, t0, 8);
5821 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5822 tcg_temp_free(t0);
5823 }
5824
5825 /* stfqu */
5826 static void gen_stfqu(DisasContext *ctx)
5827 {
5828 int ra = rA(ctx->opcode);
5829 int rd = rD(ctx->opcode);
5830 TCGv t0, t1;
5831 gen_set_access_type(ctx, ACCESS_FLOAT);
5832 t0 = tcg_temp_new();
5833 gen_addr_imm_index(ctx, t0, 0);
5834 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5835 t1 = tcg_temp_new();
5836 gen_addr_add(ctx, t1, t0, 8);
5837 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5838 tcg_temp_free(t1);
5839 if (ra != 0)
5840 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5841 tcg_temp_free(t0);
5842 }
5843
5844 /* stfqux */
5845 static void gen_stfqux(DisasContext *ctx)
5846 {
5847 int ra = rA(ctx->opcode);
5848 int rd = rD(ctx->opcode);
5849 TCGv t0, t1;
5850 gen_set_access_type(ctx, ACCESS_FLOAT);
5851 t0 = tcg_temp_new();
5852 gen_addr_reg_index(ctx, t0);
5853 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5854 t1 = tcg_temp_new();
5855 gen_addr_add(ctx, t1, t0, 8);
5856 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5857 tcg_temp_free(t1);
5858 if (ra != 0)
5859 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5860 tcg_temp_free(t0);
5861 }
5862
5863 /* stfqx */
5864 static void gen_stfqx(DisasContext *ctx)
5865 {
5866 int rd = rD(ctx->opcode);
5867 TCGv t0;
5868 gen_set_access_type(ctx, ACCESS_FLOAT);
5869 t0 = tcg_temp_new();
5870 gen_addr_reg_index(ctx, t0);
5871 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5872 gen_addr_add(ctx, t0, t0, 8);
5873 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5874 tcg_temp_free(t0);
5875 }
5876
5877 /* BookE specific instructions */
5878
5879 /* XXX: not implemented on 440 ? */
5880 static void gen_mfapidi(DisasContext *ctx)
5881 {
5882 /* XXX: TODO */
5883 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5884 }
5885
5886 /* XXX: not implemented on 440 ? */
5887 static void gen_tlbiva(DisasContext *ctx)
5888 {
5889 #if defined(CONFIG_USER_ONLY)
5890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5891 #else
5892 TCGv t0;
5893 if (unlikely(ctx->pr)) {
5894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5895 return;
5896 }
5897 t0 = tcg_temp_new();
5898 gen_addr_reg_index(ctx, t0);
5899 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5900 tcg_temp_free(t0);
5901 #endif
5902 }
5903
5904 /* All 405 MAC instructions are translated here */
5905 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5906 int ra, int rb, int rt, int Rc)
5907 {
5908 TCGv t0, t1;
5909
5910 t0 = tcg_temp_local_new();
5911 t1 = tcg_temp_local_new();
5912
5913 switch (opc3 & 0x0D) {
5914 case 0x05:
5915 /* macchw - macchw. - macchwo - macchwo. */
5916 /* macchws - macchws. - macchwso - macchwso. */
5917 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5918 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5919 /* mulchw - mulchw. */
5920 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5921 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5922 tcg_gen_ext16s_tl(t1, t1);
5923 break;
5924 case 0x04:
5925 /* macchwu - macchwu. - macchwuo - macchwuo. */
5926 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5927 /* mulchwu - mulchwu. */
5928 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5929 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5930 tcg_gen_ext16u_tl(t1, t1);
5931 break;
5932 case 0x01:
5933 /* machhw - machhw. - machhwo - machhwo. */
5934 /* machhws - machhws. - machhwso - machhwso. */
5935 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5936 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5937 /* mulhhw - mulhhw. */
5938 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5939 tcg_gen_ext16s_tl(t0, t0);
5940 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5941 tcg_gen_ext16s_tl(t1, t1);
5942 break;
5943 case 0x00:
5944 /* machhwu - machhwu. - machhwuo - machhwuo. */
5945 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5946 /* mulhhwu - mulhhwu. */
5947 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5948 tcg_gen_ext16u_tl(t0, t0);
5949 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5950 tcg_gen_ext16u_tl(t1, t1);
5951 break;
5952 case 0x0D:
5953 /* maclhw - maclhw. - maclhwo - maclhwo. */
5954 /* maclhws - maclhws. - maclhwso - maclhwso. */
5955 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5956 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5957 /* mullhw - mullhw. */
5958 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5959 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5960 break;
5961 case 0x0C:
5962 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5963 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5964 /* mullhwu - mullhwu. */
5965 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5966 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5967 break;
5968 }
5969 if (opc2 & 0x04) {
5970 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5971 tcg_gen_mul_tl(t1, t0, t1);
5972 if (opc2 & 0x02) {
5973 /* nmultiply-and-accumulate (0x0E) */
5974 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5975 } else {
5976 /* multiply-and-accumulate (0x0C) */
5977 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5978 }
5979
5980 if (opc3 & 0x12) {
5981 /* Check overflow and/or saturate */
5982 TCGLabel *l1 = gen_new_label();
5983
5984 if (opc3 & 0x10) {
5985 /* Start with XER OV disabled, the most likely case */
5986 tcg_gen_movi_tl(cpu_ov, 0);
5987 }
5988 if (opc3 & 0x01) {
5989 /* Signed */
5990 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5991 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5992 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5993 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5994 if (opc3 & 0x02) {
5995 /* Saturate */
5996 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5997 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5998 }
5999 } else {
6000 /* Unsigned */
6001 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6002 if (opc3 & 0x02) {
6003 /* Saturate */
6004 tcg_gen_movi_tl(t0, UINT32_MAX);
6005 }
6006 }
6007 if (opc3 & 0x10) {
6008 /* Check overflow */
6009 tcg_gen_movi_tl(cpu_ov, 1);
6010 tcg_gen_movi_tl(cpu_so, 1);
6011 }
6012 gen_set_label(l1);
6013 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6014 }
6015 } else {
6016 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6017 }
6018 tcg_temp_free(t0);
6019 tcg_temp_free(t1);
6020 if (unlikely(Rc) != 0) {
6021 /* Update Rc0 */
6022 gen_set_Rc0(ctx, cpu_gpr[rt]);
6023 }
6024 }
6025
6026 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6027 static void glue(gen_, name)(DisasContext *ctx) \
6028 { \
6029 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6030 rD(ctx->opcode), Rc(ctx->opcode)); \
6031 }
6032
6033 /* macchw - macchw. */
6034 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6035 /* macchwo - macchwo. */
6036 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6037 /* macchws - macchws. */
6038 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6039 /* macchwso - macchwso. */
6040 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6041 /* macchwsu - macchwsu. */
6042 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6043 /* macchwsuo - macchwsuo. */
6044 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6045 /* macchwu - macchwu. */
6046 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6047 /* macchwuo - macchwuo. */
6048 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6049 /* machhw - machhw. */
6050 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6051 /* machhwo - machhwo. */
6052 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6053 /* machhws - machhws. */
6054 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6055 /* machhwso - machhwso. */
6056 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6057 /* machhwsu - machhwsu. */
6058 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6059 /* machhwsuo - machhwsuo. */
6060 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6061 /* machhwu - machhwu. */
6062 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6063 /* machhwuo - machhwuo. */
6064 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6065 /* maclhw - maclhw. */
6066 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6067 /* maclhwo - maclhwo. */
6068 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6069 /* maclhws - maclhws. */
6070 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6071 /* maclhwso - maclhwso. */
6072 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6073 /* maclhwu - maclhwu. */
6074 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6075 /* maclhwuo - maclhwuo. */
6076 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6077 /* maclhwsu - maclhwsu. */
6078 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6079 /* maclhwsuo - maclhwsuo. */
6080 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6081 /* nmacchw - nmacchw. */
6082 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6083 /* nmacchwo - nmacchwo. */
6084 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6085 /* nmacchws - nmacchws. */
6086 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6087 /* nmacchwso - nmacchwso. */
6088 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6089 /* nmachhw - nmachhw. */
6090 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6091 /* nmachhwo - nmachhwo. */
6092 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6093 /* nmachhws - nmachhws. */
6094 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6095 /* nmachhwso - nmachhwso. */
6096 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6097 /* nmaclhw - nmaclhw. */
6098 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6099 /* nmaclhwo - nmaclhwo. */
6100 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6101 /* nmaclhws - nmaclhws. */
6102 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6103 /* nmaclhwso - nmaclhwso. */
6104 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6105
6106 /* mulchw - mulchw. */
6107 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6108 /* mulchwu - mulchwu. */
6109 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6110 /* mulhhw - mulhhw. */
6111 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6112 /* mulhhwu - mulhhwu. */
6113 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6114 /* mullhw - mullhw. */
6115 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6116 /* mullhwu - mullhwu. */
6117 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6118
6119 /* mfdcr */
6120 static void gen_mfdcr(DisasContext *ctx)
6121 {
6122 #if defined(CONFIG_USER_ONLY)
6123 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6124 #else
6125 TCGv dcrn;
6126 if (unlikely(ctx->pr)) {
6127 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6128 return;
6129 }
6130 /* NIP cannot be restored if the memory exception comes from an helper */
6131 gen_update_nip(ctx, ctx->nip - 4);
6132 dcrn = tcg_const_tl(SPR(ctx->opcode));
6133 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6134 tcg_temp_free(dcrn);
6135 #endif
6136 }
6137
6138 /* mtdcr */
6139 static void gen_mtdcr(DisasContext *ctx)
6140 {
6141 #if defined(CONFIG_USER_ONLY)
6142 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6143 #else
6144 TCGv dcrn;
6145 if (unlikely(ctx->pr)) {
6146 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6147 return;
6148 }
6149 /* NIP cannot be restored if the memory exception comes from an helper */
6150 gen_update_nip(ctx, ctx->nip - 4);
6151 dcrn = tcg_const_tl(SPR(ctx->opcode));
6152 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6153 tcg_temp_free(dcrn);
6154 #endif
6155 }
6156
6157 /* mfdcrx */
6158 /* XXX: not implemented on 440 ? */
6159 static void gen_mfdcrx(DisasContext *ctx)
6160 {
6161 #if defined(CONFIG_USER_ONLY)
6162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6163 #else
6164 if (unlikely(ctx->pr)) {
6165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6166 return;
6167 }
6168 /* NIP cannot be restored if the memory exception comes from an helper */
6169 gen_update_nip(ctx, ctx->nip - 4);
6170 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6171 cpu_gpr[rA(ctx->opcode)]);
6172 /* Note: Rc update flag set leads to undefined state of Rc0 */
6173 #endif
6174 }
6175
6176 /* mtdcrx */
6177 /* XXX: not implemented on 440 ? */
6178 static void gen_mtdcrx(DisasContext *ctx)
6179 {
6180 #if defined(CONFIG_USER_ONLY)
6181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6182 #else
6183 if (unlikely(ctx->pr)) {
6184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6185 return;
6186 }
6187 /* NIP cannot be restored if the memory exception comes from an helper */
6188 gen_update_nip(ctx, ctx->nip - 4);
6189 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6190 cpu_gpr[rS(ctx->opcode)]);
6191 /* Note: Rc update flag set leads to undefined state of Rc0 */
6192 #endif
6193 }
6194
6195 /* mfdcrux (PPC 460) : user-mode access to DCR */
6196 static void gen_mfdcrux(DisasContext *ctx)
6197 {
6198 /* NIP cannot be restored if the memory exception comes from an helper */
6199 gen_update_nip(ctx, ctx->nip - 4);
6200 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6201 cpu_gpr[rA(ctx->opcode)]);
6202 /* Note: Rc update flag set leads to undefined state of Rc0 */
6203 }
6204
6205 /* mtdcrux (PPC 460) : user-mode access to DCR */
6206 static void gen_mtdcrux(DisasContext *ctx)
6207 {
6208 /* NIP cannot be restored if the memory exception comes from an helper */
6209 gen_update_nip(ctx, ctx->nip - 4);
6210 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6211 cpu_gpr[rS(ctx->opcode)]);
6212 /* Note: Rc update flag set leads to undefined state of Rc0 */
6213 }
6214
6215 /* dccci */
6216 static void gen_dccci(DisasContext *ctx)
6217 {
6218 #if defined(CONFIG_USER_ONLY)
6219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6220 #else
6221 if (unlikely(ctx->pr)) {
6222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6223 return;
6224 }
6225 /* interpreted as no-op */
6226 #endif
6227 }
6228
6229 /* dcread */
6230 static void gen_dcread(DisasContext *ctx)
6231 {
6232 #if defined(CONFIG_USER_ONLY)
6233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6234 #else
6235 TCGv EA, val;
6236 if (unlikely(ctx->pr)) {
6237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6238 return;
6239 }
6240 gen_set_access_type(ctx, ACCESS_CACHE);
6241 EA = tcg_temp_new();
6242 gen_addr_reg_index(ctx, EA);
6243 val = tcg_temp_new();
6244 gen_qemu_ld32u(ctx, val, EA);
6245 tcg_temp_free(val);
6246 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6247 tcg_temp_free(EA);
6248 #endif
6249 }
6250
6251 /* icbt */
6252 static void gen_icbt_40x(DisasContext *ctx)
6253 {
6254 /* interpreted as no-op */
6255 /* XXX: specification say this is treated as a load by the MMU
6256 * but does not generate any exception
6257 */
6258 }
6259
6260 /* iccci */
6261 static void gen_iccci(DisasContext *ctx)
6262 {
6263 #if defined(CONFIG_USER_ONLY)
6264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6265 #else
6266 if (unlikely(ctx->pr)) {
6267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6268 return;
6269 }
6270 /* interpreted as no-op */
6271 #endif
6272 }
6273
6274 /* icread */
6275 static void gen_icread(DisasContext *ctx)
6276 {
6277 #if defined(CONFIG_USER_ONLY)
6278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6279 #else
6280 if (unlikely(ctx->pr)) {
6281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6282 return;
6283 }
6284 /* interpreted as no-op */
6285 #endif
6286 }
6287
6288 /* rfci (supervisor only) */
6289 static void gen_rfci_40x(DisasContext *ctx)
6290 {
6291 #if defined(CONFIG_USER_ONLY)
6292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6293 #else
6294 if (unlikely(ctx->pr)) {
6295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6296 return;
6297 }
6298 /* Restore CPU state */
6299 gen_helper_40x_rfci(cpu_env);
6300 gen_sync_exception(ctx);
6301 #endif
6302 }
6303
6304 static void gen_rfci(DisasContext *ctx)
6305 {
6306 #if defined(CONFIG_USER_ONLY)
6307 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6308 #else
6309 if (unlikely(ctx->pr)) {
6310 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6311 return;
6312 }
6313 /* Restore CPU state */
6314 gen_helper_rfci(cpu_env);
6315 gen_sync_exception(ctx);
6316 #endif
6317 }
6318
6319 /* BookE specific */
6320
6321 /* XXX: not implemented on 440 ? */
6322 static void gen_rfdi(DisasContext *ctx)
6323 {
6324 #if defined(CONFIG_USER_ONLY)
6325 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6326 #else
6327 if (unlikely(ctx->pr)) {
6328 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6329 return;
6330 }
6331 /* Restore CPU state */
6332 gen_helper_rfdi(cpu_env);
6333 gen_sync_exception(ctx);
6334 #endif
6335 }
6336
6337 /* XXX: not implemented on 440 ? */
6338 static void gen_rfmci(DisasContext *ctx)
6339 {
6340 #if defined(CONFIG_USER_ONLY)
6341 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6342 #else
6343 if (unlikely(ctx->pr)) {
6344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6345 return;
6346 }
6347 /* Restore CPU state */
6348 gen_helper_rfmci(cpu_env);
6349 gen_sync_exception(ctx);
6350 #endif
6351 }
6352
6353 /* TLB management - PowerPC 405 implementation */
6354
6355 /* tlbre */
6356 static void gen_tlbre_40x(DisasContext *ctx)
6357 {
6358 #if defined(CONFIG_USER_ONLY)
6359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6360 #else
6361 if (unlikely(ctx->pr)) {
6362 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6363 return;
6364 }
6365 switch (rB(ctx->opcode)) {
6366 case 0:
6367 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6368 cpu_gpr[rA(ctx->opcode)]);
6369 break;
6370 case 1:
6371 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6372 cpu_gpr[rA(ctx->opcode)]);
6373 break;
6374 default:
6375 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6376 break;
6377 }
6378 #endif
6379 }
6380
6381 /* tlbsx - tlbsx. */
6382 static void gen_tlbsx_40x(DisasContext *ctx)
6383 {
6384 #if defined(CONFIG_USER_ONLY)
6385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6386 #else
6387 TCGv t0;
6388 if (unlikely(ctx->pr)) {
6389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6390 return;
6391 }
6392 t0 = tcg_temp_new();
6393 gen_addr_reg_index(ctx, t0);
6394 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6395 tcg_temp_free(t0);
6396 if (Rc(ctx->opcode)) {
6397 TCGLabel *l1 = gen_new_label();
6398 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6399 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6400 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6401 gen_set_label(l1);
6402 }
6403 #endif
6404 }
6405
6406 /* tlbwe */
6407 static void gen_tlbwe_40x(DisasContext *ctx)
6408 {
6409 #if defined(CONFIG_USER_ONLY)
6410 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6411 #else
6412 if (unlikely(ctx->pr)) {
6413 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6414 return;
6415 }
6416 switch (rB(ctx->opcode)) {
6417 case 0:
6418 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6419 cpu_gpr[rS(ctx->opcode)]);
6420 break;
6421 case 1:
6422 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6423 cpu_gpr[rS(ctx->opcode)]);
6424 break;
6425 default:
6426 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6427 break;
6428 }
6429 #endif
6430 }
6431
6432 /* TLB management - PowerPC 440 implementation */
6433
6434 /* tlbre */
6435 static void gen_tlbre_440(DisasContext *ctx)
6436 {
6437 #if defined(CONFIG_USER_ONLY)
6438 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6439 #else
6440 if (unlikely(ctx->pr)) {
6441 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6442 return;
6443 }
6444 switch (rB(ctx->opcode)) {
6445 case 0:
6446 case 1:
6447 case 2:
6448 {
6449 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6450 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6451 t0, cpu_gpr[rA(ctx->opcode)]);
6452 tcg_temp_free_i32(t0);
6453 }
6454 break;
6455 default:
6456 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6457 break;
6458 }
6459 #endif
6460 }
6461
6462 /* tlbsx - tlbsx. */
6463 static void gen_tlbsx_440(DisasContext *ctx)
6464 {
6465 #if defined(CONFIG_USER_ONLY)
6466 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6467 #else
6468 TCGv t0;
6469 if (unlikely(ctx->pr)) {
6470 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6471 return;
6472 }
6473 t0 = tcg_temp_new();
6474 gen_addr_reg_index(ctx, t0);
6475 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6476 tcg_temp_free(t0);
6477 if (Rc(ctx->opcode)) {
6478 TCGLabel *l1 = gen_new_label();
6479 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6480 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6481 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6482 gen_set_label(l1);
6483 }
6484 #endif
6485 }
6486
6487 /* tlbwe */
6488 static void gen_tlbwe_440(DisasContext *ctx)
6489 {
6490 #if defined(CONFIG_USER_ONLY)
6491 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6492 #else
6493 if (unlikely(ctx->pr)) {
6494 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6495 return;
6496 }
6497 switch (rB(ctx->opcode)) {
6498 case 0:
6499 case 1:
6500 case 2:
6501 {
6502 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6503 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6504 cpu_gpr[rS(ctx->opcode)]);
6505 tcg_temp_free_i32(t0);
6506 }
6507 break;
6508 default:
6509 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6510 break;
6511 }
6512 #endif
6513 }
6514
6515 /* TLB management - PowerPC BookE 2.06 implementation */
6516
6517 /* tlbre */
6518 static void gen_tlbre_booke206(DisasContext *ctx)
6519 {
6520 #if defined(CONFIG_USER_ONLY)
6521 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6522 #else
6523 if (unlikely(ctx->pr)) {
6524 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6525 return;
6526 }
6527
6528 gen_helper_booke206_tlbre(cpu_env);
6529 #endif
6530 }
6531
6532 /* tlbsx - tlbsx. */
6533 static void gen_tlbsx_booke206(DisasContext *ctx)
6534 {
6535 #if defined(CONFIG_USER_ONLY)
6536 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6537 #else
6538 TCGv t0;
6539 if (unlikely(ctx->pr)) {
6540 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6541 return;
6542 }
6543
6544 if (rA(ctx->opcode)) {
6545 t0 = tcg_temp_new();
6546 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6547 } else {
6548 t0 = tcg_const_tl(0);
6549 }
6550
6551 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6552 gen_helper_booke206_tlbsx(cpu_env, t0);
6553 tcg_temp_free(t0);
6554 #endif
6555 }
6556
6557 /* tlbwe */
6558 static void gen_tlbwe_booke206(DisasContext *ctx)
6559 {
6560 #if defined(CONFIG_USER_ONLY)
6561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6562 #else
6563 if (unlikely(ctx->pr)) {
6564 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6565 return;
6566 }
6567 gen_update_nip(ctx, ctx->nip - 4);
6568 gen_helper_booke206_tlbwe(cpu_env);
6569 #endif
6570 }
6571
6572 static void gen_tlbivax_booke206(DisasContext *ctx)
6573 {
6574 #if defined(CONFIG_USER_ONLY)
6575 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6576 #else
6577 TCGv t0;
6578 if (unlikely(ctx->pr)) {
6579 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6580 return;
6581 }
6582
6583 t0 = tcg_temp_new();
6584 gen_addr_reg_index(ctx, t0);
6585
6586 gen_helper_booke206_tlbivax(cpu_env, t0);
6587 tcg_temp_free(t0);
6588 #endif
6589 }
6590
6591 static void gen_tlbilx_booke206(DisasContext *ctx)
6592 {
6593 #if defined(CONFIG_USER_ONLY)
6594 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6595 #else
6596 TCGv t0;
6597 if (unlikely(ctx->pr)) {
6598 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6599 return;
6600 }
6601
6602 t0 = tcg_temp_new();
6603 gen_addr_reg_index(ctx, t0);
6604
6605 switch((ctx->opcode >> 21) & 0x3) {
6606 case 0:
6607 gen_helper_booke206_tlbilx0(cpu_env, t0);
6608 break;
6609 case 1:
6610 gen_helper_booke206_tlbilx1(cpu_env, t0);
6611 break;
6612 case 3:
6613 gen_helper_booke206_tlbilx3(cpu_env, t0);
6614 break;
6615 default:
6616 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6617 break;
6618 }
6619
6620 tcg_temp_free(t0);
6621 #endif
6622 }
6623
6624
6625 /* wrtee */
6626 static void gen_wrtee(DisasContext *ctx)
6627 {
6628 #if defined(CONFIG_USER_ONLY)
6629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6630 #else
6631 TCGv t0;
6632 if (unlikely(ctx->pr)) {
6633 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6634 return;
6635 }
6636 t0 = tcg_temp_new();
6637 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6638 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6639 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6640 tcg_temp_free(t0);
6641 /* Stop translation to have a chance to raise an exception
6642 * if we just set msr_ee to 1
6643 */
6644 gen_stop_exception(ctx);
6645 #endif
6646 }
6647
6648 /* wrteei */
6649 static void gen_wrteei(DisasContext *ctx)
6650 {
6651 #if defined(CONFIG_USER_ONLY)
6652 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6653 #else
6654 if (unlikely(ctx->pr)) {
6655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6656 return;
6657 }
6658 if (ctx->opcode & 0x00008000) {
6659 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6660 /* Stop translation to have a chance to raise an exception */
6661 gen_stop_exception(ctx);
6662 } else {
6663 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6664 }
6665 #endif
6666 }
6667
6668 /* PowerPC 440 specific instructions */
6669
6670 /* dlmzb */
6671 static void gen_dlmzb(DisasContext *ctx)
6672 {
6673 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6674 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6675 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6676 tcg_temp_free_i32(t0);
6677 }
6678
6679 /* mbar replaces eieio on 440 */
6680 static void gen_mbar(DisasContext *ctx)
6681 {
6682 /* interpreted as no-op */
6683 }
6684
6685 /* msync replaces sync on 440 */
6686 static void gen_msync_4xx(DisasContext *ctx)
6687 {
6688 /* interpreted as no-op */
6689 }
6690
6691 /* icbt */
6692 static void gen_icbt_440(DisasContext *ctx)
6693 {
6694 /* interpreted as no-op */
6695 /* XXX: specification say this is treated as a load by the MMU
6696 * but does not generate any exception
6697 */
6698 }
6699
6700 /* Embedded.Processor Control */
6701
6702 static void gen_msgclr(DisasContext *ctx)
6703 {
6704 #if defined(CONFIG_USER_ONLY)
6705 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6706 #else
6707 if (unlikely(ctx->pr)) {
6708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6709 return;
6710 }
6711
6712 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6713 #endif
6714 }
6715
6716 static void gen_msgsnd(DisasContext *ctx)
6717 {
6718 #if defined(CONFIG_USER_ONLY)
6719 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6720 #else
6721 if (unlikely(ctx->pr)) {
6722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6723 return;
6724 }
6725
6726 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6727 #endif
6728 }
6729
6730 /*** Altivec vector extension ***/
6731 /* Altivec registers moves */
6732
6733 static inline TCGv_ptr gen_avr_ptr(int reg)
6734 {
6735 TCGv_ptr r = tcg_temp_new_ptr();
6736 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6737 return r;
6738 }
6739
6740 #define GEN_VR_LDX(name, opc2, opc3) \
6741 static void glue(gen_, name)(DisasContext *ctx) \
6742 { \
6743 TCGv EA; \
6744 if (unlikely(!ctx->altivec_enabled)) { \
6745 gen_exception(ctx, POWERPC_EXCP_VPU); \
6746 return; \
6747 } \
6748 gen_set_access_type(ctx, ACCESS_INT); \
6749 EA = tcg_temp_new(); \
6750 gen_addr_reg_index(ctx, EA); \
6751 tcg_gen_andi_tl(EA, EA, ~0xf); \
6752 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6753 64-bit byteswap already. */ \
6754 if (ctx->le_mode) { \
6755 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6756 tcg_gen_addi_tl(EA, EA, 8); \
6757 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6758 } else { \
6759 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6760 tcg_gen_addi_tl(EA, EA, 8); \
6761 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6762 } \
6763 tcg_temp_free(EA); \
6764 }
6765
6766 #define GEN_VR_STX(name, opc2, opc3) \
6767 static void gen_st##name(DisasContext *ctx) \
6768 { \
6769 TCGv EA; \
6770 if (unlikely(!ctx->altivec_enabled)) { \
6771 gen_exception(ctx, POWERPC_EXCP_VPU); \
6772 return; \
6773 } \
6774 gen_set_access_type(ctx, ACCESS_INT); \
6775 EA = tcg_temp_new(); \
6776 gen_addr_reg_index(ctx, EA); \
6777 tcg_gen_andi_tl(EA, EA, ~0xf); \
6778 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6779 64-bit byteswap already. */ \
6780 if (ctx->le_mode) { \
6781 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6782 tcg_gen_addi_tl(EA, EA, 8); \
6783 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6784 } else { \
6785 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6786 tcg_gen_addi_tl(EA, EA, 8); \
6787 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6788 } \
6789 tcg_temp_free(EA); \
6790 }
6791
6792 #define GEN_VR_LVE(name, opc2, opc3, size) \
6793 static void gen_lve##name(DisasContext *ctx) \
6794 { \
6795 TCGv EA; \
6796 TCGv_ptr rs; \
6797 if (unlikely(!ctx->altivec_enabled)) { \
6798 gen_exception(ctx, POWERPC_EXCP_VPU); \
6799 return; \
6800 } \
6801 gen_set_access_type(ctx, ACCESS_INT); \
6802 EA = tcg_temp_new(); \
6803 gen_addr_reg_index(ctx, EA); \
6804 if (size > 1) { \
6805 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6806 } \
6807 rs = gen_avr_ptr(rS(ctx->opcode)); \
6808 gen_helper_lve##name(cpu_env, rs, EA); \
6809 tcg_temp_free(EA); \
6810 tcg_temp_free_ptr(rs); \
6811 }
6812
6813 #define GEN_VR_STVE(name, opc2, opc3, size) \
6814 static void gen_stve##name(DisasContext *ctx) \
6815 { \
6816 TCGv EA; \
6817 TCGv_ptr rs; \
6818 if (unlikely(!ctx->altivec_enabled)) { \
6819 gen_exception(ctx, POWERPC_EXCP_VPU); \
6820 return; \
6821 } \
6822 gen_set_access_type(ctx, ACCESS_INT); \
6823 EA = tcg_temp_new(); \
6824 gen_addr_reg_index(ctx, EA); \
6825 if (size > 1) { \
6826 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6827 } \
6828 rs = gen_avr_ptr(rS(ctx->opcode)); \
6829 gen_helper_stve##name(cpu_env, rs, EA); \
6830 tcg_temp_free(EA); \
6831 tcg_temp_free_ptr(rs); \
6832 }
6833
6834 GEN_VR_LDX(lvx, 0x07, 0x03);
6835 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6836 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6837
6838 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6839 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6840 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6841
6842 GEN_VR_STX(svx, 0x07, 0x07);
6843 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6844 GEN_VR_STX(svxl, 0x07, 0x0F);
6845
6846 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6847 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6848 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6849
6850 static void gen_lvsl(DisasContext *ctx)
6851 {
6852 TCGv_ptr rd;
6853 TCGv EA;
6854 if (unlikely(!ctx->altivec_enabled)) {
6855 gen_exception(ctx, POWERPC_EXCP_VPU);
6856 return;
6857 }
6858 EA = tcg_temp_new();
6859 gen_addr_reg_index(ctx, EA);
6860 rd = gen_avr_ptr(rD(ctx->opcode));
6861 gen_helper_lvsl(rd, EA);
6862 tcg_temp_free(EA);
6863 tcg_temp_free_ptr(rd);
6864 }
6865
6866 static void gen_lvsr(DisasContext *ctx)
6867 {
6868 TCGv_ptr rd;
6869 TCGv EA;
6870 if (unlikely(!ctx->altivec_enabled)) {
6871 gen_exception(ctx, POWERPC_EXCP_VPU);
6872 return;
6873 }
6874 EA = tcg_temp_new();
6875 gen_addr_reg_index(ctx, EA);
6876 rd = gen_avr_ptr(rD(ctx->opcode));
6877 gen_helper_lvsr(rd, EA);
6878 tcg_temp_free(EA);
6879 tcg_temp_free_ptr(rd);
6880 }
6881
6882 static void gen_mfvscr(DisasContext *ctx)
6883 {
6884 TCGv_i32 t;
6885 if (unlikely(!ctx->altivec_enabled)) {
6886 gen_exception(ctx, POWERPC_EXCP_VPU);
6887 return;
6888 }
6889 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6890 t = tcg_temp_new_i32();
6891 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6892 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6893 tcg_temp_free_i32(t);
6894 }
6895
6896 static void gen_mtvscr(DisasContext *ctx)
6897 {
6898 TCGv_ptr p;
6899 if (unlikely(!ctx->altivec_enabled)) {
6900 gen_exception(ctx, POWERPC_EXCP_VPU);
6901 return;
6902 }
6903 p = gen_avr_ptr(rB(ctx->opcode));
6904 gen_helper_mtvscr(cpu_env, p);
6905 tcg_temp_free_ptr(p);
6906 }
6907
6908 /* Logical operations */
6909 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6910 static void glue(gen_, name)(DisasContext *ctx) \
6911 { \
6912 if (unlikely(!ctx->altivec_enabled)) { \
6913 gen_exception(ctx, POWERPC_EXCP_VPU); \
6914 return; \
6915 } \
6916 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6917 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6918 }
6919
6920 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6921 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6922 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6923 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6924 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6925 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6926 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6927 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6928
6929 #define GEN_VXFORM(name, opc2, opc3) \
6930 static void glue(gen_, name)(DisasContext *ctx) \
6931 { \
6932 TCGv_ptr ra, rb, rd; \
6933 if (unlikely(!ctx->altivec_enabled)) { \
6934 gen_exception(ctx, POWERPC_EXCP_VPU); \
6935 return; \
6936 } \
6937 ra = gen_avr_ptr(rA(ctx->opcode)); \
6938 rb = gen_avr_ptr(rB(ctx->opcode)); \
6939 rd = gen_avr_ptr(rD(ctx->opcode)); \
6940 gen_helper_##name (rd, ra, rb); \
6941 tcg_temp_free_ptr(ra); \
6942 tcg_temp_free_ptr(rb); \
6943 tcg_temp_free_ptr(rd); \
6944 }
6945
6946 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6947 static void glue(gen_, name)(DisasContext *ctx) \
6948 { \
6949 TCGv_ptr ra, rb, rd; \
6950 if (unlikely(!ctx->altivec_enabled)) { \
6951 gen_exception(ctx, POWERPC_EXCP_VPU); \
6952 return; \
6953 } \
6954 ra = gen_avr_ptr(rA(ctx->opcode)); \
6955 rb = gen_avr_ptr(rB(ctx->opcode)); \
6956 rd = gen_avr_ptr(rD(ctx->opcode)); \
6957 gen_helper_##name(cpu_env, rd, ra, rb); \
6958 tcg_temp_free_ptr(ra); \
6959 tcg_temp_free_ptr(rb); \
6960 tcg_temp_free_ptr(rd); \
6961 }
6962
6963 #define GEN_VXFORM3(name, opc2, opc3) \
6964 static void glue(gen_, name)(DisasContext *ctx) \
6965 { \
6966 TCGv_ptr ra, rb, rc, rd; \
6967 if (unlikely(!ctx->altivec_enabled)) { \
6968 gen_exception(ctx, POWERPC_EXCP_VPU); \
6969 return; \
6970 } \
6971 ra = gen_avr_ptr(rA(ctx->opcode)); \
6972 rb = gen_avr_ptr(rB(ctx->opcode)); \
6973 rc = gen_avr_ptr(rC(ctx->opcode)); \
6974 rd = gen_avr_ptr(rD(ctx->opcode)); \
6975 gen_helper_##name(rd, ra, rb, rc); \
6976 tcg_temp_free_ptr(ra); \
6977 tcg_temp_free_ptr(rb); \
6978 tcg_temp_free_ptr(rc); \
6979 tcg_temp_free_ptr(rd); \
6980 }
6981
6982 /*
6983 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6984 * an opcode bit. In general, these pairs come from different
6985 * versions of the ISA, so we must also support a pair of flags for
6986 * each instruction.
6987 */
6988 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6989 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6990 { \
6991 if ((Rc(ctx->opcode) == 0) && \
6992 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6993 gen_##name0(ctx); \
6994 } else if ((Rc(ctx->opcode) == 1) && \
6995 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6996 gen_##name1(ctx); \
6997 } else { \
6998 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6999 } \
7000 }
7001
7002 GEN_VXFORM(vaddubm, 0, 0);
7003 GEN_VXFORM(vadduhm, 0, 1);
7004 GEN_VXFORM(vadduwm, 0, 2);
7005 GEN_VXFORM(vaddudm, 0, 3);
7006 GEN_VXFORM(vsububm, 0, 16);
7007 GEN_VXFORM(vsubuhm, 0, 17);
7008 GEN_VXFORM(vsubuwm, 0, 18);
7009 GEN_VXFORM(vsubudm, 0, 19);
7010 GEN_VXFORM(vmaxub, 1, 0);
7011 GEN_VXFORM(vmaxuh, 1, 1);
7012 GEN_VXFORM(vmaxuw, 1, 2);
7013 GEN_VXFORM(vmaxud, 1, 3);
7014 GEN_VXFORM(vmaxsb, 1, 4);
7015 GEN_VXFORM(vmaxsh, 1, 5);
7016 GEN_VXFORM(vmaxsw, 1, 6);
7017 GEN_VXFORM(vmaxsd, 1, 7);
7018 GEN_VXFORM(vminub, 1, 8);
7019 GEN_VXFORM(vminuh, 1, 9);
7020 GEN_VXFORM(vminuw, 1, 10);
7021 GEN_VXFORM(vminud, 1, 11);
7022 GEN_VXFORM(vminsb, 1, 12);
7023 GEN_VXFORM(vminsh, 1, 13);
7024 GEN_VXFORM(vminsw, 1, 14);
7025 GEN_VXFORM(vminsd, 1, 15);
7026 GEN_VXFORM(vavgub, 1, 16);
7027 GEN_VXFORM(vavguh, 1, 17);
7028 GEN_VXFORM(vavguw, 1, 18);
7029 GEN_VXFORM(vavgsb, 1, 20);
7030 GEN_VXFORM(vavgsh, 1, 21);
7031 GEN_VXFORM(vavgsw, 1, 22);
7032 GEN_VXFORM(vmrghb, 6, 0);
7033 GEN_VXFORM(vmrghh, 6, 1);
7034 GEN_VXFORM(vmrghw, 6, 2);
7035 GEN_VXFORM(vmrglb, 6, 4);
7036 GEN_VXFORM(vmrglh, 6, 5);
7037 GEN_VXFORM(vmrglw, 6, 6);
7038
7039 static void gen_vmrgew(DisasContext *ctx)
7040 {
7041 TCGv_i64 tmp;
7042 int VT, VA, VB;
7043 if (unlikely(!ctx->altivec_enabled)) {
7044 gen_exception(ctx, POWERPC_EXCP_VPU);
7045 return;
7046 }
7047 VT = rD(ctx->opcode);
7048 VA = rA(ctx->opcode);
7049 VB = rB(ctx->opcode);
7050 tmp = tcg_temp_new_i64();
7051 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7052 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7053 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7054 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7055 tcg_temp_free_i64(tmp);
7056 }
7057
7058 static void gen_vmrgow(DisasContext *ctx)
7059 {
7060 int VT, VA, VB;
7061 if (unlikely(!ctx->altivec_enabled)) {
7062 gen_exception(ctx, POWERPC_EXCP_VPU);
7063 return;
7064 }
7065 VT = rD(ctx->opcode);
7066 VA = rA(ctx->opcode);
7067 VB = rB(ctx->opcode);
7068
7069 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7070 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7071 }
7072
7073 GEN_VXFORM(vmuloub, 4, 0);
7074 GEN_VXFORM(vmulouh, 4, 1);
7075 GEN_VXFORM(vmulouw, 4, 2);
7076 GEN_VXFORM(vmuluwm, 4, 2);
7077 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7078 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7079 GEN_VXFORM(vmulosb, 4, 4);
7080 GEN_VXFORM(vmulosh, 4, 5);
7081 GEN_VXFORM(vmulosw, 4, 6);
7082 GEN_VXFORM(vmuleub, 4, 8);
7083 GEN_VXFORM(vmuleuh, 4, 9);
7084 GEN_VXFORM(vmuleuw, 4, 10);
7085 GEN_VXFORM(vmulesb, 4, 12);
7086 GEN_VXFORM(vmulesh, 4, 13);
7087 GEN_VXFORM(vmulesw, 4, 14);
7088 GEN_VXFORM(vslb, 2, 4);
7089 GEN_VXFORM(vslh, 2, 5);
7090 GEN_VXFORM(vslw, 2, 6);
7091 GEN_VXFORM(vsld, 2, 23);
7092 GEN_VXFORM(vsrb, 2, 8);
7093 GEN_VXFORM(vsrh, 2, 9);
7094 GEN_VXFORM(vsrw, 2, 10);
7095 GEN_VXFORM(vsrd, 2, 27);
7096 GEN_VXFORM(vsrab, 2, 12);
7097 GEN_VXFORM(vsrah, 2, 13);
7098 GEN_VXFORM(vsraw, 2, 14);
7099 GEN_VXFORM(vsrad, 2, 15);
7100 GEN_VXFORM(vslo, 6, 16);
7101 GEN_VXFORM(vsro, 6, 17);
7102 GEN_VXFORM(vaddcuw, 0, 6);
7103 GEN_VXFORM(vsubcuw, 0, 22);
7104 GEN_VXFORM_ENV(vaddubs, 0, 8);
7105 GEN_VXFORM_ENV(vadduhs, 0, 9);
7106 GEN_VXFORM_ENV(vadduws, 0, 10);
7107 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7108 GEN_VXFORM_ENV(vaddshs, 0, 13);
7109 GEN_VXFORM_ENV(vaddsws, 0, 14);
7110 GEN_VXFORM_ENV(vsububs, 0, 24);
7111 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7112 GEN_VXFORM_ENV(vsubuws, 0, 26);
7113 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7114 GEN_VXFORM_ENV(vsubshs, 0, 29);
7115 GEN_VXFORM_ENV(vsubsws, 0, 30);
7116 GEN_VXFORM(vadduqm, 0, 4);
7117 GEN_VXFORM(vaddcuq, 0, 5);
7118 GEN_VXFORM3(vaddeuqm, 30, 0);
7119 GEN_VXFORM3(vaddecuq, 30, 0);
7120 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7121 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7122 GEN_VXFORM(vsubuqm, 0, 20);
7123 GEN_VXFORM(vsubcuq, 0, 21);
7124 GEN_VXFORM3(vsubeuqm, 31, 0);
7125 GEN_VXFORM3(vsubecuq, 31, 0);
7126 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7127 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7128 GEN_VXFORM(vrlb, 2, 0);
7129 GEN_VXFORM(vrlh, 2, 1);
7130 GEN_VXFORM(vrlw, 2, 2);
7131 GEN_VXFORM(vrld, 2, 3);
7132 GEN_VXFORM(vsl, 2, 7);
7133 GEN_VXFORM(vsr, 2, 11);
7134 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7135 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7136 GEN_VXFORM_ENV(vpkudum, 7, 17);
7137 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7138 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7139 GEN_VXFORM_ENV(vpkudus, 7, 19);
7140 GEN_VXFORM_ENV(vpkshus, 7, 4);
7141 GEN_VXFORM_ENV(vpkswus, 7, 5);
7142 GEN_VXFORM_ENV(vpksdus, 7, 21);
7143 GEN_VXFORM_ENV(vpkshss, 7, 6);
7144 GEN_VXFORM_ENV(vpkswss, 7, 7);
7145 GEN_VXFORM_ENV(vpksdss, 7, 23);
7146 GEN_VXFORM(vpkpx, 7, 12);
7147 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7148 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7149 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7150 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7151 GEN_VXFORM_ENV(vsumsws, 4, 30);
7152 GEN_VXFORM_ENV(vaddfp, 5, 0);
7153 GEN_VXFORM_ENV(vsubfp, 5, 1);
7154 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7155 GEN_VXFORM_ENV(vminfp, 5, 17);
7156
7157 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7158 static void glue(gen_, name)(DisasContext *ctx) \
7159 { \
7160 TCGv_ptr ra, rb, rd; \
7161 if (unlikely(!ctx->altivec_enabled)) { \
7162 gen_exception(ctx, POWERPC_EXCP_VPU); \
7163 return; \
7164 } \
7165 ra = gen_avr_ptr(rA(ctx->opcode)); \
7166 rb = gen_avr_ptr(rB(ctx->opcode)); \
7167 rd = gen_avr_ptr(rD(ctx->opcode)); \
7168 gen_helper_##opname(cpu_env, rd, ra, rb); \
7169 tcg_temp_free_ptr(ra); \
7170 tcg_temp_free_ptr(rb); \
7171 tcg_temp_free_ptr(rd); \
7172 }
7173
7174 #define GEN_VXRFORM(name, opc2, opc3) \
7175 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7176 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7177
7178 /*
7179 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7180 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7181 * come from different versions of the ISA, so we must also support a
7182 * pair of flags for each instruction.
7183 */
7184 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7185 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7186 { \
7187 if ((Rc(ctx->opcode) == 0) && \
7188 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7189 if (Rc21(ctx->opcode) == 0) { \
7190 gen_##name0(ctx); \
7191 } else { \
7192 gen_##name0##_(ctx); \
7193 } \
7194 } else if ((Rc(ctx->opcode) == 1) && \
7195 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7196 if (Rc21(ctx->opcode) == 0) { \
7197 gen_##name1(ctx); \
7198 } else { \
7199 gen_##name1##_(ctx); \
7200 } \
7201 } else { \
7202 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7203 } \
7204 }
7205
7206 GEN_VXRFORM(vcmpequb, 3, 0)
7207 GEN_VXRFORM(vcmpequh, 3, 1)
7208 GEN_VXRFORM(vcmpequw, 3, 2)
7209 GEN_VXRFORM(vcmpequd, 3, 3)
7210 GEN_VXRFORM(vcmpgtsb, 3, 12)
7211 GEN_VXRFORM(vcmpgtsh, 3, 13)
7212 GEN_VXRFORM(vcmpgtsw, 3, 14)
7213 GEN_VXRFORM(vcmpgtsd, 3, 15)
7214 GEN_VXRFORM(vcmpgtub, 3, 8)
7215 GEN_VXRFORM(vcmpgtuh, 3, 9)
7216 GEN_VXRFORM(vcmpgtuw, 3, 10)
7217 GEN_VXRFORM(vcmpgtud, 3, 11)
7218 GEN_VXRFORM(vcmpeqfp, 3, 3)
7219 GEN_VXRFORM(vcmpgefp, 3, 7)
7220 GEN_VXRFORM(vcmpgtfp, 3, 11)
7221 GEN_VXRFORM(vcmpbfp, 3, 15)
7222
7223 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7224 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7225 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7226 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7227 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7228 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7229
7230 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7231 static void glue(gen_, name)(DisasContext *ctx) \
7232 { \
7233 TCGv_ptr rd; \
7234 TCGv_i32 simm; \
7235 if (unlikely(!ctx->altivec_enabled)) { \
7236 gen_exception(ctx, POWERPC_EXCP_VPU); \
7237 return; \
7238 } \
7239 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7240 rd = gen_avr_ptr(rD(ctx->opcode)); \
7241 gen_helper_##name (rd, simm); \
7242 tcg_temp_free_i32(simm); \
7243 tcg_temp_free_ptr(rd); \
7244 }
7245
7246 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7247 GEN_VXFORM_SIMM(vspltish, 6, 13);
7248 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7249
7250 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7251 static void glue(gen_, name)(DisasContext *ctx) \
7252 { \
7253 TCGv_ptr rb, rd; \
7254 if (unlikely(!ctx->altivec_enabled)) { \
7255 gen_exception(ctx, POWERPC_EXCP_VPU); \
7256 return; \
7257 } \
7258 rb = gen_avr_ptr(rB(ctx->opcode)); \
7259 rd = gen_avr_ptr(rD(ctx->opcode)); \
7260 gen_helper_##name (rd, rb); \
7261 tcg_temp_free_ptr(rb); \
7262 tcg_temp_free_ptr(rd); \
7263 }
7264
7265 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7266 static void glue(gen_, name)(DisasContext *ctx) \
7267 { \
7268 TCGv_ptr rb, rd; \
7269 \
7270 if (unlikely(!ctx->altivec_enabled)) { \
7271 gen_exception(ctx, POWERPC_EXCP_VPU); \
7272 return; \
7273 } \
7274 rb = gen_avr_ptr(rB(ctx->opcode)); \
7275 rd = gen_avr_ptr(rD(ctx->opcode)); \
7276 gen_helper_##name(cpu_env, rd, rb); \
7277 tcg_temp_free_ptr(rb); \
7278 tcg_temp_free_ptr(rd); \
7279 }
7280
7281 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7282 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7283 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7284 GEN_VXFORM_NOA(vupklsb, 7, 10);
7285 GEN_VXFORM_NOA(vupklsh, 7, 11);
7286 GEN_VXFORM_NOA(vupklsw, 7, 27);
7287 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7288 GEN_VXFORM_NOA(vupklpx, 7, 15);
7289 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7290 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7291 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7292 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7293 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7294 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7295 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7296 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7297
7298 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7299 static void glue(gen_, name)(DisasContext *ctx) \
7300 { \
7301 TCGv_ptr rd; \
7302 TCGv_i32 simm; \
7303 if (unlikely(!ctx->altivec_enabled)) { \
7304 gen_exception(ctx, POWERPC_EXCP_VPU); \
7305 return; \
7306 } \
7307 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7308 rd = gen_avr_ptr(rD(ctx->opcode)); \
7309 gen_helper_##name (rd, simm); \
7310 tcg_temp_free_i32(simm); \
7311 tcg_temp_free_ptr(rd); \
7312 }
7313
7314 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7315 static void glue(gen_, name)(DisasContext *ctx) \
7316 { \
7317 TCGv_ptr rb, rd; \
7318 TCGv_i32 uimm; \
7319 if (unlikely(!ctx->altivec_enabled)) { \
7320 gen_exception(ctx, POWERPC_EXCP_VPU); \
7321 return; \
7322 } \
7323 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7324 rb = gen_avr_ptr(rB(ctx->opcode)); \
7325 rd = gen_avr_ptr(rD(ctx->opcode)); \
7326 gen_helper_##name (rd, rb, uimm); \
7327 tcg_temp_free_i32(uimm); \
7328 tcg_temp_free_ptr(rb); \
7329 tcg_temp_free_ptr(rd); \
7330 }
7331
7332 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7333 static void glue(gen_, name)(DisasContext *ctx) \
7334 { \
7335 TCGv_ptr rb, rd; \
7336 TCGv_i32 uimm; \
7337 \
7338 if (unlikely(!ctx->altivec_enabled)) { \
7339 gen_exception(ctx, POWERPC_EXCP_VPU); \
7340 return; \
7341 } \
7342 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7343 rb = gen_avr_ptr(rB(ctx->opcode)); \
7344 rd = gen_avr_ptr(rD(ctx->opcode)); \
7345 gen_helper_##name(cpu_env, rd, rb, uimm); \
7346 tcg_temp_free_i32(uimm); \
7347 tcg_temp_free_ptr(rb); \
7348 tcg_temp_free_ptr(rd); \
7349 }
7350
7351 GEN_VXFORM_UIMM(vspltb, 6, 8);
7352 GEN_VXFORM_UIMM(vsplth, 6, 9);
7353 GEN_VXFORM_UIMM(vspltw, 6, 10);
7354 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7355 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7356 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7357 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7358
7359 static void gen_vsldoi(DisasContext *ctx)
7360 {
7361 TCGv_ptr ra, rb, rd;
7362 TCGv_i32 sh;
7363 if (unlikely(!ctx->altivec_enabled)) {
7364 gen_exception(ctx, POWERPC_EXCP_VPU);
7365 return;
7366 }
7367 ra = gen_avr_ptr(rA(ctx->opcode));
7368 rb = gen_avr_ptr(rB(ctx->opcode));
7369 rd = gen_avr_ptr(rD(ctx->opcode));
7370 sh = tcg_const_i32(VSH(ctx->opcode));
7371 gen_helper_vsldoi (rd, ra, rb, sh);
7372 tcg_temp_free_ptr(ra);
7373 tcg_temp_free_ptr(rb);
7374 tcg_temp_free_ptr(rd);
7375 tcg_temp_free_i32(sh);
7376 }
7377
7378 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7379 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7380 { \
7381 TCGv_ptr ra, rb, rc, rd; \
7382 if (unlikely(!ctx->altivec_enabled)) { \
7383 gen_exception(ctx, POWERPC_EXCP_VPU); \
7384 return; \
7385 } \
7386 ra = gen_avr_ptr(rA(ctx->opcode)); \
7387 rb = gen_avr_ptr(rB(ctx->opcode)); \
7388 rc = gen_avr_ptr(rC(ctx->opcode)); \
7389 rd = gen_avr_ptr(rD(ctx->opcode)); \
7390 if (Rc(ctx->opcode)) { \
7391 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7392 } else { \
7393 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7394 } \
7395 tcg_temp_free_ptr(ra); \
7396 tcg_temp_free_ptr(rb); \
7397 tcg_temp_free_ptr(rc); \
7398 tcg_temp_free_ptr(rd); \
7399 }
7400
7401 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7402
7403 static void gen_vmladduhm(DisasContext *ctx)
7404 {
7405 TCGv_ptr ra, rb, rc, rd;
7406 if (unlikely(!ctx->altivec_enabled)) {
7407 gen_exception(ctx, POWERPC_EXCP_VPU);
7408 return;
7409 }
7410 ra = gen_avr_ptr(rA(ctx->opcode));
7411 rb = gen_avr_ptr(rB(ctx->opcode));
7412 rc = gen_avr_ptr(rC(ctx->opcode));
7413 rd = gen_avr_ptr(rD(ctx->opcode));
7414 gen_helper_vmladduhm(rd, ra, rb, rc);
7415 tcg_temp_free_ptr(ra);
7416 tcg_temp_free_ptr(rb);
7417 tcg_temp_free_ptr(rc);
7418 tcg_temp_free_ptr(rd);
7419 }
7420
7421 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7422 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7423 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7424 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7425 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7426
7427 GEN_VXFORM_NOA(vclzb, 1, 28)
7428 GEN_VXFORM_NOA(vclzh, 1, 29)
7429 GEN_VXFORM_NOA(vclzw, 1, 30)
7430 GEN_VXFORM_NOA(vclzd, 1, 31)
7431 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7432 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7433 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7434 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7435 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7436 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7437 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7438 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7439 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7440 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7441 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7442 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7443 GEN_VXFORM(vbpermq, 6, 21);
7444 GEN_VXFORM_NOA(vgbbd, 6, 20);
7445 GEN_VXFORM(vpmsumb, 4, 16)
7446 GEN_VXFORM(vpmsumh, 4, 17)
7447 GEN_VXFORM(vpmsumw, 4, 18)
7448 GEN_VXFORM(vpmsumd, 4, 19)
7449
7450 #define GEN_BCD(op) \
7451 static void gen_##op(DisasContext *ctx) \
7452 { \
7453 TCGv_ptr ra, rb, rd; \
7454 TCGv_i32 ps; \
7455 \
7456 if (unlikely(!ctx->altivec_enabled)) { \
7457 gen_exception(ctx, POWERPC_EXCP_VPU); \
7458 return; \
7459 } \
7460 \
7461 ra = gen_avr_ptr(rA(ctx->opcode)); \
7462 rb = gen_avr_ptr(rB(ctx->opcode)); \
7463 rd = gen_avr_ptr(rD(ctx->opcode)); \
7464 \
7465 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7466 \
7467 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7468 \
7469 tcg_temp_free_ptr(ra); \
7470 tcg_temp_free_ptr(rb); \
7471 tcg_temp_free_ptr(rd); \
7472 tcg_temp_free_i32(ps); \
7473 }
7474
7475 GEN_BCD(bcdadd)
7476 GEN_BCD(bcdsub)
7477
7478 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7479 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7480 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7481 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7482 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7483 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7484 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7485 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7486
7487 static void gen_vsbox(DisasContext *ctx)
7488 {
7489 TCGv_ptr ra, rd;
7490 if (unlikely(!ctx->altivec_enabled)) {
7491 gen_exception(ctx, POWERPC_EXCP_VPU);
7492 return;
7493 }
7494 ra = gen_avr_ptr(rA(ctx->opcode));
7495 rd = gen_avr_ptr(rD(ctx->opcode));
7496 gen_helper_vsbox(rd, ra);
7497 tcg_temp_free_ptr(ra);
7498 tcg_temp_free_ptr(rd);
7499 }
7500
7501 GEN_VXFORM(vcipher, 4, 20)
7502 GEN_VXFORM(vcipherlast, 4, 20)
7503 GEN_VXFORM(vncipher, 4, 21)
7504 GEN_VXFORM(vncipherlast, 4, 21)
7505
7506 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7507 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7508 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7509 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7510
7511 #define VSHASIGMA(op) \
7512 static void gen_##op(DisasContext *ctx) \
7513 { \
7514 TCGv_ptr ra, rd; \
7515 TCGv_i32 st_six; \
7516 if (unlikely(!ctx->altivec_enabled)) { \
7517 gen_exception(ctx, POWERPC_EXCP_VPU); \
7518 return; \
7519 } \
7520 ra = gen_avr_ptr(rA(ctx->opcode)); \
7521 rd = gen_avr_ptr(rD(ctx->opcode)); \
7522 st_six = tcg_const_i32(rB(ctx->opcode)); \
7523 gen_helper_##op(rd, ra, st_six); \
7524 tcg_temp_free_ptr(ra); \
7525 tcg_temp_free_ptr(rd); \
7526 tcg_temp_free_i32(st_six); \
7527 }
7528
7529 VSHASIGMA(vshasigmaw)
7530 VSHASIGMA(vshasigmad)
7531
7532 GEN_VXFORM3(vpermxor, 22, 0xFF)
7533 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7534 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7535
7536 /*** VSX extension ***/
7537
7538 static inline TCGv_i64 cpu_vsrh(int n)
7539 {
7540 if (n < 32) {
7541 return cpu_fpr[n];
7542 } else {
7543 return cpu_avrh[n-32];
7544 }
7545 }
7546
7547 static inline TCGv_i64 cpu_vsrl(int n)
7548 {
7549 if (n < 32) {
7550 return cpu_vsr[n];
7551 } else {
7552 return cpu_avrl[n-32];
7553 }
7554 }
7555
7556 #define VSX_LOAD_SCALAR(name, operation) \
7557 static void gen_##name(DisasContext *ctx) \
7558 { \
7559 TCGv EA; \
7560 if (unlikely(!ctx->vsx_enabled)) { \
7561 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7562 return; \
7563 } \
7564 gen_set_access_type(ctx, ACCESS_INT); \
7565 EA = tcg_temp_new(); \
7566 gen_addr_reg_index(ctx, EA); \
7567 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7568 /* NOTE: cpu_vsrl is undefined */ \
7569 tcg_temp_free(EA); \
7570 }
7571
7572 VSX_LOAD_SCALAR(lxsdx, ld64)
7573 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7574 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7575 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7576
7577 static void gen_lxvd2x(DisasContext *ctx)
7578 {
7579 TCGv EA;
7580 if (unlikely(!ctx->vsx_enabled)) {
7581 gen_exception(ctx, POWERPC_EXCP_VSXU);
7582 return;
7583 }
7584 gen_set_access_type(ctx, ACCESS_INT);
7585 EA = tcg_temp_new();
7586 gen_addr_reg_index(ctx, EA);
7587 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7588 tcg_gen_addi_tl(EA, EA, 8);
7589 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7590 tcg_temp_free(EA);
7591 }
7592
7593 static void gen_lxvdsx(DisasContext *ctx)
7594 {
7595 TCGv EA;
7596 if (unlikely(!ctx->vsx_enabled)) {
7597 gen_exception(ctx, POWERPC_EXCP_VSXU);
7598 return;
7599 }
7600 gen_set_access_type(ctx, ACCESS_INT);
7601 EA = tcg_temp_new();
7602 gen_addr_reg_index(ctx, EA);
7603 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7604 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7605 tcg_temp_free(EA);
7606 }
7607
7608 static void gen_lxvw4x(DisasContext *ctx)
7609 {
7610 TCGv EA;
7611 TCGv_i64 tmp;
7612 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7613 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7614 if (unlikely(!ctx->vsx_enabled)) {
7615 gen_exception(ctx, POWERPC_EXCP_VSXU);
7616 return;
7617 }
7618 gen_set_access_type(ctx, ACCESS_INT);
7619 EA = tcg_temp_new();
7620 tmp = tcg_temp_new_i64();
7621
7622 gen_addr_reg_index(ctx, EA);
7623 gen_qemu_ld32u_i64(ctx, tmp, EA);
7624 tcg_gen_addi_tl(EA, EA, 4);
7625 gen_qemu_ld32u_i64(ctx, xth, EA);
7626 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7627
7628 tcg_gen_addi_tl(EA, EA, 4);
7629 gen_qemu_ld32u_i64(ctx, tmp, EA);
7630 tcg_gen_addi_tl(EA, EA, 4);
7631 gen_qemu_ld32u_i64(ctx, xtl, EA);
7632 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7633
7634 tcg_temp_free(EA);
7635 tcg_temp_free_i64(tmp);
7636 }
7637
7638 #define VSX_STORE_SCALAR(name, operation) \
7639 static void gen_##name(DisasContext *ctx) \
7640 { \
7641 TCGv EA; \
7642 if (unlikely(!ctx->vsx_enabled)) { \
7643 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7644 return; \
7645 } \
7646 gen_set_access_type(ctx, ACCESS_INT); \
7647 EA = tcg_temp_new(); \
7648 gen_addr_reg_index(ctx, EA); \
7649 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7650 tcg_temp_free(EA); \
7651 }
7652
7653 VSX_STORE_SCALAR(stxsdx, st64)
7654 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7655 VSX_STORE_SCALAR(stxsspx, st32fs)
7656
7657 static void gen_stxvd2x(DisasContext *ctx)
7658 {
7659 TCGv EA;
7660 if (unlikely(!ctx->vsx_enabled)) {
7661 gen_exception(ctx, POWERPC_EXCP_VSXU);
7662 return;
7663 }
7664 gen_set_access_type(ctx, ACCESS_INT);
7665 EA = tcg_temp_new();
7666 gen_addr_reg_index(ctx, EA);
7667 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7668 tcg_gen_addi_tl(EA, EA, 8);
7669 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7670 tcg_temp_free(EA);
7671 }
7672
7673 static void gen_stxvw4x(DisasContext *ctx)
7674 {
7675 TCGv_i64 tmp;
7676 TCGv EA;
7677 if (unlikely(!ctx->vsx_enabled)) {
7678 gen_exception(ctx, POWERPC_EXCP_VSXU);
7679 return;
7680 }
7681 gen_set_access_type(ctx, ACCESS_INT);
7682 EA = tcg_temp_new();
7683 gen_addr_reg_index(ctx, EA);
7684 tmp = tcg_temp_new_i64();
7685
7686 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7687 gen_qemu_st32_i64(ctx, tmp, EA);
7688 tcg_gen_addi_tl(EA, EA, 4);
7689 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7690
7691 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7692 tcg_gen_addi_tl(EA, EA, 4);
7693 gen_qemu_st32_i64(ctx, tmp, EA);
7694 tcg_gen_addi_tl(EA, EA, 4);
7695 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7696
7697 tcg_temp_free(EA);
7698 tcg_temp_free_i64(tmp);
7699 }
7700
7701 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7702 static void gen_##name(DisasContext *ctx) \
7703 { \
7704 if (xS(ctx->opcode) < 32) { \
7705 if (unlikely(!ctx->fpu_enabled)) { \
7706 gen_exception(ctx, POWERPC_EXCP_FPU); \
7707 return; \
7708 } \
7709 } else { \
7710 if (unlikely(!ctx->altivec_enabled)) { \
7711 gen_exception(ctx, POWERPC_EXCP_VPU); \
7712 return; \
7713 } \
7714 } \
7715 TCGv_i64 tmp = tcg_temp_new_i64(); \
7716 tcg_gen_##tcgop1(tmp, source); \
7717 tcg_gen_##tcgop2(target, tmp); \
7718 tcg_temp_free_i64(tmp); \
7719 }
7720
7721
7722 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7723 cpu_vsrh(xS(ctx->opcode)))
7724 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7725 cpu_gpr[rA(ctx->opcode)])
7726 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7727 cpu_gpr[rA(ctx->opcode)])
7728
7729 #if defined(TARGET_PPC64)
7730 #define MV_VSRD(name, target, source) \
7731 static void gen_##name(DisasContext *ctx) \
7732 { \
7733 if (xS(ctx->opcode) < 32) { \
7734 if (unlikely(!ctx->fpu_enabled)) { \
7735 gen_exception(ctx, POWERPC_EXCP_FPU); \
7736 return; \
7737 } \
7738 } else { \
7739 if (unlikely(!ctx->altivec_enabled)) { \
7740 gen_exception(ctx, POWERPC_EXCP_VPU); \
7741 return; \
7742 } \
7743 } \
7744 tcg_gen_mov_i64(target, source); \
7745 }
7746
7747 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7748 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7749
7750 #endif
7751
7752 static void gen_xxpermdi(DisasContext *ctx)
7753 {
7754 if (unlikely(!ctx->vsx_enabled)) {
7755 gen_exception(ctx, POWERPC_EXCP_VSXU);
7756 return;
7757 }
7758
7759 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7760 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7761 TCGv_i64 xh, xl;
7762
7763 xh = tcg_temp_new_i64();
7764 xl = tcg_temp_new_i64();
7765
7766 if ((DM(ctx->opcode) & 2) == 0) {
7767 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7768 } else {
7769 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7770 }
7771 if ((DM(ctx->opcode) & 1) == 0) {
7772 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7773 } else {
7774 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7775 }
7776
7777 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7778 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7779
7780 tcg_temp_free_i64(xh);
7781 tcg_temp_free_i64(xl);
7782 } else {
7783 if ((DM(ctx->opcode) & 2) == 0) {
7784 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7785 } else {
7786 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7787 }
7788 if ((DM(ctx->opcode) & 1) == 0) {
7789 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7790 } else {
7791 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7792 }
7793 }
7794 }
7795
7796 #define OP_ABS 1
7797 #define OP_NABS 2
7798 #define OP_NEG 3
7799 #define OP_CPSGN 4
7800 #define SGN_MASK_DP 0x8000000000000000ull
7801 #define SGN_MASK_SP 0x8000000080000000ull
7802
7803 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7804 static void glue(gen_, name)(DisasContext * ctx) \
7805 { \
7806 TCGv_i64 xb, sgm; \
7807 if (unlikely(!ctx->vsx_enabled)) { \
7808 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7809 return; \
7810 } \
7811 xb = tcg_temp_new_i64(); \
7812 sgm = tcg_temp_new_i64(); \
7813 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7814 tcg_gen_movi_i64(sgm, sgn_mask); \
7815 switch (op) { \
7816 case OP_ABS: { \
7817 tcg_gen_andc_i64(xb, xb, sgm); \
7818 break; \
7819 } \
7820 case OP_NABS: { \
7821 tcg_gen_or_i64(xb, xb, sgm); \
7822 break; \
7823 } \
7824 case OP_NEG: { \
7825 tcg_gen_xor_i64(xb, xb, sgm); \
7826 break; \
7827 } \
7828 case OP_CPSGN: { \
7829 TCGv_i64 xa = tcg_temp_new_i64(); \
7830 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7831 tcg_gen_and_i64(xa, xa, sgm); \
7832 tcg_gen_andc_i64(xb, xb, sgm); \
7833 tcg_gen_or_i64(xb, xb, xa); \
7834 tcg_temp_free_i64(xa); \
7835 break; \
7836 } \
7837 } \
7838 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7839 tcg_temp_free_i64(xb); \
7840 tcg_temp_free_i64(sgm); \
7841 }
7842
7843 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7844 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7845 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7846 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7847
7848 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7849 static void glue(gen_, name)(DisasContext * ctx) \
7850 { \
7851 TCGv_i64 xbh, xbl, sgm; \
7852 if (unlikely(!ctx->vsx_enabled)) { \
7853 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7854 return; \
7855 } \
7856 xbh = tcg_temp_new_i64(); \
7857 xbl = tcg_temp_new_i64(); \
7858 sgm = tcg_temp_new_i64(); \
7859 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7860 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7861 tcg_gen_movi_i64(sgm, sgn_mask); \
7862 switch (op) { \
7863 case OP_ABS: { \
7864 tcg_gen_andc_i64(xbh, xbh, sgm); \
7865 tcg_gen_andc_i64(xbl, xbl, sgm); \
7866 break; \
7867 } \
7868 case OP_NABS: { \
7869 tcg_gen_or_i64(xbh, xbh, sgm); \
7870 tcg_gen_or_i64(xbl, xbl, sgm); \
7871 break; \
7872 } \
7873 case OP_NEG: { \
7874 tcg_gen_xor_i64(xbh, xbh, sgm); \
7875 tcg_gen_xor_i64(xbl, xbl, sgm); \
7876 break; \
7877 } \
7878 case OP_CPSGN: { \
7879 TCGv_i64 xah = tcg_temp_new_i64(); \
7880 TCGv_i64 xal = tcg_temp_new_i64(); \
7881 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7882 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7883 tcg_gen_and_i64(xah, xah, sgm); \
7884 tcg_gen_and_i64(xal, xal, sgm); \
7885 tcg_gen_andc_i64(xbh, xbh, sgm); \
7886 tcg_gen_andc_i64(xbl, xbl, sgm); \
7887 tcg_gen_or_i64(xbh, xbh, xah); \
7888 tcg_gen_or_i64(xbl, xbl, xal); \
7889 tcg_temp_free_i64(xah); \
7890 tcg_temp_free_i64(xal); \
7891 break; \
7892 } \
7893 } \
7894 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7895 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7896 tcg_temp_free_i64(xbh); \
7897 tcg_temp_free_i64(xbl); \
7898 tcg_temp_free_i64(sgm); \
7899 }
7900
7901 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7902 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7903 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7904 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7905 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7906 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7907 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7908 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7909
7910 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7911 static void gen_##name(DisasContext * ctx) \
7912 { \
7913 TCGv_i32 opc; \
7914 if (unlikely(!ctx->vsx_enabled)) { \
7915 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7916 return; \
7917 } \
7918 /* NIP cannot be restored if the memory exception comes from an helper */ \
7919 gen_update_nip(ctx, ctx->nip - 4); \
7920 opc = tcg_const_i32(ctx->opcode); \
7921 gen_helper_##name(cpu_env, opc); \
7922 tcg_temp_free_i32(opc); \
7923 }
7924
7925 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7926 static void gen_##name(DisasContext * ctx) \
7927 { \
7928 if (unlikely(!ctx->vsx_enabled)) { \
7929 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7930 return; \
7931 } \
7932 /* NIP cannot be restored if the exception comes */ \
7933 /* from a helper. */ \
7934 gen_update_nip(ctx, ctx->nip - 4); \
7935 \
7936 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7937 cpu_vsrh(xB(ctx->opcode))); \
7938 }
7939
7940 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7941 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7942 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7943 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7944 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7945 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7946 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7947 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7948 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7949 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7950 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7951 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7952 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7953 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7954 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7955 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7956 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7957 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7958 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7959 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7960 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7961 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7962 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7963 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7964 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7965 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7966 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7967 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7968 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7969 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7970 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7971 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7972 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7973 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7974 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7975 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7976 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7977
7978 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7979 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7980 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7981 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7982 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7983 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7984 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7985 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7986 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7987 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7988 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7989 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7990 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7991 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7992 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7993 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7994 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7995
7996 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7997 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7998 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7999 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8000 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8001 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8002 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8003 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8004 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8005 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8006 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8007 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8008 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8009 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8010 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8011 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8012 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8013 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8014 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8015 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8016 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8017 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8018 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8019 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8020 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8021 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8022 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8023 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8024 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8025 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8026 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8027 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8028 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8029 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8030 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8031 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8032
8033 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8034 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8035 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8036 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8037 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8038 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8039 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8040 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8041 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8042 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8043 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8044 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8045 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8046 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8047 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8048 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8049 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8050 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8051 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8052 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8053 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8054 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8055 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8056 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8057 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8058 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8059 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8060 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8061 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8062 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8063 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8064 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8065 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8066 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8067 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8068 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8069
8070 #define VSX_LOGICAL(name, tcg_op) \
8071 static void glue(gen_, name)(DisasContext * ctx) \
8072 { \
8073 if (unlikely(!ctx->vsx_enabled)) { \
8074 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8075 return; \
8076 } \
8077 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8078 cpu_vsrh(xB(ctx->opcode))); \
8079 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8080 cpu_vsrl(xB(ctx->opcode))); \
8081 }
8082
8083 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8084 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8085 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8086 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8087 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8088 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8089 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8090 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8091
8092 #define VSX_XXMRG(name, high) \
8093 static void glue(gen_, name)(DisasContext * ctx) \
8094 { \
8095 TCGv_i64 a0, a1, b0, b1; \
8096 if (unlikely(!ctx->vsx_enabled)) { \
8097 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8098 return; \
8099 } \
8100 a0 = tcg_temp_new_i64(); \
8101 a1 = tcg_temp_new_i64(); \
8102 b0 = tcg_temp_new_i64(); \
8103 b1 = tcg_temp_new_i64(); \
8104 if (high) { \
8105 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8106 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8107 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8108 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8109 } else { \
8110 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8111 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8112 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8113 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8114 } \
8115 tcg_gen_shri_i64(a0, a0, 32); \
8116 tcg_gen_shri_i64(b0, b0, 32); \
8117 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8118 b0, a0, 32, 32); \
8119 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8120 b1, a1, 32, 32); \
8121 tcg_temp_free_i64(a0); \
8122 tcg_temp_free_i64(a1); \
8123 tcg_temp_free_i64(b0); \
8124 tcg_temp_free_i64(b1); \
8125 }
8126
8127 VSX_XXMRG(xxmrghw, 1)
8128 VSX_XXMRG(xxmrglw, 0)
8129
8130 static void gen_xxsel(DisasContext * ctx)
8131 {
8132 TCGv_i64 a, b, c;
8133 if (unlikely(!ctx->vsx_enabled)) {
8134 gen_exception(ctx, POWERPC_EXCP_VSXU);
8135 return;
8136 }
8137 a = tcg_temp_new_i64();
8138 b = tcg_temp_new_i64();
8139 c = tcg_temp_new_i64();
8140
8141 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8142 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8143 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8144
8145 tcg_gen_and_i64(b, b, c);
8146 tcg_gen_andc_i64(a, a, c);
8147 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8148
8149 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8150 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8151 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8152
8153 tcg_gen_and_i64(b, b, c);
8154 tcg_gen_andc_i64(a, a, c);
8155 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8156
8157 tcg_temp_free_i64(a);
8158 tcg_temp_free_i64(b);
8159 tcg_temp_free_i64(c);
8160 }
8161
8162 static void gen_xxspltw(DisasContext *ctx)
8163 {
8164 TCGv_i64 b, b2;
8165 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8166 cpu_vsrl(xB(ctx->opcode)) :
8167 cpu_vsrh(xB(ctx->opcode));
8168
8169 if (unlikely(!ctx->vsx_enabled)) {
8170 gen_exception(ctx, POWERPC_EXCP_VSXU);
8171 return;
8172 }
8173
8174 b = tcg_temp_new_i64();
8175 b2 = tcg_temp_new_i64();
8176
8177 if (UIM(ctx->opcode) & 1) {
8178 tcg_gen_ext32u_i64(b, vsr);
8179 } else {
8180 tcg_gen_shri_i64(b, vsr, 32);
8181 }
8182
8183 tcg_gen_shli_i64(b2, b, 32);
8184 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8185 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8186
8187 tcg_temp_free_i64(b);
8188 tcg_temp_free_i64(b2);
8189 }
8190
8191 static void gen_xxsldwi(DisasContext *ctx)
8192 {
8193 TCGv_i64 xth, xtl;
8194 if (unlikely(!ctx->vsx_enabled)) {
8195 gen_exception(ctx, POWERPC_EXCP_VSXU);
8196 return;
8197 }
8198 xth = tcg_temp_new_i64();
8199 xtl = tcg_temp_new_i64();
8200
8201 switch (SHW(ctx->opcode)) {
8202 case 0: {
8203 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8204 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8205 break;
8206 }
8207 case 1: {
8208 TCGv_i64 t0 = tcg_temp_new_i64();
8209 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8210 tcg_gen_shli_i64(xth, xth, 32);
8211 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8212 tcg_gen_shri_i64(t0, t0, 32);
8213 tcg_gen_or_i64(xth, xth, t0);
8214 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8215 tcg_gen_shli_i64(xtl, xtl, 32);
8216 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8217 tcg_gen_shri_i64(t0, t0, 32);
8218 tcg_gen_or_i64(xtl, xtl, t0);
8219 tcg_temp_free_i64(t0);
8220 break;
8221 }
8222 case 2: {
8223 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8224 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8225 break;
8226 }
8227 case 3: {
8228 TCGv_i64 t0 = tcg_temp_new_i64();
8229 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8230 tcg_gen_shli_i64(xth, xth, 32);
8231 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8232 tcg_gen_shri_i64(t0, t0, 32);
8233 tcg_gen_or_i64(xth, xth, t0);
8234 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8235 tcg_gen_shli_i64(xtl, xtl, 32);
8236 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8237 tcg_gen_shri_i64(t0, t0, 32);
8238 tcg_gen_or_i64(xtl, xtl, t0);
8239 tcg_temp_free_i64(t0);
8240 break;
8241 }
8242 }
8243
8244 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8245 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8246
8247 tcg_temp_free_i64(xth);
8248 tcg_temp_free_i64(xtl);
8249 }
8250
8251 /*** Decimal Floating Point ***/
8252
8253 static inline TCGv_ptr gen_fprp_ptr(int reg)
8254 {
8255 TCGv_ptr r = tcg_temp_new_ptr();
8256 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8257 return r;
8258 }
8259
8260 #define GEN_DFP_T_A_B_Rc(name) \
8261 static void gen_##name(DisasContext *ctx) \
8262 { \
8263 TCGv_ptr rd, ra, rb; \
8264 if (unlikely(!ctx->fpu_enabled)) { \
8265 gen_exception(ctx, POWERPC_EXCP_FPU); \
8266 return; \
8267 } \
8268 gen_update_nip(ctx, ctx->nip - 4); \
8269 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8270 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8271 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8272 gen_helper_##name(cpu_env, rd, ra, rb); \
8273 if (unlikely(Rc(ctx->opcode) != 0)) { \
8274 gen_set_cr1_from_fpscr(ctx); \
8275 } \
8276 tcg_temp_free_ptr(rd); \
8277 tcg_temp_free_ptr(ra); \
8278 tcg_temp_free_ptr(rb); \
8279 }
8280
8281 #define GEN_DFP_BF_A_B(name) \
8282 static void gen_##name(DisasContext *ctx) \
8283 { \
8284 TCGv_ptr ra, rb; \
8285 if (unlikely(!ctx->fpu_enabled)) { \
8286 gen_exception(ctx, POWERPC_EXCP_FPU); \
8287 return; \
8288 } \
8289 gen_update_nip(ctx, ctx->nip - 4); \
8290 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8291 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8292 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8293 cpu_env, ra, rb); \
8294 tcg_temp_free_ptr(ra); \
8295 tcg_temp_free_ptr(rb); \
8296 }
8297
8298 #define GEN_DFP_BF_A_DCM(name) \
8299 static void gen_##name(DisasContext *ctx) \
8300 { \
8301 TCGv_ptr ra; \
8302 TCGv_i32 dcm; \
8303 if (unlikely(!ctx->fpu_enabled)) { \
8304 gen_exception(ctx, POWERPC_EXCP_FPU); \
8305 return; \
8306 } \
8307 gen_update_nip(ctx, ctx->nip - 4); \
8308 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8309 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8310 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8311 cpu_env, ra, dcm); \
8312 tcg_temp_free_ptr(ra); \
8313 tcg_temp_free_i32(dcm); \
8314 }
8315
8316 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8317 static void gen_##name(DisasContext *ctx) \
8318 { \
8319 TCGv_ptr rt, rb; \
8320 TCGv_i32 u32_1, u32_2; \
8321 if (unlikely(!ctx->fpu_enabled)) { \
8322 gen_exception(ctx, POWERPC_EXCP_FPU); \
8323 return; \
8324 } \
8325 gen_update_nip(ctx, ctx->nip - 4); \
8326 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8327 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8328 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8329 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8330 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8331 if (unlikely(Rc(ctx->opcode) != 0)) { \
8332 gen_set_cr1_from_fpscr(ctx); \
8333 } \
8334 tcg_temp_free_ptr(rt); \
8335 tcg_temp_free_ptr(rb); \
8336 tcg_temp_free_i32(u32_1); \
8337 tcg_temp_free_i32(u32_2); \
8338 }
8339
8340 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8341 static void gen_##name(DisasContext *ctx) \
8342 { \
8343 TCGv_ptr rt, ra, rb; \
8344 TCGv_i32 i32; \
8345 if (unlikely(!ctx->fpu_enabled)) { \
8346 gen_exception(ctx, POWERPC_EXCP_FPU); \
8347 return; \
8348 } \
8349 gen_update_nip(ctx, ctx->nip - 4); \
8350 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8351 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8352 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8353 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8354 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8355 if (unlikely(Rc(ctx->opcode) != 0)) { \
8356 gen_set_cr1_from_fpscr(ctx); \
8357 } \
8358 tcg_temp_free_ptr(rt); \
8359 tcg_temp_free_ptr(rb); \
8360 tcg_temp_free_ptr(ra); \
8361 tcg_temp_free_i32(i32); \
8362 }
8363
8364 #define GEN_DFP_T_B_Rc(name) \
8365 static void gen_##name(DisasContext *ctx) \
8366 { \
8367 TCGv_ptr rt, rb; \
8368 if (unlikely(!ctx->fpu_enabled)) { \
8369 gen_exception(ctx, POWERPC_EXCP_FPU); \
8370 return; \
8371 } \
8372 gen_update_nip(ctx, ctx->nip - 4); \
8373 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8374 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8375 gen_helper_##name(cpu_env, rt, rb); \
8376 if (unlikely(Rc(ctx->opcode) != 0)) { \
8377 gen_set_cr1_from_fpscr(ctx); \
8378 } \
8379 tcg_temp_free_ptr(rt); \
8380 tcg_temp_free_ptr(rb); \
8381 }
8382
8383 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8384 static void gen_##name(DisasContext *ctx) \
8385 { \
8386 TCGv_ptr rt, rs; \
8387 TCGv_i32 i32; \
8388 if (unlikely(!ctx->fpu_enabled)) { \
8389 gen_exception(ctx, POWERPC_EXCP_FPU); \
8390 return; \
8391 } \
8392 gen_update_nip(ctx, ctx->nip - 4); \
8393 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8394 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8395 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8396 gen_helper_##name(cpu_env, rt, rs, i32); \
8397 if (unlikely(Rc(ctx->opcode) != 0)) { \
8398 gen_set_cr1_from_fpscr(ctx); \
8399 } \
8400 tcg_temp_free_ptr(rt); \
8401 tcg_temp_free_ptr(rs); \
8402 tcg_temp_free_i32(i32); \
8403 }
8404
8405 GEN_DFP_T_A_B_Rc(dadd)
8406 GEN_DFP_T_A_B_Rc(daddq)
8407 GEN_DFP_T_A_B_Rc(dsub)
8408 GEN_DFP_T_A_B_Rc(dsubq)
8409 GEN_DFP_T_A_B_Rc(dmul)
8410 GEN_DFP_T_A_B_Rc(dmulq)
8411 GEN_DFP_T_A_B_Rc(ddiv)
8412 GEN_DFP_T_A_B_Rc(ddivq)
8413 GEN_DFP_BF_A_B(dcmpu)
8414 GEN_DFP_BF_A_B(dcmpuq)
8415 GEN_DFP_BF_A_B(dcmpo)
8416 GEN_DFP_BF_A_B(dcmpoq)
8417 GEN_DFP_BF_A_DCM(dtstdc)
8418 GEN_DFP_BF_A_DCM(dtstdcq)
8419 GEN_DFP_BF_A_DCM(dtstdg)
8420 GEN_DFP_BF_A_DCM(dtstdgq)
8421 GEN_DFP_BF_A_B(dtstex)
8422 GEN_DFP_BF_A_B(dtstexq)
8423 GEN_DFP_BF_A_B(dtstsf)
8424 GEN_DFP_BF_A_B(dtstsfq)
8425 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8426 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8427 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8428 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8429 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8430 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8431 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8432 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8433 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8434 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8435 GEN_DFP_T_B_Rc(dctdp)
8436 GEN_DFP_T_B_Rc(dctqpq)
8437 GEN_DFP_T_B_Rc(drsp)
8438 GEN_DFP_T_B_Rc(drdpq)
8439 GEN_DFP_T_B_Rc(dcffix)
8440 GEN_DFP_T_B_Rc(dcffixq)
8441 GEN_DFP_T_B_Rc(dctfix)
8442 GEN_DFP_T_B_Rc(dctfixq)
8443 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8444 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8445 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8446 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8447 GEN_DFP_T_B_Rc(dxex)
8448 GEN_DFP_T_B_Rc(dxexq)
8449 GEN_DFP_T_A_B_Rc(diex)
8450 GEN_DFP_T_A_B_Rc(diexq)
8451 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8452 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8453 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8454 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8455
8456 /*** SPE extension ***/
8457 /* Register moves */
8458
8459 static inline void gen_evmra(DisasContext *ctx)
8460 {
8461
8462 if (unlikely(!ctx->spe_enabled)) {
8463 gen_exception(ctx, POWERPC_EXCP_SPEU);
8464 return;
8465 }
8466
8467 TCGv_i64 tmp = tcg_temp_new_i64();
8468
8469 /* tmp := rA_lo + rA_hi << 32 */
8470 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8471
8472 /* spe_acc := tmp */
8473 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8474 tcg_temp_free_i64(tmp);
8475
8476 /* rD := rA */
8477 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8478 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8479 }
8480
8481 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8482 {
8483 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8484 }
8485
8486 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8487 {
8488 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8489 }
8490
8491 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8492 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8493 { \
8494 if (Rc(ctx->opcode)) \
8495 gen_##name1(ctx); \
8496 else \
8497 gen_##name0(ctx); \
8498 }
8499
8500 /* Handler for undefined SPE opcodes */
8501 static inline void gen_speundef(DisasContext *ctx)
8502 {
8503 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8504 }
8505
8506 /* SPE logic */
8507 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8508 static inline void gen_##name(DisasContext *ctx) \
8509 { \
8510 if (unlikely(!ctx->spe_enabled)) { \
8511 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8512 return; \
8513 } \
8514 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8515 cpu_gpr[rB(ctx->opcode)]); \
8516 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8517 cpu_gprh[rB(ctx->opcode)]); \
8518 }
8519
8520 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8521 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8522 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8523 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8524 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8525 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8526 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8527 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8528
8529 /* SPE logic immediate */
8530 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8531 static inline void gen_##name(DisasContext *ctx) \
8532 { \
8533 TCGv_i32 t0; \
8534 if (unlikely(!ctx->spe_enabled)) { \
8535 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8536 return; \
8537 } \
8538 t0 = tcg_temp_new_i32(); \
8539 \
8540 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8541 tcg_opi(t0, t0, rB(ctx->opcode)); \
8542 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8543 \
8544 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8545 tcg_opi(t0, t0, rB(ctx->opcode)); \
8546 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8547 \
8548 tcg_temp_free_i32(t0); \
8549 }
8550 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8551 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8552 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8553 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8554
8555 /* SPE arithmetic */
8556 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8557 static inline void gen_##name(DisasContext *ctx) \
8558 { \
8559 TCGv_i32 t0; \
8560 if (unlikely(!ctx->spe_enabled)) { \
8561 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8562 return; \
8563 } \
8564 t0 = tcg_temp_new_i32(); \
8565 \
8566 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8567 tcg_op(t0, t0); \
8568 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8569 \
8570 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8571 tcg_op(t0, t0); \
8572 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8573 \
8574 tcg_temp_free_i32(t0); \
8575 }
8576
8577 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8578 {
8579 TCGLabel *l1 = gen_new_label();
8580 TCGLabel *l2 = gen_new_label();
8581
8582 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8583 tcg_gen_neg_i32(ret, arg1);
8584 tcg_gen_br(l2);
8585 gen_set_label(l1);
8586 tcg_gen_mov_i32(ret, arg1);
8587 gen_set_label(l2);
8588 }
8589 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8590 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8591 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8592 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8593 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8594 {
8595 tcg_gen_addi_i32(ret, arg1, 0x8000);
8596 tcg_gen_ext16u_i32(ret, ret);
8597 }
8598 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8599 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8600 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8601
8602 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8603 static inline void gen_##name(DisasContext *ctx) \
8604 { \
8605 TCGv_i32 t0, t1; \
8606 if (unlikely(!ctx->spe_enabled)) { \
8607 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8608 return; \
8609 } \
8610 t0 = tcg_temp_new_i32(); \
8611 t1 = tcg_temp_new_i32(); \
8612 \
8613 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8614 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8615 tcg_op(t0, t0, t1); \
8616 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8617 \
8618 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8619 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8620 tcg_op(t0, t0, t1); \
8621 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8622 \
8623 tcg_temp_free_i32(t0); \
8624 tcg_temp_free_i32(t1); \
8625 }
8626
8627 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8628 {
8629 TCGLabel *l1 = gen_new_label();
8630 TCGLabel *l2 = gen_new_label();
8631 TCGv_i32 t0 = tcg_temp_local_new_i32();
8632
8633 /* No error here: 6 bits are used */
8634 tcg_gen_andi_i32(t0, arg2, 0x3F);
8635 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8636 tcg_gen_shr_i32(ret, arg1, t0);
8637 tcg_gen_br(l2);
8638 gen_set_label(l1);
8639 tcg_gen_movi_i32(ret, 0);
8640 gen_set_label(l2);
8641 tcg_temp_free_i32(t0);
8642 }
8643 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8644 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8645 {
8646 TCGLabel *l1 = gen_new_label();
8647 TCGLabel *l2 = gen_new_label();
8648 TCGv_i32 t0 = tcg_temp_local_new_i32();
8649
8650 /* No error here: 6 bits are used */
8651 tcg_gen_andi_i32(t0, arg2, 0x3F);
8652 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8653 tcg_gen_sar_i32(ret, arg1, t0);
8654 tcg_gen_br(l2);
8655 gen_set_label(l1);
8656 tcg_gen_movi_i32(ret, 0);
8657 gen_set_label(l2);
8658 tcg_temp_free_i32(t0);
8659 }
8660 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8661 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8662 {
8663 TCGLabel *l1 = gen_new_label();
8664 TCGLabel *l2 = gen_new_label();
8665 TCGv_i32 t0 = tcg_temp_local_new_i32();
8666
8667 /* No error here: 6 bits are used */
8668 tcg_gen_andi_i32(t0, arg2, 0x3F);
8669 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8670 tcg_gen_shl_i32(ret, arg1, t0);
8671 tcg_gen_br(l2);
8672 gen_set_label(l1);
8673 tcg_gen_movi_i32(ret, 0);
8674 gen_set_label(l2);
8675 tcg_temp_free_i32(t0);
8676 }
8677 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8678 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8679 {
8680 TCGv_i32 t0 = tcg_temp_new_i32();
8681 tcg_gen_andi_i32(t0, arg2, 0x1F);
8682 tcg_gen_rotl_i32(ret, arg1, t0);
8683 tcg_temp_free_i32(t0);
8684 }
8685 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8686 static inline void gen_evmergehi(DisasContext *ctx)
8687 {
8688 if (unlikely(!ctx->spe_enabled)) {
8689 gen_exception(ctx, POWERPC_EXCP_SPEU);
8690 return;
8691 }
8692 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8693 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8694 }
8695 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8696 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8697 {
8698 tcg_gen_sub_i32(ret, arg2, arg1);
8699 }
8700 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8701
8702 /* SPE arithmetic immediate */
8703 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8704 static inline void gen_##name(DisasContext *ctx) \
8705 { \
8706 TCGv_i32 t0; \
8707 if (unlikely(!ctx->spe_enabled)) { \
8708 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8709 return; \
8710 } \
8711 t0 = tcg_temp_new_i32(); \
8712 \
8713 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8714 tcg_op(t0, t0, rA(ctx->opcode)); \
8715 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8716 \
8717 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8718 tcg_op(t0, t0, rA(ctx->opcode)); \
8719 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8720 \
8721 tcg_temp_free_i32(t0); \
8722 }
8723 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8724 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8725
8726 /* SPE comparison */
8727 #define GEN_SPEOP_COMP(name, tcg_cond) \
8728 static inline void gen_##name(DisasContext *ctx) \
8729 { \
8730 if (unlikely(!ctx->spe_enabled)) { \
8731 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8732 return; \
8733 } \
8734 TCGLabel *l1 = gen_new_label(); \
8735 TCGLabel *l2 = gen_new_label(); \
8736 TCGLabel *l3 = gen_new_label(); \
8737 TCGLabel *l4 = gen_new_label(); \
8738 \
8739 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8740 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8741 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8742 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8743 \
8744 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8745 cpu_gpr[rB(ctx->opcode)], l1); \
8746 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8747 tcg_gen_br(l2); \
8748 gen_set_label(l1); \
8749 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8750 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8751 gen_set_label(l2); \
8752 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8753 cpu_gprh[rB(ctx->opcode)], l3); \
8754 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8755 ~(CRF_CH | CRF_CH_AND_CL)); \
8756 tcg_gen_br(l4); \
8757 gen_set_label(l3); \
8758 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8759 CRF_CH | CRF_CH_OR_CL); \
8760 gen_set_label(l4); \
8761 }
8762 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8763 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8764 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8765 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8766 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8767
8768 /* SPE misc */
8769 static inline void gen_brinc(DisasContext *ctx)
8770 {
8771 /* Note: brinc is usable even if SPE is disabled */
8772 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8773 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8774 }
8775 static inline void gen_evmergelo(DisasContext *ctx)
8776 {
8777 if (unlikely(!ctx->spe_enabled)) {
8778 gen_exception(ctx, POWERPC_EXCP_SPEU);
8779 return;
8780 }
8781 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8782 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8783 }
8784 static inline void gen_evmergehilo(DisasContext *ctx)
8785 {
8786 if (unlikely(!ctx->spe_enabled)) {
8787 gen_exception(ctx, POWERPC_EXCP_SPEU);
8788 return;
8789 }
8790 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8791 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8792 }
8793 static inline void gen_evmergelohi(DisasContext *ctx)
8794 {
8795 if (unlikely(!ctx->spe_enabled)) {
8796 gen_exception(ctx, POWERPC_EXCP_SPEU);
8797 return;
8798 }
8799 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8800 TCGv tmp = tcg_temp_new();
8801 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8802 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8803 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8804 tcg_temp_free(tmp);
8805 } else {
8806 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8807 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8808 }
8809 }
8810 static inline void gen_evsplati(DisasContext *ctx)
8811 {
8812 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8813
8814 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8815 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8816 }
8817 static inline void gen_evsplatfi(DisasContext *ctx)
8818 {
8819 uint64_t imm = rA(ctx->opcode) << 27;
8820
8821 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8822 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8823 }
8824
8825 static inline void gen_evsel(DisasContext *ctx)
8826 {
8827 TCGLabel *l1 = gen_new_label();
8828 TCGLabel *l2 = gen_new_label();
8829 TCGLabel *l3 = gen_new_label();
8830 TCGLabel *l4 = gen_new_label();
8831 TCGv_i32 t0 = tcg_temp_local_new_i32();
8832
8833 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8834 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8835 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8836 tcg_gen_br(l2);
8837 gen_set_label(l1);
8838 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8839 gen_set_label(l2);
8840 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8841 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8842 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8843 tcg_gen_br(l4);
8844 gen_set_label(l3);
8845 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8846 gen_set_label(l4);
8847 tcg_temp_free_i32(t0);
8848 }
8849
8850 static void gen_evsel0(DisasContext *ctx)
8851 {
8852 gen_evsel(ctx);
8853 }
8854
8855 static void gen_evsel1(DisasContext *ctx)
8856 {
8857 gen_evsel(ctx);
8858 }
8859
8860 static void gen_evsel2(DisasContext *ctx)
8861 {
8862 gen_evsel(ctx);
8863 }
8864
8865 static void gen_evsel3(DisasContext *ctx)
8866 {
8867 gen_evsel(ctx);
8868 }
8869
8870 /* Multiply */
8871
8872 static inline void gen_evmwumi(DisasContext *ctx)
8873 {
8874 TCGv_i64 t0, t1;
8875
8876 if (unlikely(!ctx->spe_enabled)) {
8877 gen_exception(ctx, POWERPC_EXCP_SPEU);
8878 return;
8879 }
8880
8881 t0 = tcg_temp_new_i64();
8882 t1 = tcg_temp_new_i64();
8883
8884 /* t0 := rA; t1 := rB */
8885 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8886 tcg_gen_ext32u_i64(t0, t0);
8887 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8888 tcg_gen_ext32u_i64(t1, t1);
8889
8890 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8891
8892 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8893
8894 tcg_temp_free_i64(t0);
8895 tcg_temp_free_i64(t1);
8896 }
8897
8898 static inline void gen_evmwumia(DisasContext *ctx)
8899 {
8900 TCGv_i64 tmp;
8901
8902 if (unlikely(!ctx->spe_enabled)) {
8903 gen_exception(ctx, POWERPC_EXCP_SPEU);
8904 return;
8905 }
8906
8907 gen_evmwumi(ctx); /* rD := rA * rB */
8908
8909 tmp = tcg_temp_new_i64();
8910
8911 /* acc := rD */
8912 gen_load_gpr64(tmp, rD(ctx->opcode));
8913 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8914 tcg_temp_free_i64(tmp);
8915 }
8916
8917 static inline void gen_evmwumiaa(DisasContext *ctx)
8918 {
8919 TCGv_i64 acc;
8920 TCGv_i64 tmp;
8921
8922 if (unlikely(!ctx->spe_enabled)) {
8923 gen_exception(ctx, POWERPC_EXCP_SPEU);
8924 return;
8925 }
8926
8927 gen_evmwumi(ctx); /* rD := rA * rB */
8928
8929 acc = tcg_temp_new_i64();
8930 tmp = tcg_temp_new_i64();
8931
8932 /* tmp := rD */
8933 gen_load_gpr64(tmp, rD(ctx->opcode));
8934
8935 /* Load acc */
8936 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8937
8938 /* acc := tmp + acc */
8939 tcg_gen_add_i64(acc, acc, tmp);
8940
8941 /* Store acc */
8942 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8943
8944 /* rD := acc */
8945 gen_store_gpr64(rD(ctx->opcode), acc);
8946
8947 tcg_temp_free_i64(acc);
8948 tcg_temp_free_i64(tmp);
8949 }
8950
8951 static inline void gen_evmwsmi(DisasContext *ctx)
8952 {
8953 TCGv_i64 t0, t1;
8954
8955 if (unlikely(!ctx->spe_enabled)) {
8956 gen_exception(ctx, POWERPC_EXCP_SPEU);
8957 return;
8958 }
8959
8960 t0 = tcg_temp_new_i64();
8961 t1 = tcg_temp_new_i64();
8962
8963 /* t0 := rA; t1 := rB */
8964 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8965 tcg_gen_ext32s_i64(t0, t0);
8966 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8967 tcg_gen_ext32s_i64(t1, t1);
8968
8969 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8970
8971 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8972
8973 tcg_temp_free_i64(t0);
8974 tcg_temp_free_i64(t1);
8975 }
8976
8977 static inline void gen_evmwsmia(DisasContext *ctx)
8978 {
8979 TCGv_i64 tmp;
8980
8981 gen_evmwsmi(ctx); /* rD := rA * rB */
8982
8983 tmp = tcg_temp_new_i64();
8984
8985 /* acc := rD */
8986 gen_load_gpr64(tmp, rD(ctx->opcode));
8987 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8988
8989 tcg_temp_free_i64(tmp);
8990 }
8991
8992 static inline void gen_evmwsmiaa(DisasContext *ctx)
8993 {
8994 TCGv_i64 acc = tcg_temp_new_i64();
8995 TCGv_i64 tmp = tcg_temp_new_i64();
8996
8997 gen_evmwsmi(ctx); /* rD := rA * rB */
8998
8999 acc = tcg_temp_new_i64();
9000 tmp = tcg_temp_new_i64();
9001
9002 /* tmp := rD */
9003 gen_load_gpr64(tmp, rD(ctx->opcode));
9004
9005 /* Load acc */
9006 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9007
9008 /* acc := tmp + acc */
9009 tcg_gen_add_i64(acc, acc, tmp);
9010
9011 /* Store acc */
9012 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9013
9014 /* rD := acc */
9015 gen_store_gpr64(rD(ctx->opcode), acc);
9016
9017 tcg_temp_free_i64(acc);
9018 tcg_temp_free_i64(tmp);
9019 }
9020
9021 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9022 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9023 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9024 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9025 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9026 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9027 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9028 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9029 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9030 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9031 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9032 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9033 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9034 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9035 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9036 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9037 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9038 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9039 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9040 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9041 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9042 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9043 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9044 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9045 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9046 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9047 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9048 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9049 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9050
9051 /* SPE load and stores */
9052 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9053 {
9054 target_ulong uimm = rB(ctx->opcode);
9055
9056 if (rA(ctx->opcode) == 0) {
9057 tcg_gen_movi_tl(EA, uimm << sh);
9058 } else {
9059 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9060 if (NARROW_MODE(ctx)) {
9061 tcg_gen_ext32u_tl(EA, EA);
9062 }
9063 }
9064 }
9065
9066 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9067 {
9068 TCGv_i64 t0 = tcg_temp_new_i64();
9069 gen_qemu_ld64(ctx, t0, addr);
9070 gen_store_gpr64(rD(ctx->opcode), t0);
9071 tcg_temp_free_i64(t0);
9072 }
9073
9074 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9075 {
9076 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9077 gen_addr_add(ctx, addr, addr, 4);
9078 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9079 }
9080
9081 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9082 {
9083 TCGv t0 = tcg_temp_new();
9084 gen_qemu_ld16u(ctx, t0, addr);
9085 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9086 gen_addr_add(ctx, addr, addr, 2);
9087 gen_qemu_ld16u(ctx, t0, addr);
9088 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9089 gen_addr_add(ctx, addr, addr, 2);
9090 gen_qemu_ld16u(ctx, t0, addr);
9091 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9092 gen_addr_add(ctx, addr, addr, 2);
9093 gen_qemu_ld16u(ctx, t0, addr);
9094 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9095 tcg_temp_free(t0);
9096 }
9097
9098 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9099 {
9100 TCGv t0 = tcg_temp_new();
9101 gen_qemu_ld16u(ctx, t0, addr);
9102 tcg_gen_shli_tl(t0, t0, 16);
9103 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9104 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9105 tcg_temp_free(t0);
9106 }
9107
9108 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9109 {
9110 TCGv t0 = tcg_temp_new();
9111 gen_qemu_ld16u(ctx, t0, addr);
9112 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9113 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9114 tcg_temp_free(t0);
9115 }
9116
9117 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9118 {
9119 TCGv t0 = tcg_temp_new();
9120 gen_qemu_ld16s(ctx, t0, addr);
9121 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9122 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9123 tcg_temp_free(t0);
9124 }
9125
9126 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9127 {
9128 TCGv t0 = tcg_temp_new();
9129 gen_qemu_ld16u(ctx, t0, addr);
9130 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9131 gen_addr_add(ctx, addr, addr, 2);
9132 gen_qemu_ld16u(ctx, t0, addr);
9133 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9134 tcg_temp_free(t0);
9135 }
9136
9137 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9138 {
9139 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9140 gen_addr_add(ctx, addr, addr, 2);
9141 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9142 }
9143
9144 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9145 {
9146 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9147 gen_addr_add(ctx, addr, addr, 2);
9148 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9149 }
9150
9151 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9152 {
9153 TCGv t0 = tcg_temp_new();
9154 gen_qemu_ld32u(ctx, t0, addr);
9155 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9156 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9157 tcg_temp_free(t0);
9158 }
9159
9160 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9161 {
9162 TCGv t0 = tcg_temp_new();
9163 gen_qemu_ld16u(ctx, t0, addr);
9164 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9165 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9166 gen_addr_add(ctx, addr, addr, 2);
9167 gen_qemu_ld16u(ctx, t0, addr);
9168 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9169 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9170 tcg_temp_free(t0);
9171 }
9172
9173 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9174 {
9175 TCGv_i64 t0 = tcg_temp_new_i64();
9176 gen_load_gpr64(t0, rS(ctx->opcode));
9177 gen_qemu_st64(ctx, t0, addr);
9178 tcg_temp_free_i64(t0);
9179 }
9180
9181 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9182 {
9183 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9184 gen_addr_add(ctx, addr, addr, 4);
9185 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9186 }
9187
9188 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9189 {
9190 TCGv t0 = tcg_temp_new();
9191 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9192 gen_qemu_st16(ctx, t0, addr);
9193 gen_addr_add(ctx, addr, addr, 2);
9194 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9195 gen_addr_add(ctx, addr, addr, 2);
9196 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9197 gen_qemu_st16(ctx, t0, addr);
9198 tcg_temp_free(t0);
9199 gen_addr_add(ctx, addr, addr, 2);
9200 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9201 }
9202
9203 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9204 {
9205 TCGv t0 = tcg_temp_new();
9206 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9207 gen_qemu_st16(ctx, t0, addr);
9208 gen_addr_add(ctx, addr, addr, 2);
9209 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9210 gen_qemu_st16(ctx, t0, addr);
9211 tcg_temp_free(t0);
9212 }
9213
9214 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9215 {
9216 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9217 gen_addr_add(ctx, addr, addr, 2);
9218 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9219 }
9220
9221 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9222 {
9223 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9224 }
9225
9226 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9227 {
9228 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9229 }
9230
9231 #define GEN_SPEOP_LDST(name, opc2, sh) \
9232 static void glue(gen_, name)(DisasContext *ctx) \
9233 { \
9234 TCGv t0; \
9235 if (unlikely(!ctx->spe_enabled)) { \
9236 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9237 return; \
9238 } \
9239 gen_set_access_type(ctx, ACCESS_INT); \
9240 t0 = tcg_temp_new(); \
9241 if (Rc(ctx->opcode)) { \
9242 gen_addr_spe_imm_index(ctx, t0, sh); \
9243 } else { \
9244 gen_addr_reg_index(ctx, t0); \
9245 } \
9246 gen_op_##name(ctx, t0); \
9247 tcg_temp_free(t0); \
9248 }
9249
9250 GEN_SPEOP_LDST(evldd, 0x00, 3);
9251 GEN_SPEOP_LDST(evldw, 0x01, 3);
9252 GEN_SPEOP_LDST(evldh, 0x02, 3);
9253 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9254 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9255 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9256 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9257 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9258 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9259 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9260 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9261
9262 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9263 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9264 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9265 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9266 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9267 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9268 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9269
9270 /* Multiply and add - TODO */
9271 #if 0
9272 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9273 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9274 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9275 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9276 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9277 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9278 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9279 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9280 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9281 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9282 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9283 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9284
9285 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9286 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9287 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9288 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9289 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9290 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9291 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9292 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9293 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9294 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9295 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9296 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9297
9298 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9299 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9300 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9301 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9302 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9303
9304 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9305 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9306 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9307 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9308 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9309 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9310 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9311 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9312 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9313 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9314 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9315 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9316
9317 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9318 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9319 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9320 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9321
9322 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9323 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9324 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9325 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9326 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9327 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9328 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9329 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9330 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9331 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9332 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9333 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9334
9335 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9336 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9337 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9338 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9339 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9340 #endif
9341
9342 /*** SPE floating-point extension ***/
9343 #define GEN_SPEFPUOP_CONV_32_32(name) \
9344 static inline void gen_##name(DisasContext *ctx) \
9345 { \
9346 TCGv_i32 t0 = tcg_temp_new_i32(); \
9347 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9348 gen_helper_##name(t0, cpu_env, t0); \
9349 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9350 tcg_temp_free_i32(t0); \
9351 }
9352 #define GEN_SPEFPUOP_CONV_32_64(name) \
9353 static inline void gen_##name(DisasContext *ctx) \
9354 { \
9355 TCGv_i64 t0 = tcg_temp_new_i64(); \
9356 TCGv_i32 t1 = tcg_temp_new_i32(); \
9357 gen_load_gpr64(t0, rB(ctx->opcode)); \
9358 gen_helper_##name(t1, cpu_env, t0); \
9359 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9360 tcg_temp_free_i64(t0); \
9361 tcg_temp_free_i32(t1); \
9362 }
9363 #define GEN_SPEFPUOP_CONV_64_32(name) \
9364 static inline void gen_##name(DisasContext *ctx) \
9365 { \
9366 TCGv_i64 t0 = tcg_temp_new_i64(); \
9367 TCGv_i32 t1 = tcg_temp_new_i32(); \
9368 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9369 gen_helper_##name(t0, cpu_env, t1); \
9370 gen_store_gpr64(rD(ctx->opcode), t0); \
9371 tcg_temp_free_i64(t0); \
9372 tcg_temp_free_i32(t1); \
9373 }
9374 #define GEN_SPEFPUOP_CONV_64_64(name) \
9375 static inline void gen_##name(DisasContext *ctx) \
9376 { \
9377 TCGv_i64 t0 = tcg_temp_new_i64(); \
9378 gen_load_gpr64(t0, rB(ctx->opcode)); \
9379 gen_helper_##name(t0, cpu_env, t0); \
9380 gen_store_gpr64(rD(ctx->opcode), t0); \
9381 tcg_temp_free_i64(t0); \
9382 }
9383 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9384 static inline void gen_##name(DisasContext *ctx) \
9385 { \
9386 TCGv_i32 t0, t1; \
9387 if (unlikely(!ctx->spe_enabled)) { \
9388 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9389 return; \
9390 } \
9391 t0 = tcg_temp_new_i32(); \
9392 t1 = tcg_temp_new_i32(); \
9393 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9394 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9395 gen_helper_##name(t0, cpu_env, t0, t1); \
9396 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9397 \
9398 tcg_temp_free_i32(t0); \
9399 tcg_temp_free_i32(t1); \
9400 }
9401 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9402 static inline void gen_##name(DisasContext *ctx) \
9403 { \
9404 TCGv_i64 t0, t1; \
9405 if (unlikely(!ctx->spe_enabled)) { \
9406 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9407 return; \
9408 } \
9409 t0 = tcg_temp_new_i64(); \
9410 t1 = tcg_temp_new_i64(); \
9411 gen_load_gpr64(t0, rA(ctx->opcode)); \
9412 gen_load_gpr64(t1, rB(ctx->opcode)); \
9413 gen_helper_##name(t0, cpu_env, t0, t1); \
9414 gen_store_gpr64(rD(ctx->opcode), t0); \
9415 tcg_temp_free_i64(t0); \
9416 tcg_temp_free_i64(t1); \
9417 }
9418 #define GEN_SPEFPUOP_COMP_32(name) \
9419 static inline void gen_##name(DisasContext *ctx) \
9420 { \
9421 TCGv_i32 t0, t1; \
9422 if (unlikely(!ctx->spe_enabled)) { \
9423 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9424 return; \
9425 } \
9426 t0 = tcg_temp_new_i32(); \
9427 t1 = tcg_temp_new_i32(); \
9428 \
9429 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9430 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9431 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9432 \
9433 tcg_temp_free_i32(t0); \
9434 tcg_temp_free_i32(t1); \
9435 }
9436 #define GEN_SPEFPUOP_COMP_64(name) \
9437 static inline void gen_##name(DisasContext *ctx) \
9438 { \
9439 TCGv_i64 t0, t1; \
9440 if (unlikely(!ctx->spe_enabled)) { \
9441 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9442 return; \
9443 } \
9444 t0 = tcg_temp_new_i64(); \
9445 t1 = tcg_temp_new_i64(); \
9446 gen_load_gpr64(t0, rA(ctx->opcode)); \
9447 gen_load_gpr64(t1, rB(ctx->opcode)); \
9448 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9449 tcg_temp_free_i64(t0); \
9450 tcg_temp_free_i64(t1); \
9451 }
9452
9453 /* Single precision floating-point vectors operations */
9454 /* Arithmetic */
9455 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9456 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9457 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9458 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9459 static inline void gen_evfsabs(DisasContext *ctx)
9460 {
9461 if (unlikely(!ctx->spe_enabled)) {
9462 gen_exception(ctx, POWERPC_EXCP_SPEU);
9463 return;
9464 }
9465 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9466 ~0x80000000);
9467 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9468 ~0x80000000);
9469 }
9470 static inline void gen_evfsnabs(DisasContext *ctx)
9471 {
9472 if (unlikely(!ctx->spe_enabled)) {
9473 gen_exception(ctx, POWERPC_EXCP_SPEU);
9474 return;
9475 }
9476 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9477 0x80000000);
9478 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9479 0x80000000);
9480 }
9481 static inline void gen_evfsneg(DisasContext *ctx)
9482 {
9483 if (unlikely(!ctx->spe_enabled)) {
9484 gen_exception(ctx, POWERPC_EXCP_SPEU);
9485 return;
9486 }
9487 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9488 0x80000000);
9489 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9490 0x80000000);
9491 }
9492
9493 /* Conversion */
9494 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9495 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9496 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9497 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9498 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9499 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9500 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9501 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9502 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9503 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9504
9505 /* Comparison */
9506 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9507 GEN_SPEFPUOP_COMP_64(evfscmplt);
9508 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9509 GEN_SPEFPUOP_COMP_64(evfststgt);
9510 GEN_SPEFPUOP_COMP_64(evfststlt);
9511 GEN_SPEFPUOP_COMP_64(evfststeq);
9512
9513 /* Opcodes definitions */
9514 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9515 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9516 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9517 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9518 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9519 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9520 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9521 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9522 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9523 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9524 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9525 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9526 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9527 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9528
9529 /* Single precision floating-point operations */
9530 /* Arithmetic */
9531 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9532 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9533 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9534 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9535 static inline void gen_efsabs(DisasContext *ctx)
9536 {
9537 if (unlikely(!ctx->spe_enabled)) {
9538 gen_exception(ctx, POWERPC_EXCP_SPEU);
9539 return;
9540 }
9541 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9542 }
9543 static inline void gen_efsnabs(DisasContext *ctx)
9544 {
9545 if (unlikely(!ctx->spe_enabled)) {
9546 gen_exception(ctx, POWERPC_EXCP_SPEU);
9547 return;
9548 }
9549 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9550 }
9551 static inline void gen_efsneg(DisasContext *ctx)
9552 {
9553 if (unlikely(!ctx->spe_enabled)) {
9554 gen_exception(ctx, POWERPC_EXCP_SPEU);
9555 return;
9556 }
9557 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9558 }
9559
9560 /* Conversion */
9561 GEN_SPEFPUOP_CONV_32_32(efscfui);
9562 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9563 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9564 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9565 GEN_SPEFPUOP_CONV_32_32(efsctui);
9566 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9567 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9568 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9569 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9570 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9571 GEN_SPEFPUOP_CONV_32_64(efscfd);
9572
9573 /* Comparison */
9574 GEN_SPEFPUOP_COMP_32(efscmpgt);
9575 GEN_SPEFPUOP_COMP_32(efscmplt);
9576 GEN_SPEFPUOP_COMP_32(efscmpeq);
9577 GEN_SPEFPUOP_COMP_32(efststgt);
9578 GEN_SPEFPUOP_COMP_32(efststlt);
9579 GEN_SPEFPUOP_COMP_32(efststeq);
9580
9581 /* Opcodes definitions */
9582 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9583 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9584 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9585 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9586 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9587 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9588 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9589 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9590 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9591 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9592 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9593 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9594 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9595 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9596
9597 /* Double precision floating-point operations */
9598 /* Arithmetic */
9599 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9600 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9601 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9602 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9603 static inline void gen_efdabs(DisasContext *ctx)
9604 {
9605 if (unlikely(!ctx->spe_enabled)) {
9606 gen_exception(ctx, POWERPC_EXCP_SPEU);
9607 return;
9608 }
9609 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9610 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9611 ~0x80000000);
9612 }
9613 static inline void gen_efdnabs(DisasContext *ctx)
9614 {
9615 if (unlikely(!ctx->spe_enabled)) {
9616 gen_exception(ctx, POWERPC_EXCP_SPEU);
9617 return;
9618 }
9619 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9620 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9621 0x80000000);
9622 }
9623 static inline void gen_efdneg(DisasContext *ctx)
9624 {
9625 if (unlikely(!ctx->spe_enabled)) {
9626 gen_exception(ctx, POWERPC_EXCP_SPEU);
9627 return;
9628 }
9629 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9630 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9631 0x80000000);
9632 }
9633
9634 /* Conversion */
9635 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9636 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9637 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9638 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9639 GEN_SPEFPUOP_CONV_32_64(efdctui);
9640 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9641 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9642 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9643 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9644 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9645 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9646 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9647 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9648 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9649 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9650
9651 /* Comparison */
9652 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9653 GEN_SPEFPUOP_COMP_64(efdcmplt);
9654 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9655 GEN_SPEFPUOP_COMP_64(efdtstgt);
9656 GEN_SPEFPUOP_COMP_64(efdtstlt);
9657 GEN_SPEFPUOP_COMP_64(efdtsteq);
9658
9659 /* Opcodes definitions */
9660 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9661 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9662 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9663 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9664 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9665 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9666 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9667 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9668 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9669 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9670 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9671 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9672 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9673 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9674 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9675 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9676
9677 static void gen_tbegin(DisasContext *ctx)
9678 {
9679 if (unlikely(!ctx->tm_enabled)) {
9680 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9681 return;
9682 }
9683 gen_helper_tbegin(cpu_env);
9684 }
9685
9686 #define GEN_TM_NOOP(name) \
9687 static inline void gen_##name(DisasContext *ctx) \
9688 { \
9689 if (unlikely(!ctx->tm_enabled)) { \
9690 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9691 return; \
9692 } \
9693 /* Because tbegin always fails in QEMU, these user \
9694 * space instructions all have a simple implementation: \
9695 * \
9696 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9697 * = 0b0 || 0b00 || 0b0 \
9698 */ \
9699 tcg_gen_movi_i32(cpu_crf[0], 0); \
9700 }
9701
9702 GEN_TM_NOOP(tend);
9703 GEN_TM_NOOP(tabort);
9704 GEN_TM_NOOP(tabortwc);
9705 GEN_TM_NOOP(tabortwci);
9706 GEN_TM_NOOP(tabortdc);
9707 GEN_TM_NOOP(tabortdci);
9708 GEN_TM_NOOP(tsr);
9709
9710 static void gen_tcheck(DisasContext *ctx)
9711 {
9712 if (unlikely(!ctx->tm_enabled)) {
9713 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9714 return;
9715 }
9716 /* Because tbegin always fails, the tcheck implementation
9717 * is simple:
9718 *
9719 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9720 * = 0b1 || 0b00 || 0b0
9721 */
9722 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9723 }
9724
9725 #if defined(CONFIG_USER_ONLY)
9726 #define GEN_TM_PRIV_NOOP(name) \
9727 static inline void gen_##name(DisasContext *ctx) \
9728 { \
9729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9730 }
9731
9732 #else
9733
9734 #define GEN_TM_PRIV_NOOP(name) \
9735 static inline void gen_##name(DisasContext *ctx) \
9736 { \
9737 if (unlikely(ctx->pr)) { \
9738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9739 return; \
9740 } \
9741 if (unlikely(!ctx->tm_enabled)) { \
9742 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9743 return; \
9744 } \
9745 /* Because tbegin always fails, the implementation is \
9746 * simple: \
9747 * \
9748 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9749 * = 0b0 || 0b00 | 0b0 \
9750 */ \
9751 tcg_gen_movi_i32(cpu_crf[0], 0); \
9752 }
9753
9754 #endif
9755
9756 GEN_TM_PRIV_NOOP(treclaim);
9757 GEN_TM_PRIV_NOOP(trechkpt);
9758
9759 static opcode_t opcodes[] = {
9760 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9761 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9762 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9763 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9764 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9765 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9766 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9767 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9768 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9769 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9770 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9771 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9772 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9773 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9774 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9775 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9776 #if defined(TARGET_PPC64)
9777 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9778 #endif
9779 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9780 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9781 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9782 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9783 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9784 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9785 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9786 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9787 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9788 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9789 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9790 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9791 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9792 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9793 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9794 #if defined(TARGET_PPC64)
9795 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9796 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9797 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9798 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9799 #endif
9800 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9801 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9802 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9803 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9804 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9805 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9806 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9807 #if defined(TARGET_PPC64)
9808 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9809 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9810 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9811 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9812 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9813 #endif
9814 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9815 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9816 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9817 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9818 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9819 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9820 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9821 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9822 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9823 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9824 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9825 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9826 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9827 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9828 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9829 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9830 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9831 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9832 #if defined(TARGET_PPC64)
9833 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9834 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9835 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9836 #endif
9837 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9838 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9839 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9840 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9841 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9842 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9843 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9844 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9845 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9846 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9847 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9848 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9849 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9850 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9851 #if defined(TARGET_PPC64)
9852 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9853 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9854 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9855 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9856 #endif
9857 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9858 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9859 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9860 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9861 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9862 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9863 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9864 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9865 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9866 #if defined(TARGET_PPC64)
9867 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9868 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9869 #endif
9870 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9871 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9872 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9873 #if defined(TARGET_PPC64)
9874 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9875 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9876 #endif
9877 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9878 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9879 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9880 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9881 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9882 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9883 #if defined(TARGET_PPC64)
9884 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9885 #endif
9886 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9887 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
9888 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9889 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9890 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9891 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9892 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9893 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9894 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9895 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9896 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9897 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9898 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9899 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9900 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9901 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9902 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9903 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9904 #if defined(TARGET_PPC64)
9905 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9906 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9907 PPC_SEGMENT_64B),
9908 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9909 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9910 PPC_SEGMENT_64B),
9911 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9912 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9913 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9914 #endif
9915 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9916 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9917 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9918 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9919 #if defined(TARGET_PPC64)
9920 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9921 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9922 #endif
9923 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9924 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9925 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9926 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9927 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9928 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9929 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9930 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9931 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9932 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9933 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9934 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9935 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9936 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9937 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9938 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9939 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9940 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9941 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9942 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9943 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9944 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9945 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9946 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9947 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9948 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9949 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9950 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9951 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9952 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9953 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9954 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9955 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9956 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9957 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9958 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9959 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9960 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9961 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9962 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9963 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9964 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9965 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9966 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9967 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9968 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9969 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9970 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9971 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9972 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9973 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9974 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9975 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9976 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9977 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9978 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9979 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9980 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9981 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9982 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9983 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9984 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9985 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9986 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9987 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9988 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9989 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9990 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9991 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9992 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9993 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9994 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9995 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9996 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9997 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9998 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9999 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10000 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10001 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10002 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10003 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10004 PPC_NONE, PPC2_BOOKE206),
10005 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10006 PPC_NONE, PPC2_BOOKE206),
10007 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10008 PPC_NONE, PPC2_BOOKE206),
10009 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10010 PPC_NONE, PPC2_BOOKE206),
10011 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10012 PPC_NONE, PPC2_BOOKE206),
10013 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10014 PPC_NONE, PPC2_PRCNTL),
10015 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10016 PPC_NONE, PPC2_PRCNTL),
10017 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10018 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10019 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10020 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10021 PPC_BOOKE, PPC2_BOOKE206),
10022 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10023 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10024 PPC_BOOKE, PPC2_BOOKE206),
10025 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10026 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10027 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10028 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10029 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10030 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10031 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10032 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10033 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10034
10035 #undef GEN_INT_ARITH_ADD
10036 #undef GEN_INT_ARITH_ADD_CONST
10037 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10038 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10039 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10040 add_ca, compute_ca, compute_ov) \
10041 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10042 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10043 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10044 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10045 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10046 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10047 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10048 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10049 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10050 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10051 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10052
10053 #undef GEN_INT_ARITH_DIVW
10054 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10055 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10056 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10057 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10058 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10059 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10060 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10061 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10062 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10063 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10064
10065 #if defined(TARGET_PPC64)
10066 #undef GEN_INT_ARITH_DIVD
10067 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10068 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10069 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10070 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10071 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10072 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10073
10074 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10075 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10076 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10077 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10078
10079 #undef GEN_INT_ARITH_MUL_HELPER
10080 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10081 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10082 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10083 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10084 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10085 #endif
10086
10087 #undef GEN_INT_ARITH_SUBF
10088 #undef GEN_INT_ARITH_SUBF_CONST
10089 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10090 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10091 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10092 add_ca, compute_ca, compute_ov) \
10093 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10094 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10095 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10096 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10097 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10098 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10099 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10100 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10101 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10102 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10103 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10104
10105 #undef GEN_LOGICAL1
10106 #undef GEN_LOGICAL2
10107 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10108 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10109 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10110 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10111 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10112 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10113 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10114 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10115 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10116 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10117 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10118 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10119 #if defined(TARGET_PPC64)
10120 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10121 #endif
10122
10123 #if defined(TARGET_PPC64)
10124 #undef GEN_PPC64_R2
10125 #undef GEN_PPC64_R4
10126 #define GEN_PPC64_R2(name, opc1, opc2) \
10127 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10128 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10129 PPC_64B)
10130 #define GEN_PPC64_R4(name, opc1, opc2) \
10131 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10132 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10133 PPC_64B), \
10134 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10135 PPC_64B), \
10136 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10137 PPC_64B)
10138 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10139 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10140 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10141 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10142 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10143 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10144 #endif
10145
10146 #undef _GEN_FLOAT_ACB
10147 #undef GEN_FLOAT_ACB
10148 #undef _GEN_FLOAT_AB
10149 #undef GEN_FLOAT_AB
10150 #undef _GEN_FLOAT_AC
10151 #undef GEN_FLOAT_AC
10152 #undef GEN_FLOAT_B
10153 #undef GEN_FLOAT_BS
10154 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10155 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10156 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10157 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10158 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10159 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10160 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10161 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10162 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10163 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10164 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10165 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10166 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10167 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10168 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10169 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10170 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10171 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10172 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10173
10174 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10175 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10176 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10177 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10178 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10179 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10180 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10181 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10182 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10183 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10184 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10185 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10186 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10187 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10188 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10189 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10190 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10191 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10192 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10193 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10194 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10195 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10196 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10197 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10198 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10199 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10200 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10201 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10202 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10203 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10204 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10205
10206 #undef GEN_LD
10207 #undef GEN_LDU
10208 #undef GEN_LDUX
10209 #undef GEN_LDX_E
10210 #undef GEN_LDS
10211 #define GEN_LD(name, ldop, opc, type) \
10212 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10213 #define GEN_LDU(name, ldop, opc, type) \
10214 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10215 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10216 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10217 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10218 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10219 #define GEN_LDS(name, ldop, op, type) \
10220 GEN_LD(name, ldop, op | 0x20, type) \
10221 GEN_LDU(name, ldop, op | 0x21, type) \
10222 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10223 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10224
10225 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10226 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10227 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10228 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10229 #if defined(TARGET_PPC64)
10230 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10231 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10232 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10233 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10234 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10235 #endif
10236 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10237 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10238
10239 #undef GEN_ST
10240 #undef GEN_STU
10241 #undef GEN_STUX
10242 #undef GEN_STX_E
10243 #undef GEN_STS
10244 #define GEN_ST(name, stop, opc, type) \
10245 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10246 #define GEN_STU(name, stop, opc, type) \
10247 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10248 #define GEN_STUX(name, stop, opc2, opc3, type) \
10249 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10250 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10251 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10252 #define GEN_STS(name, stop, op, type) \
10253 GEN_ST(name, stop, op | 0x20, type) \
10254 GEN_STU(name, stop, op | 0x21, type) \
10255 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10256 GEN_STX(name, stop, 0x17, op | 0x00, type)
10257
10258 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10259 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10260 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10261 #if defined(TARGET_PPC64)
10262 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10263 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10264 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10265 #endif
10266 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10267 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10268
10269 #undef GEN_LDF
10270 #undef GEN_LDUF
10271 #undef GEN_LDUXF
10272 #undef GEN_LDXF
10273 #undef GEN_LDFS
10274 #define GEN_LDF(name, ldop, opc, type) \
10275 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10276 #define GEN_LDUF(name, ldop, opc, type) \
10277 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10278 #define GEN_LDUXF(name, ldop, opc, type) \
10279 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10280 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10281 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10282 #define GEN_LDFS(name, ldop, op, type) \
10283 GEN_LDF(name, ldop, op | 0x20, type) \
10284 GEN_LDUF(name, ldop, op | 0x21, type) \
10285 GEN_LDUXF(name, ldop, op | 0x01, type) \
10286 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10287
10288 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10289 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10290 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10291 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10292 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10293 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10294
10295 #undef GEN_STF
10296 #undef GEN_STUF
10297 #undef GEN_STUXF
10298 #undef GEN_STXF
10299 #undef GEN_STFS
10300 #define GEN_STF(name, stop, opc, type) \
10301 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10302 #define GEN_STUF(name, stop, opc, type) \
10303 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10304 #define GEN_STUXF(name, stop, opc, type) \
10305 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10306 #define GEN_STXF(name, stop, opc2, opc3, type) \
10307 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10308 #define GEN_STFS(name, stop, op, type) \
10309 GEN_STF(name, stop, op | 0x20, type) \
10310 GEN_STUF(name, stop, op | 0x21, type) \
10311 GEN_STUXF(name, stop, op | 0x01, type) \
10312 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10313
10314 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10315 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10316 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10317 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10318 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10319
10320 #undef GEN_CRLOGIC
10321 #define GEN_CRLOGIC(name, tcg_op, opc) \
10322 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10323 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10324 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10325 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10326 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10327 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10328 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10329 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10330 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10331
10332 #undef GEN_MAC_HANDLER
10333 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10334 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10335 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10336 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10337 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10338 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10339 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10340 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10341 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10342 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10343 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10344 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10345 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10346 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10347 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10348 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10349 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10350 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10351 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10352 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10353 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10354 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10355 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10356 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10357 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10358 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10359 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10360 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10361 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10362 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10363 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10364 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10365 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10366 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10367 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10368 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10369 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10370 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10371 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10372 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10373 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10374 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10375 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10376 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10377
10378 #undef GEN_VR_LDX
10379 #undef GEN_VR_STX
10380 #undef GEN_VR_LVE
10381 #undef GEN_VR_STVE
10382 #define GEN_VR_LDX(name, opc2, opc3) \
10383 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10384 #define GEN_VR_STX(name, opc2, opc3) \
10385 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10386 #define GEN_VR_LVE(name, opc2, opc3) \
10387 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10388 #define GEN_VR_STVE(name, opc2, opc3) \
10389 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10390 GEN_VR_LDX(lvx, 0x07, 0x03),
10391 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10392 GEN_VR_LVE(bx, 0x07, 0x00),
10393 GEN_VR_LVE(hx, 0x07, 0x01),
10394 GEN_VR_LVE(wx, 0x07, 0x02),
10395 GEN_VR_STX(svx, 0x07, 0x07),
10396 GEN_VR_STX(svxl, 0x07, 0x0F),
10397 GEN_VR_STVE(bx, 0x07, 0x04),
10398 GEN_VR_STVE(hx, 0x07, 0x05),
10399 GEN_VR_STVE(wx, 0x07, 0x06),
10400
10401 #undef GEN_VX_LOGICAL
10402 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10403 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10404
10405 #undef GEN_VX_LOGICAL_207
10406 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10407 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10408
10409 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10410 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10411 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10412 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10413 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10414 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10415 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10416 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10417
10418 #undef GEN_VXFORM
10419 #define GEN_VXFORM(name, opc2, opc3) \
10420 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10421
10422 #undef GEN_VXFORM_207
10423 #define GEN_VXFORM_207(name, opc2, opc3) \
10424 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10425
10426 #undef GEN_VXFORM_DUAL
10427 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10428 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10429
10430 #undef GEN_VXRFORM_DUAL
10431 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10432 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10433 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10434
10435 GEN_VXFORM(vaddubm, 0, 0),
10436 GEN_VXFORM(vadduhm, 0, 1),
10437 GEN_VXFORM(vadduwm, 0, 2),
10438 GEN_VXFORM_207(vaddudm, 0, 3),
10439 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10440 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10441 GEN_VXFORM(vsubuwm, 0, 18),
10442 GEN_VXFORM_207(vsubudm, 0, 19),
10443 GEN_VXFORM(vmaxub, 1, 0),
10444 GEN_VXFORM(vmaxuh, 1, 1),
10445 GEN_VXFORM(vmaxuw, 1, 2),
10446 GEN_VXFORM_207(vmaxud, 1, 3),
10447 GEN_VXFORM(vmaxsb, 1, 4),
10448 GEN_VXFORM(vmaxsh, 1, 5),
10449 GEN_VXFORM(vmaxsw, 1, 6),
10450 GEN_VXFORM_207(vmaxsd, 1, 7),
10451 GEN_VXFORM(vminub, 1, 8),
10452 GEN_VXFORM(vminuh, 1, 9),
10453 GEN_VXFORM(vminuw, 1, 10),
10454 GEN_VXFORM_207(vminud, 1, 11),
10455 GEN_VXFORM(vminsb, 1, 12),
10456 GEN_VXFORM(vminsh, 1, 13),
10457 GEN_VXFORM(vminsw, 1, 14),
10458 GEN_VXFORM_207(vminsd, 1, 15),
10459 GEN_VXFORM(vavgub, 1, 16),
10460 GEN_VXFORM(vavguh, 1, 17),
10461 GEN_VXFORM(vavguw, 1, 18),
10462 GEN_VXFORM(vavgsb, 1, 20),
10463 GEN_VXFORM(vavgsh, 1, 21),
10464 GEN_VXFORM(vavgsw, 1, 22),
10465 GEN_VXFORM(vmrghb, 6, 0),
10466 GEN_VXFORM(vmrghh, 6, 1),
10467 GEN_VXFORM(vmrghw, 6, 2),
10468 GEN_VXFORM(vmrglb, 6, 4),
10469 GEN_VXFORM(vmrglh, 6, 5),
10470 GEN_VXFORM(vmrglw, 6, 6),
10471 GEN_VXFORM_207(vmrgew, 6, 30),
10472 GEN_VXFORM_207(vmrgow, 6, 26),
10473 GEN_VXFORM(vmuloub, 4, 0),
10474 GEN_VXFORM(vmulouh, 4, 1),
10475 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10476 GEN_VXFORM(vmulosb, 4, 4),
10477 GEN_VXFORM(vmulosh, 4, 5),
10478 GEN_VXFORM_207(vmulosw, 4, 6),
10479 GEN_VXFORM(vmuleub, 4, 8),
10480 GEN_VXFORM(vmuleuh, 4, 9),
10481 GEN_VXFORM_207(vmuleuw, 4, 10),
10482 GEN_VXFORM(vmulesb, 4, 12),
10483 GEN_VXFORM(vmulesh, 4, 13),
10484 GEN_VXFORM_207(vmulesw, 4, 14),
10485 GEN_VXFORM(vslb, 2, 4),
10486 GEN_VXFORM(vslh, 2, 5),
10487 GEN_VXFORM(vslw, 2, 6),
10488 GEN_VXFORM_207(vsld, 2, 23),
10489 GEN_VXFORM(vsrb, 2, 8),
10490 GEN_VXFORM(vsrh, 2, 9),
10491 GEN_VXFORM(vsrw, 2, 10),
10492 GEN_VXFORM_207(vsrd, 2, 27),
10493 GEN_VXFORM(vsrab, 2, 12),
10494 GEN_VXFORM(vsrah, 2, 13),
10495 GEN_VXFORM(vsraw, 2, 14),
10496 GEN_VXFORM_207(vsrad, 2, 15),
10497 GEN_VXFORM(vslo, 6, 16),
10498 GEN_VXFORM(vsro, 6, 17),
10499 GEN_VXFORM(vaddcuw, 0, 6),
10500 GEN_VXFORM(vsubcuw, 0, 22),
10501 GEN_VXFORM(vaddubs, 0, 8),
10502 GEN_VXFORM(vadduhs, 0, 9),
10503 GEN_VXFORM(vadduws, 0, 10),
10504 GEN_VXFORM(vaddsbs, 0, 12),
10505 GEN_VXFORM(vaddshs, 0, 13),
10506 GEN_VXFORM(vaddsws, 0, 14),
10507 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10508 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10509 GEN_VXFORM(vsubuws, 0, 26),
10510 GEN_VXFORM(vsubsbs, 0, 28),
10511 GEN_VXFORM(vsubshs, 0, 29),
10512 GEN_VXFORM(vsubsws, 0, 30),
10513 GEN_VXFORM_207(vadduqm, 0, 4),
10514 GEN_VXFORM_207(vaddcuq, 0, 5),
10515 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10516 GEN_VXFORM_207(vsubuqm, 0, 20),
10517 GEN_VXFORM_207(vsubcuq, 0, 21),
10518 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10519 GEN_VXFORM(vrlb, 2, 0),
10520 GEN_VXFORM(vrlh, 2, 1),
10521 GEN_VXFORM(vrlw, 2, 2),
10522 GEN_VXFORM_207(vrld, 2, 3),
10523 GEN_VXFORM(vsl, 2, 7),
10524 GEN_VXFORM(vsr, 2, 11),
10525 GEN_VXFORM(vpkuhum, 7, 0),
10526 GEN_VXFORM(vpkuwum, 7, 1),
10527 GEN_VXFORM_207(vpkudum, 7, 17),
10528 GEN_VXFORM(vpkuhus, 7, 2),
10529 GEN_VXFORM(vpkuwus, 7, 3),
10530 GEN_VXFORM_207(vpkudus, 7, 19),
10531 GEN_VXFORM(vpkshus, 7, 4),
10532 GEN_VXFORM(vpkswus, 7, 5),
10533 GEN_VXFORM_207(vpksdus, 7, 21),
10534 GEN_VXFORM(vpkshss, 7, 6),
10535 GEN_VXFORM(vpkswss, 7, 7),
10536 GEN_VXFORM_207(vpksdss, 7, 23),
10537 GEN_VXFORM(vpkpx, 7, 12),
10538 GEN_VXFORM(vsum4ubs, 4, 24),
10539 GEN_VXFORM(vsum4sbs, 4, 28),
10540 GEN_VXFORM(vsum4shs, 4, 25),
10541 GEN_VXFORM(vsum2sws, 4, 26),
10542 GEN_VXFORM(vsumsws, 4, 30),
10543 GEN_VXFORM(vaddfp, 5, 0),
10544 GEN_VXFORM(vsubfp, 5, 1),
10545 GEN_VXFORM(vmaxfp, 5, 16),
10546 GEN_VXFORM(vminfp, 5, 17),
10547
10548 #undef GEN_VXRFORM1
10549 #undef GEN_VXRFORM
10550 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10551 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10552 #define GEN_VXRFORM(name, opc2, opc3) \
10553 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10554 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10555 GEN_VXRFORM(vcmpequb, 3, 0)
10556 GEN_VXRFORM(vcmpequh, 3, 1)
10557 GEN_VXRFORM(vcmpequw, 3, 2)
10558 GEN_VXRFORM(vcmpgtsb, 3, 12)
10559 GEN_VXRFORM(vcmpgtsh, 3, 13)
10560 GEN_VXRFORM(vcmpgtsw, 3, 14)
10561 GEN_VXRFORM(vcmpgtub, 3, 8)
10562 GEN_VXRFORM(vcmpgtuh, 3, 9)
10563 GEN_VXRFORM(vcmpgtuw, 3, 10)
10564 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10565 GEN_VXRFORM(vcmpgefp, 3, 7)
10566 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10567 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10568
10569 #undef GEN_VXFORM_SIMM
10570 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10571 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10572 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10573 GEN_VXFORM_SIMM(vspltish, 6, 13),
10574 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10575
10576 #undef GEN_VXFORM_NOA
10577 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10578 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10579 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10580 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10581 GEN_VXFORM_207(vupkhsw, 7, 25),
10582 GEN_VXFORM_NOA(vupklsb, 7, 10),
10583 GEN_VXFORM_NOA(vupklsh, 7, 11),
10584 GEN_VXFORM_207(vupklsw, 7, 27),
10585 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10586 GEN_VXFORM_NOA(vupklpx, 7, 15),
10587 GEN_VXFORM_NOA(vrefp, 5, 4),
10588 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10589 GEN_VXFORM_NOA(vexptefp, 5, 6),
10590 GEN_VXFORM_NOA(vlogefp, 5, 7),
10591 GEN_VXFORM_NOA(vrfim, 5, 11),
10592 GEN_VXFORM_NOA(vrfin, 5, 8),
10593 GEN_VXFORM_NOA(vrfip, 5, 10),
10594 GEN_VXFORM_NOA(vrfiz, 5, 9),
10595
10596 #undef GEN_VXFORM_UIMM
10597 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10598 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10599 GEN_VXFORM_UIMM(vspltb, 6, 8),
10600 GEN_VXFORM_UIMM(vsplth, 6, 9),
10601 GEN_VXFORM_UIMM(vspltw, 6, 10),
10602 GEN_VXFORM_UIMM(vcfux, 5, 12),
10603 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10604 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10605 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10606
10607 #undef GEN_VAFORM_PAIRED
10608 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10609 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10610 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10611 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10612 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10613 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10614 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10615 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10616
10617 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10618 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10619 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10620 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10621
10622 GEN_VXFORM_207(vbpermq, 6, 21),
10623 GEN_VXFORM_207(vgbbd, 6, 20),
10624 GEN_VXFORM_207(vpmsumb, 4, 16),
10625 GEN_VXFORM_207(vpmsumh, 4, 17),
10626 GEN_VXFORM_207(vpmsumw, 4, 18),
10627 GEN_VXFORM_207(vpmsumd, 4, 19),
10628
10629 GEN_VXFORM_207(vsbox, 4, 23),
10630
10631 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10632 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10633
10634 GEN_VXFORM_207(vshasigmaw, 1, 26),
10635 GEN_VXFORM_207(vshasigmad, 1, 27),
10636
10637 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10638
10639 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10640 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10641 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10642 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10643 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10644 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10645 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10646
10647 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10648 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10649 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10650 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10651 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10652
10653 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10654 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10655 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10656 #if defined(TARGET_PPC64)
10657 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10658 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10659 #endif
10660
10661 #undef GEN_XX2FORM
10662 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10663 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10664 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10665
10666 #undef GEN_XX3FORM
10667 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10668 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10669 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10670 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10671 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10672
10673 #undef GEN_XX2IFORM
10674 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10675 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10676 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10677 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10678 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10679
10680 #undef GEN_XX3_RC_FORM
10681 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10682 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10683 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10684 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10685 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10686 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10687 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10688 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10689 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10690
10691 #undef GEN_XX3FORM_DM
10692 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10693 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10694 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10695 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10696 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10697 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10698 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10699 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10700 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10701 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10702 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10703 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10704 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10705 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10706 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10707 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10708 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10709
10710 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10711 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10712 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10713 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10714
10715 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10716 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10717 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10718 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10719 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10720 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10721 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10722 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10723
10724 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10725 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10726 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10727 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10728 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10729 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10730 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10731 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10732 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10733 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10734 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10735 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10736 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10737 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10738 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10739 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10740 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10741 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10742 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10743 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10744 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10745 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10746 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10747 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10748 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10749 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10750 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10751 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10752 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10753 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10754 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10755 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10756 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10757 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10758 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10759 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10760
10761 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10762 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10763 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10764 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10765 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10766 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10767 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10768 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10769 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10770 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10771 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10772 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10773 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10774 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10775 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10776 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10777 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10778 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10779
10780 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10781 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10782 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10783 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10784 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10785 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10786 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10787 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10788 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10789 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10790 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10791 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10792 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10793 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10794 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10795 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10796 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10797 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10798 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10799 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10800 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10801 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10802 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10803 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10804 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10805 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10806 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10807 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10808 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10809 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10810 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10811 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10812 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10813 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10814 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10815 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10816
10817 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10818 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10819 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10820 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10821 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10822 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10823 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10824 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10825 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10826 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10827 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10828 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10829 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10830 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10831 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10832 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10833 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10834 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10835 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10836 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10837 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10838 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10839 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10840 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10841 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10842 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10843 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10844 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10845 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10846 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10847 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10848 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10849 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10850 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10851 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10852 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10853
10854 #undef VSX_LOGICAL
10855 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10856 GEN_XX3FORM(name, opc2, opc3, fl2)
10857
10858 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10859 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10860 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10861 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10862 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10863 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10864 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10865 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10866 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10867 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10868 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10869 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10870
10871 #define GEN_XXSEL_ROW(opc3) \
10872 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10873 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10874 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10875 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10876 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10877 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10878 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10879 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10880
10881 GEN_XXSEL_ROW(0x00)
10882 GEN_XXSEL_ROW(0x01)
10883 GEN_XXSEL_ROW(0x02)
10884 GEN_XXSEL_ROW(0x03)
10885 GEN_XXSEL_ROW(0x04)
10886 GEN_XXSEL_ROW(0x05)
10887 GEN_XXSEL_ROW(0x06)
10888 GEN_XXSEL_ROW(0x07)
10889 GEN_XXSEL_ROW(0x08)
10890 GEN_XXSEL_ROW(0x09)
10891 GEN_XXSEL_ROW(0x0A)
10892 GEN_XXSEL_ROW(0x0B)
10893 GEN_XXSEL_ROW(0x0C)
10894 GEN_XXSEL_ROW(0x0D)
10895 GEN_XXSEL_ROW(0x0E)
10896 GEN_XXSEL_ROW(0x0F)
10897 GEN_XXSEL_ROW(0x10)
10898 GEN_XXSEL_ROW(0x11)
10899 GEN_XXSEL_ROW(0x12)
10900 GEN_XXSEL_ROW(0x13)
10901 GEN_XXSEL_ROW(0x14)
10902 GEN_XXSEL_ROW(0x15)
10903 GEN_XXSEL_ROW(0x16)
10904 GEN_XXSEL_ROW(0x17)
10905 GEN_XXSEL_ROW(0x18)
10906 GEN_XXSEL_ROW(0x19)
10907 GEN_XXSEL_ROW(0x1A)
10908 GEN_XXSEL_ROW(0x1B)
10909 GEN_XXSEL_ROW(0x1C)
10910 GEN_XXSEL_ROW(0x1D)
10911 GEN_XXSEL_ROW(0x1E)
10912 GEN_XXSEL_ROW(0x1F)
10913
10914 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10915
10916 #undef GEN_DFP_T_A_B_Rc
10917 #undef GEN_DFP_BF_A_B
10918 #undef GEN_DFP_BF_A_DCM
10919 #undef GEN_DFP_T_B_U32_U32_Rc
10920 #undef GEN_DFP_T_A_B_I32_Rc
10921 #undef GEN_DFP_T_B_Rc
10922 #undef GEN_DFP_T_FPR_I32_Rc
10923
10924 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10925 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10926
10927 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10928 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10929 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10930
10931 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10932 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10933 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10934 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10935 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10936
10937 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10938 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10939
10940 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10941 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10942 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10943
10944 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10945 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10946 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10947 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10948 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10949
10950 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10951 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10952
10953 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10954 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10955
10956 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10957 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10958
10959 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10960 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10961
10962 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10963 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10964
10965 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10966 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10967
10968 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10969 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10970
10971 #define GEN_DFP_BF_A_B(name, op1, op2) \
10972 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10973
10974 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10975 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10976
10977 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
10978 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10979
10980 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
10981 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10982
10983 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10984 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10985
10986 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10987 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10988
10989 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10990 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10991
10992 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10993 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10994
10995 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10996 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10997
10998 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10999 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11000
11001 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11002 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11003
11004 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11005 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11006
11007 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11008 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11009
11010 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11011 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11012
11013 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11014 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11015
11016 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11017 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11018
11019 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11020 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11021
11022 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11023 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11024
11025 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11026 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11027 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11028 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11029 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11030 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11031 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11032 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11033 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11034 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11035 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11036 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11037 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11038 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11039 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11040 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11041 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11042 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11043 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11044 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11045 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11046 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11047 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11048 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11049 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11050 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11051 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11052 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11053 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11054 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11055 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11056 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11057 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11058 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11059 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11060 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11061 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11062 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11063 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11064 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11065 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11066 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11067 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11068 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11069 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11070 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11071 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11072 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11073 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11074 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11075
11076 #undef GEN_SPE
11077 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11078 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11079 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11080 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11081 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11082 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11083 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11084 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11085 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11086 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11087 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11088 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11089 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11090 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11091 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11092 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11093 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11094 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11095 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11096 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11097 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11098 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11099 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11100 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11101 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11102 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11103 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11104 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11105 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11106 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11107 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11108
11109 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11110 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11111 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11112 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11113 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11114 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11115 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11116 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11117 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11118 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11119 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11120 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11121 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11122 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11123
11124 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11125 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11126 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11127 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11128 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11129 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11130 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11131 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11132 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11133 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11134 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11135 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11136 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11137 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11138
11139 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11140 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11141 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11142 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11143 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11144 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11145 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11146 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11147 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11148 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11149 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11150 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11151 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11152 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11153 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11154 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11155
11156 #undef GEN_SPEOP_LDST
11157 #define GEN_SPEOP_LDST(name, opc2, sh) \
11158 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11159 GEN_SPEOP_LDST(evldd, 0x00, 3),
11160 GEN_SPEOP_LDST(evldw, 0x01, 3),
11161 GEN_SPEOP_LDST(evldh, 0x02, 3),
11162 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11163 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11164 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11165 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11166 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11167 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11168 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11169 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11170
11171 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11172 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11173 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11174 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11175 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11176 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11177 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11178
11179 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11180 PPC_NONE, PPC2_TM),
11181 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11182 PPC_NONE, PPC2_TM),
11183 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11184 PPC_NONE, PPC2_TM),
11185 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11186 PPC_NONE, PPC2_TM),
11187 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11188 PPC_NONE, PPC2_TM),
11189 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11190 PPC_NONE, PPC2_TM),
11191 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11192 PPC_NONE, PPC2_TM),
11193 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11194 PPC_NONE, PPC2_TM),
11195 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11196 PPC_NONE, PPC2_TM),
11197 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11198 PPC_NONE, PPC2_TM),
11199 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11200 PPC_NONE, PPC2_TM),
11201 };
11202
11203 #include "helper_regs.h"
11204 #include "translate_init.c"
11205
11206 /*****************************************************************************/
11207 /* Misc PowerPC helpers */
11208 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11209 int flags)
11210 {
11211 #define RGPL 4
11212 #define RFPL 4
11213
11214 PowerPCCPU *cpu = POWERPC_CPU(cs);
11215 CPUPPCState *env = &cpu->env;
11216 int i;
11217
11218 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11219 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11220 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11221 cs->cpu_index);
11222 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11223 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11224 env->hflags, env->mmu_idx);
11225 #if !defined(NO_TIMER_DUMP)
11226 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11227 #if !defined(CONFIG_USER_ONLY)
11228 " DECR %08" PRIu32
11229 #endif
11230 "\n",
11231 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11232 #if !defined(CONFIG_USER_ONLY)
11233 , cpu_ppc_load_decr(env)
11234 #endif
11235 );
11236 #endif
11237 for (i = 0; i < 32; i++) {
11238 if ((i & (RGPL - 1)) == 0)
11239 cpu_fprintf(f, "GPR%02d", i);
11240 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11241 if ((i & (RGPL - 1)) == (RGPL - 1))
11242 cpu_fprintf(f, "\n");
11243 }
11244 cpu_fprintf(f, "CR ");
11245 for (i = 0; i < 8; i++)
11246 cpu_fprintf(f, "%01x", env->crf[i]);
11247 cpu_fprintf(f, " [");
11248 for (i = 0; i < 8; i++) {
11249 char a = '-';
11250 if (env->crf[i] & 0x08)
11251 a = 'L';
11252 else if (env->crf[i] & 0x04)
11253 a = 'G';
11254 else if (env->crf[i] & 0x02)
11255 a = 'E';
11256 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11257 }
11258 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11259 env->reserve_addr);
11260 for (i = 0; i < 32; i++) {
11261 if ((i & (RFPL - 1)) == 0)
11262 cpu_fprintf(f, "FPR%02d", i);
11263 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11264 if ((i & (RFPL - 1)) == (RFPL - 1))
11265 cpu_fprintf(f, "\n");
11266 }
11267 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11268 #if !defined(CONFIG_USER_ONLY)
11269 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11270 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11271 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11272 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11273
11274 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11275 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11276 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11277 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11278
11279 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11280 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11281 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11282 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11283
11284 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11285 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11286 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11287 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11288 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11289
11290 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11291 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11292 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11293 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11294
11295 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11296 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11297 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11298 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11299
11300 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11301 " EPR " TARGET_FMT_lx "\n",
11302 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11303 env->spr[SPR_BOOKE_EPR]);
11304
11305 /* FSL-specific */
11306 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11307 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11308 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11309 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11310
11311 /*
11312 * IVORs are left out as they are large and do not change often --
11313 * they can be read with "p $ivor0", "p $ivor1", etc.
11314 */
11315 }
11316
11317 #if defined(TARGET_PPC64)
11318 if (env->flags & POWERPC_FLAG_CFAR) {
11319 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11320 }
11321 #endif
11322
11323 switch (env->mmu_model) {
11324 case POWERPC_MMU_32B:
11325 case POWERPC_MMU_601:
11326 case POWERPC_MMU_SOFT_6xx:
11327 case POWERPC_MMU_SOFT_74xx:
11328 #if defined(TARGET_PPC64)
11329 case POWERPC_MMU_64B:
11330 case POWERPC_MMU_2_03:
11331 case POWERPC_MMU_2_06:
11332 case POWERPC_MMU_2_06a:
11333 case POWERPC_MMU_2_07:
11334 case POWERPC_MMU_2_07a:
11335 #endif
11336 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11337 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11338 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11339 break;
11340 case POWERPC_MMU_BOOKE206:
11341 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11342 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11343 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11344 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11345
11346 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11347 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11348 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11349 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11350
11351 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11352 " TLB1CFG " TARGET_FMT_lx "\n",
11353 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11354 env->spr[SPR_BOOKE_TLB1CFG]);
11355 break;
11356 default:
11357 break;
11358 }
11359 #endif
11360
11361 #undef RGPL
11362 #undef RFPL
11363 }
11364
11365 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11366 fprintf_function cpu_fprintf, int flags)
11367 {
11368 #if defined(DO_PPC_STATISTICS)
11369 PowerPCCPU *cpu = POWERPC_CPU(cs);
11370 opc_handler_t **t1, **t2, **t3, *handler;
11371 int op1, op2, op3;
11372
11373 t1 = cpu->env.opcodes;
11374 for (op1 = 0; op1 < 64; op1++) {
11375 handler = t1[op1];
11376 if (is_indirect_opcode(handler)) {
11377 t2 = ind_table(handler);
11378 for (op2 = 0; op2 < 32; op2++) {
11379 handler = t2[op2];
11380 if (is_indirect_opcode(handler)) {
11381 t3 = ind_table(handler);
11382 for (op3 = 0; op3 < 32; op3++) {
11383 handler = t3[op3];
11384 if (handler->count == 0)
11385 continue;
11386 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11387 "%016" PRIx64 " %" PRId64 "\n",
11388 op1, op2, op3, op1, (op3 << 5) | op2,
11389 handler->oname,
11390 handler->count, handler->count);
11391 }
11392 } else {
11393 if (handler->count == 0)
11394 continue;
11395 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11396 "%016" PRIx64 " %" PRId64 "\n",
11397 op1, op2, op1, op2, handler->oname,
11398 handler->count, handler->count);
11399 }
11400 }
11401 } else {
11402 if (handler->count == 0)
11403 continue;
11404 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11405 " %" PRId64 "\n",
11406 op1, op1, handler->oname,
11407 handler->count, handler->count);
11408 }
11409 }
11410 #endif
11411 }
11412
11413 /*****************************************************************************/
11414 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11415 {
11416 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11417 CPUState *cs = CPU(cpu);
11418 DisasContext ctx, *ctxp = &ctx;
11419 opc_handler_t **table, *handler;
11420 target_ulong pc_start;
11421 int num_insns;
11422 int max_insns;
11423
11424 pc_start = tb->pc;
11425 ctx.nip = pc_start;
11426 ctx.tb = tb;
11427 ctx.exception = POWERPC_EXCP_NONE;
11428 ctx.spr_cb = env->spr_cb;
11429 ctx.pr = msr_pr;
11430 ctx.hv = !msr_pr && msr_hv;
11431 ctx.mem_idx = env->mmu_idx;
11432 ctx.insns_flags = env->insns_flags;
11433 ctx.insns_flags2 = env->insns_flags2;
11434 ctx.access_type = -1;
11435 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11436 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11437 #if defined(TARGET_PPC64)
11438 ctx.sf_mode = msr_is_64bit(env, env->msr);
11439 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11440 #endif
11441 ctx.fpu_enabled = msr_fp;
11442 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11443 ctx.spe_enabled = msr_spe;
11444 else
11445 ctx.spe_enabled = 0;
11446 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11447 ctx.altivec_enabled = msr_vr;
11448 else
11449 ctx.altivec_enabled = 0;
11450 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11451 ctx.vsx_enabled = msr_vsx;
11452 } else {
11453 ctx.vsx_enabled = 0;
11454 }
11455 #if defined(TARGET_PPC64)
11456 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11457 ctx.tm_enabled = msr_tm;
11458 } else {
11459 ctx.tm_enabled = 0;
11460 }
11461 #endif
11462 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11463 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11464 else
11465 ctx.singlestep_enabled = 0;
11466 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11467 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11468 if (unlikely(cs->singlestep_enabled)) {
11469 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11470 }
11471 #if defined (DO_SINGLE_STEP) && 0
11472 /* Single step trace mode */
11473 msr_se = 1;
11474 #endif
11475 num_insns = 0;
11476 max_insns = tb->cflags & CF_COUNT_MASK;
11477 if (max_insns == 0) {
11478 max_insns = CF_COUNT_MASK;
11479 }
11480 if (max_insns > TCG_MAX_INSNS) {
11481 max_insns = TCG_MAX_INSNS;
11482 }
11483
11484 gen_tb_start(tb);
11485 tcg_clear_temp_count();
11486 /* Set env in case of segfault during code fetch */
11487 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11488 tcg_gen_insn_start(ctx.nip);
11489 num_insns++;
11490
11491 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11492 gen_debug_exception(ctxp);
11493 /* The address covered by the breakpoint must be included in
11494 [tb->pc, tb->pc + tb->size) in order to for it to be
11495 properly cleared -- thus we increment the PC here so that
11496 the logic setting tb->size below does the right thing. */
11497 ctx.nip += 4;
11498 break;
11499 }
11500
11501 LOG_DISAS("----------------\n");
11502 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11503 ctx.nip, ctx.mem_idx, (int)msr_ir);
11504 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11505 gen_io_start();
11506 if (unlikely(need_byteswap(&ctx))) {
11507 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11508 } else {
11509 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11510 }
11511 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11512 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11513 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11514 ctx.nip += 4;
11515 table = env->opcodes;
11516 handler = table[opc1(ctx.opcode)];
11517 if (is_indirect_opcode(handler)) {
11518 table = ind_table(handler);
11519 handler = table[opc2(ctx.opcode)];
11520 if (is_indirect_opcode(handler)) {
11521 table = ind_table(handler);
11522 handler = table[opc3(ctx.opcode)];
11523 }
11524 }
11525 /* Is opcode *REALLY* valid ? */
11526 if (unlikely(handler->handler == &gen_invalid)) {
11527 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11528 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11529 opc1(ctx.opcode), opc2(ctx.opcode),
11530 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11531 } else {
11532 uint32_t inval;
11533
11534 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11535 inval = handler->inval2;
11536 } else {
11537 inval = handler->inval1;
11538 }
11539
11540 if (unlikely((ctx.opcode & inval) != 0)) {
11541 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11542 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11543 ctx.opcode & inval, opc1(ctx.opcode),
11544 opc2(ctx.opcode), opc3(ctx.opcode),
11545 ctx.opcode, ctx.nip - 4);
11546 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11547 break;
11548 }
11549 }
11550 (*(handler->handler))(&ctx);
11551 #if defined(DO_PPC_STATISTICS)
11552 handler->count++;
11553 #endif
11554 /* Check trace mode exceptions */
11555 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11556 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11557 ctx.exception != POWERPC_SYSCALL &&
11558 ctx.exception != POWERPC_EXCP_TRAP &&
11559 ctx.exception != POWERPC_EXCP_BRANCH)) {
11560 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11561 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11562 (cs->singlestep_enabled) ||
11563 singlestep ||
11564 num_insns >= max_insns)) {
11565 /* if we reach a page boundary or are single stepping, stop
11566 * generation
11567 */
11568 break;
11569 }
11570 if (tcg_check_temp_count()) {
11571 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11572 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11573 ctx.opcode);
11574 exit(1);
11575 }
11576 }
11577 if (tb->cflags & CF_LAST_IO)
11578 gen_io_end();
11579 if (ctx.exception == POWERPC_EXCP_NONE) {
11580 gen_goto_tb(&ctx, 0, ctx.nip);
11581 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11582 if (unlikely(cs->singlestep_enabled)) {
11583 gen_debug_exception(ctxp);
11584 }
11585 /* Generate the return instruction */
11586 tcg_gen_exit_tb(0);
11587 }
11588 gen_tb_end(tb, num_insns);
11589
11590 tb->size = ctx.nip - pc_start;
11591 tb->icount = num_insns;
11592
11593 #if defined(DEBUG_DISAS)
11594 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11595 int flags;
11596 flags = env->bfd_mach;
11597 flags |= ctx.le_mode << 16;
11598 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11599 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11600 qemu_log("\n");
11601 }
11602 #endif
11603 }
11604
11605 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11606 target_ulong *data)
11607 {
11608 env->nip = data[0];
11609 }
AR7 emulation for QEMU